2 * This file implements functions to finalize the irg for emit.
3 * @author Christian Wuerdig
19 #include "../bearch.h"
20 #include "../besched_t.h"
21 #include "../benode_t.h"
23 #include "bearch_ia32_t.h"
24 #include "ia32_finish.h"
25 #include "ia32_new_nodes.h"
26 #include "ia32_map_regs.h"
27 #include "ia32_transform.h"
28 #include "ia32_dbg_stat.h"
29 #include "ia32_optimize.h"
30 #include "gen_ia32_regalloc_if.h"
33 * Transforms a Sub or xSub into Neg--Add iff OUT_REG == SRC2_REG.
34 * THIS FUNCTIONS MUST BE CALLED AFTER REGISTER ALLOCATION.
36 static void ia32_transform_sub_to_neg_add(ir_node *irn, ia32_code_gen_t *cg) {
38 ir_node *in1, *in2, *noreg, *nomem, *res;
39 ir_node *noreg_fp, *block;
40 ir_mode *mode = get_irn_mode(irn);
41 dbg_info *dbg = get_irn_dbg_info(irn);
42 const arch_register_t *in1_reg, *in2_reg, *out_reg, **slots;
45 /* Return if AM node or not a Sub or xSub */
46 if (!(is_ia32_Sub(irn) || is_ia32_xSub(irn)) || get_ia32_op_type(irn) != ia32_Normal)
49 noreg = ia32_new_NoReg_gp(cg);
50 noreg_fp = ia32_new_NoReg_fp(cg);
51 nomem = new_rd_NoMem(cg->irg);
52 in1 = get_irn_n(irn, 2);
53 in2 = get_irn_n(irn, 3);
54 in1_reg = arch_get_irn_register(cg->arch_env, in1);
55 in2_reg = arch_get_irn_register(cg->arch_env, in2);
56 out_reg = get_ia32_out_reg(irn, 0);
59 block = get_nodes_block(irn);
61 /* in case of sub and OUT == SRC2 we can transform the sequence into neg src2 -- add */
62 if (!REGS_ARE_EQUAL(out_reg, in2_reg))
65 /* generate the neg src2 */
66 if(mode_is_float(mode)) {
70 res = new_rd_ia32_xXor(dbg, irg, block, noreg, noreg, in2, noreg_fp, nomem);
71 size = get_mode_size_bits(mode);
72 name = ia32_gen_fp_known_const(size == 32 ? ia32_SSIGN : ia32_DSIGN);
73 set_ia32_am_sc(res, name);
74 set_ia32_op_type(res, ia32_AddrModeS);
75 set_ia32_ls_mode(res, get_ia32_ls_mode(irn));
77 res = new_rd_ia32_Neg(dbg, irg, block, noreg, noreg, in2, nomem);
79 arch_set_irn_register(cg->arch_env, res, in2_reg);
82 sched_add_before(irn, res);
84 /* generate the add */
85 if (mode_is_float(mode)) {
86 res = new_rd_ia32_xAdd(dbg, irg, block, noreg, noreg, res, in1, nomem);
87 set_ia32_am_support(res, ia32_am_Source);
88 set_ia32_ls_mode(res, get_ia32_ls_mode(irn));
91 res = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, res, in1, nomem);
92 set_ia32_am_support(res, ia32_am_Full);
93 set_ia32_commutative(res);
96 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(cg, irn));
98 slots = get_ia32_slots(res);
101 /* exchange the add and the sub */
102 edges_reroute(irn, res, irg);
104 /* add to schedule */
105 sched_add_before(irn, res);
107 /* remove the old sub */
109 arity = get_irn_arity(irn);
110 for(i = 0; i < arity; ++i) {
111 set_irn_n(irn, i, new_Bad());
114 DBG_OPT_SUB2NEGADD(irn, res);
118 * Transforms a LEA into an Add if possible
119 * THIS FUNCTIONS MUST BE CALLED AFTER REGISTER ALLOCATION.
121 static void ia32_transform_lea_to_add(ir_node *irn, ia32_code_gen_t *cg) {
122 ia32_am_flavour_t am_flav;
124 dbg_info *dbg = get_irn_dbg_info(irn);
127 ir_node *nomem, *noreg, *base, *index, *op1, *op2;
130 const arch_register_t *out_reg, *base_reg, *index_reg;
133 if (! is_ia32_Lea(irn))
136 am_flav = get_ia32_am_flavour(irn);
138 /* mustn't have a symconst */
139 if (get_ia32_am_sc(irn))
142 /* only some LEAs can be transformed to an Add */
143 if (am_flav != ia32_am_B && am_flav != ia32_am_OB && am_flav != ia32_am_OI && am_flav != ia32_am_BI)
146 noreg = ia32_new_NoReg_gp(cg);
147 nomem = new_rd_NoMem(cg->irg);
150 base = get_irn_n(irn, 0);
151 index = get_irn_n(irn,1);
153 if (am_flav & ia32_O) {
154 offs = get_ia32_am_offs_int(irn);
157 out_reg = arch_get_irn_register(cg->arch_env, irn);
158 base_reg = arch_get_irn_register(cg->arch_env, base);
159 index_reg = arch_get_irn_register(cg->arch_env, index);
162 block = get_nodes_block(irn);
164 switch(get_ia32_am_flavour(irn)) {
166 /* out register must be same as base register */
167 if (! REGS_ARE_EQUAL(out_reg, base_reg))
173 /* out register must be same as base register */
174 if (! REGS_ARE_EQUAL(out_reg, base_reg))
181 /* out register must be same as index register */
182 if (! REGS_ARE_EQUAL(out_reg, index_reg))
189 /* out register must be same as one in register */
190 if (REGS_ARE_EQUAL(out_reg, base_reg)) {
194 else if (REGS_ARE_EQUAL(out_reg, index_reg)) {
199 /* in registers a different from out -> no Add possible */
206 res = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, op1, op2, nomem);
207 arch_set_irn_register(cg->arch_env, res, out_reg);
208 set_ia32_op_type(res, ia32_Normal);
209 set_ia32_commutative(res);
212 tarval *tv = new_tarval_from_long(offs, mode_Iu);
213 set_ia32_Immop_tarval(res, tv);
216 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(cg, irn));
218 /* add Add to schedule */
219 sched_add_before(irn, res);
221 DBG_OPT_LEA2ADD(irn, res);
223 /* remove the old LEA */
226 /* exchange the Add and the LEA */
230 static INLINE int need_constraint_copy(ir_node *irn) {
232 ! is_ia32_Lea(irn) && \
233 ! is_ia32_Conv_I2I(irn) && \
234 ! is_ia32_Conv_I2I8Bit(irn) && \
235 ! is_ia32_CmpCMov(irn) && \
236 ! is_ia32_PsiCondCMov(irn) && \
237 ! is_ia32_CmpSet(irn);
241 * Insert copies for all ia32 nodes where the should_be_same requirement
243 * Transform Sub into Neg -- Add if IN2 == OUT
245 static void ia32_finish_node(ir_node *irn, void *env) {
246 ia32_code_gen_t *cg = env;
247 const arch_register_req_t **reqs;
248 const arch_register_t *out_reg, *in_reg, *in2_reg;
250 ir_node *copy, *in_node, *block, *in2_node;
251 ia32_op_type_t op_tp;
253 if (is_ia32_irn(irn)) {
254 /* AM Dest nodes don't produce any values */
255 op_tp = get_ia32_op_type(irn);
256 if (op_tp == ia32_AddrModeD)
259 reqs = get_ia32_out_req_all(irn);
260 n_res = get_ia32_n_res(irn);
261 block = get_nodes_block(irn);
263 /* check all OUT requirements, if there is a should_be_same */
264 if ((op_tp == ia32_Normal || op_tp == ia32_AddrModeS) && need_constraint_copy(irn))
266 for (i = 0; i < n_res; i++) {
267 if (arch_register_req_is(reqs[i], should_be_same)) {
268 int same_pos = reqs[i]->other_same;
270 /* get in and out register */
271 out_reg = get_ia32_out_reg(irn, i);
272 in_node = get_irn_n(irn, same_pos);
273 in_reg = arch_get_irn_register(cg->arch_env, in_node);
275 /* don't copy ignore nodes */
276 if (arch_irn_is(cg->arch_env, in_node, ignore) && is_Proj(in_node))
279 /* check if in and out register are equal */
280 if (! REGS_ARE_EQUAL(out_reg, in_reg)) {
281 /* in case of a commutative op: just exchange the in's */
282 /* beware: the current op could be everything, so test for ia32 */
283 /* commutativity first before getting the second in */
284 if (is_ia32_commutative(irn)) {
285 in2_node = get_irn_n(irn, same_pos ^ 1);
286 in2_reg = arch_get_irn_register(cg->arch_env, in2_node);
288 if (REGS_ARE_EQUAL(out_reg, in2_reg)) {
289 set_irn_n(irn, same_pos, in2_node);
290 set_irn_n(irn, same_pos ^ 1, in_node);
297 DBG((cg->mod, LEVEL_1, "inserting copy for %+F in_pos %d\n", irn, same_pos));
298 /* create copy from in register */
299 copy = be_new_Copy(arch_register_get_class(in_reg), cg->irg, block, in_node);
301 DBG_OPT_2ADDRCPY(copy);
303 /* destination is the out register */
304 arch_set_irn_register(cg->arch_env, copy, out_reg);
306 /* insert copy before the node into the schedule */
307 sched_add_before(irn, copy);
310 set_irn_n(irn, same_pos, copy);
317 /* check xCmp: try to avoid unordered cmp */
318 if ((is_ia32_xCmp(irn) || is_ia32_xCmpCMov(irn) || is_ia32_xCmpSet(irn)) &&
319 op_tp == ia32_Normal &&
320 ! is_ia32_ImmConst(irn) && ! is_ia32_ImmSymConst(irn))
322 long pnc = get_ia32_pncode(irn);
324 if (pnc & pn_Cmp_Uo) {
326 int idx1 = 2, idx2 = 3;
328 if (is_ia32_xCmpCMov(irn)) {
333 tmp = get_irn_n(irn, idx1);
334 set_irn_n(irn, idx1, get_irn_n(irn, idx2));
335 set_irn_n(irn, idx2, tmp);
337 set_ia32_pncode(irn, get_negated_pnc(pnc, mode_E));
346 * We have a source address mode node with base or index register equal to
347 * result register. The constraint handler will insert a copy from the
348 * remaining input operand to the result register -> base or index is
350 * Solution: Turn back this address mode into explicit Load + Operation.
352 static void fix_am_source(ir_node *irn, void *env) {
353 ia32_code_gen_t *cg = env;
354 ir_node *base, *index, *noreg;
355 const arch_register_t *reg_base, *reg_index;
356 const arch_register_req_t **reqs;
359 /* check only ia32 nodes with source address mode */
360 if (! is_ia32_irn(irn) || get_ia32_op_type(irn) != ia32_AddrModeS)
362 /* no need to fix unary operations */
363 if (get_irn_arity(irn) == 4)
366 base = get_irn_n(irn, 0);
367 index = get_irn_n(irn, 1);
369 reg_base = arch_get_irn_register(cg->arch_env, base);
370 reg_index = arch_get_irn_register(cg->arch_env, index);
371 reqs = get_ia32_out_req_all(irn);
373 noreg = ia32_new_NoReg_gp(cg);
375 n_res = get_ia32_n_res(irn);
377 for (i = 0; i < n_res; i++) {
378 if (arch_register_req_is(reqs[i], should_be_same)) {
379 /* get in and out register */
380 const arch_register_t *out_reg = get_ia32_out_reg(irn, i);
381 int same_pos = reqs[i]->other_same;
384 there is a constraint for the remaining operand
385 and the result register is equal to base or index register
388 (REGS_ARE_EQUAL(out_reg, reg_base) || REGS_ARE_EQUAL(out_reg, reg_index)))
390 /* turn back address mode */
391 ir_node *in_node = get_irn_n(irn, 2);
392 const arch_register_t *in_reg = arch_get_irn_register(cg->arch_env, in_node);
393 ir_node *block = get_nodes_block(irn);
394 ir_mode *ls_mode = get_ia32_ls_mode(irn);
398 if (arch_register_get_class(in_reg) == &ia32_reg_classes[CLASS_ia32_gp]) {
399 load = new_rd_ia32_Load(NULL, cg->irg, block, base, index, get_irn_n(irn, 4));
400 pnres = pn_ia32_Load_res;
402 else if (arch_register_get_class(in_reg) == &ia32_reg_classes[CLASS_ia32_xmm]) {
403 load = new_rd_ia32_xLoad(NULL, cg->irg, block, base, index, get_irn_n(irn, 4));
404 pnres = pn_ia32_xLoad_res;
407 panic("cannot turn back address mode for this register class");
410 /* copy address mode information to load */
411 set_ia32_ls_mode(load, ls_mode);
412 set_ia32_am_flavour(load, get_ia32_am_flavour(irn));
413 set_ia32_op_type(load, ia32_AddrModeS);
414 set_ia32_am_support(load, ia32_am_Source);
415 set_ia32_am_scale(load, get_ia32_am_scale(irn));
416 set_ia32_am_sc(load, get_ia32_am_sc(irn));
417 add_ia32_am_offs_int(load, get_ia32_am_offs_int(irn));
418 set_ia32_frame_ent(load, get_ia32_frame_ent(irn));
420 if (is_ia32_use_frame(irn))
421 set_ia32_use_frame(load);
423 /* insert the load into schedule */
424 sched_add_before(irn, load);
426 DBG((cg->mod, LEVEL_3, "irg %+F: build back AM source for node %+F, inserted load %+F\n", cg->irg, irn, load));
428 load = new_r_Proj(cg->irg, block, load, ls_mode, pnres);
429 arch_set_irn_register(cg->arch_env, load, out_reg);
431 /* insert the load result proj into schedule */
432 sched_add_before(irn, load);
434 /* set the new input operand */
435 set_irn_n(irn, 3, load);
437 /* this is a normal node now */
438 set_irn_n(irn, 0, noreg);
439 set_irn_n(irn, 1, noreg);
440 set_ia32_op_type(irn, ia32_Normal);
448 static void ia32_finish_irg_walker(ir_node *block, void *env) {
451 /* first: turn back AM source if necessary */
452 for (irn = sched_first(block); ! sched_is_end(irn); irn = next) {
453 next = sched_next(irn);
454 fix_am_source(irn, env);
457 for (irn = sched_first(block); ! sched_is_end(irn); irn = next) {
458 ia32_code_gen_t *cg = env;
460 next = sched_next(irn);
462 /* check if there is a sub which need to be transformed */
463 ia32_transform_sub_to_neg_add(irn, cg);
465 /* transform a LEA into an Add if possible */
466 ia32_transform_lea_to_add(irn, cg);
469 /* second: insert copies and finish irg */
470 for (irn = sched_first(block); ! sched_is_end(irn); irn = next) {
471 next = sched_next(irn);
472 ia32_finish_node(irn, env);
476 static void ia32_push_on_queue_walker(ir_node *block, void *env) {
478 waitq_put(wq, block);
483 * Add Copy nodes for not fulfilled should_be_equal constraints
485 void ia32_finish_irg(ir_graph *irg, ia32_code_gen_t *cg) {
486 waitq *wq = new_waitq();
488 /* Push the blocks on the waitq because ia32_finish_irg_walker starts more walks ... */
489 irg_block_walk_graph(irg, NULL, ia32_push_on_queue_walker, wq);
491 while (! waitq_empty(wq)) {
492 ir_node *block = waitq_get(wq);
493 ia32_finish_irg_walker(block, cg);