2 * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This file implements functions to finalize the irg for emit.
23 * @author Christian Wuerdig
37 #include "../bearch.h"
38 #include "../besched.h"
39 #include "../benode.h"
41 #include "bearch_ia32_t.h"
42 #include "ia32_finish.h"
43 #include "ia32_new_nodes.h"
44 #include "ia32_map_regs.h"
45 #include "ia32_common_transform.h"
46 #include "ia32_transform.h"
47 #include "ia32_dbg_stat.h"
48 #include "ia32_optimize.h"
49 #include "gen_ia32_regalloc_if.h"
51 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
54 * Transforms a Sub or xSub into Neg--Add iff OUT_REG != SRC1_REG && OUT_REG == SRC2_REG.
55 * THIS FUNCTIONS MUST BE CALLED AFTER REGISTER ALLOCATION.
57 static void ia32_transform_sub_to_neg_add(ir_node *irn, ia32_code_gen_t *cg)
60 ir_node *in1, *in2, *noreg, *nomem, *res;
61 ir_node *noreg_fp, *block;
63 const arch_register_t *in1_reg, *in2_reg, *out_reg;
65 /* fix_am will solve this for AddressMode variants */
66 if (get_ia32_op_type(irn) != ia32_Normal)
69 noreg = ia32_new_NoReg_gp(cg);
70 noreg_fp = ia32_new_NoReg_xmm(cg);
72 in1 = get_irn_n(irn, n_ia32_binary_left);
73 in2 = get_irn_n(irn, n_ia32_binary_right);
74 in1_reg = arch_get_irn_register(in1);
75 in2_reg = arch_get_irn_register(in2);
76 out_reg = arch_irn_get_register(irn, 0);
79 block = get_nodes_block(irn);
81 if (out_reg == in1_reg)
84 /* in case of sub and OUT == SRC2 we can transform the sequence into neg src2 -- add */
85 if (out_reg != in2_reg)
88 dbg = get_irn_dbg_info(irn);
90 /* generate the neg src2 */
91 if (is_ia32_xSub(irn)) {
94 ir_mode *op_mode = get_ia32_ls_mode(irn);
96 assert(get_irn_mode(irn) != mode_T);
98 res = new_bd_ia32_xXor(dbg, block, noreg, noreg, nomem, in2, noreg_fp);
99 size = get_mode_size_bits(op_mode);
100 entity = ia32_gen_fp_known_const(size == 32 ? ia32_SSIGN : ia32_DSIGN);
101 set_ia32_am_sc(res, entity);
102 set_ia32_op_type(res, ia32_AddrModeS);
103 set_ia32_ls_mode(res, op_mode);
105 arch_set_irn_register(res, in2_reg);
107 /* add to schedule */
108 sched_add_before(irn, res);
110 /* generate the add */
111 res = new_bd_ia32_xAdd(dbg, block, noreg, noreg, nomem, res, in1);
112 set_ia32_ls_mode(res, get_ia32_ls_mode(irn));
114 /* exchange the add and the sub */
115 edges_reroute(irn, res, irg);
117 /* add to schedule */
118 sched_add_before(irn, res);
120 ir_node *res_proj = NULL;
121 ir_node *flags_proj = NULL;
122 const ir_edge_t *edge;
124 if (get_irn_mode(irn) == mode_T) {
125 /* collect the Proj uses */
126 foreach_out_edge(irn, edge) {
127 ir_node *proj = get_edge_src_irn(edge);
128 long pn = get_Proj_proj(proj);
129 if (pn == pn_ia32_Sub_res) {
130 assert(res_proj == NULL);
133 assert(pn == pn_ia32_Sub_flags);
134 assert(flags_proj == NULL);
140 if (flags_proj == NULL) {
141 res = new_bd_ia32_Neg(dbg, block, in2);
142 arch_set_irn_register(res, in2_reg);
144 /* add to schedule */
145 sched_add_before(irn, res);
147 /* generate the add */
148 res = new_bd_ia32_Add(dbg, block, noreg, noreg, nomem, res, in1);
149 arch_set_irn_register(res, out_reg);
150 set_ia32_commutative(res);
152 /* exchange the add and the sub */
153 edges_reroute(irn, res, irg);
155 /* add to schedule */
156 sched_add_before(irn, res);
158 ir_node *stc, *cmc, *not, *adc;
162 * ARG, the above technique does NOT set the flags right.
163 * So, we must produce the following code:
165 * t2 = a + ~b + Carry
168 * a + -b = a + (~b + 1) would set the carry flag IF a == b ...
170 not = new_bd_ia32_Not(dbg, block, in2);
171 arch_set_irn_register(not, in2_reg);
172 sched_add_before(irn, not);
174 stc = new_bd_ia32_Stc(dbg, block);
175 arch_set_irn_register(stc, &ia32_flags_regs[REG_EFLAGS]);
176 sched_add_before(irn, stc);
178 adc = new_bd_ia32_Adc(dbg, block, noreg, noreg, nomem, not, in1, stc);
179 arch_set_irn_register(adc, out_reg);
180 sched_add_before(irn, adc);
182 set_irn_mode(adc, mode_T);
183 adc_flags = new_r_Proj(adc, mode_Iu, pn_ia32_Adc_flags);
184 arch_set_irn_register(adc_flags, &ia32_flags_regs[REG_EFLAGS]);
186 cmc = new_bd_ia32_Cmc(dbg, block, adc_flags);
187 arch_set_irn_register(cmc, &ia32_flags_regs[REG_EFLAGS]);
188 sched_add_before(irn, cmc);
190 exchange(flags_proj, cmc);
191 if (res_proj != NULL) {
192 set_Proj_pred(res_proj, adc);
193 set_Proj_proj(res_proj, pn_ia32_Adc_res);
200 set_irn_mode(res, get_irn_mode(irn));
202 SET_IA32_ORIG_NODE(res, irn);
204 /* remove the old sub */
208 DBG_OPT_SUB2NEGADD(irn, res);
211 static inline int need_constraint_copy(ir_node *irn)
213 /* TODO this should be determined from the node specification */
214 switch (get_ia32_irn_opcode(irn)) {
215 case iro_ia32_IMul: {
216 /* the 3 operand form of IMul needs no constraint copy */
217 ir_node *right = get_irn_n(irn, n_ia32_IMul_right);
218 return !is_ia32_Immediate(right);
222 case iro_ia32_Conv_I2I:
223 case iro_ia32_Conv_I2I8Bit:
224 case iro_ia32_CMovcc:
233 * Returns the index of the "same" register.
234 * On the x86, we should have only one.
236 static int get_first_same(const arch_register_req_t* req)
238 const unsigned other = req->other_same;
241 for (i = 0; i < 32; ++i) {
242 if (other & (1U << i)) return i;
244 assert(! "same position not found");
248 static inline bool is_unknown_reg(const arch_register_t *reg)
250 if (reg == &ia32_gp_regs[REG_GP_UKNWN]
251 || reg == &ia32_xmm_regs[REG_XMM_UKNWN]
252 || reg == &ia32_vfp_regs[REG_VFP_UKNWN])
259 * Insert copies for all ia32 nodes where the should_be_same requirement
261 * Transform Sub into Neg -- Add if IN2 == OUT
263 static void assure_should_be_same_requirements(ir_node *node)
265 const arch_register_t *out_reg, *in_reg;
267 ir_node *in_node, *block;
269 n_res = arch_irn_get_n_outs(node);
270 block = get_nodes_block(node);
272 /* check all OUT requirements, if there is a should_be_same */
273 for (i = 0; i < n_res; i++) {
280 ir_node *uses_out_reg;
281 const arch_register_req_t *req = arch_get_out_register_req(node, i);
282 const arch_register_class_t *cls;
283 int uses_out_reg_pos;
285 if (!arch_register_req_is(req, should_be_same))
288 same_pos = get_first_same(req);
290 /* get in and out register */
291 out_reg = arch_irn_get_register(node, i);
292 in_node = get_irn_n(node, same_pos);
293 in_reg = arch_get_irn_register(in_node);
295 /* requirement already fulfilled? */
296 if (in_reg == out_reg)
298 /* unknowns can be changed to any register we want on emitting */
299 if (is_unknown_reg(in_reg))
301 cls = arch_register_get_class(in_reg);
302 assert(cls == arch_register_get_class(out_reg));
304 /* check if any other input operands uses the out register */
305 arity = get_irn_arity(node);
307 uses_out_reg_pos = -1;
308 for (i2 = 0; i2 < arity; ++i2) {
309 ir_node *in = get_irn_n(node, i2);
310 const arch_register_t *in_reg;
312 if (!mode_is_data(get_irn_mode(in)))
315 in_reg = arch_get_irn_register(in);
317 if (in_reg != out_reg)
320 if (uses_out_reg != NULL && in != uses_out_reg) {
321 panic("invalid register allocation");
324 if (uses_out_reg_pos >= 0)
325 uses_out_reg_pos = -1; /* multiple inputs... */
327 uses_out_reg_pos = i2;
330 /* no-one else is using the out reg, we can simply copy it
331 * (the register can't be live since the operation will override it
333 if (uses_out_reg == NULL) {
334 ir_node *copy = be_new_Copy(cls, block, in_node);
335 DBG_OPT_2ADDRCPY(copy);
337 /* destination is the out register */
338 arch_set_irn_register(copy, out_reg);
340 /* insert copy before the node into the schedule */
341 sched_add_before(node, copy);
344 set_irn_n(node, same_pos, copy);
347 "created copy %+F for should be same argument at input %d of %+F\n",
348 copy, same_pos, node));
352 /* for commutative nodes we can simply swap the left/right */
353 if (uses_out_reg_pos == n_ia32_binary_right && is_ia32_commutative(node)) {
354 ia32_swap_left_right(node);
356 "swapped left/right input of %+F to resolve should be same constraint\n",
362 ir_fprintf(stderr, "Note: need perm to resolve should_be_same constraint at %+F (this is unsafe and should not happen in theory...)\n", node);
364 /* the out reg is used as node input: we need to permutate our input
365 * and the other (this is allowed, since the other node can't be live
366 * after! the operation as we will override the register. */
368 in[1] = uses_out_reg;
369 perm = be_new_Perm(cls, block, 2, in);
371 perm_proj0 = new_r_Proj(perm, get_irn_mode(in[0]), 0);
372 perm_proj1 = new_r_Proj(perm, get_irn_mode(in[1]), 1);
374 arch_set_irn_register(perm_proj0, out_reg);
375 arch_set_irn_register(perm_proj1, in_reg);
377 sched_add_before(node, perm);
380 "created perm %+F for should be same argument at input %d of %+F (need permutate with %+F)\n",
381 perm, same_pos, node, uses_out_reg));
383 /* use the perm results */
384 for (i2 = 0; i2 < arity; ++i2) {
385 ir_node *in = get_irn_n(node, i2);
388 set_irn_n(node, i2, perm_proj0);
389 } else if (in == uses_out_reg) {
390 set_irn_n(node, i2, perm_proj1);
398 * We have a source address mode node with base or index register equal to
399 * result register and unfulfilled should_be_same requirement. The constraint
400 * handler will insert a copy from the remaining input operand to the result
401 * register -> base or index is broken then.
402 * Solution: Turn back this address mode into explicit Load + Operation.
404 static void fix_am_source(ir_node *irn)
408 /* check only ia32 nodes with source address mode */
409 if (!is_ia32_irn(irn) || get_ia32_op_type(irn) != ia32_AddrModeS)
411 /* only need to fix binary operations */
412 if (get_ia32_am_support(irn) != ia32_am_binary)
415 n_res = arch_irn_get_n_outs(irn);
417 for (i = 0; i < n_res; i++) {
418 const arch_register_req_t *req = arch_get_out_register_req(irn, i);
419 const arch_register_t *out_reg;
422 const arch_register_t *same_reg;
425 if (!arch_register_req_is(req, should_be_same))
428 /* get in and out register */
429 out_reg = arch_irn_get_register(irn, i);
430 same_pos = get_first_same(req);
431 same_node = get_irn_n(irn, same_pos);
432 same_reg = arch_get_irn_register(same_node);
434 /* should_be same constraint is fullfilled, nothing to do */
435 if (out_reg == same_reg)
438 /* we only need to do something if the out reg is the same as base
440 if (out_reg != arch_get_irn_register(get_irn_n(irn, n_ia32_base)) &&
441 out_reg != arch_get_irn_register(get_irn_n(irn, n_ia32_index)))
444 load_res = turn_back_am(irn);
445 arch_set_irn_register(load_res, out_reg);
448 "irg %+F: build back AM source for node %+F, inserted load %+F\n",
449 get_irn_irg(irn), irn, get_Proj_pred(load_res)));
455 * Block walker: finishes a block
457 static void ia32_finish_irg_walker(ir_node *block, void *env)
459 ia32_code_gen_t *cg = env;
462 /* first: turn back AM source if necessary */
463 for (irn = sched_first(block); ! sched_is_end(irn); irn = next) {
464 next = sched_next(irn);
468 for (irn = sched_first(block); ! sched_is_end(irn); irn = next) {
469 next = sched_next(irn);
471 /* check if there is a sub which need to be transformed */
472 if (is_ia32_Sub(irn) || is_ia32_xSub(irn)) {
473 ia32_transform_sub_to_neg_add(irn, cg);
477 /* second: insert copies and finish irg */
478 for (irn = sched_first(block); ! sched_is_end(irn); irn = next) {
479 next = sched_next(irn);
480 if (is_ia32_irn(irn)) {
481 /* some nodes are just a bit less efficient, but need no fixing if the
482 * should be same requirement is not fulfilled */
483 if (need_constraint_copy(irn))
484 assure_should_be_same_requirements(irn);
490 * Block walker: pushes all blocks on a wait queue
492 static void ia32_push_on_queue_walker(ir_node *block, void *env)
495 waitq_put(wq, block);
500 * Add Copy nodes for not fulfilled should_be_equal constraints
502 void ia32_finish_irg(ir_graph *irg, ia32_code_gen_t *cg)
504 waitq *wq = new_waitq();
506 /* Push the blocks on the waitq because ia32_finish_irg_walker starts more walks ... */
507 irg_block_walk_graph(irg, NULL, ia32_push_on_queue_walker, wq);
509 while (! waitq_empty(wq)) {
510 ir_node *block = waitq_get(wq);
511 ia32_finish_irg_walker(block, cg);
516 void ia32_init_finish(void)
518 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.finish");