2 * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This file implements functions to finalize the irg for emit.
23 * @author Christian Wuerdig
39 #include "../bearch_t.h"
40 #include "../besched_t.h"
41 #include "../benode_t.h"
43 #include "bearch_ia32_t.h"
44 #include "ia32_finish.h"
45 #include "ia32_new_nodes.h"
46 #include "ia32_map_regs.h"
47 #include "ia32_transform.h"
48 #include "ia32_dbg_stat.h"
49 #include "ia32_optimize.h"
50 #include "gen_ia32_regalloc_if.h"
52 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
55 * Transforms a Sub or xSub into Neg--Add iff OUT_REG == SRC2_REG.
56 * THIS FUNCTIONS MUST BE CALLED AFTER REGISTER ALLOCATION.
58 static void ia32_transform_sub_to_neg_add(ir_node *irn, ia32_code_gen_t *cg) {
60 ir_node *in1, *in2, *noreg, *nomem, *res;
61 ir_node *noreg_fp, *block;
63 const arch_register_t *in1_reg, *in2_reg, *out_reg;
65 /* fix_am will solve this for AddressMode variants */
66 if(get_ia32_op_type(irn) != ia32_Normal)
69 noreg = ia32_new_NoReg_gp(cg);
70 noreg_fp = ia32_new_NoReg_xmm(cg);
71 nomem = new_rd_NoMem(cg->irg);
72 in1 = get_irn_n(irn, n_ia32_binary_left);
73 in2 = get_irn_n(irn, n_ia32_binary_right);
74 in1_reg = arch_get_irn_register(cg->arch_env, in1);
75 in2_reg = arch_get_irn_register(cg->arch_env, in2);
76 out_reg = get_ia32_out_reg(irn, 0);
79 block = get_nodes_block(irn);
81 /* in case of sub and OUT == SRC2 we can transform the sequence into neg src2 -- add */
82 if (out_reg != in2_reg)
85 dbg = get_irn_dbg_info(irn);
87 /* generate the neg src2 */
88 if(is_ia32_xSub(irn)) {
91 ir_mode *op_mode = get_ia32_ls_mode(irn);
93 assert(get_irn_mode(irn) != mode_T);
95 res = new_rd_ia32_xXor(dbg, irg, block, noreg, noreg, nomem, in2, noreg_fp);
96 size = get_mode_size_bits(op_mode);
97 entity = ia32_gen_fp_known_const(size == 32 ? ia32_SSIGN : ia32_DSIGN);
98 set_ia32_am_sc(res, entity);
99 set_ia32_op_type(res, ia32_AddrModeS);
100 set_ia32_ls_mode(res, op_mode);
102 arch_set_irn_register(cg->arch_env, res, in2_reg);
104 /* add to schedule */
105 sched_add_before(irn, res);
107 /* generate the add */
108 res = new_rd_ia32_xAdd(dbg, irg, block, noreg, noreg, nomem, res, in1);
109 set_ia32_am_support(res, ia32_am_Source, ia32_am_binary);
110 set_ia32_ls_mode(res, get_ia32_ls_mode(irn));
112 /* exchange the add and the sub */
113 edges_reroute(irn, res, irg);
115 /* add to schedule */
116 sched_add_before(irn, res);
118 ir_node *res_proj = NULL;
119 ir_node *flags_proj = NULL;
120 const ir_edge_t *edge;
122 if(get_irn_mode(irn) == mode_T) {
123 foreach_out_edge(irn, edge) {
124 ir_node *proj = get_edge_src_irn(edge);
125 long pn = get_Proj_proj(proj);
126 if(pn == pn_ia32_Sub_res) {
127 assert(res_proj == NULL);
130 assert(pn == pn_ia32_Sub_flags);
131 assert(flags_proj == NULL);
137 if (flags_proj == NULL) {
138 res = new_rd_ia32_Neg(dbg, irg, block, in2);
139 arch_set_irn_register(cg->arch_env, res, in2_reg);
141 /* add to schedule */
142 sched_add_before(irn, res);
144 /* generate the add */
145 res = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, nomem, res, in1);
146 arch_set_irn_register(cg->arch_env, res, out_reg);
147 set_ia32_am_support(res, ia32_am_Full, ia32_am_binary);
148 set_ia32_commutative(res);
150 /* exchange the add and the sub */
151 edges_reroute(irn, res, irg);
153 /* add to schedule */
154 sched_add_before(irn, res);
156 ir_node *stc, *cmc, *not, *adc;
159 /* ARG, the above technique does NOT set the flags right */
160 not = new_rd_ia32_Not(dbg, irg, block, in2);
161 arch_set_irn_register(cg->arch_env, not, in2_reg);
162 sched_add_before(irn, not);
164 stc = new_rd_ia32_Stc(dbg, irg, block);
165 arch_set_irn_register(cg->arch_env, res,
166 &ia32_flags_regs[REG_EFLAGS]);
168 /* generate the adc */
169 adc = new_rd_ia32_Adc(dbg, irg, block, noreg, noreg, nomem, not,
171 arch_set_irn_register(cg->arch_env, adc, out_reg);
172 sched_add_before(irn, adc);
174 adc_flags = new_r_Proj(irg, block, res, mode_Iu, pn_ia32_Adc_flags);
176 cmc = new_rd_ia32_Cmc(dbg, irg, block, adc_flags);
177 sched_add_before(irn, cmc);
179 exchange(flags_proj, cmc);
180 if(res_proj != NULL) {
181 set_Proj_pred(res_proj, adc);
182 set_Proj_proj(res_proj, pn_ia32_Adc_res);
189 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(cg, irn));
191 /* remove the old sub */
195 DBG_OPT_SUB2NEGADD(irn, res);
198 static INLINE int need_constraint_copy(ir_node *irn) {
199 /* the 3 operand form of IMul needs no constraint copy */
200 if(is_ia32_IMul(irn)) {
201 ir_node *right = get_irn_n(irn, n_ia32_IMul_right);
202 if(is_ia32_Immediate(right))
206 return ! is_ia32_Lea(irn) &&
207 ! is_ia32_Conv_I2I(irn) &&
208 ! is_ia32_Conv_I2I8Bit(irn) &&
212 static int get_first_same(const arch_register_req_t* req)
214 const unsigned other = req->other_same;
218 if (other & (1U << i)) return i;
223 * Insert copies for all ia32 nodes where the should_be_same requirement
225 * Transform Sub into Neg -- Add if IN2 == OUT
227 static void assure_should_be_same_requirements(ia32_code_gen_t *cg,
230 ir_graph *irg = cg->irg;
231 const arch_env_t *arch_env = cg->arch_env;
232 const arch_register_req_t **reqs;
233 const arch_register_t *out_reg, *in_reg;
235 ir_node *in_node, *block;
236 ia32_op_type_t op_tp;
238 if(!is_ia32_irn(node))
241 /* some nodes are just a bit less efficient, but need no fixing if the
242 * should be same requirement is not fulfilled */
243 if(!need_constraint_copy(node))
246 op_tp = get_ia32_op_type(node);
247 reqs = get_ia32_out_req_all(node);
248 n_res = get_ia32_n_res(node);
249 block = get_nodes_block(node);
251 /* check all OUT requirements, if there is a should_be_same */
252 for (i = 0; i < n_res; i++) {
259 ir_node *uses_out_reg;
260 const arch_register_req_t *req = reqs[i];
261 const arch_register_class_t *class;
262 int uses_out_reg_pos;
264 if (!arch_register_req_is(req, should_be_same))
267 same_pos = get_first_same(req);
269 /* get in and out register */
270 out_reg = get_ia32_out_reg(node, i);
271 in_node = get_irn_n(node, same_pos);
272 in_reg = arch_get_irn_register(arch_env, in_node);
274 /* requirement already fulfilled? */
275 if (in_reg == out_reg)
277 /* unknowns can be changed to any register we want on emitting */
278 if (is_unknown_reg(in_reg))
280 class = arch_register_get_class(in_reg);
281 assert(class == arch_register_get_class(out_reg));
283 /* check if any other input operands uses the out register */
284 arity = get_irn_arity(node);
286 uses_out_reg_pos = -1;
287 for(i2 = 0; i2 < arity; ++i2) {
288 ir_node *in = get_irn_n(node, i2);
289 const arch_register_t *in_reg;
291 if(!mode_is_data(get_irn_mode(in)))
294 in_reg = arch_get_irn_register(arch_env, in);
296 if(in_reg != out_reg)
299 if(uses_out_reg != NULL && in != uses_out_reg) {
300 panic("invalid register allocation");
303 if(uses_out_reg_pos >= 0)
304 uses_out_reg_pos = -1; /* multiple inputs... */
306 uses_out_reg_pos = i2;
309 /* no-one else is using the out reg, we can simply copy it
310 * (the register can't be live since the operation will override it
312 if(uses_out_reg == NULL) {
313 ir_node *copy = be_new_Copy(class, irg, block, in_node);
314 DBG_OPT_2ADDRCPY(copy);
316 /* destination is the out register */
317 arch_set_irn_register(arch_env, copy, out_reg);
319 /* insert copy before the node into the schedule */
320 sched_add_before(node, copy);
323 set_irn_n(node, same_pos, copy);
325 DBG((dbg, LEVEL_1, "created copy %+F for should be same argument "
326 "at input %d of %+F\n", copy, same_pos, node));
330 /* for commutative nodes we can simply swap the left/right */
331 if(is_ia32_commutative(node) && uses_out_reg_pos == n_ia32_binary_right) {
332 ia32_swap_left_right(node);
333 DBG((dbg, LEVEL_1, "swapped left/right input of %+F to resolve "
334 "should be same constraint\n", node));
339 ir_fprintf(stderr, "Note: need perm to resolve should_be_same constraint at %+F (this is unsafe and should not happen in theory...)\n", node);
341 /* the out reg is used as node input: we need to permutate our input
342 * and the other (this is allowed, since the other node can't be live
343 * after! the operation as we will override the register. */
345 in[1] = uses_out_reg;
346 perm = be_new_Perm(class, irg, block, 2, in);
348 perm_proj0 = new_r_Proj(irg, block, perm, get_irn_mode(in[0]), 0);
349 perm_proj1 = new_r_Proj(irg, block, perm, get_irn_mode(in[1]), 1);
351 arch_set_irn_register(arch_env, perm_proj0, out_reg);
352 arch_set_irn_register(arch_env, perm_proj1, in_reg);
354 sched_add_before(node, perm);
356 DBG((dbg, LEVEL_1, "created perm %+F for should be same argument "
357 "at input %d of %+F (need permutate with %+F)\n", perm, same_pos,
358 node, uses_out_reg));
360 /* use the perm results */
361 for(i2 = 0; i2 < arity; ++i2) {
362 ir_node *in = get_irn_n(node, i2);
365 set_irn_n(node, i2, perm_proj0);
366 } else if(in == uses_out_reg) {
367 set_irn_n(node, i2, perm_proj1);
375 * We have a source address mode node with base or index register equal to
376 * result register and unfulfilled should_be_same requirement. The constraint
377 * handler will insert a copy from the remaining input operand to the result
378 * register -> base or index is broken then.
379 * Solution: Turn back this address mode into explicit Load + Operation.
381 static void fix_am_source(ir_node *irn, void *env) {
382 ia32_code_gen_t *cg = env;
383 const arch_env_t *arch_env = cg->arch_env;
387 const arch_register_t *reg_base;
388 const arch_register_t *reg_index;
389 const arch_register_req_t **reqs;
392 /* check only ia32 nodes with source address mode */
393 if (! is_ia32_irn(irn) || get_ia32_op_type(irn) != ia32_AddrModeS)
395 /* only need to fix binary operations */
396 if (get_ia32_am_arity(irn) != ia32_am_binary)
399 base = get_irn_n(irn, 0);
400 index = get_irn_n(irn, 1);
402 reg_base = arch_get_irn_register(arch_env, base);
403 reg_index = arch_get_irn_register(arch_env, index);
404 reqs = get_ia32_out_req_all(irn);
406 noreg = ia32_new_NoReg_gp(cg);
408 n_res = get_ia32_n_res(irn);
410 for (i = 0; i < n_res; i++) {
411 if (arch_register_req_is(reqs[i], should_be_same)) {
412 /* get in and out register */
413 const arch_register_t *out_reg = get_ia32_out_reg(irn, i);
414 int same_pos = get_first_same(reqs[i]);
415 ir_node *same_node = get_irn_n(irn, same_pos);
416 const arch_register_t *same_reg
417 = arch_get_irn_register(arch_env, same_node);
418 const arch_register_class_t *same_cls;
419 ir_graph *irg = cg->irg;
420 dbg_info *dbgi = get_irn_dbg_info(irn);
421 ir_node *block = get_nodes_block(irn);
428 /* should_be same constraint is fullfilled, nothing to do */
429 if(out_reg == same_reg)
432 /* we only need to do something if the out reg is the same as base
434 if (out_reg != reg_base && out_reg != reg_index)
437 /* turn back address mode */
438 same_cls = arch_register_get_class(same_reg);
439 mem = get_irn_n(irn, n_ia32_mem);
440 assert(get_irn_mode(mem) == mode_M);
441 if (same_cls == &ia32_reg_classes[CLASS_ia32_gp]) {
442 load = new_rd_ia32_Load(dbgi, irg, block, base, index, mem);
443 pnres = pn_ia32_Load_res;
445 } else if (same_cls == &ia32_reg_classes[CLASS_ia32_xmm]) {
446 load = new_rd_ia32_xLoad(dbgi, irg, block, base, index, mem,
447 get_ia32_ls_mode(irn));
448 pnres = pn_ia32_xLoad_res;
451 panic("cannot turn back address mode for this register class");
454 /* copy address mode information to load */
455 set_ia32_op_type(load, ia32_AddrModeS);
456 ia32_copy_am_attrs(load, irn);
458 /* insert the load into schedule */
459 sched_add_before(irn, load);
461 DBG((dbg, LEVEL_3, "irg %+F: build back AM source for node %+F, inserted load %+F\n", cg->irg, irn, load));
463 load_res = new_r_Proj(cg->irg, block, load, proj_mode, pnres);
464 arch_set_irn_register(cg->arch_env, load_res, out_reg);
466 /* set the new input operand */
467 set_irn_n(irn, n_ia32_binary_right, load_res);
468 if(get_irn_mode(irn) == mode_T) {
469 const ir_edge_t *edge, *next;
470 foreach_out_edge_safe(irn, edge, next) {
471 ir_node *node = get_edge_src_irn(edge);
472 int pn = get_Proj_proj(node);
477 set_Proj_pred(node, load);
480 set_irn_mode(irn, mode_Iu);
483 /* this is a normal node now */
484 set_irn_n(irn, n_ia32_base, noreg);
485 set_irn_n(irn, n_ia32_index, noreg);
486 set_ia32_op_type(irn, ia32_Normal);
493 * Block walker: finishes a block
495 static void ia32_finish_irg_walker(ir_node *block, void *env) {
496 ia32_code_gen_t *cg = env;
499 /* first: turn back AM source if necessary */
500 for (irn = sched_first(block); ! sched_is_end(irn); irn = next) {
501 next = sched_next(irn);
502 fix_am_source(irn, env);
505 for (irn = sched_first(block); ! sched_is_end(irn); irn = next) {
506 ia32_code_gen_t *cg = env;
508 next = sched_next(irn);
510 /* check if there is a sub which need to be transformed */
511 if (is_ia32_Sub(irn) || is_ia32_xSub(irn)) {
512 ia32_transform_sub_to_neg_add(irn, cg);
516 /* second: insert copies and finish irg */
517 for (irn = sched_first(block); ! sched_is_end(irn); irn = next) {
518 next = sched_next(irn);
519 assure_should_be_same_requirements(cg, irn);
524 * Block walker: pushes all blocks on a wait queue
526 static void ia32_push_on_queue_walker(ir_node *block, void *env) {
528 waitq_put(wq, block);
533 * Add Copy nodes for not fulfilled should_be_equal constraints
535 void ia32_finish_irg(ir_graph *irg, ia32_code_gen_t *cg) {
536 waitq *wq = new_waitq();
538 /* Push the blocks on the waitq because ia32_finish_irg_walker starts more walks ... */
539 irg_block_walk_graph(irg, NULL, ia32_push_on_queue_walker, wq);
541 while (! waitq_empty(wq)) {
542 ir_node *block = waitq_get(wq);
543 ia32_finish_irg_walker(block, cg);
548 void ia32_init_finish(void)
550 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.finish");