3 * @brief This file implements functions to finalize the irg for emit.
4 * @author Christian Wuerdig
19 #include "../bearch_t.h"
20 #include "../besched_t.h"
21 #include "../benode_t.h"
23 #include "bearch_ia32_t.h"
24 #include "ia32_finish.h"
25 #include "ia32_new_nodes.h"
26 #include "ia32_map_regs.h"
27 #include "ia32_transform.h"
28 #include "ia32_dbg_stat.h"
29 #include "ia32_optimize.h"
30 #include "gen_ia32_regalloc_if.h"
32 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
35 * Transforms a Sub or xSub into Neg--Add iff OUT_REG == SRC2_REG.
36 * THIS FUNCTIONS MUST BE CALLED AFTER REGISTER ALLOCATION.
38 static void ia32_transform_sub_to_neg_add(ir_node *irn, ia32_code_gen_t *cg) {
40 ir_node *in1, *in2, *noreg, *nomem, *res;
41 ir_node *noreg_fp, *block;
42 ir_mode *mode = get_irn_mode(irn);
43 dbg_info *dbg = get_irn_dbg_info(irn);
44 const arch_register_t *in1_reg, *in2_reg, *out_reg, **slots;
47 /* Return if AM node or not a Sub or xSub */
48 if (!(is_ia32_Sub(irn) || is_ia32_xSub(irn)) || get_ia32_op_type(irn) != ia32_Normal)
51 noreg = ia32_new_NoReg_gp(cg);
52 noreg_fp = ia32_new_NoReg_fp(cg);
53 nomem = new_rd_NoMem(cg->irg);
54 in1 = get_irn_n(irn, 2);
55 in2 = get_irn_n(irn, 3);
56 in1_reg = arch_get_irn_register(cg->arch_env, in1);
57 in2_reg = arch_get_irn_register(cg->arch_env, in2);
58 out_reg = get_ia32_out_reg(irn, 0);
61 block = get_nodes_block(irn);
63 /* in case of sub and OUT == SRC2 we can transform the sequence into neg src2 -- add */
64 if (!REGS_ARE_EQUAL(out_reg, in2_reg))
67 /* generate the neg src2 */
68 if(mode_is_float(mode)) {
72 res = new_rd_ia32_xXor(dbg, irg, block, noreg, noreg, in2, noreg_fp, nomem);
73 size = get_mode_size_bits(mode);
74 entity = ia32_gen_fp_known_const(size == 32 ? ia32_SSIGN : ia32_DSIGN);
75 set_ia32_am_sc(res, entity);
76 set_ia32_op_type(res, ia32_AddrModeS);
77 set_ia32_ls_mode(res, get_ia32_ls_mode(irn));
79 res = new_rd_ia32_Neg(dbg, irg, block, noreg, noreg, in2, nomem);
81 arch_set_irn_register(cg->arch_env, res, in2_reg);
84 sched_add_before(irn, res);
86 /* generate the add */
87 if (mode_is_float(mode)) {
88 res = new_rd_ia32_xAdd(dbg, irg, block, noreg, noreg, res, in1, nomem);
89 set_ia32_am_support(res, ia32_am_Source);
90 set_ia32_ls_mode(res, get_ia32_ls_mode(irn));
93 res = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, res, in1, nomem);
94 set_ia32_am_support(res, ia32_am_Full);
95 set_ia32_commutative(res);
98 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(cg, irn));
100 slots = get_ia32_slots(res);
103 /* exchange the add and the sub */
104 edges_reroute(irn, res, irg);
106 /* add to schedule */
107 sched_add_before(irn, res);
109 /* remove the old sub */
111 arity = get_irn_arity(irn);
112 for(i = 0; i < arity; ++i) {
113 set_irn_n(irn, i, new_Bad());
116 DBG_OPT_SUB2NEGADD(irn, res);
120 * Transforms a LEA into an Add if possible
121 * THIS FUNCTIONS MUST BE CALLED AFTER REGISTER ALLOCATION.
123 static void ia32_transform_lea_to_add(ir_node *irn, ia32_code_gen_t *cg) {
124 ia32_am_flavour_t am_flav;
126 dbg_info *dbg = get_irn_dbg_info(irn);
129 ir_node *nomem, *noreg, *base, *index, *op1, *op2;
132 const arch_register_t *out_reg, *base_reg, *index_reg;
135 if (! is_ia32_Lea(irn))
138 am_flav = get_ia32_am_flavour(irn);
140 /* mustn't have a symconst */
141 if (get_ia32_am_sc(irn) != NULL || get_ia32_frame_ent(irn) != NULL)
144 /* only some LEAs can be transformed to an Add */
145 if (am_flav != ia32_am_B && am_flav != ia32_am_OB && am_flav != ia32_am_OI && am_flav != ia32_am_BI)
148 noreg = ia32_new_NoReg_gp(cg);
149 nomem = new_rd_NoMem(cg->irg);
152 base = get_irn_n(irn, 0);
153 index = get_irn_n(irn,1);
155 if (am_flav & ia32_O) {
156 offs = get_ia32_am_offs_int(irn);
159 out_reg = arch_get_irn_register(cg->arch_env, irn);
160 base_reg = arch_get_irn_register(cg->arch_env, base);
161 index_reg = arch_get_irn_register(cg->arch_env, index);
164 block = get_nodes_block(irn);
166 switch(get_ia32_am_flavour(irn)) {
168 /* out register must be same as base register */
169 if (! REGS_ARE_EQUAL(out_reg, base_reg))
175 /* out register must be same as base register */
176 if (! REGS_ARE_EQUAL(out_reg, base_reg))
183 /* out register must be same as index register */
184 if (! REGS_ARE_EQUAL(out_reg, index_reg))
191 /* out register must be same as one in register */
192 if (REGS_ARE_EQUAL(out_reg, base_reg)) {
196 else if (REGS_ARE_EQUAL(out_reg, index_reg)) {
201 /* in registers a different from out -> no Add possible */
208 res = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, op1, op2, nomem);
209 arch_set_irn_register(cg->arch_env, res, out_reg);
210 set_ia32_op_type(res, ia32_Normal);
211 set_ia32_commutative(res);
214 tarval *tv = new_tarval_from_long(offs, mode_Iu);
215 set_ia32_Immop_tarval(res, tv);
218 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(cg, irn));
220 /* add Add to schedule */
221 sched_add_before(irn, res);
223 DBG_OPT_LEA2ADD(irn, res);
225 /* remove the old LEA */
228 /* exchange the Add and the LEA */
232 static INLINE int need_constraint_copy(ir_node *irn) {
234 ! is_ia32_Lea(irn) && \
235 ! is_ia32_Conv_I2I(irn) && \
236 ! is_ia32_Conv_I2I8Bit(irn) && \
237 ! is_ia32_CmpCMov(irn) && \
238 ! is_ia32_PsiCondCMov(irn) && \
239 ! is_ia32_CmpSet(irn);
243 * Insert copies for all ia32 nodes where the should_be_same requirement
245 * Transform Sub into Neg -- Add if IN2 == OUT
247 static void ia32_finish_node(ir_node *irn, void *env) {
248 ia32_code_gen_t *cg = env;
249 const arch_register_req_t **reqs;
250 const arch_register_t *out_reg, *in_reg, *in2_reg;
252 ir_node *copy, *in_node, *block, *in2_node;
253 ia32_op_type_t op_tp;
255 if (is_ia32_irn(irn)) {
256 /* AM Dest nodes don't produce any values */
257 op_tp = get_ia32_op_type(irn);
258 if (op_tp == ia32_AddrModeD)
261 reqs = get_ia32_out_req_all(irn);
262 n_res = get_ia32_n_res(irn);
263 block = get_nodes_block(irn);
265 /* check all OUT requirements, if there is a should_be_same */
266 if ((op_tp == ia32_Normal || op_tp == ia32_AddrModeS) && need_constraint_copy(irn))
268 for (i = 0; i < n_res; i++) {
269 if (arch_register_req_is(reqs[i], should_be_same)) {
270 int same_pos = reqs[i]->other_same;
272 /* get in and out register */
273 out_reg = get_ia32_out_reg(irn, i);
274 in_node = get_irn_n(irn, same_pos);
275 in_reg = arch_get_irn_register(cg->arch_env, in_node);
277 /* don't copy ignore nodes */
278 if (arch_irn_is(cg->arch_env, in_node, ignore) && is_Proj(in_node))
281 /* check if in and out register are equal */
282 if (! REGS_ARE_EQUAL(out_reg, in_reg)) {
283 /* in case of a commutative op: just exchange the in's */
284 /* beware: the current op could be everything, so test for ia32 */
285 /* commutativity first before getting the second in */
286 if (is_ia32_commutative(irn)) {
287 in2_node = get_irn_n(irn, same_pos ^ 1);
288 in2_reg = arch_get_irn_register(cg->arch_env, in2_node);
290 if (REGS_ARE_EQUAL(out_reg, in2_reg)) {
291 set_irn_n(irn, same_pos, in2_node);
292 set_irn_n(irn, same_pos ^ 1, in_node);
299 DBG((dbg, LEVEL_1, "inserting copy for %+F in_pos %d\n", irn, same_pos));
300 /* create copy from in register */
301 copy = be_new_Copy(arch_register_get_class(in_reg), cg->irg, block, in_node);
303 DBG_OPT_2ADDRCPY(copy);
305 /* destination is the out register */
306 arch_set_irn_register(cg->arch_env, copy, out_reg);
308 /* insert copy before the node into the schedule */
309 sched_add_before(irn, copy);
312 set_irn_n(irn, same_pos, copy);
319 /* check xCmp: try to avoid unordered cmp */
320 if ((is_ia32_xCmp(irn) || is_ia32_xCmpCMov(irn) || is_ia32_xCmpSet(irn)) &&
321 op_tp == ia32_Normal &&
322 ! is_ia32_ImmConst(irn) && ! is_ia32_ImmSymConst(irn))
324 long pnc = get_ia32_pncode(irn);
326 if (pnc & pn_Cmp_Uo) {
328 int idx1 = 2, idx2 = 3;
330 if (is_ia32_xCmpCMov(irn)) {
335 tmp = get_irn_n(irn, idx1);
336 set_irn_n(irn, idx1, get_irn_n(irn, idx2));
337 set_irn_n(irn, idx2, tmp);
339 set_ia32_pncode(irn, get_negated_pnc(pnc, mode_E));
348 * We have a source address mode node with base or index register equal to
349 * result register. The constraint handler will insert a copy from the
350 * remaining input operand to the result register -> base or index is
352 * Solution: Turn back this address mode into explicit Load + Operation.
354 static void fix_am_source(ir_node *irn, void *env) {
355 ia32_code_gen_t *cg = env;
356 ir_node *base, *index, *noreg;
357 const arch_register_t *reg_base, *reg_index;
358 const arch_register_req_t **reqs;
361 /* check only ia32 nodes with source address mode */
362 if (! is_ia32_irn(irn) || get_ia32_op_type(irn) != ia32_AddrModeS)
364 /* no need to fix unary operations */
365 if (get_irn_arity(irn) == 4)
368 base = get_irn_n(irn, 0);
369 index = get_irn_n(irn, 1);
371 reg_base = arch_get_irn_register(cg->arch_env, base);
372 reg_index = arch_get_irn_register(cg->arch_env, index);
373 reqs = get_ia32_out_req_all(irn);
375 noreg = ia32_new_NoReg_gp(cg);
377 n_res = get_ia32_n_res(irn);
379 for (i = 0; i < n_res; i++) {
380 if (arch_register_req_is(reqs[i], should_be_same)) {
381 /* get in and out register */
382 const arch_register_t *out_reg = get_ia32_out_reg(irn, i);
383 int same_pos = reqs[i]->other_same;
386 there is a constraint for the remaining operand
387 and the result register is equal to base or index register
390 (REGS_ARE_EQUAL(out_reg, reg_base) || REGS_ARE_EQUAL(out_reg, reg_index)))
392 /* turn back address mode */
393 ir_node *in_node = get_irn_n(irn, 2);
394 const arch_register_t *in_reg = arch_get_irn_register(cg->arch_env, in_node);
395 ir_node *block = get_nodes_block(irn);
396 ir_mode *ls_mode = get_ia32_ls_mode(irn);
400 if (arch_register_get_class(in_reg) == &ia32_reg_classes[CLASS_ia32_gp]) {
401 load = new_rd_ia32_Load(NULL, cg->irg, block, base, index, get_irn_n(irn, 4));
402 pnres = pn_ia32_Load_res;
404 else if (arch_register_get_class(in_reg) == &ia32_reg_classes[CLASS_ia32_xmm]) {
405 load = new_rd_ia32_xLoad(NULL, cg->irg, block, base, index, get_irn_n(irn, 4));
406 pnres = pn_ia32_xLoad_res;
409 panic("cannot turn back address mode for this register class");
412 /* copy address mode information to load */
413 set_ia32_ls_mode(load, ls_mode);
414 set_ia32_am_flavour(load, get_ia32_am_flavour(irn));
415 set_ia32_op_type(load, ia32_AddrModeS);
416 set_ia32_am_support(load, ia32_am_Source);
417 set_ia32_am_scale(load, get_ia32_am_scale(irn));
418 set_ia32_am_sc(load, get_ia32_am_sc(irn));
419 add_ia32_am_offs_int(load, get_ia32_am_offs_int(irn));
420 set_ia32_frame_ent(load, get_ia32_frame_ent(irn));
422 if (is_ia32_use_frame(irn))
423 set_ia32_use_frame(load);
425 /* insert the load into schedule */
426 sched_add_before(irn, load);
428 DBG((dbg, LEVEL_3, "irg %+F: build back AM source for node %+F, inserted load %+F\n", cg->irg, irn, load));
430 load = new_r_Proj(cg->irg, block, load, ls_mode, pnres);
431 arch_set_irn_register(cg->arch_env, load, out_reg);
433 /* insert the load result proj into schedule */
434 sched_add_before(irn, load);
436 /* set the new input operand */
437 set_irn_n(irn, 3, load);
439 /* this is a normal node now */
440 set_irn_n(irn, 0, noreg);
441 set_irn_n(irn, 1, noreg);
442 set_ia32_op_type(irn, ia32_Normal);
450 static void ia32_finish_irg_walker(ir_node *block, void *env) {
453 /* first: turn back AM source if necessary */
454 for (irn = sched_first(block); ! sched_is_end(irn); irn = next) {
455 next = sched_next(irn);
456 fix_am_source(irn, env);
459 for (irn = sched_first(block); ! sched_is_end(irn); irn = next) {
460 ia32_code_gen_t *cg = env;
462 next = sched_next(irn);
464 /* check if there is a sub which need to be transformed */
465 ia32_transform_sub_to_neg_add(irn, cg);
467 /* transform a LEA into an Add if possible */
468 ia32_transform_lea_to_add(irn, cg);
471 /* second: insert copies and finish irg */
472 for (irn = sched_first(block); ! sched_is_end(irn); irn = next) {
473 next = sched_next(irn);
474 ia32_finish_node(irn, env);
478 static void ia32_push_on_queue_walker(ir_node *block, void *env) {
480 waitq_put(wq, block);
485 * Add Copy nodes for not fulfilled should_be_equal constraints
487 void ia32_finish_irg(ir_graph *irg, ia32_code_gen_t *cg) {
488 waitq *wq = new_waitq();
490 /* Push the blocks on the waitq because ia32_finish_irg_walker starts more walks ... */
491 irg_block_walk_graph(irg, NULL, ia32_push_on_queue_walker, wq);
493 while (! waitq_empty(wq)) {
494 ir_node *block = waitq_get(wq);
495 ia32_finish_irg_walker(block, cg);
500 void ia32_init_finish(void)
502 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.finish");