2 * Copyright (C) 1995-2007 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This file implements functions to finalize the irg for emit.
23 * @author Christian Wuerdig
39 #include "../bearch_t.h"
40 #include "../besched_t.h"
41 #include "../benode_t.h"
43 #include "bearch_ia32_t.h"
44 #include "ia32_finish.h"
45 #include "ia32_new_nodes.h"
46 #include "ia32_map_regs.h"
47 #include "ia32_transform.h"
48 #include "ia32_dbg_stat.h"
49 #include "ia32_optimize.h"
50 #include "gen_ia32_regalloc_if.h"
52 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
55 * Transforms a Sub or xSub into Neg--Add iff OUT_REG == SRC2_REG.
56 * THIS FUNCTIONS MUST BE CALLED AFTER REGISTER ALLOCATION.
58 static void ia32_transform_sub_to_neg_add(ir_node *irn, ia32_code_gen_t *cg) {
60 ir_node *in1, *in2, *noreg, *nomem, *res;
61 ir_node *noreg_fp, *block;
62 ir_mode *mode = get_irn_mode(irn);
63 dbg_info *dbg = get_irn_dbg_info(irn);
64 const arch_register_t *in1_reg, *in2_reg, *out_reg, **slots;
67 /* Return if not a Sub or xSub */
68 if (!is_ia32_Sub(irn) && !is_ia32_xSub(irn))
70 /* fix_am will solve this for AddressMode variants */
71 if(get_ia32_op_type(irn) != ia32_Normal)
74 noreg = ia32_new_NoReg_gp(cg);
75 noreg_fp = ia32_new_NoReg_xmm(cg);
76 nomem = new_rd_NoMem(cg->irg);
77 in1 = get_irn_n(irn, n_ia32_binary_left);
78 in2 = get_irn_n(irn, n_ia32_binary_right);
79 in1_reg = arch_get_irn_register(cg->arch_env, in1);
80 in2_reg = arch_get_irn_register(cg->arch_env, in2);
81 out_reg = get_ia32_out_reg(irn, 0);
83 assert(get_irn_mode(irn) != mode_T);
86 block = get_nodes_block(irn);
88 /* in case of sub and OUT == SRC2 we can transform the sequence into neg src2 -- add */
89 if (out_reg != in2_reg)
92 /* generate the neg src2 */
93 if(mode_is_float(mode)) {
96 ir_mode *op_mode = get_ia32_ls_mode(irn);
98 res = new_rd_ia32_xXor(dbg, irg, block, noreg, noreg, nomem, in2, noreg_fp);
99 size = get_mode_size_bits(op_mode);
100 entity = ia32_gen_fp_known_const(size == 32 ? ia32_SSIGN : ia32_DSIGN);
101 set_ia32_am_sc(res, entity);
102 set_ia32_op_type(res, ia32_AddrModeS);
103 set_ia32_ls_mode(res, op_mode);
105 res = new_rd_ia32_Neg(dbg, irg, block, in2);
107 arch_set_irn_register(cg->arch_env, res, in2_reg);
109 /* add to schedule */
110 sched_add_before(irn, res);
112 /* generate the add */
113 if (mode_is_float(mode)) {
114 res = new_rd_ia32_xAdd(dbg, irg, block, noreg, noreg, nomem, res, in1);
115 set_ia32_am_support(res, ia32_am_Source, ia32_am_binary);
116 set_ia32_ls_mode(res, get_ia32_ls_mode(irn));
118 res = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, nomem, res, in1);
119 set_ia32_am_support(res, ia32_am_Full, ia32_am_binary);
120 set_ia32_commutative(res);
123 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(cg, irn));
125 slots = get_ia32_slots(res);
128 /* exchange the add and the sub */
129 edges_reroute(irn, res, irg);
131 /* add to schedule */
132 sched_add_before(irn, res);
134 /* remove the old sub */
136 arity = get_irn_arity(irn);
137 for(i = 0; i < arity; ++i) {
138 set_irn_n(irn, i, new_Bad());
141 DBG_OPT_SUB2NEGADD(irn, res);
144 static INLINE int need_constraint_copy(ir_node *irn) {
145 /* the 3 operand form of IMul needs no constraint copy */
146 if(is_ia32_IMul(irn)) {
147 ir_node *right = get_irn_n(irn, n_ia32_IMul_right);
148 if(is_ia32_Immediate(right))
152 return ! is_ia32_Lea(irn) &&
153 ! is_ia32_Conv_I2I(irn) &&
154 ! is_ia32_Conv_I2I8Bit(irn) &&
158 static int get_first_same(const arch_register_req_t* req)
160 const unsigned other = req->other_same;
164 if (other & (1U << i)) return i;
169 * Insert copies for all ia32 nodes where the should_be_same requirement
171 * Transform Sub into Neg -- Add if IN2 == OUT
173 static void assure_should_be_same_requirements(ia32_code_gen_t *cg,
176 ir_graph *irg = cg->irg;
177 const arch_env_t *arch_env = cg->arch_env;
178 const arch_register_req_t **reqs;
179 const arch_register_t *out_reg, *in_reg;
181 ir_node *in_node, *block;
182 ia32_op_type_t op_tp;
184 if(!is_ia32_irn(node))
187 /* some nodes are just a bit less efficient, but need no fixing if the
188 * should be same requirement is not fulfilled */
189 if(!need_constraint_copy(node))
192 op_tp = get_ia32_op_type(node);
193 reqs = get_ia32_out_req_all(node);
194 n_res = get_ia32_n_res(node);
195 block = get_nodes_block(node);
197 /* check all OUT requirements, if there is a should_be_same */
198 for (i = 0; i < n_res; i++) {
205 ir_node *uses_out_reg;
206 const arch_register_req_t *req = reqs[i];
207 const arch_register_class_t *class;
208 int uses_out_reg_pos;
210 if (!arch_register_req_is(req, should_be_same))
213 same_pos = get_first_same(req);
215 /* get in and out register */
216 out_reg = get_ia32_out_reg(node, i);
217 in_node = get_irn_n(node, same_pos);
218 in_reg = arch_get_irn_register(arch_env, in_node);
220 /* requirement already fulfilled? */
221 if (in_reg == out_reg)
223 /* unknowns can be changed to any register we want on emitting */
224 if (is_unknown_reg(in_reg))
226 class = arch_register_get_class(in_reg);
227 assert(class == arch_register_get_class(out_reg));
229 /* check if any other input operands uses the out register */
230 arity = get_irn_arity(node);
232 uses_out_reg_pos = -1;
233 for(i2 = 0; i2 < arity; ++i2) {
234 ir_node *in = get_irn_n(node, i2);
235 const arch_register_t *in_reg;
237 if(!mode_is_data(get_irn_mode(in)))
240 in_reg = arch_get_irn_register(arch_env, in);
242 if(in_reg != out_reg)
245 if(uses_out_reg != NULL && in != uses_out_reg) {
246 panic("invalid register allocation");
249 if(uses_out_reg_pos >= 0)
250 uses_out_reg_pos = -1; /* multiple inputs... */
252 uses_out_reg_pos = i2;
255 /* no-one else is using the out reg, we can simply copy it
256 * (the register can't be live since the operation will override it
258 if(uses_out_reg == NULL) {
259 ir_node *copy = be_new_Copy(class, irg, block, in_node);
260 DBG_OPT_2ADDRCPY(copy);
262 /* destination is the out register */
263 arch_set_irn_register(arch_env, copy, out_reg);
265 /* insert copy before the node into the schedule */
266 sched_add_before(node, copy);
269 set_irn_n(node, same_pos, copy);
271 DBG((dbg, LEVEL_1, "created copy %+F for should be same argument "
272 "at input %d of %+F\n", copy, same_pos, node));
276 /* for commutative nodes we can simply swap the left/right */
277 if(is_ia32_commutative(node) && uses_out_reg_pos == n_ia32_binary_right) {
278 ia32_swap_left_right(node);
279 DBG((dbg, LEVEL_1, "swapped left/right input of %+F to resolve "
280 "should be same constraint\n", node));
285 ir_fprintf(stderr, "Note: need perm to resolve should_be_same constraint at %+F (this is unsafe and should not happen in theory...)\n", node);
287 /* the out reg is used as node input: we need to permutate our input
288 * and the other (this is allowed, since the other node can't be live
289 * after! the operation as we will override the register. */
291 in[1] = uses_out_reg;
292 perm = be_new_Perm(class, irg, block, 2, in);
294 perm_proj0 = new_r_Proj(irg, block, perm, get_irn_mode(in[0]), 0);
295 perm_proj1 = new_r_Proj(irg, block, perm, get_irn_mode(in[1]), 1);
297 arch_set_irn_register(arch_env, perm_proj0, out_reg);
298 arch_set_irn_register(arch_env, perm_proj1, in_reg);
300 sched_add_before(node, perm);
302 DBG((dbg, LEVEL_1, "created perm %+F for should be same argument "
303 "at input %d of %+F (need permutate with %+F)\n", perm, same_pos,
304 node, uses_out_reg));
306 /* use the perm results */
307 for(i2 = 0; i2 < arity; ++i2) {
308 ir_node *in = get_irn_n(node, i2);
311 set_irn_n(node, i2, perm_proj0);
312 } else if(in == uses_out_reg) {
313 set_irn_n(node, i2, perm_proj1);
321 * We have a source address mode node with base or index register equal to
322 * result register and unfulfilled should_be_same requirement. The constraint
323 * handler will insert a copy from the remaining input operand to the result
324 * register -> base or index is broken then.
325 * Solution: Turn back this address mode into explicit Load + Operation.
327 static void fix_am_source(ir_node *irn, void *env) {
328 ia32_code_gen_t *cg = env;
329 const arch_env_t *arch_env = cg->arch_env;
333 const arch_register_t *reg_base;
334 const arch_register_t *reg_index;
335 const arch_register_req_t **reqs;
338 /* check only ia32 nodes with source address mode */
339 if (! is_ia32_irn(irn) || get_ia32_op_type(irn) != ia32_AddrModeS)
341 /* only need to fix binary operations */
342 if (get_ia32_am_arity(irn) != ia32_am_binary)
345 base = get_irn_n(irn, 0);
346 index = get_irn_n(irn, 1);
348 reg_base = arch_get_irn_register(arch_env, base);
349 reg_index = arch_get_irn_register(arch_env, index);
350 reqs = get_ia32_out_req_all(irn);
352 noreg = ia32_new_NoReg_gp(cg);
354 n_res = get_ia32_n_res(irn);
356 for (i = 0; i < n_res; i++) {
357 if (arch_register_req_is(reqs[i], should_be_same)) {
358 /* get in and out register */
359 const arch_register_t *out_reg = get_ia32_out_reg(irn, i);
360 int same_pos = get_first_same(reqs[i]);
361 ir_node *same_node = get_irn_n(irn, same_pos);
362 const arch_register_t *same_reg
363 = arch_get_irn_register(arch_env, same_node);
364 const arch_register_class_t *same_cls;
365 ir_graph *irg = cg->irg;
366 dbg_info *dbgi = get_irn_dbg_info(irn);
367 ir_node *block = get_nodes_block(irn);
374 /* should_be same constraint is fullfilled, nothing to do */
375 if(out_reg == same_reg)
378 /* we only need to do something if the out reg is the same as base
380 if (out_reg != reg_base && out_reg != reg_index)
383 /* turn back address mode */
384 same_cls = arch_register_get_class(same_reg);
385 mem = get_irn_n(irn, n_ia32_mem);
386 assert(get_irn_mode(mem) == mode_M);
387 if (same_cls == &ia32_reg_classes[CLASS_ia32_gp]) {
388 load = new_rd_ia32_Load(dbgi, irg, block, base, index, mem);
389 pnres = pn_ia32_Load_res;
391 } else if (same_cls == &ia32_reg_classes[CLASS_ia32_xmm]) {
392 load = new_rd_ia32_xLoad(dbgi, irg, block, base, index, mem,
393 get_ia32_ls_mode(irn));
394 pnres = pn_ia32_xLoad_res;
397 panic("cannot turn back address mode for this register class");
400 /* copy address mode information to load */
401 set_ia32_op_type(load, ia32_AddrModeS);
402 ia32_copy_am_attrs(load, irn);
404 /* insert the load into schedule */
405 sched_add_before(irn, load);
407 DBG((dbg, LEVEL_3, "irg %+F: build back AM source for node %+F, inserted load %+F\n", cg->irg, irn, load));
409 load_res = new_r_Proj(cg->irg, block, load, proj_mode, pnres);
410 arch_set_irn_register(cg->arch_env, load_res, out_reg);
412 /* set the new input operand */
413 set_irn_n(irn, n_ia32_binary_right, load_res);
414 if(get_irn_mode(irn) == mode_T) {
415 const ir_edge_t *edge, *next;
416 foreach_out_edge_safe(irn, edge, next) {
417 ir_node *node = get_edge_src_irn(edge);
418 int pn = get_Proj_proj(node);
423 set_Proj_pred(node, load);
426 set_irn_mode(irn, mode_Iu);
429 /* this is a normal node now */
430 set_irn_n(irn, n_ia32_base, noreg);
431 set_irn_n(irn, n_ia32_index, noreg);
432 set_ia32_op_type(irn, ia32_Normal);
439 * Block walker: finishes a block
441 static void ia32_finish_irg_walker(ir_node *block, void *env) {
442 ia32_code_gen_t *cg = env;
445 /* first: turn back AM source if necessary */
446 for (irn = sched_first(block); ! sched_is_end(irn); irn = next) {
447 next = sched_next(irn);
448 fix_am_source(irn, env);
451 for (irn = sched_first(block); ! sched_is_end(irn); irn = next) {
452 ia32_code_gen_t *cg = env;
454 next = sched_next(irn);
456 /* check if there is a sub which need to be transformed */
457 ia32_transform_sub_to_neg_add(irn, cg);
460 /* second: insert copies and finish irg */
461 for (irn = sched_first(block); ! sched_is_end(irn); irn = next) {
462 next = sched_next(irn);
463 assure_should_be_same_requirements(cg, irn);
468 * Block walker: pushes all blocks on a wait queue
470 static void ia32_push_on_queue_walker(ir_node *block, void *env) {
472 waitq_put(wq, block);
477 * Add Copy nodes for not fulfilled should_be_equal constraints
479 void ia32_finish_irg(ir_graph *irg, ia32_code_gen_t *cg) {
480 waitq *wq = new_waitq();
482 /* Push the blocks on the waitq because ia32_finish_irg_walker starts more walks ... */
483 irg_block_walk_graph(irg, NULL, ia32_push_on_queue_walker, wq);
485 while (! waitq_empty(wq)) {
486 ir_node *block = waitq_get(wq);
487 ia32_finish_irg_walker(block, cg);
492 void ia32_init_finish(void)
494 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.finish");