2 * This file implements functions to finalize the irg for emit.
3 * @author Christian Wuerdig
13 #include "../bearch.h"
14 #include "../besched_t.h"
15 #include "../benode_t.h"
17 #include "bearch_ia32_t.h"
18 #include "ia32_finish.h"
19 #include "ia32_new_nodes.h"
20 #include "ia32_map_regs.h"
21 #include "ia32_transform.h"
22 #include "ia32_dbg_stat.h"
23 #include "ia32_optimize.h"
24 #include "gen_ia32_regalloc_if.h"
27 * Transforms a Sub or xSub into Neg--Add iff OUT_REG == SRC2_REG.
28 * THIS FUNCTIONS MUST BE CALLED AFTER REGISTER ALLOCATION.
30 static void ia32_transform_sub_to_neg_add(ir_node *irn, ia32_code_gen_t *cg) {
31 ia32_transform_env_t tenv;
32 ir_node *in1, *in2, *noreg, *nomem, *res;
33 const arch_register_t *in1_reg, *in2_reg, *out_reg, **slots;
35 /* Return if AM node or not a Sub or xSub */
36 if (!(is_ia32_Sub(irn) || is_ia32_xSub(irn)) || get_ia32_op_type(irn) != ia32_Normal)
39 noreg = ia32_new_NoReg_gp(cg);
40 nomem = new_rd_NoMem(cg->irg);
41 in1 = get_irn_n(irn, 2);
42 in2 = get_irn_n(irn, 3);
43 in1_reg = arch_get_irn_register(cg->arch_env, in1);
44 in2_reg = arch_get_irn_register(cg->arch_env, in2);
45 out_reg = get_ia32_out_reg(irn, 0);
47 tenv.block = get_nodes_block(irn);
48 tenv.dbg = get_irn_dbg_info(irn);
51 tenv.mode = get_ia32_res_mode(irn);
53 DEBUG_ONLY(tenv.mod = cg->mod;)
55 /* in case of sub and OUT == SRC2 we can transform the sequence into neg src2 -- add */
56 if (REGS_ARE_EQUAL(out_reg, in2_reg)) {
57 /* generate the neg src2 */
58 res = gen_Minus_ex(&tenv, in2);
59 arch_set_irn_register(cg->arch_env, res, in2_reg);
62 sched_add_before(irn, get_Proj_pred(res));
63 sched_add_before(irn, res);
65 /* generate the add */
66 if (mode_is_float(tenv.mode)) {
67 res = new_rd_ia32_xAdd(tenv.dbg, tenv.irg, tenv.block, noreg, noreg, res, in1, nomem);
68 set_ia32_am_support(res, ia32_am_Source);
71 res = new_rd_ia32_Add(tenv.dbg, tenv.irg, tenv.block, noreg, noreg, res, in1, nomem);
72 set_ia32_am_support(res, ia32_am_Full);
73 set_ia32_commutative(res);
75 set_ia32_res_mode(res, tenv.mode);
77 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(tenv.cg, irn));
79 slots = get_ia32_slots(res);
83 sched_add_before(irn, res);
85 /* remove the old sub */
88 DBG_OPT_SUB2NEGADD(irn, res);
90 /* exchange the add and the sub */
96 * Transforms a LEA into an Add if possible
97 * THIS FUNCTIONS MUST BE CALLED AFTER REGISTER ALLOCATION.
99 static void ia32_transform_lea_to_add(ir_node *irn, ia32_code_gen_t *cg) {
100 ia32_am_flavour_t am_flav;
103 ir_node *nomem, *noreg, *base, *index, *op1, *op2;
104 const char *offs = NULL;
105 ia32_transform_env_t tenv;
106 const arch_register_t *out_reg, *base_reg, *index_reg;
107 int imm_tp = ia32_ImmConst;
110 if (! is_ia32_Lea(irn))
113 am_flav = get_ia32_am_flavour(irn);
115 if (get_ia32_am_sc(irn))
118 /* only some LEAs can be transformed to an Add */
119 if (am_flav != ia32_am_B && am_flav != ia32_am_OB && am_flav != ia32_am_OI && am_flav != ia32_am_BI)
122 noreg = ia32_new_NoReg_gp(cg);
123 nomem = new_rd_NoMem(cg->irg);
126 base = get_irn_n(irn, 0);
127 index = get_irn_n(irn,1);
129 if (am_flav & ia32_O) {
130 offs = get_ia32_am_offs(irn);
133 ident *id = get_ia32_am_sc(irn);
136 offs = get_id_str(id);
137 imm_tp = ia32_ImmSymConst;
139 /* offset has a explicit sign -> we need to skip + */
140 else if (offs[0] == '+')
144 out_reg = arch_get_irn_register(cg->arch_env, irn);
145 base_reg = arch_get_irn_register(cg->arch_env, base);
146 index_reg = arch_get_irn_register(cg->arch_env, index);
148 tenv.block = get_nodes_block(irn);
149 tenv.dbg = get_irn_dbg_info(irn);
152 DEBUG_ONLY(tenv.mod = cg->mod;)
153 tenv.mode = get_irn_mode(irn);
156 switch(get_ia32_am_flavour(irn)) {
158 /* out register must be same as base register */
159 if (! REGS_ARE_EQUAL(out_reg, base_reg))
165 /* out register must be same as base register */
166 if (! REGS_ARE_EQUAL(out_reg, base_reg))
173 /* out register must be same as index register */
174 if (! REGS_ARE_EQUAL(out_reg, index_reg))
181 /* out register must be same as one in register */
182 if (REGS_ARE_EQUAL(out_reg, base_reg)) {
186 else if (REGS_ARE_EQUAL(out_reg, index_reg)) {
191 /* in registers a different from out -> no Add possible */
198 res = new_rd_ia32_Add(tenv.dbg, tenv.irg, tenv.block, noreg, noreg, op1, op2, nomem);
199 arch_set_irn_register(cg->arch_env, res, out_reg);
200 set_ia32_op_type(res, ia32_Normal);
201 set_ia32_commutative(res);
202 set_ia32_res_mode(res, tenv.mode);
205 set_ia32_cnst(res, offs);
206 set_ia32_immop_type(res, imm_tp);
209 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(cg, irn));
211 /* add Add to schedule */
212 sched_add_before(irn, res);
214 DBG_OPT_LEA2ADD(irn, res);
216 res = new_rd_Proj(tenv.dbg, tenv.irg, tenv.block, res, tenv.mode, pn_ia32_Add_res);
218 /* add result Proj to schedule */
219 sched_add_before(irn, res);
221 /* remove the old LEA */
224 /* exchange the Add and the LEA */
228 static INLINE int need_constraint_copy(ir_node *irn) {
230 ! is_ia32_Lea(irn) && \
231 ! is_ia32_Conv_I2I(irn) && \
232 ! is_ia32_Conv_I2I8Bit(irn) && \
233 ! is_ia32_CmpCMov(irn) && \
234 ! is_ia32_PsiCondCMov(irn) && \
235 ! is_ia32_CmpSet(irn);
239 * Insert copies for all ia32 nodes where the should_be_same requirement
241 * Transform Sub into Neg -- Add if IN2 == OUT
243 static void ia32_finish_node(ir_node *irn, void *env) {
244 ia32_code_gen_t *cg = env;
245 const ia32_register_req_t **reqs;
246 const arch_register_t *out_reg, *in_reg, *in2_reg;
248 ir_node *copy, *in_node, *block, *in2_node;
249 ia32_op_type_t op_tp;
251 if (is_ia32_irn(irn)) {
252 /* AM Dest nodes don't produce any values */
253 op_tp = get_ia32_op_type(irn);
254 if (op_tp == ia32_AddrModeD)
257 reqs = get_ia32_out_req_all(irn);
258 n_res = get_ia32_n_res(irn);
259 block = get_nodes_block(irn);
261 /* check all OUT requirements, if there is a should_be_same */
262 if ((op_tp == ia32_Normal || op_tp == ia32_AddrModeS) && need_constraint_copy(irn))
264 for (i = 0; i < n_res; i++) {
265 if (arch_register_req_is(&(reqs[i]->req), should_be_same)) {
266 /* get in and out register */
267 out_reg = get_ia32_out_reg(irn, i);
268 in_node = get_irn_n(irn, reqs[i]->same_pos);
269 in_reg = arch_get_irn_register(cg->arch_env, in_node);
271 /* don't copy ignore nodes */
272 if (arch_irn_is(cg->arch_env, in_node, ignore) && is_Proj(in_node))
275 /* check if in and out register are equal */
276 if (! REGS_ARE_EQUAL(out_reg, in_reg)) {
277 /* in case of a commutative op: just exchange the in's */
278 /* beware: the current op could be everything, so test for ia32 */
279 /* commutativity first before getting the second in */
280 if (is_ia32_commutative(irn)) {
281 in2_node = get_irn_n(irn, reqs[i]->same_pos ^ 1);
282 in2_reg = arch_get_irn_register(cg->arch_env, in2_node);
284 if (REGS_ARE_EQUAL(out_reg, in2_reg)) {
285 set_irn_n(irn, reqs[i]->same_pos, in2_node);
286 set_irn_n(irn, reqs[i]->same_pos ^ 1, in_node);
293 DBG((cg->mod, LEVEL_1, "inserting copy for %+F in_pos %d\n", irn, reqs[i]->same_pos));
294 /* create copy from in register */
295 copy = be_new_Copy(arch_register_get_class(in_reg), cg->irg, block, in_node);
297 DBG_OPT_2ADDRCPY(copy);
299 /* destination is the out register */
300 arch_set_irn_register(cg->arch_env, copy, out_reg);
302 /* insert copy before the node into the schedule */
303 sched_add_before(irn, copy);
306 set_irn_n(irn, reqs[i]->same_pos, copy);
313 /* check xCmp: try to avoid unordered cmp */
314 if ((is_ia32_xCmp(irn) || is_ia32_xCmpCMov(irn) || is_ia32_xCmpSet(irn)) &&
315 op_tp == ia32_Normal &&
316 ! is_ia32_ImmConst(irn) && ! is_ia32_ImmSymConst(irn))
318 long pnc = get_ia32_pncode(irn);
320 if (pnc & pn_Cmp_Uo) {
322 int idx1 = 2, idx2 = 3;
324 if (is_ia32_xCmpCMov(irn)) {
329 tmp = get_irn_n(irn, idx1);
330 set_irn_n(irn, idx1, get_irn_n(irn, idx2));
331 set_irn_n(irn, idx2, tmp);
333 set_ia32_pncode(irn, get_negated_pnc(pnc, mode_D));
338 If we have a CondJmp/CmpSet/xCmpSet with immediate,
339 we need to check if it's the right operand, otherwise
340 we have to change it, as CMP doesn't support immediate
344 if ((is_ia32_CondJmp(irn) || is_ia32_CmpSet(irn) || is_ia32_xCmpSet(irn)) &&
345 (is_ia32_ImmConst(irn) || is_ia32_ImmSymConst(irn)) &&
346 op_tp == ia32_AddrModeS)
348 set_ia32_op_type(irn, ia32_AddrModeD);
349 set_ia32_pncode(irn, get_inversed_pnc(get_ia32_pncode(irn)));
358 * We have a source address mode node with base or index register equal to
359 * result register. The constraint handler will insert a copy from the
360 * remaining input operand to the result register -> base or index is
362 * Solution: Turn back this address mode into explicit Load + Operation.
364 static void fix_am_source(ir_node *irn, void *env) {
365 ia32_code_gen_t *cg = env;
366 ir_node *base, *index, *noreg;
367 const arch_register_t *reg_base, *reg_index;
368 const ia32_register_req_t **reqs;
371 /* check only ia32 nodes with source address mode */
372 if (! is_ia32_irn(irn) || get_ia32_op_type(irn) != ia32_AddrModeS)
375 base = get_irn_n(irn, 0);
376 index = get_irn_n(irn, 1);
378 reg_base = arch_get_irn_register(cg->arch_env, base);
379 reg_index = arch_get_irn_register(cg->arch_env, index);
380 reqs = get_ia32_out_req_all(irn);
382 noreg = ia32_new_NoReg_gp(cg);
384 n_res = get_ia32_n_res(irn);
386 for (i = 0; i < n_res; i++) {
387 if (arch_register_req_is(&(reqs[i]->req), should_be_same)) {
388 /* get in and out register */
389 const arch_register_t *out_reg = get_ia32_out_reg(irn, i);
392 there is a constraint for the remaining operand
393 and the result register is equal to base or index register
395 if (reqs[i]->same_pos == 2 &&
396 (REGS_ARE_EQUAL(out_reg, reg_base) || REGS_ARE_EQUAL(out_reg, reg_index)))
398 /* turn back address mode */
399 ir_node *in_node = get_irn_n(irn, 2);
400 const arch_register_t *in_reg = arch_get_irn_register(cg->arch_env, in_node);
401 ir_node *block = get_nodes_block(irn);
402 ir_mode *ls_mode = get_ia32_ls_mode(irn);
406 if (arch_register_get_class(in_reg) == &ia32_reg_classes[CLASS_ia32_gp]) {
407 load = new_rd_ia32_Load(NULL, cg->irg, block, base, index, get_irn_n(irn, 4));
408 pnres = pn_ia32_Load_res;
410 else if (arch_register_get_class(in_reg) == &ia32_reg_classes[CLASS_ia32_xmm]) {
411 load = new_rd_ia32_xLoad(NULL, cg->irg, block, base, index, get_irn_n(irn, 4));
412 pnres = pn_ia32_xLoad_res;
415 assert(0 && "cannot turn back address mode for this register class");
418 /* copy address mode information to load */
419 set_ia32_ls_mode(load, ls_mode);
420 set_ia32_am_flavour(load, get_ia32_am_flavour(irn));
421 set_ia32_op_type(load, ia32_AddrModeS);
422 set_ia32_am_support(load, ia32_am_Source);
423 set_ia32_am_scale(load, get_ia32_am_scale(irn));
424 set_ia32_am_sc(load, get_ia32_am_sc(irn));
425 add_ia32_am_offs(load, get_ia32_am_offs(irn));
426 set_ia32_frame_ent(load, get_ia32_frame_ent(irn));
428 if (is_ia32_use_frame(irn))
429 set_ia32_use_frame(load);
431 /* insert the load into schedule */
432 sched_add_before(irn, load);
434 DBG((cg->mod, LEVEL_3, "irg %+F: build back AM source for node %+F, inserted load %+F\n", cg->irg, irn, load));
436 load = new_r_Proj(cg->irg, block, load, ls_mode, pnres);
437 arch_set_irn_register(cg->arch_env, load, out_reg);
439 /* insert the load result proj into schedule */
440 sched_add_before(irn, load);
442 /* set the new input operand */
443 set_irn_n(irn, 3, load);
445 /* this is a normal node now */
446 set_irn_n(irn, 0, noreg);
447 set_irn_n(irn, 1, noreg);
448 set_ia32_op_type(irn, ia32_Normal);
456 static void ia32_finish_irg_walker(ir_node *block, void *env) {
459 /* first: turn back AM source if necessary */
460 for (irn = sched_first(block); ! sched_is_end(irn); irn = next) {
461 next = sched_next(irn);
462 fix_am_source(irn, env);
465 for (irn = sched_first(block); ! sched_is_end(irn); irn = next) {
466 ia32_code_gen_t *cg = env;
468 next = sched_next(irn);
470 /* check if there is a sub which need to be transformed */
471 ia32_transform_sub_to_neg_add(irn, cg);
473 /* transform a LEA into an Add if possible */
474 ia32_transform_lea_to_add(irn, cg);
477 /* second: insert copies and finish irg */
478 for (irn = sched_first(block); ! sched_is_end(irn); irn = next) {
479 next = sched_next(irn);
480 ia32_finish_node(irn, env);
484 static void ia32_push_on_queue_walker(ir_node *block, void *env) {
486 waitq_put(wq, block);
491 * Add Copy nodes for not fulfilled should_be_equal constraints
493 void ia32_finish_irg(ir_graph *irg, ia32_code_gen_t *cg) {
494 waitq *wq = new_waitq();
496 /* Push the blocks on the waitq because ia32_finish_irg_walker starts more walks ... */
497 irg_block_walk_graph(irg, NULL, ia32_push_on_queue_walker, wq);
499 while (! waitq_empty(wq)) {
500 ir_node *block = waitq_get(wq);
501 ia32_finish_irg_walker(block, cg);