2 * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This file implements functions to finalize the irg for emit.
23 * @author Christian Wuerdig
37 #include "../bearch_t.h"
38 #include "../besched_t.h"
39 #include "../benode_t.h"
41 #include "bearch_ia32_t.h"
42 #include "ia32_finish.h"
43 #include "ia32_new_nodes.h"
44 #include "ia32_map_regs.h"
45 #include "ia32_common_transform.h"
46 #include "ia32_transform.h"
47 #include "ia32_dbg_stat.h"
48 #include "ia32_optimize.h"
49 #include "gen_ia32_regalloc_if.h"
51 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
54 * Transforms a Sub or xSub into Neg--Add iff OUT_REG == SRC2_REG.
55 * THIS FUNCTIONS MUST BE CALLED AFTER REGISTER ALLOCATION.
57 static void ia32_transform_sub_to_neg_add(ir_node *irn, ia32_code_gen_t *cg)
60 ir_node *in1, *in2, *noreg, *nomem, *res;
61 ir_node *noreg_fp, *block;
63 const arch_register_t *in1_reg, *in2_reg, *out_reg;
65 /* fix_am will solve this for AddressMode variants */
66 if (get_ia32_op_type(irn) != ia32_Normal)
69 noreg = ia32_new_NoReg_gp(cg);
70 noreg_fp = ia32_new_NoReg_xmm(cg);
71 nomem = new_rd_NoMem(cg->irg);
72 in1 = get_irn_n(irn, n_ia32_binary_left);
73 in2 = get_irn_n(irn, n_ia32_binary_right);
74 in1_reg = arch_get_irn_register(in1);
75 in2_reg = arch_get_irn_register(in2);
76 out_reg = arch_irn_get_register(irn, 0);
79 block = get_nodes_block(irn);
81 /* in case of sub and OUT == SRC2 we can transform the sequence into neg src2 -- add */
82 if (out_reg != in2_reg)
85 dbg = get_irn_dbg_info(irn);
87 /* generate the neg src2 */
88 if (is_ia32_xSub(irn)) {
91 ir_mode *op_mode = get_ia32_ls_mode(irn);
93 assert(get_irn_mode(irn) != mode_T);
95 res = new_rd_ia32_xXor(dbg, irg, block, noreg, noreg, nomem, in2, noreg_fp);
96 size = get_mode_size_bits(op_mode);
97 entity = ia32_gen_fp_known_const(size == 32 ? ia32_SSIGN : ia32_DSIGN);
98 set_ia32_am_sc(res, entity);
99 set_ia32_op_type(res, ia32_AddrModeS);
100 set_ia32_ls_mode(res, op_mode);
102 arch_set_irn_register(res, in2_reg);
104 /* add to schedule */
105 sched_add_before(irn, res);
107 /* generate the add */
108 res = new_rd_ia32_xAdd(dbg, irg, block, noreg, noreg, nomem, res, in1);
109 set_ia32_ls_mode(res, get_ia32_ls_mode(irn));
111 /* exchange the add and the sub */
112 edges_reroute(irn, res, irg);
114 /* add to schedule */
115 sched_add_before(irn, res);
117 ir_node *res_proj = NULL;
118 ir_node *flags_proj = NULL;
119 const ir_edge_t *edge;
121 if (get_irn_mode(irn) == mode_T) {
122 /* collect the Proj uses */
123 foreach_out_edge(irn, edge) {
124 ir_node *proj = get_edge_src_irn(edge);
125 long pn = get_Proj_proj(proj);
126 if (pn == pn_ia32_Sub_res) {
127 assert(res_proj == NULL);
130 assert(pn == pn_ia32_Sub_flags);
131 assert(flags_proj == NULL);
137 if (flags_proj == NULL) {
138 res = new_rd_ia32_Neg(dbg, irg, block, in2);
139 arch_set_irn_register(res, in2_reg);
141 /* add to schedule */
142 sched_add_before(irn, res);
144 /* generate the add */
145 res = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, nomem, res, in1);
146 arch_set_irn_register(res, out_reg);
147 set_ia32_commutative(res);
149 /* exchange the add and the sub */
150 edges_reroute(irn, res, irg);
152 /* add to schedule */
153 sched_add_before(irn, res);
155 ir_node *stc, *cmc, *not, *adc;
159 * ARG, the above technique does NOT set the flags right.
160 * So, we must produce the following code:
162 * t2 = a + ~b + Carry
165 * a + -b = a + (~b + 1) would set the carry flag IF a == b ...
167 not = new_rd_ia32_Not(dbg, irg, block, in2);
168 arch_set_irn_register(not, in2_reg);
169 sched_add_before(irn, not);
171 stc = new_rd_ia32_Stc(dbg, irg, block);
172 arch_set_irn_register(stc, &ia32_flags_regs[REG_EFLAGS]);
173 sched_add_before(irn, stc);
175 adc = new_rd_ia32_Adc(dbg, irg, block, noreg, noreg, nomem, not,
177 arch_set_irn_register(adc, out_reg);
178 sched_add_before(irn, adc);
180 set_irn_mode(adc, mode_T);
181 adc_flags = new_r_Proj(irg, block, adc, mode_Iu, pn_ia32_Adc_flags);
182 arch_set_irn_register(adc_flags, &ia32_flags_regs[REG_EFLAGS]);
184 cmc = new_rd_ia32_Cmc(dbg, irg, block, adc_flags);
185 arch_set_irn_register(cmc, &ia32_flags_regs[REG_EFLAGS]);
186 sched_add_before(irn, cmc);
188 exchange(flags_proj, cmc);
189 if (res_proj != NULL) {
190 set_Proj_pred(res_proj, adc);
191 set_Proj_proj(res_proj, pn_ia32_Adc_res);
198 set_irn_mode(res, get_irn_mode(irn));
200 SET_IA32_ORIG_NODE(res, irn);
202 /* remove the old sub */
206 DBG_OPT_SUB2NEGADD(irn, res);
209 static inline int need_constraint_copy(ir_node *irn)
211 /* TODO this should be determined from the node specification */
212 switch (get_ia32_irn_opcode(irn)) {
213 case iro_ia32_IMul: {
214 /* the 3 operand form of IMul needs no constraint copy */
215 ir_node *right = get_irn_n(irn, n_ia32_IMul_right);
216 return !is_ia32_Immediate(right);
220 case iro_ia32_Conv_I2I:
221 case iro_ia32_Conv_I2I8Bit:
231 * Returns the index of the "same" register.
232 * On the x86, we should have only one.
234 static int get_first_same(const arch_register_req_t* req)
236 const unsigned other = req->other_same;
239 for (i = 0; i < 32; ++i) {
240 if (other & (1U << i)) return i;
242 assert(! "same position not found");
247 * Insert copies for all ia32 nodes where the should_be_same requirement
249 * Transform Sub into Neg -- Add if IN2 == OUT
251 static void assure_should_be_same_requirements(ia32_code_gen_t *cg,
254 ir_graph *irg = cg->irg;
255 const arch_register_req_t **reqs;
256 const arch_register_t *out_reg, *in_reg;
258 ir_node *in_node, *block;
260 reqs = get_ia32_out_req_all(node);
261 n_res = arch_irn_get_n_outs(node);
262 block = get_nodes_block(node);
264 /* check all OUT requirements, if there is a should_be_same */
265 for (i = 0; i < n_res; i++) {
272 ir_node *uses_out_reg;
273 const arch_register_req_t *req = reqs[i];
274 const arch_register_class_t *cls;
275 int uses_out_reg_pos;
277 if (!arch_register_req_is(req, should_be_same))
280 same_pos = get_first_same(req);
282 /* get in and out register */
283 out_reg = arch_irn_get_register(node, i);
284 in_node = get_irn_n(node, same_pos);
285 in_reg = arch_get_irn_register(in_node);
287 /* requirement already fulfilled? */
288 if (in_reg == out_reg)
290 /* unknowns can be changed to any register we want on emitting */
291 if (is_unknown_reg(in_reg))
293 cls = arch_register_get_class(in_reg);
294 assert(cls == arch_register_get_class(out_reg));
296 /* check if any other input operands uses the out register */
297 arity = get_irn_arity(node);
299 uses_out_reg_pos = -1;
300 for (i2 = 0; i2 < arity; ++i2) {
301 ir_node *in = get_irn_n(node, i2);
302 const arch_register_t *in_reg;
304 if (!mode_is_data(get_irn_mode(in)))
307 in_reg = arch_get_irn_register(in);
309 if (in_reg != out_reg)
312 if (uses_out_reg != NULL && in != uses_out_reg) {
313 panic("invalid register allocation");
316 if (uses_out_reg_pos >= 0)
317 uses_out_reg_pos = -1; /* multiple inputs... */
319 uses_out_reg_pos = i2;
322 /* no-one else is using the out reg, we can simply copy it
323 * (the register can't be live since the operation will override it
325 if (uses_out_reg == NULL) {
326 ir_node *copy = be_new_Copy(cls, irg, block, in_node);
327 DBG_OPT_2ADDRCPY(copy);
329 /* destination is the out register */
330 arch_set_irn_register(copy, out_reg);
332 /* insert copy before the node into the schedule */
333 sched_add_before(node, copy);
336 set_irn_n(node, same_pos, copy);
339 "created copy %+F for should be same argument at input %d of %+F\n",
340 copy, same_pos, node));
344 /* for commutative nodes we can simply swap the left/right */
345 if (uses_out_reg_pos == n_ia32_binary_right && is_ia32_commutative(node)) {
346 ia32_swap_left_right(node);
348 "swapped left/right input of %+F to resolve should be same constraint\n",
354 ir_fprintf(stderr, "Note: need perm to resolve should_be_same constraint at %+F (this is unsafe and should not happen in theory...)\n", node);
356 /* the out reg is used as node input: we need to permutate our input
357 * and the other (this is allowed, since the other node can't be live
358 * after! the operation as we will override the register. */
360 in[1] = uses_out_reg;
361 perm = be_new_Perm(cls, irg, block, 2, in);
363 perm_proj0 = new_r_Proj(irg, block, perm, get_irn_mode(in[0]), 0);
364 perm_proj1 = new_r_Proj(irg, block, perm, get_irn_mode(in[1]), 1);
366 arch_set_irn_register(perm_proj0, out_reg);
367 arch_set_irn_register(perm_proj1, in_reg);
369 sched_add_before(node, perm);
372 "created perm %+F for should be same argument at input %d of %+F (need permutate with %+F)\n",
373 perm, same_pos, node, uses_out_reg));
375 /* use the perm results */
376 for (i2 = 0; i2 < arity; ++i2) {
377 ir_node *in = get_irn_n(node, i2);
380 set_irn_n(node, i2, perm_proj0);
381 } else if (in == uses_out_reg) {
382 set_irn_n(node, i2, perm_proj1);
390 * We have a source address mode node with base or index register equal to
391 * result register and unfulfilled should_be_same requirement. The constraint
392 * handler will insert a copy from the remaining input operand to the result
393 * register -> base or index is broken then.
394 * Solution: Turn back this address mode into explicit Load + Operation.
396 static void fix_am_source(ir_node *irn)
398 const arch_register_req_t **reqs;
401 /* check only ia32 nodes with source address mode */
402 if (!is_ia32_irn(irn) || get_ia32_op_type(irn) != ia32_AddrModeS)
404 /* only need to fix binary operations */
405 if (get_ia32_am_support(irn) != ia32_am_binary)
408 reqs = get_ia32_out_req_all(irn);
409 n_res = arch_irn_get_n_outs(irn);
411 for (i = 0; i < n_res; i++) {
412 const arch_register_t *out_reg;
415 const arch_register_t *same_reg;
418 if (!arch_register_req_is(reqs[i], should_be_same))
421 /* get in and out register */
422 out_reg = arch_irn_get_register(irn, i);
423 same_pos = get_first_same(reqs[i]);
424 same_node = get_irn_n(irn, same_pos);
425 same_reg = arch_get_irn_register(same_node);
427 /* should_be same constraint is fullfilled, nothing to do */
428 if (out_reg == same_reg)
431 /* we only need to do something if the out reg is the same as base
433 if (out_reg != arch_get_irn_register(get_irn_n(irn, n_ia32_base)) &&
434 out_reg != arch_get_irn_register(get_irn_n(irn, n_ia32_index)))
437 load_res = turn_back_am(irn);
438 arch_set_irn_register(load_res, out_reg);
441 "irg %+F: build back AM source for node %+F, inserted load %+F\n",
442 get_irn_irg(irn), irn, get_Proj_pred(load_res)));
448 * Block walker: finishes a block
450 static void ia32_finish_irg_walker(ir_node *block, void *env)
452 ia32_code_gen_t *cg = env;
455 /* first: turn back AM source if necessary */
456 for (irn = sched_first(block); ! sched_is_end(irn); irn = next) {
457 next = sched_next(irn);
461 for (irn = sched_first(block); ! sched_is_end(irn); irn = next) {
462 ia32_code_gen_t *cg = env;
464 next = sched_next(irn);
466 /* check if there is a sub which need to be transformed */
467 if (is_ia32_Sub(irn) || is_ia32_xSub(irn)) {
468 ia32_transform_sub_to_neg_add(irn, cg);
472 /* second: insert copies and finish irg */
473 for (irn = sched_first(block); ! sched_is_end(irn); irn = next) {
474 next = sched_next(irn);
475 if (is_ia32_irn(irn)) {
476 /* some nodes are just a bit less efficient, but need no fixing if the
477 * should be same requirement is not fulfilled */
478 if (need_constraint_copy(irn))
479 assure_should_be_same_requirements(cg, irn);
485 * Block walker: pushes all blocks on a wait queue
487 static void ia32_push_on_queue_walker(ir_node *block, void *env)
490 waitq_put(wq, block);
495 * Add Copy nodes for not fulfilled should_be_equal constraints
497 void ia32_finish_irg(ir_graph *irg, ia32_code_gen_t *cg)
499 waitq *wq = new_waitq();
501 /* Push the blocks on the waitq because ia32_finish_irg_walker starts more walks ... */
502 irg_block_walk_graph(irg, NULL, ia32_push_on_queue_walker, wq);
504 while (! waitq_empty(wq)) {
505 ir_node *block = waitq_get(wq);
506 ia32_finish_irg_walker(block, cg);
511 void ia32_init_finish(void)
513 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.finish");