2 * This file implements functions to finalize the irg for emit.
3 * @author Christian Wuerdig
13 #include "../bearch.h"
14 #include "../besched_t.h"
15 #include "../benode_t.h"
17 #include "bearch_ia32_t.h"
18 #include "ia32_finish.h"
19 #include "ia32_new_nodes.h"
20 #include "ia32_map_regs.h"
21 #include "ia32_transform.h"
22 #include "ia32_dbg_stat.h"
23 #include "ia32_optimize.h"
26 * Transforms a Sub or xSub into Neg--Add iff OUT_REG == SRC2_REG.
27 * THIS FUNCTIONS MUST BE CALLED AFTER REGISTER ALLOCATION.
29 static void ia32_transform_sub_to_neg_add(ir_node *irn, ia32_code_gen_t *cg) {
30 ia32_transform_env_t tenv;
31 ir_node *in1, *in2, *noreg, *nomem, *res;
32 const arch_register_t *in1_reg, *in2_reg, *out_reg, **slots;
34 /* Return if AM node or not a Sub or xSub */
35 if (get_ia32_op_type(irn) != ia32_Normal || !(is_ia32_Sub(irn) || is_ia32_xSub(irn)))
38 noreg = ia32_new_NoReg_gp(cg);
39 nomem = new_rd_NoMem(cg->irg);
40 in1 = get_irn_n(irn, 2);
41 in2 = get_irn_n(irn, 3);
42 in1_reg = arch_get_irn_register(cg->arch_env, in1);
43 in2_reg = arch_get_irn_register(cg->arch_env, in2);
44 out_reg = get_ia32_out_reg(irn, 0);
46 tenv.block = get_nodes_block(irn);
47 tenv.dbg = get_irn_dbg_info(irn);
50 tenv.mode = get_ia32_res_mode(irn);
52 DEBUG_ONLY(tenv.mod = cg->mod;)
54 /* in case of sub and OUT == SRC2 we can transform the sequence into neg src2 -- add */
55 if (REGS_ARE_EQUAL(out_reg, in2_reg)) {
56 /* generate the neg src2 */
57 res = gen_Minus_ex(&tenv, in2);
58 arch_set_irn_register(cg->arch_env, res, in2_reg);
61 sched_add_before(irn, res);
63 /* generate the add */
64 if (mode_is_float(tenv.mode)) {
65 res = new_rd_ia32_xAdd(tenv.dbg, tenv.irg, tenv.block, noreg, noreg, res, in1, nomem);
66 set_ia32_am_support(res, ia32_am_Source);
69 res = new_rd_ia32_Add(tenv.dbg, tenv.irg, tenv.block, noreg, noreg, res, in1, nomem);
70 set_ia32_am_support(res, ia32_am_Full);
71 set_ia32_commutative(res);
73 set_ia32_res_mode(res, tenv.mode);
75 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(tenv.cg, irn));
77 slots = get_ia32_slots(res);
81 sched_add_before(irn, res);
83 /* remove the old sub */
86 DBG_OPT_SUB2NEGADD(irn, res);
88 /* exchange the add and the sub */
94 * Transforms a LEA into an Add if possible
95 * THIS FUNCTIONS MUST BE CALLED AFTER REGISTER ALLOCATION.
97 static void ia32_transform_lea_to_add(ir_node *irn, ia32_code_gen_t *cg) {
98 ia32_am_flavour_t am_flav;
101 ir_node *nomem, *noreg, *base, *index, *op1, *op2;
103 ia32_transform_env_t tenv;
104 const arch_register_t *out_reg, *base_reg, *index_reg;
107 if (! is_ia32_Lea(irn))
110 am_flav = get_ia32_am_flavour(irn);
112 if (get_ia32_am_sc(irn))
115 /* only some LEAs can be transformed to an Add */
116 if (am_flav != ia32_am_B && am_flav != ia32_am_OB && am_flav != ia32_am_OI && am_flav != ia32_am_BI)
119 noreg = ia32_new_NoReg_gp(cg);
120 nomem = new_rd_NoMem(cg->irg);
123 base = get_irn_n(irn, 0);
124 index = get_irn_n(irn,1);
126 offs = get_ia32_am_offs(irn);
128 /* offset has a explicit sign -> we need to skip + */
129 if (offs && offs[0] == '+')
132 out_reg = arch_get_irn_register(cg->arch_env, irn);
133 base_reg = arch_get_irn_register(cg->arch_env, base);
134 index_reg = arch_get_irn_register(cg->arch_env, index);
136 tenv.block = get_nodes_block(irn);
137 tenv.dbg = get_irn_dbg_info(irn);
140 DEBUG_ONLY(tenv.mod = cg->mod;)
141 tenv.mode = get_irn_mode(irn);
144 switch(get_ia32_am_flavour(irn)) {
146 /* out register must be same as base register */
147 if (! REGS_ARE_EQUAL(out_reg, base_reg))
153 /* out register must be same as base register */
154 if (! REGS_ARE_EQUAL(out_reg, base_reg))
161 /* out register must be same as index register */
162 if (! REGS_ARE_EQUAL(out_reg, index_reg))
169 /* out register must be same as one in register */
170 if (REGS_ARE_EQUAL(out_reg, base_reg)) {
174 else if (REGS_ARE_EQUAL(out_reg, index_reg)) {
179 /* in registers a different from out -> no Add possible */
186 res = new_rd_ia32_Add(tenv.dbg, tenv.irg, tenv.block, noreg, noreg, op1, op2, nomem);
187 arch_set_irn_register(cg->arch_env, res, out_reg);
188 set_ia32_op_type(res, ia32_Normal);
189 set_ia32_commutative(res);
190 set_ia32_res_mode(res, tenv.mode);
193 set_ia32_cnst(res, offs);
194 set_ia32_immop_type(res, ia32_ImmConst);
197 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(cg, irn));
199 /* add Add to schedule */
200 sched_add_before(irn, res);
202 DBG_OPT_LEA2ADD(irn, res);
204 res = new_rd_Proj(tenv.dbg, tenv.irg, tenv.block, res, tenv.mode, pn_ia32_Add_res);
206 /* add result Proj to schedule */
207 sched_add_before(irn, res);
209 /* remove the old LEA */
212 /* exchange the Add and the LEA */
216 static INLINE int need_constraint_copy(ir_node *irn) {
218 ! is_ia32_Lea(irn) && \
219 ! is_ia32_Conv_I2I(irn) && \
220 ! is_ia32_Conv_I2I8Bit(irn) && \
221 ! is_ia32_CmpCMov(irn) && \
222 ! is_ia32_CmpSet(irn);
226 * Insert copies for all ia32 nodes where the should_be_same requirement
228 * Transform Sub into Neg -- Add if IN2 == OUT
230 static void ia32_finish_node(ir_node *irn, void *env) {
231 ia32_code_gen_t *cg = env;
232 const ia32_register_req_t **reqs;
233 const arch_register_t *out_reg, *in_reg, *in2_reg;
235 ir_node *copy, *in_node, *block, *in2_node;
236 ia32_op_type_t op_tp;
238 if (is_ia32_irn(irn)) {
239 /* AM Dest nodes don't produce any values */
240 op_tp = get_ia32_op_type(irn);
241 if (op_tp == ia32_AddrModeD)
244 reqs = get_ia32_out_req_all(irn);
245 n_res = get_ia32_n_res(irn);
246 block = get_nodes_block(irn);
248 /* check all OUT requirements, if there is a should_be_same */
249 if ((op_tp == ia32_Normal || op_tp == ia32_AddrModeS) && need_constraint_copy(irn))
251 for (i = 0; i < n_res; i++) {
252 if (arch_register_req_is(&(reqs[i]->req), should_be_same)) {
253 /* get in and out register */
254 out_reg = get_ia32_out_reg(irn, i);
255 in_node = get_irn_n(irn, reqs[i]->same_pos);
256 in_reg = arch_get_irn_register(cg->arch_env, in_node);
258 /* don't copy ignore nodes */
259 if (arch_irn_is(cg->arch_env, in_node, ignore) && is_Proj(in_node))
262 /* check if in and out register are equal */
263 if (! REGS_ARE_EQUAL(out_reg, in_reg)) {
264 /* in case of a commutative op: just exchange the in's */
265 /* beware: the current op could be everything, so test for ia32 */
266 /* commutativity first before getting the second in */
267 if (is_ia32_commutative(irn)) {
268 in2_node = get_irn_n(irn, reqs[i]->same_pos ^ 1);
269 in2_reg = arch_get_irn_register(cg->arch_env, in2_node);
271 if (REGS_ARE_EQUAL(out_reg, in2_reg)) {
272 set_irn_n(irn, reqs[i]->same_pos, in2_node);
273 set_irn_n(irn, reqs[i]->same_pos ^ 1, in_node);
280 DBG((cg->mod, LEVEL_1, "inserting copy for %+F in_pos %d\n", irn, reqs[i]->same_pos));
281 /* create copy from in register */
282 copy = be_new_Copy(arch_register_get_class(in_reg), cg->irg, block, in_node);
284 DBG_OPT_2ADDRCPY(copy);
286 /* destination is the out register */
287 arch_set_irn_register(cg->arch_env, copy, out_reg);
289 /* insert copy before the node into the schedule */
290 sched_add_before(irn, copy);
293 set_irn_n(irn, reqs[i]->same_pos, copy);
300 /* If we have a CondJmp/CmpSet/xCmpSet with immediate, we need to */
301 /* check if it's the right operand, otherwise we have */
302 /* to change it, as CMP doesn't support immediate as */
304 if ((is_ia32_CondJmp(irn) || is_ia32_CmpSet(irn) || is_ia32_xCmpSet(irn)) &&
305 (is_ia32_ImmConst(irn) || is_ia32_ImmSymConst(irn)) &&
306 op_tp == ia32_AddrModeS)
308 set_ia32_op_type(irn, ia32_AddrModeD);
309 set_ia32_pncode(irn, get_inversed_pnc(get_ia32_pncode(irn)));
312 /* check if there is a sub which need to be transformed */
313 ia32_transform_sub_to_neg_add(irn, cg);
315 /* transform a LEA into an Add if possible */
316 ia32_transform_lea_to_add(irn, cg);
320 /* check for peephole optimization */
321 ia32_peephole_optimization(irn, cg);
324 static void ia32_finish_irg_walker(ir_node *block, void *env) {
327 for (irn = sched_first(block); ! sched_is_end(irn); irn = next) {
328 next = sched_next(irn);
329 ia32_finish_node(irn, env);
333 static void ia32_push_on_queue_walker(ir_node *block, void *env) {
335 waitq_put(wq, block);
340 * Add Copy nodes for not fulfilled should_be_equal constraints
342 void ia32_finish_irg(ir_graph *irg, ia32_code_gen_t *cg) {
343 waitq *wq = new_waitq();
345 /* Push the blocks on the waitq because ia32_finish_irg_walker starts more walks ... */
346 irg_block_walk_graph(irg, NULL, ia32_push_on_queue_walker, wq);
348 while (! waitq_empty(wq)) {
349 ir_node *block = waitq_get(wq);
350 ia32_finish_irg_walker(block, cg);