2 * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This file implements functions to finalize the irg for emit.
23 * @author Christian Wuerdig
37 #include "../bearch.h"
38 #include "../besched.h"
39 #include "../benode.h"
41 #include "bearch_ia32_t.h"
42 #include "ia32_finish.h"
43 #include "ia32_new_nodes.h"
44 #include "ia32_common_transform.h"
45 #include "ia32_transform.h"
46 #include "ia32_dbg_stat.h"
47 #include "ia32_optimize.h"
48 #include "gen_ia32_regalloc_if.h"
50 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
53 * Transforms a Sub or xSub into Neg--Add iff OUT_REG != SRC1_REG && OUT_REG == SRC2_REG.
54 * THIS FUNCTIONS MUST BE CALLED AFTER REGISTER ALLOCATION.
56 static void ia32_transform_sub_to_neg_add(ir_node *irn)
59 ir_node *in1, *in2, *noreg, *nomem, *res;
60 ir_node *noreg_fp, *block;
62 const arch_register_t *in1_reg, *in2_reg, *out_reg;
64 /* fix_am will solve this for AddressMode variants */
65 if (get_ia32_op_type(irn) != ia32_Normal)
68 irg = get_irn_irg(irn);
69 noreg = ia32_new_NoReg_gp(irg);
70 noreg_fp = ia32_new_NoReg_xmm(irg);
71 nomem = get_irg_no_mem(irg);
72 in1 = get_irn_n(irn, n_ia32_binary_left);
73 in2 = get_irn_n(irn, n_ia32_binary_right);
74 in1_reg = arch_get_irn_register(in1);
75 in2_reg = arch_get_irn_register(in2);
76 out_reg = arch_irn_get_register(irn, 0);
78 if (out_reg == in1_reg)
81 /* in case of sub and OUT == SRC2 we can transform the sequence into neg src2 -- add */
82 if (out_reg != in2_reg)
85 block = get_nodes_block(irn);
86 dbgi = get_irn_dbg_info(irn);
88 /* generate the neg src2 */
89 if (is_ia32_xSub(irn)) {
92 ir_mode *op_mode = get_ia32_ls_mode(irn);
94 assert(get_irn_mode(irn) != mode_T);
96 res = new_bd_ia32_xXor(dbgi, block, noreg, noreg, nomem, in2, noreg_fp);
97 size = get_mode_size_bits(op_mode);
98 entity = ia32_gen_fp_known_const(size == 32 ? ia32_SSIGN : ia32_DSIGN);
99 set_ia32_am_sc(res, entity);
100 set_ia32_op_type(res, ia32_AddrModeS);
101 set_ia32_ls_mode(res, op_mode);
103 arch_set_irn_register(res, in2_reg);
105 /* add to schedule */
106 sched_add_before(irn, res);
108 /* generate the add */
109 res = new_bd_ia32_xAdd(dbgi, block, noreg, noreg, nomem, res, in1);
110 set_ia32_ls_mode(res, get_ia32_ls_mode(irn));
112 /* exchange the add and the sub */
113 edges_reroute(irn, res);
115 /* add to schedule */
116 sched_add_before(irn, res);
118 ir_node *res_proj = NULL;
119 ir_node *flags_proj = NULL;
120 const ir_edge_t *edge;
122 if (get_irn_mode(irn) == mode_T) {
123 /* collect the Proj uses */
124 foreach_out_edge(irn, edge) {
125 ir_node *proj = get_edge_src_irn(edge);
126 long pn = get_Proj_proj(proj);
127 if (pn == pn_ia32_Sub_res) {
128 assert(res_proj == NULL);
131 assert(pn == pn_ia32_Sub_flags);
132 assert(flags_proj == NULL);
138 if (flags_proj == NULL) {
139 res = new_bd_ia32_Neg(dbgi, block, in2);
140 arch_set_irn_register(res, in2_reg);
142 /* add to schedule */
143 sched_add_before(irn, res);
145 /* generate the add */
146 res = new_bd_ia32_Add(dbgi, block, noreg, noreg, nomem, res, in1);
147 arch_set_irn_register(res, out_reg);
148 set_ia32_commutative(res);
150 /* exchange the add and the sub */
151 edges_reroute(irn, res);
153 /* add to schedule */
154 sched_add_before(irn, res);
156 ir_node *stc, *cmc, *nnot, *adc;
160 * ARG, the above technique does NOT set the flags right.
161 * So, we must produce the following code:
163 * t2 = a + ~b + Carry
166 * a + -b = a + (~b + 1) would set the carry flag IF a == b ...
168 nnot = new_bd_ia32_Not(dbgi, block, in2);
169 arch_set_irn_register(nnot, in2_reg);
170 sched_add_before(irn, nnot);
172 stc = new_bd_ia32_Stc(dbgi, block);
173 arch_set_irn_register(stc, &ia32_registers[REG_EFLAGS]);
174 sched_add_before(irn, stc);
176 adc = new_bd_ia32_Adc(dbgi, block, noreg, noreg, nomem, nnot, in1, stc);
177 arch_set_irn_register(adc, out_reg);
178 sched_add_before(irn, adc);
180 set_irn_mode(adc, mode_T);
181 adc_flags = new_r_Proj(adc, mode_Iu, pn_ia32_Adc_flags);
182 arch_set_irn_register(adc_flags, &ia32_registers[REG_EFLAGS]);
184 cmc = new_bd_ia32_Cmc(dbgi, block, adc_flags);
185 arch_set_irn_register(cmc, &ia32_registers[REG_EFLAGS]);
186 sched_add_before(irn, cmc);
188 exchange(flags_proj, cmc);
189 if (res_proj != NULL) {
190 set_Proj_pred(res_proj, adc);
191 set_Proj_proj(res_proj, pn_ia32_Adc_res);
198 set_irn_mode(res, get_irn_mode(irn));
200 SET_IA32_ORIG_NODE(res, irn);
202 /* remove the old sub */
206 DBG_OPT_SUB2NEGADD(irn, res);
209 static inline int need_constraint_copy(ir_node *irn)
211 /* TODO this should be determined from the node specification */
212 switch (get_ia32_irn_opcode(irn)) {
213 case iro_ia32_IMul: {
214 /* the 3 operand form of IMul needs no constraint copy */
215 ir_node *right = get_irn_n(irn, n_ia32_IMul_right);
216 return !is_ia32_Immediate(right);
220 case iro_ia32_Conv_I2I:
221 case iro_ia32_Conv_I2I8Bit:
222 case iro_ia32_CMovcc:
231 * Returns the index of the "same" register.
232 * On the x86, we should have only one.
234 static int get_first_same(const arch_register_req_t* req)
236 const unsigned other = req->other_same;
239 for (i = 0; i < 32; ++i) {
240 if (other & (1U << i)) return i;
242 panic("same position not found");
246 * Insert copies for all ia32 nodes where the should_be_same requirement
248 * Transform Sub into Neg -- Add if IN2 == OUT
250 static void assure_should_be_same_requirements(ir_node *node)
252 const arch_register_t *out_reg, *in_reg;
254 ir_node *in_node, *block;
256 n_res = arch_irn_get_n_outs(node);
257 block = get_nodes_block(node);
259 /* check all OUT requirements, if there is a should_be_same */
260 for (i = 0; i < n_res; i++) {
263 ir_node *uses_out_reg;
264 const arch_register_req_t *req = arch_get_out_register_req(node, i);
265 const arch_register_class_t *cls;
266 int uses_out_reg_pos;
268 if (!arch_register_req_is(req, should_be_same))
271 same_pos = get_first_same(req);
273 /* get in and out register */
274 out_reg = arch_irn_get_register(node, i);
275 in_node = get_irn_n(node, same_pos);
276 in_reg = arch_get_irn_register(in_node);
278 /* requirement already fulfilled? */
279 if (in_reg == out_reg)
281 cls = arch_register_get_class(in_reg);
282 assert(cls == arch_register_get_class(out_reg));
284 /* check if any other input operands uses the out register */
285 arity = get_irn_arity(node);
287 uses_out_reg_pos = -1;
288 for (i2 = 0; i2 < arity; ++i2) {
289 ir_node *in = get_irn_n(node, i2);
290 const arch_register_t *other_in_reg;
292 if (!mode_is_data(get_irn_mode(in)))
295 other_in_reg = arch_get_irn_register(in);
297 if (other_in_reg != out_reg)
300 if (uses_out_reg != NULL && in != uses_out_reg) {
301 panic("invalid register allocation");
304 if (uses_out_reg_pos >= 0)
305 uses_out_reg_pos = -1; /* multiple inputs... */
307 uses_out_reg_pos = i2;
310 /* no-one else is using the out reg, we can simply copy it
311 * (the register can't be live since the operation will override it
313 if (uses_out_reg == NULL) {
314 ir_node *copy = be_new_Copy(cls, block, in_node);
315 DBG_OPT_2ADDRCPY(copy);
317 /* destination is the out register */
318 arch_set_irn_register(copy, out_reg);
320 /* insert copy before the node into the schedule */
321 sched_add_before(node, copy);
324 set_irn_n(node, same_pos, copy);
327 "created copy %+F for should be same argument at input %d of %+F\n",
328 copy, same_pos, node));
332 /* for commutative nodes we can simply swap the left/right */
333 if (uses_out_reg_pos == n_ia32_binary_right && is_ia32_commutative(node)) {
334 ia32_swap_left_right(node);
336 "swapped left/right input of %+F to resolve should be same constraint\n",
341 panic("Unresolved should_be_same constraint");
347 * We have a source address mode node with base or index register equal to
348 * result register and unfulfilled should_be_same requirement. The constraint
349 * handler will insert a copy from the remaining input operand to the result
350 * register -> base or index is broken then.
351 * Solution: Turn back this address mode into explicit Load + Operation.
353 static void fix_am_source(ir_node *irn)
357 /* check only ia32 nodes with source address mode */
358 if (!is_ia32_irn(irn) || get_ia32_op_type(irn) != ia32_AddrModeS)
360 /* only need to fix binary operations */
361 if (get_ia32_am_support(irn) != ia32_am_binary)
364 n_res = arch_irn_get_n_outs(irn);
366 for (i = 0; i < n_res; i++) {
367 const arch_register_req_t *req = arch_get_out_register_req(irn, i);
368 const arch_register_t *out_reg;
371 const arch_register_t *same_reg;
374 if (!arch_register_req_is(req, should_be_same))
377 /* get in and out register */
378 out_reg = arch_irn_get_register(irn, i);
379 same_pos = get_first_same(req);
380 same_node = get_irn_n(irn, same_pos);
381 same_reg = arch_get_irn_register(same_node);
383 /* should_be same constraint is fullfilled, nothing to do */
384 if (out_reg == same_reg)
387 /* we only need to do something if the out reg is the same as base
389 if (out_reg != arch_get_irn_register(get_irn_n(irn, n_ia32_base)) &&
390 out_reg != arch_get_irn_register(get_irn_n(irn, n_ia32_index)))
393 load_res = ia32_turn_back_am(irn);
394 arch_set_irn_register(load_res, out_reg);
397 "irg %+F: build back AM source for node %+F, inserted load %+F\n",
398 get_irn_irg(irn), irn, get_Proj_pred(load_res)));
404 * Block walker: finishes a block
406 static void ia32_finish_irg_walker(ir_node *block, void *env)
411 /* first: turn back AM source if necessary */
412 for (irn = sched_first(block); ! sched_is_end(irn); irn = next) {
413 next = sched_next(irn);
417 for (irn = sched_first(block); ! sched_is_end(irn); irn = next) {
418 next = sched_next(irn);
420 /* check if there is a sub which need to be transformed */
421 if (is_ia32_Sub(irn) || is_ia32_xSub(irn)) {
422 ia32_transform_sub_to_neg_add(irn);
426 /* second: insert copies and finish irg */
427 for (irn = sched_first(block); ! sched_is_end(irn); irn = next) {
428 next = sched_next(irn);
429 if (is_ia32_irn(irn)) {
430 /* some nodes are just a bit less efficient, but need no fixing if the
431 * should be same requirement is not fulfilled */
432 if (need_constraint_copy(irn))
433 assure_should_be_same_requirements(irn);
439 * Block walker: pushes all blocks on a wait queue
441 static void ia32_push_on_queue_walker(ir_node *block, void *env)
443 waitq *wq = (waitq*)env;
444 waitq_put(wq, block);
449 * Add Copy nodes for not fulfilled should_be_equal constraints
451 void ia32_finish_irg(ir_graph *irg)
453 waitq *wq = new_waitq();
455 /* Push the blocks on the waitq because ia32_finish_irg_walker starts more walks ... */
456 irg_block_walk_graph(irg, NULL, ia32_push_on_queue_walker, wq);
458 while (! waitq_empty(wq)) {
459 ir_node *block = (ir_node*)waitq_get(wq);
460 ia32_finish_irg_walker(block, NULL);
465 void ia32_init_finish(void)
467 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.finish");