2 * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This file implements functions to finalize the irg for emit.
23 * @author Christian Wuerdig
40 #include "bearch_ia32_t.h"
41 #include "ia32_finish.h"
42 #include "ia32_new_nodes.h"
43 #include "ia32_common_transform.h"
44 #include "ia32_transform.h"
45 #include "ia32_dbg_stat.h"
46 #include "ia32_optimize.h"
47 #include "gen_ia32_regalloc_if.h"
49 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
52 * Transforms a Sub or xSub into Neg--Add iff OUT_REG != SRC1_REG && OUT_REG == SRC2_REG.
53 * THIS FUNCTIONS MUST BE CALLED AFTER REGISTER ALLOCATION.
55 static void ia32_transform_sub_to_neg_add(ir_node *irn)
58 ir_node *in1, *in2, *noreg, *nomem, *res;
59 ir_node *noreg_fp, *block;
61 const arch_register_t *in1_reg, *in2_reg, *out_reg;
63 /* fix_am will solve this for AddressMode variants */
64 if (get_ia32_op_type(irn) != ia32_Normal)
67 irg = get_irn_irg(irn);
68 noreg = ia32_new_NoReg_gp(irg);
69 noreg_fp = ia32_new_NoReg_xmm(irg);
70 nomem = get_irg_no_mem(irg);
71 in1 = get_irn_n(irn, n_ia32_binary_left);
72 in2 = get_irn_n(irn, n_ia32_binary_right);
73 in1_reg = arch_get_irn_register(in1);
74 in2_reg = arch_get_irn_register(in2);
75 out_reg = arch_get_irn_register_out(irn, 0);
77 if (out_reg == in1_reg)
80 /* in case of sub and OUT == SRC2 we can transform the sequence into neg src2 -- add */
81 if (out_reg != in2_reg)
84 block = get_nodes_block(irn);
85 dbgi = get_irn_dbg_info(irn);
87 /* generate the neg src2 */
88 if (is_ia32_xSub(irn)) {
91 ir_mode *op_mode = get_ia32_ls_mode(irn);
93 assert(get_irn_mode(irn) != mode_T);
95 res = new_bd_ia32_xXor(dbgi, block, noreg, noreg, nomem, in2, noreg_fp);
96 size = get_mode_size_bits(op_mode);
97 entity = ia32_gen_fp_known_const(size == 32 ? ia32_SSIGN : ia32_DSIGN);
98 set_ia32_am_sc(res, entity);
99 set_ia32_op_type(res, ia32_AddrModeS);
100 set_ia32_ls_mode(res, op_mode);
102 arch_set_irn_register(res, in2_reg);
104 /* add to schedule */
105 sched_add_before(irn, res);
107 /* generate the add */
108 res = new_bd_ia32_xAdd(dbgi, block, noreg, noreg, nomem, res, in1);
109 set_ia32_ls_mode(res, get_ia32_ls_mode(irn));
111 ir_node *flags_proj = NULL;
114 if (get_irn_mode(irn) == mode_T) {
115 /* collect the Proj uses */
116 foreach_out_edge(irn, edge) {
117 ir_node *proj = get_edge_src_irn(edge);
118 long pn = get_Proj_proj(proj);
119 if (pn == pn_ia32_flags) {
120 assert(flags_proj == NULL);
127 if (is_ia32_Sbb(irn)) {
128 /* Feed borrow (in CF) as carry (via CMC) into NOT+ADC. */
129 carry = get_irn_n(irn, n_ia32_Sbb_eflags);
130 carry = new_bd_ia32_Cmc(dbgi, block, carry);
132 } else if (flags_proj != 0) {
134 * ARG, the above technique does NOT set the flags right.
135 * So, we must produce the following code:
137 * t2 = a + ~b + Carry
140 * a + -b = a + (~b + 1) would set the carry flag wrong IFF both a and b are zero.
147 carry = new_bd_ia32_Stc(dbgi, block);
150 nnot = new_bd_ia32_Not(dbgi, block, in2);
151 arch_set_irn_register(nnot, in2_reg);
152 sched_add_before(irn, nnot);
154 arch_set_irn_register(carry, &ia32_registers[REG_EFLAGS]);
155 sched_add_before(irn, carry);
157 adc = new_bd_ia32_Adc(dbgi, block, noreg, noreg, nomem, nnot, in1, carry);
158 arch_set_irn_register(adc, out_reg);
159 set_ia32_commutative(adc);
161 if (flags_proj != NULL) {
162 set_irn_mode(adc, mode_T);
163 adc_flags = new_r_Proj(adc, mode_Iu, pn_ia32_Adc_flags);
164 arch_set_irn_register(adc_flags, &ia32_registers[REG_EFLAGS]);
166 cmc = new_bd_ia32_Cmc(dbgi, block, adc_flags);
167 arch_set_irn_register(cmc, &ia32_registers[REG_EFLAGS]);
168 sched_add_after(irn, cmc);
169 exchange(flags_proj, cmc);
174 res = new_bd_ia32_Neg(dbgi, block, in2);
175 arch_set_irn_register(res, in2_reg);
177 /* add to schedule */
178 sched_add_before(irn, res);
180 /* generate the add */
181 res = new_bd_ia32_Add(dbgi, block, noreg, noreg, nomem, res, in1);
182 arch_set_irn_register(res, out_reg);
183 set_ia32_commutative(res);
187 /* exchange the add and the sub */
188 edges_reroute(irn, res);
189 sched_add_before(irn, res);
191 set_irn_mode(res, get_irn_mode(irn));
193 SET_IA32_ORIG_NODE(res, irn);
195 /* remove the old sub */
199 DBG_OPT_SUB2NEGADD(irn, res);
202 static inline int need_constraint_copy(ir_node *irn)
204 /* TODO this should be determined from the node specification */
205 switch (get_ia32_irn_opcode(irn)) {
206 case iro_ia32_IMul: {
207 /* the 3 operand form of IMul needs no constraint copy */
208 ir_node *right = get_irn_n(irn, n_ia32_IMul_right);
209 return !is_ia32_Immediate(right);
213 case iro_ia32_Conv_I2I:
214 case iro_ia32_Conv_I2I8Bit:
215 case iro_ia32_CMovcc:
216 case iro_ia32_Minus64Bit:
225 * Returns the index of the "same" register.
226 * On the x86, we should have only one.
228 static int get_first_same(const arch_register_req_t* req)
230 const unsigned other = req->other_same;
233 for (i = 0; i < 32; ++i) {
234 if (other & (1U << i)) return i;
236 panic("same position not found");
240 * Insert copies for all ia32 nodes where the should_be_same requirement
242 * Transform Sub into Neg -- Add if IN2 == OUT
244 static void assure_should_be_same_requirements(ir_node *node)
246 const arch_register_t *out_reg, *in_reg;
248 ir_node *in_node, *block;
250 n_res = arch_get_irn_n_outs(node);
251 block = get_nodes_block(node);
253 /* check all OUT requirements, if there is a should_be_same */
254 for (i = 0; i < n_res; i++) {
257 ir_node *uses_out_reg;
258 const arch_register_req_t *req = arch_get_irn_register_req_out(node, i);
259 const arch_register_class_t *cls;
260 int uses_out_reg_pos;
262 if (!arch_register_req_is(req, should_be_same))
265 same_pos = get_first_same(req);
267 /* get in and out register */
268 out_reg = arch_get_irn_register_out(node, i);
269 in_node = get_irn_n(node, same_pos);
270 in_reg = arch_get_irn_register(in_node);
272 /* requirement already fulfilled? */
273 if (in_reg == out_reg)
275 cls = arch_register_get_class(in_reg);
276 assert(cls == arch_register_get_class(out_reg));
278 /* check if any other input operands uses the out register */
279 arity = get_irn_arity(node);
281 uses_out_reg_pos = -1;
282 for (i2 = 0; i2 < arity; ++i2) {
283 ir_node *in = get_irn_n(node, i2);
284 const arch_register_t *other_in_reg;
286 if (!mode_is_data(get_irn_mode(in)))
289 other_in_reg = arch_get_irn_register(in);
291 if (other_in_reg != out_reg)
294 if (uses_out_reg != NULL && in != uses_out_reg) {
295 panic("invalid register allocation");
298 if (uses_out_reg_pos >= 0)
299 uses_out_reg_pos = -1; /* multiple inputs... */
301 uses_out_reg_pos = i2;
304 /* no-one else is using the out reg, we can simply copy it
305 * (the register can't be live since the operation will override it
307 if (uses_out_reg == NULL) {
308 ir_node *copy = be_new_Copy(block, in_node);
309 DBG_OPT_2ADDRCPY(copy);
311 /* destination is the out register */
312 arch_set_irn_register(copy, out_reg);
314 /* insert copy before the node into the schedule */
315 sched_add_before(node, copy);
318 set_irn_n(node, same_pos, copy);
321 "created copy %+F for should be same argument at input %d of %+F\n",
322 copy, same_pos, node));
326 /* for commutative nodes we can simply swap the left/right */
327 if (uses_out_reg_pos == n_ia32_binary_right && is_ia32_commutative(node)) {
328 ia32_swap_left_right(node);
330 "swapped left/right input of %+F to resolve should be same constraint\n",
335 panic("Unresolved should_be_same constraint");
341 * We have a source address mode node with base or index register equal to
342 * result register and unfulfilled should_be_same requirement. The constraint
343 * handler will insert a copy from the remaining input operand to the result
344 * register -> base or index is broken then.
345 * Solution: Turn back this address mode into explicit Load + Operation.
347 static void fix_am_source(ir_node *irn)
351 /* check only ia32 nodes with source address mode */
352 if (!is_ia32_irn(irn) || get_ia32_op_type(irn) != ia32_AddrModeS)
354 /* only need to fix binary operations */
355 if (get_ia32_am_support(irn) != ia32_am_binary)
358 n_res = arch_get_irn_n_outs(irn);
360 for (i = 0; i < n_res; i++) {
361 const arch_register_req_t *req = arch_get_irn_register_req_out(irn, i);
362 const arch_register_t *out_reg;
365 const arch_register_t *same_reg;
368 if (!arch_register_req_is(req, should_be_same))
371 /* get in and out register */
372 out_reg = arch_get_irn_register_out(irn, i);
373 same_pos = get_first_same(req);
374 same_node = get_irn_n(irn, same_pos);
375 same_reg = arch_get_irn_register(same_node);
377 /* should_be same constraint is fullfilled, nothing to do */
378 if (out_reg == same_reg)
381 /* we only need to do something if the out reg is the same as base
383 if (out_reg != arch_get_irn_register(get_irn_n(irn, n_ia32_base)) &&
384 out_reg != arch_get_irn_register(get_irn_n(irn, n_ia32_index)))
387 load_res = ia32_turn_back_am(irn);
388 arch_set_irn_register(load_res, out_reg);
391 "irg %+F: build back AM source for node %+F, inserted load %+F\n",
392 get_irn_irg(irn), irn, get_Proj_pred(load_res)));
398 * Block walker: finishes a block
400 static void ia32_finish_irg_walker(ir_node *block, void *env)
405 /* first: turn back AM source if necessary */
406 for (irn = sched_first(block); ! sched_is_end(irn); irn = next) {
407 next = sched_next(irn);
411 for (irn = sched_first(block); ! sched_is_end(irn); irn = next) {
412 next = sched_next(irn);
414 /* check if there is a sub which need to be transformed */
415 if (is_ia32_Sub(irn) || is_ia32_Sbb(irn) || is_ia32_xSub(irn)) {
416 ia32_transform_sub_to_neg_add(irn);
420 /* second: insert copies and finish irg */
421 for (irn = sched_first(block); ! sched_is_end(irn); irn = next) {
422 next = sched_next(irn);
423 if (is_ia32_irn(irn)) {
424 /* some nodes are just a bit less efficient, but need no fixing if the
425 * should be same requirement is not fulfilled */
426 if (need_constraint_copy(irn))
427 assure_should_be_same_requirements(irn);
433 * Block walker: pushes all blocks on a wait queue
435 static void ia32_push_on_queue_walker(ir_node *block, void *env)
437 waitq *wq = (waitq*)env;
438 waitq_put(wq, block);
443 * Add Copy nodes for not fulfilled should_be_equal constraints
445 void ia32_finish_irg(ir_graph *irg)
447 waitq *wq = new_waitq();
449 /* Push the blocks on the waitq because ia32_finish_irg_walker starts more walks ... */
450 irg_block_walk_graph(irg, NULL, ia32_push_on_queue_walker, wq);
452 while (! waitq_empty(wq)) {
453 ir_node *block = (ir_node*)waitq_get(wq);
454 ia32_finish_irg_walker(block, NULL);
459 void ia32_init_finish(void)
461 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.finish");