2 * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This file implements functions to finalize the irg for emit.
23 * @author Christian Wuerdig
37 #include "../bearch.h"
38 #include "../besched.h"
39 #include "../benode.h"
41 #include "bearch_ia32_t.h"
42 #include "ia32_finish.h"
43 #include "ia32_new_nodes.h"
44 #include "ia32_map_regs.h"
45 #include "ia32_common_transform.h"
46 #include "ia32_transform.h"
47 #include "ia32_dbg_stat.h"
48 #include "ia32_optimize.h"
49 #include "gen_ia32_regalloc_if.h"
51 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
54 * Transforms a Sub or xSub into Neg--Add iff OUT_REG != SRC1_REG && OUT_REG == SRC2_REG.
55 * THIS FUNCTIONS MUST BE CALLED AFTER REGISTER ALLOCATION.
57 static void ia32_transform_sub_to_neg_add(ir_node *irn)
60 ir_node *in1, *in2, *noreg, *nomem, *res;
61 ir_node *noreg_fp, *block;
63 const arch_register_t *in1_reg, *in2_reg, *out_reg;
65 /* fix_am will solve this for AddressMode variants */
66 if (get_ia32_op_type(irn) != ia32_Normal)
69 irg = get_irn_irg(irn);
70 noreg = ia32_new_NoReg_gp(irg);
71 noreg_fp = ia32_new_NoReg_xmm(irg);
72 nomem = new_r_NoMem(irg);
73 in1 = get_irn_n(irn, n_ia32_binary_left);
74 in2 = get_irn_n(irn, n_ia32_binary_right);
75 in1_reg = arch_get_irn_register(in1);
76 in2_reg = arch_get_irn_register(in2);
77 out_reg = arch_irn_get_register(irn, 0);
79 if (out_reg == in1_reg)
82 /* in case of sub and OUT == SRC2 we can transform the sequence into neg src2 -- add */
83 if (out_reg != in2_reg)
86 block = get_nodes_block(irn);
87 dbg = get_irn_dbg_info(irn);
89 /* generate the neg src2 */
90 if (is_ia32_xSub(irn)) {
93 ir_mode *op_mode = get_ia32_ls_mode(irn);
95 assert(get_irn_mode(irn) != mode_T);
97 res = new_bd_ia32_xXor(dbg, block, noreg, noreg, nomem, in2, noreg_fp);
98 size = get_mode_size_bits(op_mode);
99 entity = ia32_gen_fp_known_const(size == 32 ? ia32_SSIGN : ia32_DSIGN);
100 set_ia32_am_sc(res, entity);
101 set_ia32_op_type(res, ia32_AddrModeS);
102 set_ia32_ls_mode(res, op_mode);
104 arch_set_irn_register(res, in2_reg);
106 /* add to schedule */
107 sched_add_before(irn, res);
109 /* generate the add */
110 res = new_bd_ia32_xAdd(dbg, block, noreg, noreg, nomem, res, in1);
111 set_ia32_ls_mode(res, get_ia32_ls_mode(irn));
113 /* exchange the add and the sub */
114 edges_reroute(irn, res, irg);
116 /* add to schedule */
117 sched_add_before(irn, res);
119 ir_node *res_proj = NULL;
120 ir_node *flags_proj = NULL;
121 const ir_edge_t *edge;
123 if (get_irn_mode(irn) == mode_T) {
124 /* collect the Proj uses */
125 foreach_out_edge(irn, edge) {
126 ir_node *proj = get_edge_src_irn(edge);
127 long pn = get_Proj_proj(proj);
128 if (pn == pn_ia32_Sub_res) {
129 assert(res_proj == NULL);
132 assert(pn == pn_ia32_Sub_flags);
133 assert(flags_proj == NULL);
139 if (flags_proj == NULL) {
140 res = new_bd_ia32_Neg(dbg, block, in2);
141 arch_set_irn_register(res, in2_reg);
143 /* add to schedule */
144 sched_add_before(irn, res);
146 /* generate the add */
147 res = new_bd_ia32_Add(dbg, block, noreg, noreg, nomem, res, in1);
148 arch_set_irn_register(res, out_reg);
149 set_ia32_commutative(res);
151 /* exchange the add and the sub */
152 edges_reroute(irn, res, irg);
154 /* add to schedule */
155 sched_add_before(irn, res);
157 ir_node *stc, *cmc, *nnot, *adc;
161 * ARG, the above technique does NOT set the flags right.
162 * So, we must produce the following code:
164 * t2 = a + ~b + Carry
167 * a + -b = a + (~b + 1) would set the carry flag IF a == b ...
169 nnot = new_bd_ia32_Not(dbg, block, in2);
170 arch_set_irn_register(nnot, in2_reg);
171 sched_add_before(irn, nnot);
173 stc = new_bd_ia32_Stc(dbg, block);
174 arch_set_irn_register(stc, &ia32_registers[REG_EFLAGS]);
175 sched_add_before(irn, stc);
177 adc = new_bd_ia32_Adc(dbg, block, noreg, noreg, nomem, nnot, in1, stc);
178 arch_set_irn_register(adc, out_reg);
179 sched_add_before(irn, adc);
181 set_irn_mode(adc, mode_T);
182 adc_flags = new_r_Proj(adc, mode_Iu, pn_ia32_Adc_flags);
183 arch_set_irn_register(adc_flags, &ia32_registers[REG_EFLAGS]);
185 cmc = new_bd_ia32_Cmc(dbg, block, adc_flags);
186 arch_set_irn_register(cmc, &ia32_registers[REG_EFLAGS]);
187 sched_add_before(irn, cmc);
189 exchange(flags_proj, cmc);
190 if (res_proj != NULL) {
191 set_Proj_pred(res_proj, adc);
192 set_Proj_proj(res_proj, pn_ia32_Adc_res);
199 set_irn_mode(res, get_irn_mode(irn));
201 SET_IA32_ORIG_NODE(res, irn);
203 /* remove the old sub */
207 DBG_OPT_SUB2NEGADD(irn, res);
210 static inline int need_constraint_copy(ir_node *irn)
212 /* TODO this should be determined from the node specification */
213 switch (get_ia32_irn_opcode(irn)) {
214 case iro_ia32_IMul: {
215 /* the 3 operand form of IMul needs no constraint copy */
216 ir_node *right = get_irn_n(irn, n_ia32_IMul_right);
217 return !is_ia32_Immediate(right);
221 case iro_ia32_Conv_I2I:
222 case iro_ia32_Conv_I2I8Bit:
223 case iro_ia32_CMovcc:
232 * Returns the index of the "same" register.
233 * On the x86, we should have only one.
235 static int get_first_same(const arch_register_req_t* req)
237 const unsigned other = req->other_same;
240 for (i = 0; i < 32; ++i) {
241 if (other & (1U << i)) return i;
243 panic("same position not found");
247 * Insert copies for all ia32 nodes where the should_be_same requirement
249 * Transform Sub into Neg -- Add if IN2 == OUT
251 static void assure_should_be_same_requirements(ir_node *node)
253 const arch_register_t *out_reg, *in_reg;
255 ir_node *in_node, *block;
257 n_res = arch_irn_get_n_outs(node);
258 block = get_nodes_block(node);
260 /* check all OUT requirements, if there is a should_be_same */
261 for (i = 0; i < n_res; i++) {
268 ir_node *uses_out_reg;
269 const arch_register_req_t *req = arch_get_out_register_req(node, i);
270 const arch_register_class_t *cls;
271 int uses_out_reg_pos;
273 if (!arch_register_req_is(req, should_be_same))
276 same_pos = get_first_same(req);
278 /* get in and out register */
279 out_reg = arch_irn_get_register(node, i);
280 in_node = get_irn_n(node, same_pos);
281 in_reg = arch_get_irn_register(in_node);
283 /* requirement already fulfilled? */
284 if (in_reg == out_reg)
286 cls = arch_register_get_class(in_reg);
287 assert(cls == arch_register_get_class(out_reg));
289 /* check if any other input operands uses the out register */
290 arity = get_irn_arity(node);
292 uses_out_reg_pos = -1;
293 for (i2 = 0; i2 < arity; ++i2) {
294 ir_node *in = get_irn_n(node, i2);
295 const arch_register_t *in_reg;
297 if (!mode_is_data(get_irn_mode(in)))
300 in_reg = arch_get_irn_register(in);
302 if (in_reg != out_reg)
305 if (uses_out_reg != NULL && in != uses_out_reg) {
306 panic("invalid register allocation");
309 if (uses_out_reg_pos >= 0)
310 uses_out_reg_pos = -1; /* multiple inputs... */
312 uses_out_reg_pos = i2;
315 /* no-one else is using the out reg, we can simply copy it
316 * (the register can't be live since the operation will override it
318 if (uses_out_reg == NULL) {
319 ir_node *copy = be_new_Copy(cls, block, in_node);
320 DBG_OPT_2ADDRCPY(copy);
322 /* destination is the out register */
323 arch_set_irn_register(copy, out_reg);
325 /* insert copy before the node into the schedule */
326 sched_add_before(node, copy);
329 set_irn_n(node, same_pos, copy);
332 "created copy %+F for should be same argument at input %d of %+F\n",
333 copy, same_pos, node));
337 /* for commutative nodes we can simply swap the left/right */
338 if (uses_out_reg_pos == n_ia32_binary_right && is_ia32_commutative(node)) {
339 ia32_swap_left_right(node);
341 "swapped left/right input of %+F to resolve should be same constraint\n",
347 ir_fprintf(stderr, "Note: need perm to resolve should_be_same constraint at %+F (this is unsafe and should not happen in theory...)\n", node);
349 /* the out reg is used as node input: we need to permutate our input
350 * and the other (this is allowed, since the other node can't be live
351 * after! the operation as we will override the register. */
353 in[1] = uses_out_reg;
354 perm = be_new_Perm(cls, block, 2, in);
356 perm_proj0 = new_r_Proj(perm, get_irn_mode(in[0]), 0);
357 perm_proj1 = new_r_Proj(perm, get_irn_mode(in[1]), 1);
359 arch_set_irn_register(perm_proj0, out_reg);
360 arch_set_irn_register(perm_proj1, in_reg);
362 sched_add_before(node, perm);
365 "created perm %+F for should be same argument at input %d of %+F (need permutate with %+F)\n",
366 perm, same_pos, node, uses_out_reg));
368 /* use the perm results */
369 for (i2 = 0; i2 < arity; ++i2) {
370 ir_node *in = get_irn_n(node, i2);
373 set_irn_n(node, i2, perm_proj0);
374 } else if (in == uses_out_reg) {
375 set_irn_n(node, i2, perm_proj1);
383 * We have a source address mode node with base or index register equal to
384 * result register and unfulfilled should_be_same requirement. The constraint
385 * handler will insert a copy from the remaining input operand to the result
386 * register -> base or index is broken then.
387 * Solution: Turn back this address mode into explicit Load + Operation.
389 static void fix_am_source(ir_node *irn)
393 /* check only ia32 nodes with source address mode */
394 if (!is_ia32_irn(irn) || get_ia32_op_type(irn) != ia32_AddrModeS)
396 /* only need to fix binary operations */
397 if (get_ia32_am_support(irn) != ia32_am_binary)
400 n_res = arch_irn_get_n_outs(irn);
402 for (i = 0; i < n_res; i++) {
403 const arch_register_req_t *req = arch_get_out_register_req(irn, i);
404 const arch_register_t *out_reg;
407 const arch_register_t *same_reg;
410 if (!arch_register_req_is(req, should_be_same))
413 /* get in and out register */
414 out_reg = arch_irn_get_register(irn, i);
415 same_pos = get_first_same(req);
416 same_node = get_irn_n(irn, same_pos);
417 same_reg = arch_get_irn_register(same_node);
419 /* should_be same constraint is fullfilled, nothing to do */
420 if (out_reg == same_reg)
423 /* we only need to do something if the out reg is the same as base
425 if (out_reg != arch_get_irn_register(get_irn_n(irn, n_ia32_base)) &&
426 out_reg != arch_get_irn_register(get_irn_n(irn, n_ia32_index)))
429 load_res = turn_back_am(irn);
430 arch_set_irn_register(load_res, out_reg);
433 "irg %+F: build back AM source for node %+F, inserted load %+F\n",
434 get_irn_irg(irn), irn, get_Proj_pred(load_res)));
440 * Block walker: finishes a block
442 static void ia32_finish_irg_walker(ir_node *block, void *env)
447 /* first: turn back AM source if necessary */
448 for (irn = sched_first(block); ! sched_is_end(irn); irn = next) {
449 next = sched_next(irn);
453 for (irn = sched_first(block); ! sched_is_end(irn); irn = next) {
454 next = sched_next(irn);
456 /* check if there is a sub which need to be transformed */
457 if (is_ia32_Sub(irn) || is_ia32_xSub(irn)) {
458 ia32_transform_sub_to_neg_add(irn);
462 /* second: insert copies and finish irg */
463 for (irn = sched_first(block); ! sched_is_end(irn); irn = next) {
464 next = sched_next(irn);
465 if (is_ia32_irn(irn)) {
466 /* some nodes are just a bit less efficient, but need no fixing if the
467 * should be same requirement is not fulfilled */
468 if (need_constraint_copy(irn))
469 assure_should_be_same_requirements(irn);
475 * Block walker: pushes all blocks on a wait queue
477 static void ia32_push_on_queue_walker(ir_node *block, void *env)
479 waitq *wq = (waitq*)env;
480 waitq_put(wq, block);
485 * Add Copy nodes for not fulfilled should_be_equal constraints
487 void ia32_finish_irg(ir_graph *irg)
489 waitq *wq = new_waitq();
491 /* Push the blocks on the waitq because ia32_finish_irg_walker starts more walks ... */
492 irg_block_walk_graph(irg, NULL, ia32_push_on_queue_walker, wq);
494 while (! waitq_empty(wq)) {
495 ir_node *block = (ir_node*)waitq_get(wq);
496 ia32_finish_irg_walker(block, NULL);
501 void ia32_init_finish(void)
503 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.finish");