2 * This file implements functions to finalize the irg for emit.
3 * @author Christian Wuerdig
13 #include "../bearch.h"
14 #include "../besched_t.h"
15 #include "../benode_t.h"
17 #include "bearch_ia32_t.h"
18 #include "ia32_finish.h"
19 #include "ia32_new_nodes.h"
20 #include "ia32_map_regs.h"
21 #include "ia32_transform.h"
22 #include "ia32_dbg_stat.h"
23 #include "ia32_optimize.h"
24 #include "gen_ia32_regalloc_if.h"
27 * Transforms a Sub or xSub into Neg--Add iff OUT_REG == SRC2_REG.
28 * THIS FUNCTIONS MUST BE CALLED AFTER REGISTER ALLOCATION.
30 static void ia32_transform_sub_to_neg_add(ir_node *irn, ia32_code_gen_t *cg) {
31 ia32_transform_env_t tenv;
32 ir_node *in1, *in2, *noreg, *nomem, *res;
33 const arch_register_t *in1_reg, *in2_reg, *out_reg, **slots;
35 /* Return if AM node or not a Sub or xSub */
36 if (get_ia32_op_type(irn) != ia32_Normal || !(is_ia32_Sub(irn) || is_ia32_xSub(irn)))
39 noreg = ia32_new_NoReg_gp(cg);
40 nomem = new_rd_NoMem(cg->irg);
41 in1 = get_irn_n(irn, 2);
42 in2 = get_irn_n(irn, 3);
43 in1_reg = arch_get_irn_register(cg->arch_env, in1);
44 in2_reg = arch_get_irn_register(cg->arch_env, in2);
45 out_reg = get_ia32_out_reg(irn, 0);
47 tenv.block = get_nodes_block(irn);
48 tenv.dbg = get_irn_dbg_info(irn);
51 tenv.mode = get_ia32_res_mode(irn);
53 DEBUG_ONLY(tenv.mod = cg->mod;)
55 /* in case of sub and OUT == SRC2 we can transform the sequence into neg src2 -- add */
56 if (REGS_ARE_EQUAL(out_reg, in2_reg)) {
57 /* generate the neg src2 */
58 res = gen_Minus_ex(&tenv, in2);
59 arch_set_irn_register(cg->arch_env, res, in2_reg);
62 sched_add_before(irn, res);
64 /* generate the add */
65 if (mode_is_float(tenv.mode)) {
66 res = new_rd_ia32_xAdd(tenv.dbg, tenv.irg, tenv.block, noreg, noreg, res, in1, nomem);
67 set_ia32_am_support(res, ia32_am_Source);
70 res = new_rd_ia32_Add(tenv.dbg, tenv.irg, tenv.block, noreg, noreg, res, in1, nomem);
71 set_ia32_am_support(res, ia32_am_Full);
72 set_ia32_commutative(res);
74 set_ia32_res_mode(res, tenv.mode);
76 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(tenv.cg, irn));
78 slots = get_ia32_slots(res);
82 sched_add_before(irn, res);
84 /* remove the old sub */
87 DBG_OPT_SUB2NEGADD(irn, res);
89 /* exchange the add and the sub */
95 * Transforms a LEA into an Add if possible
96 * THIS FUNCTIONS MUST BE CALLED AFTER REGISTER ALLOCATION.
98 static void ia32_transform_lea_to_add(ir_node *irn, ia32_code_gen_t *cg) {
99 ia32_am_flavour_t am_flav;
102 ir_node *nomem, *noreg, *base, *index, *op1, *op2;
104 ia32_transform_env_t tenv;
105 const arch_register_t *out_reg, *base_reg, *index_reg;
108 if (! is_ia32_Lea(irn))
111 am_flav = get_ia32_am_flavour(irn);
113 if (get_ia32_am_sc(irn))
116 /* only some LEAs can be transformed to an Add */
117 if (am_flav != ia32_am_B && am_flav != ia32_am_OB && am_flav != ia32_am_OI && am_flav != ia32_am_BI)
120 noreg = ia32_new_NoReg_gp(cg);
121 nomem = new_rd_NoMem(cg->irg);
124 base = get_irn_n(irn, 0);
125 index = get_irn_n(irn,1);
127 offs = get_ia32_am_offs(irn);
129 /* offset has a explicit sign -> we need to skip + */
130 if (offs && offs[0] == '+')
133 out_reg = arch_get_irn_register(cg->arch_env, irn);
134 base_reg = arch_get_irn_register(cg->arch_env, base);
135 index_reg = arch_get_irn_register(cg->arch_env, index);
137 tenv.block = get_nodes_block(irn);
138 tenv.dbg = get_irn_dbg_info(irn);
141 DEBUG_ONLY(tenv.mod = cg->mod;)
142 tenv.mode = get_irn_mode(irn);
145 switch(get_ia32_am_flavour(irn)) {
147 /* out register must be same as base register */
148 if (! REGS_ARE_EQUAL(out_reg, base_reg))
154 /* out register must be same as base register */
155 if (! REGS_ARE_EQUAL(out_reg, base_reg))
162 /* out register must be same as index register */
163 if (! REGS_ARE_EQUAL(out_reg, index_reg))
170 /* out register must be same as one in register */
171 if (REGS_ARE_EQUAL(out_reg, base_reg)) {
175 else if (REGS_ARE_EQUAL(out_reg, index_reg)) {
180 /* in registers a different from out -> no Add possible */
187 res = new_rd_ia32_Add(tenv.dbg, tenv.irg, tenv.block, noreg, noreg, op1, op2, nomem);
188 arch_set_irn_register(cg->arch_env, res, out_reg);
189 set_ia32_op_type(res, ia32_Normal);
190 set_ia32_commutative(res);
191 set_ia32_res_mode(res, tenv.mode);
194 set_ia32_cnst(res, offs);
195 set_ia32_immop_type(res, ia32_ImmConst);
198 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(cg, irn));
200 /* add Add to schedule */
201 sched_add_before(irn, res);
203 DBG_OPT_LEA2ADD(irn, res);
205 res = new_rd_Proj(tenv.dbg, tenv.irg, tenv.block, res, tenv.mode, pn_ia32_Add_res);
207 /* add result Proj to schedule */
208 sched_add_before(irn, res);
210 /* remove the old LEA */
213 /* exchange the Add and the LEA */
217 static INLINE int need_constraint_copy(ir_node *irn) {
219 ! is_ia32_Lea(irn) && \
220 ! is_ia32_Conv_I2I(irn) && \
221 ! is_ia32_Conv_I2I8Bit(irn) && \
222 ! is_ia32_CmpCMov(irn) && \
223 ! is_ia32_CmpSet(irn);
227 * Insert copies for all ia32 nodes where the should_be_same requirement
229 * Transform Sub into Neg -- Add if IN2 == OUT
231 static void ia32_finish_node(ir_node *irn, void *env) {
232 ia32_code_gen_t *cg = env;
233 const ia32_register_req_t **reqs;
234 const arch_register_t *out_reg, *in_reg, *in2_reg;
236 ir_node *copy, *in_node, *block, *in2_node;
237 ia32_op_type_t op_tp;
239 if (is_ia32_irn(irn)) {
240 /* AM Dest nodes don't produce any values */
241 op_tp = get_ia32_op_type(irn);
242 if (op_tp == ia32_AddrModeD)
245 reqs = get_ia32_out_req_all(irn);
246 n_res = get_ia32_n_res(irn);
247 block = get_nodes_block(irn);
249 /* check all OUT requirements, if there is a should_be_same */
250 if ((op_tp == ia32_Normal || op_tp == ia32_AddrModeS) && need_constraint_copy(irn))
252 for (i = 0; i < n_res; i++) {
253 if (arch_register_req_is(&(reqs[i]->req), should_be_same)) {
254 /* get in and out register */
255 out_reg = get_ia32_out_reg(irn, i);
256 in_node = get_irn_n(irn, reqs[i]->same_pos);
257 in_reg = arch_get_irn_register(cg->arch_env, in_node);
259 /* don't copy ignore nodes */
260 if (arch_irn_is(cg->arch_env, in_node, ignore) && is_Proj(in_node))
263 /* check if in and out register are equal */
264 if (! REGS_ARE_EQUAL(out_reg, in_reg)) {
265 /* in case of a commutative op: just exchange the in's */
266 /* beware: the current op could be everything, so test for ia32 */
267 /* commutativity first before getting the second in */
268 if (is_ia32_commutative(irn)) {
269 in2_node = get_irn_n(irn, reqs[i]->same_pos ^ 1);
270 in2_reg = arch_get_irn_register(cg->arch_env, in2_node);
272 if (REGS_ARE_EQUAL(out_reg, in2_reg)) {
273 set_irn_n(irn, reqs[i]->same_pos, in2_node);
274 set_irn_n(irn, reqs[i]->same_pos ^ 1, in_node);
281 DBG((cg->mod, LEVEL_1, "inserting copy for %+F in_pos %d\n", irn, reqs[i]->same_pos));
282 /* create copy from in register */
283 copy = be_new_Copy(arch_register_get_class(in_reg), cg->irg, block, in_node);
285 DBG_OPT_2ADDRCPY(copy);
287 /* destination is the out register */
288 arch_set_irn_register(cg->arch_env, copy, out_reg);
290 /* insert copy before the node into the schedule */
291 sched_add_before(irn, copy);
294 set_irn_n(irn, reqs[i]->same_pos, copy);
301 /* If we have a CondJmp/CmpSet/xCmpSet with immediate, we need to */
302 /* check if it's the right operand, otherwise we have */
303 /* to change it, as CMP doesn't support immediate as */
305 if ((is_ia32_CondJmp(irn) || is_ia32_CmpSet(irn) || is_ia32_xCmpSet(irn)) &&
306 (is_ia32_ImmConst(irn) || is_ia32_ImmSymConst(irn)) &&
307 op_tp == ia32_AddrModeS)
309 set_ia32_op_type(irn, ia32_AddrModeD);
310 set_ia32_pncode(irn, get_inversed_pnc(get_ia32_pncode(irn)));
313 /* check if there is a sub which need to be transformed */
314 ia32_transform_sub_to_neg_add(irn, cg);
316 /* transform a LEA into an Add if possible */
317 ia32_transform_lea_to_add(irn, cg);
321 /* check for peephole optimization */
322 ia32_peephole_optimization(irn, cg);
327 * We have a source address mode node with base or index register equal to
328 * result register. The constraint handler will insert a copy from the
329 * remaining input operand to the result register -> base or index is
331 * Solution: Turn back this address mode into explicit Load + Operation.
333 static void fix_am_source(ir_node *irn, void *env) {
334 ia32_code_gen_t *cg = env;
335 ir_node *base, *index;
336 const arch_register_t *reg_base, *reg_index;
337 const ia32_register_req_t **reqs;
340 /* check only ia32 nodes with source address mode */
341 if (! is_ia32_irn(irn) || get_ia32_op_type(irn) != ia32_AddrModeS)
344 base = get_irn_n(irn, 0);
345 index = get_irn_n(irn, 1);
347 reg_base = arch_get_irn_register(cg->arch_env, base);
348 reg_index = arch_get_irn_register(cg->arch_env, index);
349 reqs = get_ia32_out_req_all(irn);
351 n_res = get_ia32_n_res(irn);
353 for (i = 0; i < n_res; i++) {
354 if (arch_register_req_is(&(reqs[i]->req), should_be_same)) {
355 /* get in and out register */
356 const arch_register_t *out_reg = get_ia32_out_reg(irn, i);
359 there is a constraint for the remaining operand
360 and the result register is equal to base or index register
362 if (reqs[i]->same_pos == 2 &&
363 (REGS_ARE_EQUAL(out_reg, reg_base) || REGS_ARE_EQUAL(out_reg, reg_index)))
365 /* turn back address mode */
366 ir_node *in_node = get_irn_n(irn, 2);
367 const arch_register_t *in_reg = arch_get_irn_register(cg->arch_env, in_node);
368 ir_node *block = get_nodes_block(irn);
369 ir_mode *ls_mode = get_ia32_ls_mode(irn);
373 if (arch_register_get_class(in_reg) == &ia32_reg_classes[CLASS_ia32_gp]) {
374 load = new_rd_ia32_Load(NULL, cg->irg, block, base, index, get_irn_n(irn, 4));
375 pnres = pn_ia32_Load_res;
377 else if (arch_register_get_class(in_reg) == &ia32_reg_classes[CLASS_ia32_xmm]) {
378 load = new_rd_ia32_xLoad(NULL, cg->irg, block, base, index, get_irn_n(irn, 4));
379 pnres = pn_ia32_xLoad_res;
382 assert(0 && "cannot turn back address mode for this register class");
385 /* copy address mode information to load */
386 set_ia32_ls_mode(load, ls_mode);
387 set_ia32_am_flavour(load, get_ia32_am_flavour(irn));
388 set_ia32_op_type(load, ia32_AddrModeS);
389 set_ia32_am_support(load, ia32_am_Source);
390 set_ia32_am_scale(load, get_ia32_am_scale(irn));
391 set_ia32_am_sc(load, get_ia32_am_sc(irn));
392 add_ia32_am_offs(load, get_ia32_am_offs(irn));
393 set_ia32_frame_ent(load, get_ia32_frame_ent(irn));
395 if (is_ia32_use_frame(irn))
396 set_ia32_use_frame(load);
398 /* insert the load into schedule */
399 sched_add_before(irn, load);
401 DBG((cg->mod, LEVEL_3, "irg %+F: build back AM source for node %+F, inserted load %+F\n", cg->irg, irn, load));
403 load = new_r_Proj(cg->irg, block, load, ls_mode, pnres);
404 arch_set_irn_register(cg->arch_env, load, out_reg);
406 /* insert the load result proj into schedule */
407 sched_add_before(irn, load);
409 /* set the new input operand */
410 set_irn_n(irn, 3, load);
412 /* this is a normal node now */
413 set_ia32_op_type(irn, ia32_Normal);
421 static void ia32_finish_irg_walker(ir_node *block, void *env) {
424 /* first: turn back AM source if necessary */
425 for (irn = sched_first(block); ! sched_is_end(irn); irn = next) {
426 next = sched_next(irn);
427 fix_am_source(irn, env);
430 /* second: insert copies and finish irg */
431 for (irn = sched_first(block); ! sched_is_end(irn); irn = next) {
432 next = sched_next(irn);
433 ia32_finish_node(irn, env);
437 static void ia32_push_on_queue_walker(ir_node *block, void *env) {
439 waitq_put(wq, block);
444 * Add Copy nodes for not fulfilled should_be_equal constraints
446 void ia32_finish_irg(ir_graph *irg, ia32_code_gen_t *cg) {
447 waitq *wq = new_waitq();
449 /* Push the blocks on the waitq because ia32_finish_irg_walker starts more walks ... */
450 irg_block_walk_graph(irg, NULL, ia32_push_on_queue_walker, wq);
452 while (! waitq_empty(wq)) {
453 ir_node *block = waitq_get(wq);
454 ia32_finish_irg_walker(block, cg);