2 * Copyright (C) 1995-2007 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This file implements functions to finalize the irg for emit.
23 * @author Christian Wuerdig
39 #include "../bearch_t.h"
40 #include "../besched_t.h"
41 #include "../benode_t.h"
43 #include "bearch_ia32_t.h"
44 #include "ia32_finish.h"
45 #include "ia32_new_nodes.h"
46 #include "ia32_map_regs.h"
47 #include "ia32_transform.h"
48 #include "ia32_dbg_stat.h"
49 #include "ia32_optimize.h"
50 #include "gen_ia32_regalloc_if.h"
52 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
55 * Transforms a Sub or xSub into Neg--Add iff OUT_REG == SRC2_REG.
56 * THIS FUNCTIONS MUST BE CALLED AFTER REGISTER ALLOCATION.
58 static void ia32_transform_sub_to_neg_add(ir_node *irn, ia32_code_gen_t *cg) {
60 ir_node *in1, *in2, *noreg, *nomem, *res;
61 ir_node *noreg_fp, *block;
62 ir_mode *mode = get_irn_mode(irn);
63 dbg_info *dbg = get_irn_dbg_info(irn);
64 const arch_register_t *in1_reg, *in2_reg, *out_reg, **slots;
67 /* Return if not a Sub or xSub */
68 if (!is_ia32_Sub(irn) && !is_ia32_xSub(irn))
70 /* fix_am will solve this for AddressMode variants */
71 if(get_ia32_op_type(irn) != ia32_Normal)
74 noreg = ia32_new_NoReg_gp(cg);
75 noreg_fp = ia32_new_NoReg_fp(cg);
76 nomem = new_rd_NoMem(cg->irg);
77 in1 = get_irn_n(irn, 2);
78 in2 = get_irn_n(irn, 3);
79 in1_reg = arch_get_irn_register(cg->arch_env, in1);
80 in2_reg = arch_get_irn_register(cg->arch_env, in2);
81 out_reg = get_ia32_out_reg(irn, 0);
83 assert(get_irn_mode(irn) != mode_T);
86 block = get_nodes_block(irn);
88 /* in case of sub and OUT == SRC2 we can transform the sequence into neg src2 -- add */
89 if (out_reg != in2_reg)
92 /* generate the neg src2 */
93 if(mode_is_float(mode)) {
97 res = new_rd_ia32_xXor(dbg, irg, block, noreg, noreg, in2, noreg_fp, nomem);
98 size = get_mode_size_bits(mode);
99 entity = ia32_gen_fp_known_const(size == 32 ? ia32_SSIGN : ia32_DSIGN);
100 set_ia32_am_sc(res, entity);
101 set_ia32_op_type(res, ia32_AddrModeS);
102 set_ia32_ls_mode(res, get_ia32_ls_mode(irn));
104 res = new_rd_ia32_Neg(dbg, irg, block, in2);
106 arch_set_irn_register(cg->arch_env, res, in2_reg);
108 /* add to schedule */
109 sched_add_before(irn, res);
111 /* generate the add */
112 if (mode_is_float(mode)) {
113 res = new_rd_ia32_xAdd(dbg, irg, block, noreg, noreg, res, in1, nomem);
114 set_ia32_am_support(res, ia32_am_Source, ia32_am_binary);
115 set_ia32_ls_mode(res, get_ia32_ls_mode(irn));
117 res = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, res, in1, nomem);
118 set_ia32_am_support(res, ia32_am_Full, ia32_am_binary);
119 set_ia32_commutative(res);
122 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(cg, irn));
124 slots = get_ia32_slots(res);
127 /* exchange the add and the sub */
128 edges_reroute(irn, res, irg);
130 /* add to schedule */
131 sched_add_before(irn, res);
133 /* remove the old sub */
135 arity = get_irn_arity(irn);
136 for(i = 0; i < arity; ++i) {
137 set_irn_n(irn, i, new_Bad());
140 DBG_OPT_SUB2NEGADD(irn, res);
143 static INLINE int is_noreg(ia32_code_gen_t *cg, const ir_node *node)
145 return node == cg->noreg_gp;
148 static ir_node *create_immediate_from_int(ia32_code_gen_t *cg, int val)
150 ir_graph *irg = current_ir_graph;
151 ir_node *start_block = get_irg_start_block(irg);
152 ir_node *immediate = new_rd_ia32_Immediate(NULL, irg, start_block, NULL,
154 arch_set_irn_register(cg->arch_env, immediate, &ia32_gp_regs[REG_GP_NOREG]);
159 static ir_node *create_immediate_from_am(ia32_code_gen_t *cg,
162 ir_graph *irg = get_irn_irg(node);
163 ir_node *block = get_nodes_block(node);
164 int offset = get_ia32_am_offs_int(node);
165 int sc_sign = is_ia32_am_sc_sign(node);
166 ir_entity *entity = get_ia32_am_sc(node);
169 res = new_rd_ia32_Immediate(NULL, irg, block, entity, sc_sign, offset);
170 arch_set_irn_register(cg->arch_env, res, &ia32_gp_regs[REG_GP_NOREG]);
175 * Transforms a LEA into an Add or SHL if possible.
176 * THIS FUNCTIONS MUST BE CALLED AFTER REGISTER ALLOCATION.
178 static void ia32_transform_lea_to_add_or_shl(ir_node *node, ia32_code_gen_t *cg)
180 const arch_env_t *arch_env = cg->arch_env;
181 ir_graph *irg = current_ir_graph;
184 const arch_register_t *base_reg;
185 const arch_register_t *index_reg;
186 const arch_register_t *out_reg;
197 if(!is_ia32_Lea(node))
200 base = get_irn_n(node, n_ia32_Lea_base);
201 index = get_irn_n(node, n_ia32_Lea_index);
203 if(is_noreg(cg, base)) {
207 base_reg = arch_get_irn_register(arch_env, base);
209 if(is_noreg(cg, index)) {
213 index_reg = arch_get_irn_register(arch_env, index);
216 if(base == NULL && index == NULL) {
217 /* we shouldn't construct these in the first place... */
219 ir_fprintf(stderr, "Optimisation warning: found immediate only lea\n");
224 out_reg = arch_get_irn_register(arch_env, node);
225 scale = get_ia32_am_scale(node);
226 assert(!is_ia32_need_stackent(node) || get_ia32_frame_ent(node) != NULL);
227 /* check if we have immediates values (frame entities should already be
228 * expressed in the offsets) */
229 if(get_ia32_am_offs_int(node) != 0 || get_ia32_am_sc(node) != NULL) {
235 /* we can transform leas where the out register is the same as either the
236 * base or index register back to an Add or Shl */
237 if(out_reg == base_reg) {
240 if(!has_immediates) {
241 ir_fprintf(stderr, "Optimisation warning: found lea which is "
246 op2 = create_immediate_from_am(cg, node);
249 if(scale == 0 && !has_immediates) {
254 /* can't create an add */
256 } else if(out_reg == index_reg) {
258 if(has_immediates && scale == 0) {
260 op2 = create_immediate_from_am(cg, node);
262 } else if(!has_immediates && scale > 0) {
264 op2 = create_immediate_from_int(cg, scale);
266 } else if(!has_immediates) {
268 ir_fprintf(stderr, "Optimisation warning: found lea which is "
272 } else if(scale == 0 && !has_immediates) {
277 /* can't create an add */
280 /* can't create an add */
285 dbgi = get_irn_dbg_info(node);
286 block = get_nodes_block(node);
287 noreg = ia32_new_NoReg_gp(cg);
289 res = new_rd_ia32_Add(dbgi, irg, block, noreg, noreg, op1, op2, nomem);
290 arch_set_irn_register(arch_env, res, out_reg);
291 set_ia32_op_type(res, ia32_Normal);
292 set_ia32_commutative(res);
296 dbgi = get_irn_dbg_info(node);
297 block = get_nodes_block(node);
298 noreg = ia32_new_NoReg_gp(cg);
300 res = new_rd_ia32_Shl(dbgi, irg, block, op1, op2);
301 arch_set_irn_register(arch_env, res, out_reg);
302 set_ia32_op_type(res, ia32_Normal);
306 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(cg, node));
308 /* add new ADD/SHL to schedule */
309 sched_add_before(node, res);
311 DBG_OPT_LEA2ADD(node, res);
313 /* remove the old LEA */
316 /* exchange the Add and the LEA */
320 static INLINE int need_constraint_copy(ir_node *irn) {
321 return ! is_ia32_Lea(irn) &&
322 ! is_ia32_Conv_I2I(irn) &&
323 ! is_ia32_Conv_I2I8Bit(irn) &&
324 ! is_ia32_TestCMov(irn) &&
325 ! is_ia32_CmpCMov(irn);
329 * Insert copies for all ia32 nodes where the should_be_same requirement
331 * Transform Sub into Neg -- Add if IN2 == OUT
333 static void assure_should_be_same_requirements(ia32_code_gen_t *cg,
336 ir_graph *irg = cg->irg;
337 const arch_env_t *arch_env = cg->arch_env;
338 const arch_register_req_t **reqs;
339 const arch_register_t *out_reg, *in_reg;
341 ir_node *in_node, *block;
342 ia32_op_type_t op_tp;
344 if(!is_ia32_irn(node))
347 /* some nodes are just a bit less efficient, but need no fixing if the
348 * should be same requirement is not fulfilled */
349 if(!need_constraint_copy(node))
352 reqs = get_ia32_out_req_all(node);
353 n_res = get_ia32_n_res(node);
354 block = get_nodes_block(node);
356 /* check all OUT requirements, if there is a should_be_same */
357 for (i = 0; i < n_res; i++) {
364 ir_node *uses_out_reg;
365 const arch_register_req_t *req = reqs[i];
366 const arch_register_class_t *class;
367 int uses_out_reg_pos;
369 if (!arch_register_req_is(req, should_be_same))
372 same_pos = req->other_same;
374 /* get in and out register */
375 out_reg = get_ia32_out_reg(node, i);
376 in_node = get_irn_n(node, same_pos);
377 in_reg = arch_get_irn_register(arch_env, in_node);
379 /* requirement already fulfilled? */
380 if (in_reg == out_reg)
382 /* unknowns can be changed to any register we want on emitting */
383 if (is_unknown_reg(in_reg))
385 class = arch_register_get_class(in_reg);
386 assert(class == arch_register_get_class(out_reg));
388 /* check if any other input operands uses the out register */
389 arity = get_irn_arity(node);
391 uses_out_reg_pos = -1;
392 for(i2 = 0; i2 < arity; ++i2) {
393 ir_node *in = get_irn_n(node, i2);
394 const arch_register_t *in_reg = arch_get_irn_register(arch_env, in);
396 if(in_reg != out_reg)
399 if(uses_out_reg != NULL && in != uses_out_reg) {
400 panic("invalid register allocation");
403 if(uses_out_reg_pos >= 0)
404 uses_out_reg_pos = -1; /* multiple inputs... */
406 uses_out_reg_pos = i2;
409 /* noone else is using the out reg, we can simply copy it
410 * (the register can't be live since the operation will override it
412 if(uses_out_reg == NULL) {
413 ir_node *copy = be_new_Copy(class, irg, block, in_node);
414 DBG_OPT_2ADDRCPY(copy);
416 /* destination is the out register */
417 arch_set_irn_register(arch_env, copy, out_reg);
419 /* insert copy before the node into the schedule */
420 sched_add_before(node, copy);
423 set_irn_n(node, same_pos, copy);
425 DBG((dbg, LEVEL_1, "created copy %+F for should be same argument "
426 "at input %d of %+F\n", copy, same_pos, node));
430 /* for commutative nodes we can simply swap the left/right */
431 if(is_ia32_commutative(node) && uses_out_reg_pos == 3) {
432 ia32_swap_left_right(node);
433 DBG((dbg, LEVEL_1, "swapped left/right input of %+F to resolve "
434 "should be same constraint\n", node));
439 ir_fprintf(stderr, "Note: need perm to resolve should_be_same constraint at %+F (this is unsafe and should not happen in theory...)\n", node);
441 /* the out reg is used as node input: we need to permutate our input
442 * and the other (this is allowed, since the other node can't be live
443 * after! the operation as we will override the register. */
445 in[1] = uses_out_reg;
446 perm = be_new_Perm(class, irg, block, 2, in);
448 perm_proj0 = new_r_Proj(irg, block, perm, get_irn_mode(in[0]), 0);
449 perm_proj1 = new_r_Proj(irg, block, perm, get_irn_mode(in[1]), 1);
451 arch_set_irn_register(arch_env, perm_proj0, out_reg);
452 arch_set_irn_register(arch_env, perm_proj1, in_reg);
454 sched_add_before(node, perm);
456 DBG((dbg, LEVEL_1, "created perm %+F for should be same argument "
457 "at input %d of %+F (need permutate with %+F)\n", perm, same_pos,
458 node, uses_out_reg));
460 /* use the perm results */
461 for(i2 = 0; i2 < arity; ++i2) {
462 ir_node *in = get_irn_n(node, i2);
465 set_irn_n(node, i2, perm_proj0);
466 } else if(in == uses_out_reg) {
467 set_irn_n(node, i2, perm_proj1);
472 /* check xCmp: try to avoid unordered cmp */
473 if ((is_ia32_xCmp(node) || is_ia32_xCmpCMov(node) || is_ia32_xCmpSet(node)) &&
474 op_tp == ia32_Normal)
476 long pnc = get_ia32_pncode(node);
478 if (pnc & pn_Cmp_Uo) {
480 int idx1 = 2, idx2 = 3;
482 if (is_ia32_xCmpCMov(node)) {
487 /** Matze: TODO this looks wrong, I assume we should exchange
488 * the proj numbers and not the inputs... */
490 tmp = get_irn_n(node, idx1);
491 set_irn_n(node, idx1, get_irn_n(node, idx2));
492 set_irn_n(node, idx2, tmp);
494 set_ia32_pncode(node, get_negated_pnc(pnc, mode_E));
501 * We have a source address mode node with base or index register equal to
502 * result register and unfulfilled should_be_same requirement. The constraint
503 * handler will insert a copy from the remaining input operand to the result
504 * register -> base or index is broken then.
505 * Solution: Turn back this address mode into explicit Load + Operation.
507 static void fix_am_source(ir_node *irn, void *env) {
508 ia32_code_gen_t *cg = env;
509 const arch_env_t *arch_env = cg->arch_env;
513 const arch_register_t *reg_base;
514 const arch_register_t *reg_index;
515 const arch_register_req_t **reqs;
518 /* check only ia32 nodes with source address mode */
519 if (! is_ia32_irn(irn) || get_ia32_op_type(irn) != ia32_AddrModeS)
521 /* only need to fix binary operations */
522 if (get_ia32_am_arity(irn) != ia32_am_binary)
525 base = get_irn_n(irn, 0);
526 index = get_irn_n(irn, 1);
528 reg_base = arch_get_irn_register(arch_env, base);
529 reg_index = arch_get_irn_register(arch_env, index);
530 reqs = get_ia32_out_req_all(irn);
532 noreg = ia32_new_NoReg_gp(cg);
534 n_res = get_ia32_n_res(irn);
536 for (i = 0; i < n_res; i++) {
537 if (arch_register_req_is(reqs[i], should_be_same)) {
538 /* get in and out register */
539 const arch_register_t *out_reg = get_ia32_out_reg(irn, i);
540 int same_pos = reqs[i]->other_same;
541 ir_node *same_node = get_irn_n(irn, same_pos);
542 const arch_register_t *same_reg
543 = arch_get_irn_register(arch_env, same_node);
544 const arch_register_class_t *same_cls;
545 ir_graph *irg = cg->irg;
546 dbg_info *dbgi = get_irn_dbg_info(irn);
547 ir_node *block = get_nodes_block(irn);
553 /* should_be same constraint is fullfilled, nothing to do */
554 if(out_reg == same_reg)
557 /* we only need to do something if the out reg is the same as base
559 if (out_reg != reg_base && out_reg != reg_index)
562 /* turn back address mode */
563 same_cls = arch_register_get_class(same_reg);
564 if (same_cls == &ia32_reg_classes[CLASS_ia32_gp]) {
565 load = new_rd_ia32_Load(dbgi, irg, block, base, index,
567 assert(get_irn_mode(get_irn_n(irn,4)) == mode_M);
568 pnres = pn_ia32_Load_res;
570 } else if (same_cls == &ia32_reg_classes[CLASS_ia32_xmm]) {
571 load = new_rd_ia32_xLoad(dbgi, irg, block, base, index,
573 get_ia32_ls_mode(irn));
574 assert(get_irn_mode(get_irn_n(irn,4)) == mode_M);
575 pnres = pn_ia32_xLoad_res;
578 panic("cannot turn back address mode for this register class");
581 /* copy address mode information to load */
582 set_ia32_ls_mode(load, get_ia32_ls_mode(irn));
583 set_ia32_op_type(load, ia32_AddrModeS);
584 set_ia32_am_scale(load, get_ia32_am_scale(irn));
585 set_ia32_am_sc(load, get_ia32_am_sc(irn));
586 if(is_ia32_am_sc_sign(irn))
587 set_ia32_am_sc_sign(load);
588 add_ia32_am_offs_int(load, get_ia32_am_offs_int(irn));
589 set_ia32_frame_ent(load, get_ia32_frame_ent(irn));
590 if (is_ia32_use_frame(irn))
591 set_ia32_use_frame(load);
593 /* insert the load into schedule */
594 sched_add_before(irn, load);
596 DBG((dbg, LEVEL_3, "irg %+F: build back AM source for node %+F, inserted load %+F\n", cg->irg, irn, load));
598 load_res = new_r_Proj(cg->irg, block, load, proj_mode, pnres);
599 arch_set_irn_register(cg->arch_env, load_res, out_reg);
601 /* set the new input operand */
602 set_irn_n(irn, 3, load_res);
603 if(get_irn_mode(irn) == mode_T) {
604 const ir_edge_t *edge, *next;
605 foreach_out_edge_safe(irn, edge, next) {
606 ir_node *node = get_edge_src_irn(edge);
607 int pn = get_Proj_proj(node);
612 set_Proj_pred(node, load);
615 set_irn_mode(irn, mode_Iu);
618 /* this is a normal node now */
619 set_irn_n(irn, 0, noreg);
620 set_irn_n(irn, 1, noreg);
621 set_ia32_op_type(irn, ia32_Normal);
628 * Block walker: finishes a block
630 static void ia32_finish_irg_walker(ir_node *block, void *env) {
631 ia32_code_gen_t *cg = env;
634 /* first: turn back AM source if necessary */
635 for (irn = sched_first(block); ! sched_is_end(irn); irn = next) {
636 next = sched_next(irn);
637 fix_am_source(irn, env);
640 for (irn = sched_first(block); ! sched_is_end(irn); irn = next) {
641 ia32_code_gen_t *cg = env;
643 next = sched_next(irn);
645 /* check if there is a sub which need to be transformed */
646 ia32_transform_sub_to_neg_add(irn, cg);
648 /* transform a LEA into an Add if possible */
649 ia32_transform_lea_to_add_or_shl(irn, cg);
652 /* second: insert copies and finish irg */
653 for (irn = sched_first(block); ! sched_is_end(irn); irn = next) {
654 next = sched_next(irn);
655 assure_should_be_same_requirements(cg, irn);
660 * Block walker: pushes all blocks on a wait queue
662 static void ia32_push_on_queue_walker(ir_node *block, void *env) {
664 waitq_put(wq, block);
669 * Add Copy nodes for not fulfilled should_be_equal constraints
671 void ia32_finish_irg(ir_graph *irg, ia32_code_gen_t *cg) {
672 waitq *wq = new_waitq();
674 /* Push the blocks on the waitq because ia32_finish_irg_walker starts more walks ... */
675 irg_block_walk_graph(irg, NULL, ia32_push_on_queue_walker, wq);
677 while (! waitq_empty(wq)) {
678 ir_node *block = waitq_get(wq);
679 ia32_finish_irg_walker(block, cg);
684 void ia32_init_finish(void)
686 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.finish");