2 * This file is part of libFirm.
3 * Copyright (C) 2012 University of Karlsruhe.
8 * @brief This file implements functions to finalize the irg for emit.
9 * @author Christian Wuerdig
21 #include "firmstat_t.h"
27 #include "bearch_ia32_t.h"
28 #include "ia32_finish.h"
29 #include "ia32_new_nodes.h"
30 #include "ia32_common_transform.h"
31 #include "ia32_transform.h"
32 #include "ia32_dbg_stat.h"
33 #include "ia32_optimize.h"
34 #include "gen_ia32_regalloc_if.h"
36 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
39 * Transforms a Sub or xSub into Neg--Add iff OUT_REG != SRC1_REG && OUT_REG == SRC2_REG.
40 * THIS FUNCTIONS MUST BE CALLED AFTER REGISTER ALLOCATION.
42 static void ia32_transform_sub_to_neg_add(ir_node *irn)
45 ir_node *in1, *in2, *noreg, *nomem, *res;
46 ir_node *noreg_fp, *block;
48 const arch_register_t *in1_reg, *in2_reg, *out_reg;
50 /* fix_am will solve this for AddressMode variants */
51 if (get_ia32_op_type(irn) != ia32_Normal)
54 irg = get_irn_irg(irn);
55 noreg = ia32_new_NoReg_gp(irg);
56 noreg_fp = ia32_new_NoReg_xmm(irg);
57 nomem = get_irg_no_mem(irg);
58 in1 = get_irn_n(irn, n_ia32_binary_left);
59 in2 = get_irn_n(irn, n_ia32_binary_right);
60 in1_reg = arch_get_irn_register(in1);
61 in2_reg = arch_get_irn_register(in2);
62 out_reg = arch_get_irn_register_out(irn, 0);
64 if (out_reg == in1_reg)
67 /* in case of sub and OUT == SRC2 we can transform the sequence into neg src2 -- add */
68 if (out_reg != in2_reg)
71 block = get_nodes_block(irn);
72 dbgi = get_irn_dbg_info(irn);
74 /* generate the neg src2 */
75 if (is_ia32_xSub(irn)) {
78 ir_mode *op_mode = get_ia32_ls_mode(irn);
80 assert(get_irn_mode(irn) != mode_T);
82 res = new_bd_ia32_xXor(dbgi, block, noreg, noreg, nomem, in2, noreg_fp);
83 size = get_mode_size_bits(op_mode);
84 entity = ia32_gen_fp_known_const(size == 32 ? ia32_SSIGN : ia32_DSIGN);
85 set_ia32_am_sc(res, entity);
86 set_ia32_op_type(res, ia32_AddrModeS);
87 set_ia32_ls_mode(res, op_mode);
89 arch_set_irn_register(res, in2_reg);
92 sched_add_before(irn, res);
94 /* generate the add */
95 res = new_bd_ia32_xAdd(dbgi, block, noreg, noreg, nomem, res, in1);
96 set_ia32_ls_mode(res, get_ia32_ls_mode(irn));
98 ir_node *flags_proj = NULL;
101 if (get_irn_mode(irn) == mode_T) {
102 /* collect the Proj uses */
103 foreach_out_edge(irn, edge) {
104 ir_node *proj = get_edge_src_irn(edge);
105 long pn = get_Proj_proj(proj);
106 if (pn == pn_ia32_flags) {
107 assert(flags_proj == NULL);
114 if (is_ia32_Sbb(irn)) {
115 /* Feed borrow (in CF) as carry (via CMC) into NOT+ADC. */
116 carry = get_irn_n(irn, n_ia32_Sbb_eflags);
117 carry = new_bd_ia32_Cmc(dbgi, block, carry);
119 } else if (flags_proj != 0) {
121 * ARG, the above technique does NOT set the flags right.
122 * So, we must produce the following code:
124 * t2 = a + ~b + Carry
127 * a + -b = a + (~b + 1) would set the carry flag wrong IFF both a and b are zero.
134 carry = new_bd_ia32_Stc(dbgi, block);
137 nnot = new_bd_ia32_Not(dbgi, block, in2);
138 arch_set_irn_register(nnot, in2_reg);
139 sched_add_before(irn, nnot);
141 arch_set_irn_register(carry, &ia32_registers[REG_EFLAGS]);
142 sched_add_before(irn, carry);
144 adc = new_bd_ia32_Adc(dbgi, block, noreg, noreg, nomem, nnot, in1, carry);
145 arch_set_irn_register(adc, out_reg);
146 set_ia32_commutative(adc);
148 if (flags_proj != NULL) {
149 set_irn_mode(adc, mode_T);
150 adc_flags = new_r_Proj(adc, mode_Iu, pn_ia32_Adc_flags);
151 arch_set_irn_register(adc_flags, &ia32_registers[REG_EFLAGS]);
153 cmc = new_bd_ia32_Cmc(dbgi, block, adc_flags);
154 arch_set_irn_register(cmc, &ia32_registers[REG_EFLAGS]);
155 sched_add_after(irn, cmc);
156 exchange(flags_proj, cmc);
161 res = new_bd_ia32_Neg(dbgi, block, in2);
162 arch_set_irn_register(res, in2_reg);
164 /* add to schedule */
165 sched_add_before(irn, res);
167 /* generate the add */
168 res = new_bd_ia32_Add(dbgi, block, noreg, noreg, nomem, res, in1);
169 arch_set_irn_register(res, out_reg);
170 set_ia32_commutative(res);
174 /* exchange the add and the sub */
175 edges_reroute(irn, res);
176 sched_replace(irn, res);
178 set_irn_mode(res, get_irn_mode(irn));
180 SET_IA32_ORIG_NODE(res, irn);
182 /* remove the old sub */
185 DBG_OPT_SUB2NEGADD(irn, res);
188 static inline int need_constraint_copy(ir_node *irn)
190 /* TODO this should be determined from the node specification */
191 switch (get_ia32_irn_opcode(irn)) {
192 case iro_ia32_IMul: {
193 /* the 3 operand form of IMul needs no constraint copy */
194 ir_node *right = get_irn_n(irn, n_ia32_IMul_right);
195 return !is_ia32_Immediate(right);
199 case iro_ia32_Conv_I2I:
200 case iro_ia32_CMovcc:
201 case iro_ia32_Minus64Bit:
210 * Returns the index of the "same" register.
211 * On the x86, we should have only one.
213 static int get_first_same(const arch_register_req_t* req)
215 const unsigned other = req->other_same;
218 for (i = 0; i < 32; ++i) {
219 if (other & (1U << i)) return i;
221 panic("same position not found");
225 * Insert copies for all ia32 nodes where the should_be_same requirement
227 * Transform Sub into Neg -- Add if IN2 == OUT
229 static void assure_should_be_same_requirements(ir_node *node)
231 const arch_register_t *out_reg, *in_reg;
232 ir_node *in_node, *block;
234 block = get_nodes_block(node);
236 /* check all OUT requirements, if there is a should_be_same */
237 be_foreach_out(node, i) {
240 ir_node *uses_out_reg;
241 const arch_register_req_t *req = arch_get_irn_register_req_out(node, i);
242 int uses_out_reg_pos;
244 if (!arch_register_req_is(req, should_be_same))
247 same_pos = get_first_same(req);
249 /* get in and out register */
250 out_reg = arch_get_irn_register_out(node, i);
251 in_node = get_irn_n(node, same_pos);
252 in_reg = arch_get_irn_register(in_node);
254 /* requirement already fulfilled? */
255 if (in_reg == out_reg)
257 assert(in_reg->reg_class == out_reg->reg_class);
259 /* check if any other input operands uses the out register */
260 arity = get_irn_arity(node);
262 uses_out_reg_pos = -1;
263 for (i2 = 0; i2 < arity; ++i2) {
264 ir_node *in = get_irn_n(node, i2);
265 const arch_register_t *other_in_reg;
267 if (!mode_is_data(get_irn_mode(in)))
270 other_in_reg = arch_get_irn_register(in);
272 if (other_in_reg != out_reg)
275 if (uses_out_reg != NULL && in != uses_out_reg) {
276 panic("invalid register allocation");
279 if (uses_out_reg_pos >= 0)
280 uses_out_reg_pos = -1; /* multiple inputs... */
282 uses_out_reg_pos = i2;
285 /* no-one else is using the out reg, we can simply copy it
286 * (the register can't be live since the operation will override it
288 if (uses_out_reg == NULL) {
289 ir_node *copy = be_new_Copy(block, in_node);
290 DBG_OPT_2ADDRCPY(copy);
292 /* destination is the out register */
293 arch_set_irn_register(copy, out_reg);
295 /* insert copy before the node into the schedule */
296 sched_add_before(node, copy);
299 set_irn_n(node, same_pos, copy);
302 "created copy %+F for should be same argument at input %d of %+F\n",
303 copy, same_pos, node));
307 /* for commutative nodes we can simply swap the left/right */
308 if (uses_out_reg_pos == n_ia32_binary_right && is_ia32_commutative(node)) {
309 ia32_swap_left_right(node);
311 "swapped left/right input of %+F to resolve should be same constraint\n",
316 panic("Unresolved should_be_same constraint");
322 * We have a source address mode node with base or index register equal to
323 * result register and unfulfilled should_be_same requirement. The constraint
324 * handler will insert a copy from the remaining input operand to the result
325 * register -> base or index is broken then.
326 * Solution: Turn back this address mode into explicit Load + Operation.
328 static void fix_am_source(ir_node *irn)
330 /* check only ia32 nodes with source address mode */
331 if (!is_ia32_irn(irn) || get_ia32_op_type(irn) != ia32_AddrModeS)
333 /* only need to fix binary operations */
334 if (get_ia32_am_support(irn) != ia32_am_binary)
337 be_foreach_out(irn, i) {
338 const arch_register_req_t *req = arch_get_irn_register_req_out(irn, i);
339 const arch_register_t *out_reg;
342 const arch_register_t *same_reg;
345 if (!arch_register_req_is(req, should_be_same))
348 /* get in and out register */
349 out_reg = arch_get_irn_register_out(irn, i);
350 same_pos = get_first_same(req);
351 same_node = get_irn_n(irn, same_pos);
352 same_reg = arch_get_irn_register(same_node);
354 /* should_be same constraint is fullfilled, nothing to do */
355 if (out_reg == same_reg)
358 /* we only need to do something if the out reg is the same as base
360 if (out_reg != arch_get_irn_register(get_irn_n(irn, n_ia32_base)) &&
361 out_reg != arch_get_irn_register(get_irn_n(irn, n_ia32_index)))
364 load_res = ia32_turn_back_am(irn);
365 arch_set_irn_register(load_res, out_reg);
368 "irg %+F: build back AM source for node %+F, inserted load %+F\n",
369 get_irn_irg(irn), irn, get_Proj_pred(load_res)));
375 * Block walker: finishes a block
377 static void ia32_finish_irg_walker(ir_node *block, void *env)
381 /* first: turn back AM source if necessary */
382 sched_foreach_safe(block, irn) {
386 sched_foreach_safe(block, irn) {
387 /* check if there is a sub which need to be transformed */
388 if (is_ia32_Sub(irn) || is_ia32_Sbb(irn) || is_ia32_xSub(irn)) {
389 ia32_transform_sub_to_neg_add(irn);
393 /* second: insert copies and finish irg */
394 sched_foreach_safe(block, irn) {
395 if (is_ia32_irn(irn)) {
396 /* some nodes are just a bit less efficient, but need no fixing if the
397 * should be same requirement is not fulfilled */
398 if (need_constraint_copy(irn))
399 assure_should_be_same_requirements(irn);
405 * Block walker: pushes all blocks on a wait queue
407 static void ia32_push_on_queue_walker(ir_node *block, void *env)
409 waitq *wq = (waitq*)env;
410 waitq_put(wq, block);
415 * Add Copy nodes for not fulfilled should_be_equal constraints
417 void ia32_finish_irg(ir_graph *irg)
419 waitq *wq = new_waitq();
421 /* Push the blocks on the waitq because ia32_finish_irg_walker starts more walks ... */
422 irg_block_walk_graph(irg, NULL, ia32_push_on_queue_walker, wq);
424 while (! waitq_empty(wq)) {
425 ir_node *block = (ir_node*)waitq_get(wq);
426 ia32_finish_irg_walker(block, NULL);
431 void ia32_init_finish(void)
433 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.finish");