2 * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This file implements functions to finalize the irg for emit.
23 * @author Christian Wuerdig
39 #include "../bearch_t.h"
40 #include "../besched_t.h"
41 #include "../benode_t.h"
43 #include "bearch_ia32_t.h"
44 #include "ia32_finish.h"
45 #include "ia32_new_nodes.h"
46 #include "ia32_map_regs.h"
47 #include "ia32_common_transform.h"
48 #include "ia32_transform.h"
49 #include "ia32_dbg_stat.h"
50 #include "ia32_optimize.h"
51 #include "gen_ia32_regalloc_if.h"
53 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
56 * Transforms a Sub or xSub into Neg--Add iff OUT_REG == SRC2_REG.
57 * THIS FUNCTIONS MUST BE CALLED AFTER REGISTER ALLOCATION.
59 static void ia32_transform_sub_to_neg_add(ir_node *irn, ia32_code_gen_t *cg) {
61 ir_node *in1, *in2, *noreg, *nomem, *res;
62 ir_node *noreg_fp, *block;
64 const arch_register_t *in1_reg, *in2_reg, *out_reg;
66 /* fix_am will solve this for AddressMode variants */
67 if (get_ia32_op_type(irn) != ia32_Normal)
70 noreg = ia32_new_NoReg_gp(cg);
71 noreg_fp = ia32_new_NoReg_xmm(cg);
72 nomem = new_rd_NoMem(cg->irg);
73 in1 = get_irn_n(irn, n_ia32_binary_left);
74 in2 = get_irn_n(irn, n_ia32_binary_right);
75 in1_reg = arch_get_irn_register(cg->arch_env, in1);
76 in2_reg = arch_get_irn_register(cg->arch_env, in2);
77 out_reg = get_ia32_out_reg(irn, 0);
80 block = get_nodes_block(irn);
82 /* in case of sub and OUT == SRC2 we can transform the sequence into neg src2 -- add */
83 if (out_reg != in2_reg)
86 dbg = get_irn_dbg_info(irn);
88 /* generate the neg src2 */
89 if (is_ia32_xSub(irn)) {
92 ir_mode *op_mode = get_ia32_ls_mode(irn);
94 assert(get_irn_mode(irn) != mode_T);
96 res = new_rd_ia32_xXor(dbg, irg, block, noreg, noreg, nomem, in2, noreg_fp);
97 size = get_mode_size_bits(op_mode);
98 entity = ia32_gen_fp_known_const(size == 32 ? ia32_SSIGN : ia32_DSIGN);
99 set_ia32_am_sc(res, entity);
100 set_ia32_op_type(res, ia32_AddrModeS);
101 set_ia32_ls_mode(res, op_mode);
103 arch_set_irn_register(cg->arch_env, res, in2_reg);
105 /* add to schedule */
106 sched_add_before(irn, res);
108 /* generate the add */
109 res = new_rd_ia32_xAdd(dbg, irg, block, noreg, noreg, nomem, res, in1);
110 set_ia32_ls_mode(res, get_ia32_ls_mode(irn));
112 /* exchange the add and the sub */
113 edges_reroute(irn, res, irg);
115 /* add to schedule */
116 sched_add_before(irn, res);
118 ir_node *res_proj = NULL;
119 ir_node *flags_proj = NULL;
120 const ir_edge_t *edge;
122 if (get_irn_mode(irn) == mode_T) {
123 /* collect the Proj uses */
124 foreach_out_edge(irn, edge) {
125 ir_node *proj = get_edge_src_irn(edge);
126 long pn = get_Proj_proj(proj);
127 if(pn == pn_ia32_Sub_res) {
128 assert(res_proj == NULL);
131 assert(pn == pn_ia32_Sub_flags);
132 assert(flags_proj == NULL);
138 if (flags_proj == NULL) {
139 res = new_rd_ia32_Neg(dbg, irg, block, in2);
140 arch_set_irn_register(cg->arch_env, res, in2_reg);
142 /* add to schedule */
143 sched_add_before(irn, res);
145 /* generate the add */
146 res = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, nomem, res, in1);
147 arch_set_irn_register(cg->arch_env, res, out_reg);
148 set_ia32_commutative(res);
150 /* exchange the add and the sub */
151 edges_reroute(irn, res, irg);
153 /* add to schedule */
154 sched_add_before(irn, res);
156 ir_node *stc, *cmc, *not, *adc;
160 * ARG, the above technique does NOT set the flags right.
161 * So, we must produce the following code:
163 * t2 = a + ~b + Carry
166 * a + -b = a + (~b + 1) would set the carry flag IF a == b ...
168 not = new_rd_ia32_Not(dbg, irg, block, in2);
169 arch_set_irn_register(cg->arch_env, not, in2_reg);
170 sched_add_before(irn, not);
172 stc = new_rd_ia32_Stc(dbg, irg, block);
173 arch_set_irn_register(cg->arch_env, stc,
174 &ia32_flags_regs[REG_EFLAGS]);
175 sched_add_before(irn, stc);
177 adc = new_rd_ia32_Adc(dbg, irg, block, noreg, noreg, nomem, not,
179 arch_set_irn_register(cg->arch_env, adc, out_reg);
180 sched_add_before(irn, adc);
182 set_irn_mode(adc, mode_T);
183 adc_flags = new_r_Proj(irg, block, adc, mode_Iu, pn_ia32_Adc_flags);
184 arch_set_irn_register(cg->arch_env, adc_flags,
185 &ia32_flags_regs[REG_EFLAGS]);
187 cmc = new_rd_ia32_Cmc(dbg, irg, block, adc_flags);
188 arch_set_irn_register(cg->arch_env, cmc,
189 &ia32_flags_regs[REG_EFLAGS]);
190 sched_add_before(irn, cmc);
192 exchange(flags_proj, cmc);
193 if (res_proj != NULL) {
194 set_Proj_pred(res_proj, adc);
195 set_Proj_proj(res_proj, pn_ia32_Adc_res);
202 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(cg, irn));
204 /* remove the old sub */
208 DBG_OPT_SUB2NEGADD(irn, res);
211 static INLINE int need_constraint_copy(ir_node *irn) {
212 /* the 3 operand form of IMul needs no constraint copy */
213 if(is_ia32_IMul(irn)) {
214 ir_node *right = get_irn_n(irn, n_ia32_IMul_right);
215 if(is_ia32_Immediate(right))
219 return ! is_ia32_Lea(irn) &&
220 ! is_ia32_Conv_I2I(irn) &&
221 ! is_ia32_Conv_I2I8Bit(irn) &&
226 * Returns the index of the "same" register.
227 * On the x86, we should have only one.
229 static int get_first_same(const arch_register_req_t* req)
231 const unsigned other = req->other_same;
234 for (i = 0; i < 32; ++i) {
235 if (other & (1U << i)) return i;
237 assert(! "same position not found");
242 * Insert copies for all ia32 nodes where the should_be_same requirement
244 * Transform Sub into Neg -- Add if IN2 == OUT
246 static void assure_should_be_same_requirements(ia32_code_gen_t *cg,
249 ir_graph *irg = cg->irg;
250 const arch_env_t *arch_env = cg->arch_env;
251 const arch_register_req_t **reqs;
252 const arch_register_t *out_reg, *in_reg;
254 ir_node *in_node, *block;
256 reqs = get_ia32_out_req_all(node);
257 n_res = get_ia32_n_res(node);
258 block = get_nodes_block(node);
260 /* check all OUT requirements, if there is a should_be_same */
261 for (i = 0; i < n_res; i++) {
268 ir_node *uses_out_reg;
269 const arch_register_req_t *req = reqs[i];
270 const arch_register_class_t *cls;
271 int uses_out_reg_pos;
273 if (!arch_register_req_is(req, should_be_same))
276 same_pos = get_first_same(req);
278 /* get in and out register */
279 out_reg = get_ia32_out_reg(node, i);
280 in_node = get_irn_n(node, same_pos);
281 in_reg = arch_get_irn_register(arch_env, in_node);
283 /* requirement already fulfilled? */
284 if (in_reg == out_reg)
286 /* unknowns can be changed to any register we want on emitting */
287 if (is_unknown_reg(in_reg))
289 cls = arch_register_get_class(in_reg);
290 assert(cls == arch_register_get_class(out_reg));
292 /* check if any other input operands uses the out register */
293 arity = get_irn_arity(node);
295 uses_out_reg_pos = -1;
296 for(i2 = 0; i2 < arity; ++i2) {
297 ir_node *in = get_irn_n(node, i2);
298 const arch_register_t *in_reg;
300 if(!mode_is_data(get_irn_mode(in)))
303 in_reg = arch_get_irn_register(arch_env, in);
305 if(in_reg != out_reg)
308 if(uses_out_reg != NULL && in != uses_out_reg) {
309 panic("invalid register allocation");
312 if(uses_out_reg_pos >= 0)
313 uses_out_reg_pos = -1; /* multiple inputs... */
315 uses_out_reg_pos = i2;
318 /* no-one else is using the out reg, we can simply copy it
319 * (the register can't be live since the operation will override it
321 if(uses_out_reg == NULL) {
322 ir_node *copy = be_new_Copy(cls, irg, block, in_node);
323 DBG_OPT_2ADDRCPY(copy);
325 /* destination is the out register */
326 arch_set_irn_register(arch_env, copy, out_reg);
328 /* insert copy before the node into the schedule */
329 sched_add_before(node, copy);
332 set_irn_n(node, same_pos, copy);
334 DBG((dbg, LEVEL_1, "created copy %+F for should be same argument "
335 "at input %d of %+F\n", copy, same_pos, node));
339 /* for commutative nodes we can simply swap the left/right */
340 if (uses_out_reg_pos == n_ia32_binary_right && is_ia32_commutative(node)) {
341 ia32_swap_left_right(node);
342 DBG((dbg, LEVEL_1, "swapped left/right input of %+F to resolve "
343 "should be same constraint\n", node));
348 ir_fprintf(stderr, "Note: need perm to resolve should_be_same constraint at %+F (this is unsafe and should not happen in theory...)\n", node);
350 /* the out reg is used as node input: we need to permutate our input
351 * and the other (this is allowed, since the other node can't be live
352 * after! the operation as we will override the register. */
354 in[1] = uses_out_reg;
355 perm = be_new_Perm(cls, irg, block, 2, in);
357 perm_proj0 = new_r_Proj(irg, block, perm, get_irn_mode(in[0]), 0);
358 perm_proj1 = new_r_Proj(irg, block, perm, get_irn_mode(in[1]), 1);
360 arch_set_irn_register(arch_env, perm_proj0, out_reg);
361 arch_set_irn_register(arch_env, perm_proj1, in_reg);
363 sched_add_before(node, perm);
365 DBG((dbg, LEVEL_1, "created perm %+F for should be same argument "
366 "at input %d of %+F (need permutate with %+F)\n", perm, same_pos,
367 node, uses_out_reg));
369 /* use the perm results */
370 for(i2 = 0; i2 < arity; ++i2) {
371 ir_node *in = get_irn_n(node, i2);
374 set_irn_n(node, i2, perm_proj0);
375 } else if(in == uses_out_reg) {
376 set_irn_n(node, i2, perm_proj1);
384 * We have a source address mode node with base or index register equal to
385 * result register and unfulfilled should_be_same requirement. The constraint
386 * handler will insert a copy from the remaining input operand to the result
387 * register -> base or index is broken then.
388 * Solution: Turn back this address mode into explicit Load + Operation.
390 static void fix_am_source(ir_node *irn, void *env)
392 ia32_code_gen_t *cg = env;
393 const arch_env_t *arch_env = cg->arch_env;
397 const arch_register_t *reg_base;
398 const arch_register_t *reg_index;
399 const arch_register_req_t **reqs;
402 /* check only ia32 nodes with source address mode */
403 if (! is_ia32_irn(irn) || get_ia32_op_type(irn) != ia32_AddrModeS)
405 /* only need to fix binary operations */
406 if (get_ia32_am_arity(irn) != ia32_am_binary)
409 base = get_irn_n(irn, n_ia32_base);
410 index = get_irn_n(irn, n_ia32_index);
412 reg_base = arch_get_irn_register(arch_env, base);
413 reg_index = arch_get_irn_register(arch_env, index);
414 reqs = get_ia32_out_req_all(irn);
416 noreg = ia32_new_NoReg_gp(cg);
418 n_res = get_ia32_n_res(irn);
420 for (i = 0; i < n_res; i++) {
421 if (arch_register_req_is(reqs[i], should_be_same)) {
422 /* get in and out register */
423 const arch_register_t *out_reg = get_ia32_out_reg(irn, i);
424 int same_pos = get_first_same(reqs[i]);
425 ir_node *same_node = get_irn_n(irn, same_pos);
426 const arch_register_t *same_reg
427 = arch_get_irn_register(arch_env, same_node);
428 const arch_register_class_t *same_cls;
429 ir_graph *irg = cg->irg;
430 dbg_info *dbgi = get_irn_dbg_info(irn);
431 ir_node *block = get_nodes_block(irn);
439 /* should_be same constraint is fullfilled, nothing to do */
440 if(out_reg == same_reg)
443 /* we only need to do something if the out reg is the same as base
445 if (out_reg != reg_base && out_reg != reg_index)
448 /* turn back address mode */
449 same_cls = arch_register_get_class(same_reg);
450 mem = get_irn_n(irn, n_ia32_mem);
451 assert(get_irn_mode(mem) == mode_M);
452 if (same_cls == &ia32_reg_classes[CLASS_ia32_gp]) {
453 load = new_rd_ia32_Load(dbgi, irg, block, base, index, mem);
454 pnres = pn_ia32_Load_res;
455 pnmem = pn_ia32_Load_M;
457 } else if (same_cls == &ia32_reg_classes[CLASS_ia32_xmm]) {
458 load = new_rd_ia32_xLoad(dbgi, irg, block, base, index, mem,
459 get_ia32_ls_mode(irn));
460 pnres = pn_ia32_xLoad_res;
461 pnmem = pn_ia32_xLoad_M;
464 panic("cannot turn back address mode for this register class");
467 /* copy address mode information to load */
468 set_ia32_op_type(load, ia32_AddrModeS);
469 ia32_copy_am_attrs(load, irn);
470 if (is_ia32_is_reload(irn))
471 set_ia32_is_reload(load);
473 /* insert the load into schedule */
474 sched_add_before(irn, load);
476 DBG((dbg, LEVEL_3, "irg %+F: build back AM source for node %+F, inserted load %+F\n", cg->irg, irn, load));
478 load_res = new_r_Proj(cg->irg, block, load, proj_mode, pnres);
479 arch_set_irn_register(cg->arch_env, load_res, out_reg);
481 /* set the new input operand */
482 set_irn_n(irn, n_ia32_binary_right, load_res);
483 if(get_irn_mode(irn) == mode_T) {
484 const ir_edge_t *edge, *next;
485 foreach_out_edge_safe(irn, edge, next) {
486 ir_node *node = get_edge_src_irn(edge);
487 int pn = get_Proj_proj(node);
488 if (pn == pn_ia32_res) {
490 } else if (pn == pn_ia32_mem) {
491 set_Proj_pred(node, load);
492 set_Proj_proj(node, pnmem);
494 panic("Unexpected Proj");
497 set_irn_mode(irn, mode_Iu);
500 /* this is a normal node now */
501 set_irn_n(irn, n_ia32_base, noreg);
502 set_irn_n(irn, n_ia32_index, noreg);
503 set_ia32_op_type(irn, ia32_Normal);
510 * Block walker: finishes a block
512 static void ia32_finish_irg_walker(ir_node *block, void *env) {
513 ia32_code_gen_t *cg = env;
516 /* first: turn back AM source if necessary */
517 for (irn = sched_first(block); ! sched_is_end(irn); irn = next) {
518 next = sched_next(irn);
519 fix_am_source(irn, env);
522 for (irn = sched_first(block); ! sched_is_end(irn); irn = next) {
523 ia32_code_gen_t *cg = env;
525 next = sched_next(irn);
527 /* check if there is a sub which need to be transformed */
528 if (is_ia32_Sub(irn) || is_ia32_xSub(irn)) {
529 ia32_transform_sub_to_neg_add(irn, cg);
533 /* second: insert copies and finish irg */
534 for (irn = sched_first(block); ! sched_is_end(irn); irn = next) {
535 next = sched_next(irn);
536 if (is_ia32_irn(irn)) {
537 /* some nodes are just a bit less efficient, but need no fixing if the
538 * should be same requirement is not fulfilled */
539 if (need_constraint_copy(irn))
540 assure_should_be_same_requirements(cg, irn);
546 * Block walker: pushes all blocks on a wait queue
548 static void ia32_push_on_queue_walker(ir_node *block, void *env) {
550 waitq_put(wq, block);
555 * Add Copy nodes for not fulfilled should_be_equal constraints
557 void ia32_finish_irg(ir_graph *irg, ia32_code_gen_t *cg) {
558 waitq *wq = new_waitq();
560 /* Push the blocks on the waitq because ia32_finish_irg_walker starts more walks ... */
561 irg_block_walk_graph(irg, NULL, ia32_push_on_queue_walker, wq);
563 while (! waitq_empty(wq)) {
564 ir_node *block = waitq_get(wq);
565 ia32_finish_irg_walker(block, cg);
570 void ia32_init_finish(void)
572 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.finish");