2 * This file implements functions to finalize the irg for emit.
3 * @author Christian Wuerdig
17 #include "../bearch.h"
18 #include "../besched_t.h"
19 #include "../benode_t.h"
21 #include "bearch_ia32_t.h"
22 #include "ia32_finish.h"
23 #include "ia32_new_nodes.h"
24 #include "ia32_map_regs.h"
25 #include "ia32_transform.h"
26 #include "ia32_dbg_stat.h"
27 #include "ia32_optimize.h"
28 #include "gen_ia32_regalloc_if.h"
31 * Transforms a Sub or xSub into Neg--Add iff OUT_REG == SRC2_REG.
32 * THIS FUNCTIONS MUST BE CALLED AFTER REGISTER ALLOCATION.
34 static void ia32_transform_sub_to_neg_add(ir_node *irn, ia32_code_gen_t *cg) {
35 ia32_transform_env_t tenv;
36 ir_node *in1, *in2, *noreg, *nomem, *res;
37 const arch_register_t *in1_reg, *in2_reg, *out_reg, **slots;
39 /* Return if AM node or not a Sub or xSub */
40 if (!(is_ia32_Sub(irn) || is_ia32_xSub(irn)) || get_ia32_op_type(irn) != ia32_Normal)
43 noreg = ia32_new_NoReg_gp(cg);
44 nomem = new_rd_NoMem(cg->irg);
45 in1 = get_irn_n(irn, 2);
46 in2 = get_irn_n(irn, 3);
47 in1_reg = arch_get_irn_register(cg->arch_env, in1);
48 in2_reg = arch_get_irn_register(cg->arch_env, in2);
49 out_reg = get_ia32_out_reg(irn, 0);
51 tenv.block = get_nodes_block(irn);
52 tenv.dbg = get_irn_dbg_info(irn);
55 tenv.mode = get_ia32_res_mode(irn);
57 DEBUG_ONLY(tenv.mod = cg->mod;)
59 /* in case of sub and OUT == SRC2 we can transform the sequence into neg src2 -- add */
60 if (REGS_ARE_EQUAL(out_reg, in2_reg)) {
61 /* generate the neg src2 */
62 res = gen_Minus_ex(&tenv, in2);
63 arch_set_irn_register(cg->arch_env, res, in2_reg);
66 sched_add_before(irn, get_Proj_pred(res));
67 sched_add_before(irn, res);
69 /* generate the add */
70 if (mode_is_float(tenv.mode)) {
71 res = new_rd_ia32_xAdd(tenv.dbg, tenv.irg, tenv.block, noreg, noreg, res, in1, nomem);
72 set_ia32_am_support(res, ia32_am_Source);
75 res = new_rd_ia32_Add(tenv.dbg, tenv.irg, tenv.block, noreg, noreg, res, in1, nomem);
76 set_ia32_am_support(res, ia32_am_Full);
77 set_ia32_commutative(res);
79 set_ia32_res_mode(res, tenv.mode);
81 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(tenv.cg, irn));
83 slots = get_ia32_slots(res);
87 sched_add_before(irn, res);
89 /* remove the old sub */
92 DBG_OPT_SUB2NEGADD(irn, res);
94 /* exchange the add and the sub */
100 * Transforms a LEA into an Add if possible
101 * THIS FUNCTIONS MUST BE CALLED AFTER REGISTER ALLOCATION.
103 static void ia32_transform_lea_to_add(ir_node *irn, ia32_code_gen_t *cg) {
104 ia32_am_flavour_t am_flav;
107 ir_node *nomem, *noreg, *base, *index, *op1, *op2;
108 const char *offs = NULL;
109 ia32_transform_env_t tenv;
110 const arch_register_t *out_reg, *base_reg, *index_reg;
111 int imm_tp = ia32_ImmConst;
114 if (! is_ia32_Lea(irn))
117 am_flav = get_ia32_am_flavour(irn);
119 if (get_ia32_am_sc(irn))
122 /* only some LEAs can be transformed to an Add */
123 if (am_flav != ia32_am_B && am_flav != ia32_am_OB && am_flav != ia32_am_OI && am_flav != ia32_am_BI)
126 noreg = ia32_new_NoReg_gp(cg);
127 nomem = new_rd_NoMem(cg->irg);
130 base = get_irn_n(irn, 0);
131 index = get_irn_n(irn,1);
133 if (am_flav & ia32_O) {
134 offs = get_ia32_am_offs(irn);
137 ident *id = get_ia32_am_sc(irn);
140 offs = get_id_str(id);
141 imm_tp = ia32_ImmSymConst;
143 /* offset has a explicit sign -> we need to skip + */
144 else if (offs[0] == '+')
148 out_reg = arch_get_irn_register(cg->arch_env, irn);
149 base_reg = arch_get_irn_register(cg->arch_env, base);
150 index_reg = arch_get_irn_register(cg->arch_env, index);
152 tenv.block = get_nodes_block(irn);
153 tenv.dbg = get_irn_dbg_info(irn);
156 DEBUG_ONLY(tenv.mod = cg->mod;)
157 tenv.mode = get_irn_mode(irn);
160 switch(get_ia32_am_flavour(irn)) {
162 /* out register must be same as base register */
163 if (! REGS_ARE_EQUAL(out_reg, base_reg))
169 /* out register must be same as base register */
170 if (! REGS_ARE_EQUAL(out_reg, base_reg))
177 /* out register must be same as index register */
178 if (! REGS_ARE_EQUAL(out_reg, index_reg))
185 /* out register must be same as one in register */
186 if (REGS_ARE_EQUAL(out_reg, base_reg)) {
190 else if (REGS_ARE_EQUAL(out_reg, index_reg)) {
195 /* in registers a different from out -> no Add possible */
202 res = new_rd_ia32_Add(tenv.dbg, tenv.irg, tenv.block, noreg, noreg, op1, op2, nomem);
203 arch_set_irn_register(cg->arch_env, res, out_reg);
204 set_ia32_op_type(res, ia32_Normal);
205 set_ia32_commutative(res);
206 set_ia32_res_mode(res, tenv.mode);
209 set_ia32_cnst(res, offs);
210 set_ia32_immop_type(res, imm_tp);
213 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(cg, irn));
215 /* add Add to schedule */
216 sched_add_before(irn, res);
218 DBG_OPT_LEA2ADD(irn, res);
220 res = new_rd_Proj(tenv.dbg, tenv.irg, tenv.block, res, tenv.mode, pn_ia32_Add_res);
222 /* add result Proj to schedule */
223 sched_add_before(irn, res);
225 /* remove the old LEA */
228 /* exchange the Add and the LEA */
232 static INLINE int need_constraint_copy(ir_node *irn) {
234 ! is_ia32_Lea(irn) && \
235 ! is_ia32_Conv_I2I(irn) && \
236 ! is_ia32_Conv_I2I8Bit(irn) && \
237 ! is_ia32_CmpCMov(irn) && \
238 ! is_ia32_PsiCondCMov(irn) && \
239 ! is_ia32_CmpSet(irn);
243 * Insert copies for all ia32 nodes where the should_be_same requirement
245 * Transform Sub into Neg -- Add if IN2 == OUT
247 static void ia32_finish_node(ir_node *irn, void *env) {
248 ia32_code_gen_t *cg = env;
249 const ia32_register_req_t **reqs;
250 const arch_register_t *out_reg, *in_reg, *in2_reg;
252 ir_node *copy, *in_node, *block, *in2_node;
253 ia32_op_type_t op_tp;
255 if (is_ia32_irn(irn)) {
256 /* AM Dest nodes don't produce any values */
257 op_tp = get_ia32_op_type(irn);
258 if (op_tp == ia32_AddrModeD)
261 reqs = get_ia32_out_req_all(irn);
262 n_res = get_ia32_n_res(irn);
263 block = get_nodes_block(irn);
265 /* check all OUT requirements, if there is a should_be_same */
266 if ((op_tp == ia32_Normal || op_tp == ia32_AddrModeS) && need_constraint_copy(irn))
268 for (i = 0; i < n_res; i++) {
269 if (arch_register_req_is(&(reqs[i]->req), should_be_same)) {
270 /* get in and out register */
271 out_reg = get_ia32_out_reg(irn, i);
272 in_node = get_irn_n(irn, reqs[i]->same_pos);
273 in_reg = arch_get_irn_register(cg->arch_env, in_node);
275 /* don't copy ignore nodes */
276 if (arch_irn_is(cg->arch_env, in_node, ignore) && is_Proj(in_node))
279 /* check if in and out register are equal */
280 if (! REGS_ARE_EQUAL(out_reg, in_reg)) {
281 /* in case of a commutative op: just exchange the in's */
282 /* beware: the current op could be everything, so test for ia32 */
283 /* commutativity first before getting the second in */
284 if (is_ia32_commutative(irn)) {
285 in2_node = get_irn_n(irn, reqs[i]->same_pos ^ 1);
286 in2_reg = arch_get_irn_register(cg->arch_env, in2_node);
288 if (REGS_ARE_EQUAL(out_reg, in2_reg)) {
289 set_irn_n(irn, reqs[i]->same_pos, in2_node);
290 set_irn_n(irn, reqs[i]->same_pos ^ 1, in_node);
297 DBG((cg->mod, LEVEL_1, "inserting copy for %+F in_pos %d\n", irn, reqs[i]->same_pos));
298 /* create copy from in register */
299 copy = be_new_Copy(arch_register_get_class(in_reg), cg->irg, block, in_node);
301 DBG_OPT_2ADDRCPY(copy);
303 /* destination is the out register */
304 arch_set_irn_register(cg->arch_env, copy, out_reg);
306 /* insert copy before the node into the schedule */
307 sched_add_before(irn, copy);
310 set_irn_n(irn, reqs[i]->same_pos, copy);
317 /* check xCmp: try to avoid unordered cmp */
318 if ((is_ia32_xCmp(irn) || is_ia32_xCmpCMov(irn) || is_ia32_xCmpSet(irn)) &&
319 op_tp == ia32_Normal &&
320 ! is_ia32_ImmConst(irn) && ! is_ia32_ImmSymConst(irn))
322 long pnc = get_ia32_pncode(irn);
324 if (pnc & pn_Cmp_Uo) {
326 int idx1 = 2, idx2 = 3;
328 if (is_ia32_xCmpCMov(irn)) {
333 tmp = get_irn_n(irn, idx1);
334 set_irn_n(irn, idx1, get_irn_n(irn, idx2));
335 set_irn_n(irn, idx2, tmp);
337 set_ia32_pncode(irn, get_negated_pnc(pnc, mode_D));
342 If we have a CondJmp/CmpSet/xCmpSet with immediate,
343 we need to check if it's the right operand, otherwise
344 we have to change it, as CMP doesn't support immediate
348 if ((is_ia32_CondJmp(irn) || is_ia32_CmpSet(irn) || is_ia32_xCmpSet(irn)) &&
349 (is_ia32_ImmConst(irn) || is_ia32_ImmSymConst(irn)) &&
350 op_tp == ia32_AddrModeS)
352 set_ia32_op_type(irn, ia32_AddrModeD);
353 set_ia32_pncode(irn, get_inversed_pnc(get_ia32_pncode(irn)));
362 * We have a source address mode node with base or index register equal to
363 * result register. The constraint handler will insert a copy from the
364 * remaining input operand to the result register -> base or index is
366 * Solution: Turn back this address mode into explicit Load + Operation.
368 static void fix_am_source(ir_node *irn, void *env) {
369 ia32_code_gen_t *cg = env;
370 ir_node *base, *index, *noreg;
371 const arch_register_t *reg_base, *reg_index;
372 const ia32_register_req_t **reqs;
375 /* check only ia32 nodes with source address mode */
376 if (! is_ia32_irn(irn) || get_ia32_op_type(irn) != ia32_AddrModeS)
378 /* no need to fix unary operations */
379 if (get_irn_arity(irn) == 4)
382 base = get_irn_n(irn, 0);
383 index = get_irn_n(irn, 1);
385 reg_base = arch_get_irn_register(cg->arch_env, base);
386 reg_index = arch_get_irn_register(cg->arch_env, index);
387 reqs = get_ia32_out_req_all(irn);
389 noreg = ia32_new_NoReg_gp(cg);
391 n_res = get_ia32_n_res(irn);
393 for (i = 0; i < n_res; i++) {
394 if (arch_register_req_is(&(reqs[i]->req), should_be_same)) {
395 /* get in and out register */
396 const arch_register_t *out_reg = get_ia32_out_reg(irn, i);
399 there is a constraint for the remaining operand
400 and the result register is equal to base or index register
402 if (reqs[i]->same_pos == 2 &&
403 (REGS_ARE_EQUAL(out_reg, reg_base) || REGS_ARE_EQUAL(out_reg, reg_index)))
405 /* turn back address mode */
406 ir_node *in_node = get_irn_n(irn, 2);
407 const arch_register_t *in_reg = arch_get_irn_register(cg->arch_env, in_node);
408 ir_node *block = get_nodes_block(irn);
409 ir_mode *ls_mode = get_ia32_ls_mode(irn);
413 if (arch_register_get_class(in_reg) == &ia32_reg_classes[CLASS_ia32_gp]) {
414 load = new_rd_ia32_Load(NULL, cg->irg, block, base, index, get_irn_n(irn, 4));
415 pnres = pn_ia32_Load_res;
417 else if (arch_register_get_class(in_reg) == &ia32_reg_classes[CLASS_ia32_xmm]) {
418 load = new_rd_ia32_xLoad(NULL, cg->irg, block, base, index, get_irn_n(irn, 4));
419 pnres = pn_ia32_xLoad_res;
422 assert(0 && "cannot turn back address mode for this register class");
425 /* copy address mode information to load */
426 set_ia32_ls_mode(load, ls_mode);
427 set_ia32_am_flavour(load, get_ia32_am_flavour(irn));
428 set_ia32_op_type(load, ia32_AddrModeS);
429 set_ia32_am_support(load, ia32_am_Source);
430 set_ia32_am_scale(load, get_ia32_am_scale(irn));
431 set_ia32_am_sc(load, get_ia32_am_sc(irn));
432 add_ia32_am_offs(load, get_ia32_am_offs(irn));
433 set_ia32_frame_ent(load, get_ia32_frame_ent(irn));
435 if (is_ia32_use_frame(irn))
436 set_ia32_use_frame(load);
438 /* insert the load into schedule */
439 sched_add_before(irn, load);
441 DBG((cg->mod, LEVEL_3, "irg %+F: build back AM source for node %+F, inserted load %+F\n", cg->irg, irn, load));
443 load = new_r_Proj(cg->irg, block, load, ls_mode, pnres);
444 arch_set_irn_register(cg->arch_env, load, out_reg);
446 /* insert the load result proj into schedule */
447 sched_add_before(irn, load);
449 /* set the new input operand */
450 set_irn_n(irn, 3, load);
452 /* this is a normal node now */
453 set_irn_n(irn, 0, noreg);
454 set_irn_n(irn, 1, noreg);
455 set_ia32_op_type(irn, ia32_Normal);
463 static void ia32_finish_irg_walker(ir_node *block, void *env) {
466 /* first: turn back AM source if necessary */
467 for (irn = sched_first(block); ! sched_is_end(irn); irn = next) {
468 next = sched_next(irn);
469 fix_am_source(irn, env);
472 for (irn = sched_first(block); ! sched_is_end(irn); irn = next) {
473 ia32_code_gen_t *cg = env;
475 next = sched_next(irn);
477 /* check if there is a sub which need to be transformed */
478 ia32_transform_sub_to_neg_add(irn, cg);
480 /* transform a LEA into an Add if possible */
481 ia32_transform_lea_to_add(irn, cg);
484 /* second: insert copies and finish irg */
485 for (irn = sched_first(block); ! sched_is_end(irn); irn = next) {
486 next = sched_next(irn);
487 ia32_finish_node(irn, env);
491 static void ia32_push_on_queue_walker(ir_node *block, void *env) {
493 waitq_put(wq, block);
498 * Add Copy nodes for not fulfilled should_be_equal constraints
500 void ia32_finish_irg(ir_graph *irg, ia32_code_gen_t *cg) {
501 waitq *wq = new_waitq();
503 /* Push the blocks on the waitq because ia32_finish_irg_walker starts more walks ... */
504 irg_block_walk_graph(irg, NULL, ia32_push_on_queue_walker, wq);
506 while (! waitq_empty(wq)) {
507 ir_node *block = waitq_get(wq);
508 ia32_finish_irg_walker(block, cg);