2 * This file implements functions to finalize the irg for emit.
3 * @author Christian Wuerdig
18 #include "../bearch.h"
19 #include "../besched_t.h"
20 #include "../benode_t.h"
22 #include "bearch_ia32_t.h"
23 #include "ia32_finish.h"
24 #include "ia32_new_nodes.h"
25 #include "ia32_map_regs.h"
26 #include "ia32_transform.h"
27 #include "ia32_dbg_stat.h"
28 #include "ia32_optimize.h"
29 #include "gen_ia32_regalloc_if.h"
32 * Transforms a Sub or xSub into Neg--Add iff OUT_REG == SRC2_REG.
33 * THIS FUNCTIONS MUST BE CALLED AFTER REGISTER ALLOCATION.
35 static void ia32_transform_sub_to_neg_add(ir_node *irn, ia32_code_gen_t *cg) {
37 ir_node *in1, *in2, *noreg, *nomem, *res;
38 ir_node *noreg_fp, *block;
39 ir_mode *mode = get_irn_mode(irn);
40 dbg_info *dbg = get_irn_dbg_info(irn);
41 const arch_register_t *in1_reg, *in2_reg, *out_reg, **slots;
44 /* Return if AM node or not a Sub or xSub */
45 if (!(is_ia32_Sub(irn) || is_ia32_xSub(irn)) || get_ia32_op_type(irn) != ia32_Normal)
48 noreg = ia32_new_NoReg_gp(cg);
49 noreg_fp = ia32_new_NoReg_fp(cg);
50 nomem = new_rd_NoMem(cg->irg);
51 in1 = get_irn_n(irn, 2);
52 in2 = get_irn_n(irn, 3);
53 in1_reg = arch_get_irn_register(cg->arch_env, in1);
54 in2_reg = arch_get_irn_register(cg->arch_env, in2);
55 out_reg = get_ia32_out_reg(irn, 0);
58 block = get_nodes_block(irn);
60 /* in case of sub and OUT == SRC2 we can transform the sequence into neg src2 -- add */
61 if (!REGS_ARE_EQUAL(out_reg, in2_reg))
64 /* generate the neg src2 */
65 if(mode_is_float(mode)) {
69 res = new_rd_ia32_xXor(dbg, irg, block, noreg, noreg, in2, noreg_fp, nomem);
70 size = get_mode_size_bits(mode);
71 name = ia32_gen_fp_known_const(size == 32 ? ia32_SSIGN : ia32_DSIGN);
72 set_ia32_am_sc(res, name);
73 set_ia32_op_type(res, ia32_AddrModeS);
74 set_ia32_ls_mode(res, get_ia32_ls_mode(irn));
76 res = new_rd_ia32_Neg(dbg, irg, block, noreg, noreg, in2, nomem);
78 arch_set_irn_register(cg->arch_env, res, in2_reg);
81 sched_add_before(irn, res);
83 /* generate the add */
84 if (mode_is_float(mode)) {
85 res = new_rd_ia32_xAdd(dbg, irg, block, noreg, noreg, res, in1, nomem);
86 set_ia32_am_support(res, ia32_am_Source);
87 set_ia32_ls_mode(res, get_ia32_ls_mode(irn));
90 res = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, res, in1, nomem);
91 set_ia32_am_support(res, ia32_am_Full);
92 set_ia32_commutative(res);
95 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(cg, irn));
97 slots = get_ia32_slots(res);
100 /* exchange the add and the sub */
101 edges_reroute(irn, res, irg);
103 /* add to schedule */
104 sched_add_before(irn, res);
106 /* remove the old sub */
108 arity = get_irn_arity(irn);
109 for(i = 0; i < arity; ++i) {
110 set_irn_n(irn, i, new_Bad());
113 DBG_OPT_SUB2NEGADD(irn, res);
117 * Transforms a LEA into an Add if possible
118 * THIS FUNCTIONS MUST BE CALLED AFTER REGISTER ALLOCATION.
120 static void ia32_transform_lea_to_add(ir_node *irn, ia32_code_gen_t *cg) {
121 ia32_am_flavour_t am_flav;
123 dbg_info *dbg = get_irn_dbg_info(irn);
126 ir_node *nomem, *noreg, *base, *index, *op1, *op2;
129 const arch_register_t *out_reg, *base_reg, *index_reg;
132 if (! is_ia32_Lea(irn))
135 am_flav = get_ia32_am_flavour(irn);
137 /* mustn't have a symconst */
138 if (get_ia32_am_sc(irn))
141 /* only some LEAs can be transformed to an Add */
142 if (am_flav != ia32_am_B && am_flav != ia32_am_OB && am_flav != ia32_am_OI && am_flav != ia32_am_BI)
145 noreg = ia32_new_NoReg_gp(cg);
146 nomem = new_rd_NoMem(cg->irg);
149 base = get_irn_n(irn, 0);
150 index = get_irn_n(irn,1);
152 if (am_flav & ia32_O) {
153 offs = get_ia32_am_offs_int(irn);
156 out_reg = arch_get_irn_register(cg->arch_env, irn);
157 base_reg = arch_get_irn_register(cg->arch_env, base);
158 index_reg = arch_get_irn_register(cg->arch_env, index);
161 block = get_nodes_block(irn);
163 switch(get_ia32_am_flavour(irn)) {
165 /* out register must be same as base register */
166 if (! REGS_ARE_EQUAL(out_reg, base_reg))
172 /* out register must be same as base register */
173 if (! REGS_ARE_EQUAL(out_reg, base_reg))
180 /* out register must be same as index register */
181 if (! REGS_ARE_EQUAL(out_reg, index_reg))
188 /* out register must be same as one in register */
189 if (REGS_ARE_EQUAL(out_reg, base_reg)) {
193 else if (REGS_ARE_EQUAL(out_reg, index_reg)) {
198 /* in registers a different from out -> no Add possible */
205 res = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, op1, op2, nomem);
206 arch_set_irn_register(cg->arch_env, res, out_reg);
207 set_ia32_op_type(res, ia32_Normal);
208 set_ia32_commutative(res);
211 tarval *tv = new_tarval_from_long(offs, mode_Iu);
212 set_ia32_Immop_tarval(res, tv);
215 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(cg, irn));
217 /* add Add to schedule */
218 sched_add_before(irn, res);
220 DBG_OPT_LEA2ADD(irn, res);
222 /* remove the old LEA */
225 /* exchange the Add and the LEA */
229 static INLINE int need_constraint_copy(ir_node *irn) {
231 ! is_ia32_Lea(irn) && \
232 ! is_ia32_Conv_I2I(irn) && \
233 ! is_ia32_Conv_I2I8Bit(irn) && \
234 ! is_ia32_CmpCMov(irn) && \
235 ! is_ia32_PsiCondCMov(irn) && \
236 ! is_ia32_CmpSet(irn);
240 * Insert copies for all ia32 nodes where the should_be_same requirement
242 * Transform Sub into Neg -- Add if IN2 == OUT
244 static void ia32_finish_node(ir_node *irn, void *env) {
245 ia32_code_gen_t *cg = env;
246 const ia32_register_req_t **reqs;
247 const arch_register_t *out_reg, *in_reg, *in2_reg;
249 ir_node *copy, *in_node, *block, *in2_node;
250 ia32_op_type_t op_tp;
252 if (is_ia32_irn(irn)) {
253 /* AM Dest nodes don't produce any values */
254 op_tp = get_ia32_op_type(irn);
255 if (op_tp == ia32_AddrModeD)
258 reqs = get_ia32_out_req_all(irn);
259 n_res = get_ia32_n_res(irn);
260 block = get_nodes_block(irn);
262 /* check all OUT requirements, if there is a should_be_same */
263 if ((op_tp == ia32_Normal || op_tp == ia32_AddrModeS) && need_constraint_copy(irn))
265 for (i = 0; i < n_res; i++) {
266 if (arch_register_req_is(&(reqs[i]->req), should_be_same)) {
267 /* get in and out register */
268 out_reg = get_ia32_out_reg(irn, i);
269 in_node = get_irn_n(irn, reqs[i]->same_pos);
270 in_reg = arch_get_irn_register(cg->arch_env, in_node);
272 /* don't copy ignore nodes */
273 if (arch_irn_is(cg->arch_env, in_node, ignore) && is_Proj(in_node))
276 /* check if in and out register are equal */
277 if (! REGS_ARE_EQUAL(out_reg, in_reg)) {
278 /* in case of a commutative op: just exchange the in's */
279 /* beware: the current op could be everything, so test for ia32 */
280 /* commutativity first before getting the second in */
281 if (is_ia32_commutative(irn)) {
282 in2_node = get_irn_n(irn, reqs[i]->same_pos ^ 1);
283 in2_reg = arch_get_irn_register(cg->arch_env, in2_node);
285 if (REGS_ARE_EQUAL(out_reg, in2_reg)) {
286 set_irn_n(irn, reqs[i]->same_pos, in2_node);
287 set_irn_n(irn, reqs[i]->same_pos ^ 1, in_node);
294 DBG((cg->mod, LEVEL_1, "inserting copy for %+F in_pos %d\n", irn, reqs[i]->same_pos));
295 /* create copy from in register */
296 copy = be_new_Copy(arch_register_get_class(in_reg), cg->irg, block, in_node);
298 DBG_OPT_2ADDRCPY(copy);
300 /* destination is the out register */
301 arch_set_irn_register(cg->arch_env, copy, out_reg);
303 /* insert copy before the node into the schedule */
304 sched_add_before(irn, copy);
307 set_irn_n(irn, reqs[i]->same_pos, copy);
314 /* check xCmp: try to avoid unordered cmp */
315 if ((is_ia32_xCmp(irn) || is_ia32_xCmpCMov(irn) || is_ia32_xCmpSet(irn)) &&
316 op_tp == ia32_Normal &&
317 ! is_ia32_ImmConst(irn) && ! is_ia32_ImmSymConst(irn))
319 long pnc = get_ia32_pncode(irn);
321 if (pnc & pn_Cmp_Uo) {
323 int idx1 = 2, idx2 = 3;
325 if (is_ia32_xCmpCMov(irn)) {
330 tmp = get_irn_n(irn, idx1);
331 set_irn_n(irn, idx1, get_irn_n(irn, idx2));
332 set_irn_n(irn, idx2, tmp);
334 set_ia32_pncode(irn, get_negated_pnc(pnc, mode_E));
339 If we have a CondJmp/CmpSet/xCmpSet with immediate,
340 we need to check if it's the right operand, otherwise
341 we have to change it, as CMP doesn't support immediate
345 if ((is_ia32_CondJmp(irn) || is_ia32_CmpSet(irn) || is_ia32_xCmpSet(irn)) &&
346 (is_ia32_ImmConst(irn) || is_ia32_ImmSymConst(irn)) &&
347 op_tp == ia32_AddrModeS)
349 set_ia32_op_type(irn, ia32_AddrModeD);
350 set_ia32_pncode(irn, get_inversed_pnc(get_ia32_pncode(irn)));
359 * We have a source address mode node with base or index register equal to
360 * result register. The constraint handler will insert a copy from the
361 * remaining input operand to the result register -> base or index is
363 * Solution: Turn back this address mode into explicit Load + Operation.
365 static void fix_am_source(ir_node *irn, void *env) {
366 ia32_code_gen_t *cg = env;
367 ir_node *base, *index, *noreg;
368 const arch_register_t *reg_base, *reg_index;
369 const ia32_register_req_t **reqs;
372 /* check only ia32 nodes with source address mode */
373 if (! is_ia32_irn(irn) || get_ia32_op_type(irn) != ia32_AddrModeS)
375 /* no need to fix unary operations */
376 if (get_irn_arity(irn) == 4)
379 base = get_irn_n(irn, 0);
380 index = get_irn_n(irn, 1);
382 reg_base = arch_get_irn_register(cg->arch_env, base);
383 reg_index = arch_get_irn_register(cg->arch_env, index);
384 reqs = get_ia32_out_req_all(irn);
386 noreg = ia32_new_NoReg_gp(cg);
388 n_res = get_ia32_n_res(irn);
390 for (i = 0; i < n_res; i++) {
391 if (arch_register_req_is(&(reqs[i]->req), should_be_same)) {
392 /* get in and out register */
393 const arch_register_t *out_reg = get_ia32_out_reg(irn, i);
396 there is a constraint for the remaining operand
397 and the result register is equal to base or index register
399 if (reqs[i]->same_pos == 2 &&
400 (REGS_ARE_EQUAL(out_reg, reg_base) || REGS_ARE_EQUAL(out_reg, reg_index)))
402 /* turn back address mode */
403 ir_node *in_node = get_irn_n(irn, 2);
404 const arch_register_t *in_reg = arch_get_irn_register(cg->arch_env, in_node);
405 ir_node *block = get_nodes_block(irn);
406 ir_mode *ls_mode = get_ia32_ls_mode(irn);
410 if (arch_register_get_class(in_reg) == &ia32_reg_classes[CLASS_ia32_gp]) {
411 load = new_rd_ia32_Load(NULL, cg->irg, block, base, index, get_irn_n(irn, 4));
412 pnres = pn_ia32_Load_res;
414 else if (arch_register_get_class(in_reg) == &ia32_reg_classes[CLASS_ia32_xmm]) {
415 load = new_rd_ia32_xLoad(NULL, cg->irg, block, base, index, get_irn_n(irn, 4));
416 pnres = pn_ia32_xLoad_res;
419 assert(0 && "cannot turn back address mode for this register class");
422 /* copy address mode information to load */
423 set_ia32_ls_mode(load, ls_mode);
424 set_ia32_am_flavour(load, get_ia32_am_flavour(irn));
425 set_ia32_op_type(load, ia32_AddrModeS);
426 set_ia32_am_support(load, ia32_am_Source);
427 set_ia32_am_scale(load, get_ia32_am_scale(irn));
428 set_ia32_am_sc(load, get_ia32_am_sc(irn));
429 add_ia32_am_offs_int(load, get_ia32_am_offs_int(irn));
430 set_ia32_frame_ent(load, get_ia32_frame_ent(irn));
432 if (is_ia32_use_frame(irn))
433 set_ia32_use_frame(load);
435 /* insert the load into schedule */
436 sched_add_before(irn, load);
438 DBG((cg->mod, LEVEL_3, "irg %+F: build back AM source for node %+F, inserted load %+F\n", cg->irg, irn, load));
440 load = new_r_Proj(cg->irg, block, load, ls_mode, pnres);
441 arch_set_irn_register(cg->arch_env, load, out_reg);
443 /* insert the load result proj into schedule */
444 sched_add_before(irn, load);
446 /* set the new input operand */
447 set_irn_n(irn, 3, load);
449 /* this is a normal node now */
450 set_irn_n(irn, 0, noreg);
451 set_irn_n(irn, 1, noreg);
452 set_ia32_op_type(irn, ia32_Normal);
460 static void ia32_finish_irg_walker(ir_node *block, void *env) {
463 /* first: turn back AM source if necessary */
464 for (irn = sched_first(block); ! sched_is_end(irn); irn = next) {
465 next = sched_next(irn);
466 fix_am_source(irn, env);
469 for (irn = sched_first(block); ! sched_is_end(irn); irn = next) {
470 ia32_code_gen_t *cg = env;
472 next = sched_next(irn);
474 /* check if there is a sub which need to be transformed */
475 ia32_transform_sub_to_neg_add(irn, cg);
477 /* transform a LEA into an Add if possible */
478 ia32_transform_lea_to_add(irn, cg);
481 /* second: insert copies and finish irg */
482 for (irn = sched_first(block); ! sched_is_end(irn); irn = next) {
483 next = sched_next(irn);
484 ia32_finish_node(irn, env);
488 static void ia32_push_on_queue_walker(ir_node *block, void *env) {
490 waitq_put(wq, block);
495 * Add Copy nodes for not fulfilled should_be_equal constraints
497 void ia32_finish_irg(ir_graph *irg, ia32_code_gen_t *cg) {
498 waitq *wq = new_waitq();
500 /* Push the blocks on the waitq because ia32_finish_irg_walker starts more walks ... */
501 irg_block_walk_graph(irg, NULL, ia32_push_on_queue_walker, wq);
503 while (! waitq_empty(wq)) {
504 ir_node *block = waitq_get(wq);
505 ia32_finish_irg_walker(block, cg);