2 * This file implements functions to finalize the irg for emit.
3 * @author Christian Wuerdig
18 #include "../bearch.h"
19 #include "../besched_t.h"
20 #include "../benode_t.h"
22 #include "bearch_ia32_t.h"
23 #include "ia32_finish.h"
24 #include "ia32_new_nodes.h"
25 #include "ia32_map_regs.h"
26 #include "ia32_transform.h"
27 #include "ia32_dbg_stat.h"
28 #include "ia32_optimize.h"
29 #include "gen_ia32_regalloc_if.h"
32 * Transforms a Sub or xSub into Neg--Add iff OUT_REG == SRC2_REG.
33 * THIS FUNCTIONS MUST BE CALLED AFTER REGISTER ALLOCATION.
35 static void ia32_transform_sub_to_neg_add(ir_node *irn, ia32_code_gen_t *cg) {
36 ia32_transform_env_t tenv;
37 ir_node *in1, *in2, *noreg, *nomem, *res;
38 const arch_register_t *in1_reg, *in2_reg, *out_reg, **slots;
41 /* Return if AM node or not a Sub or xSub */
42 if (!(is_ia32_Sub(irn) || is_ia32_xSub(irn)) || get_ia32_op_type(irn) != ia32_Normal)
45 noreg = ia32_new_NoReg_gp(cg);
46 nomem = new_rd_NoMem(cg->irg);
47 in1 = get_irn_n(irn, 2);
48 in2 = get_irn_n(irn, 3);
49 in1_reg = arch_get_irn_register(cg->arch_env, in1);
50 in2_reg = arch_get_irn_register(cg->arch_env, in2);
51 out_reg = get_ia32_out_reg(irn, 0);
53 tenv.block = get_nodes_block(irn);
54 tenv.dbg = get_irn_dbg_info(irn);
57 tenv.mode = get_ia32_res_mode(irn);
59 DEBUG_ONLY(tenv.mod = cg->mod;)
61 /* in case of sub and OUT == SRC2 we can transform the sequence into neg src2 -- add */
62 if (!REGS_ARE_EQUAL(out_reg, in2_reg))
65 /* generate the neg src2 */
66 res = gen_Minus_ex(&tenv, in2);
67 arch_set_irn_register(cg->arch_env, res, in2_reg);
70 sched_add_before(irn, res);
72 /* generate the add */
73 if (mode_is_float(tenv.mode)) {
74 res = new_rd_ia32_xAdd(tenv.dbg, tenv.irg, tenv.block, noreg, noreg, res, in1, nomem, tenv.mode);
75 set_ia32_am_support(res, ia32_am_Source);
78 res = new_rd_ia32_Add(tenv.dbg, tenv.irg, tenv.block, noreg, noreg, res, in1, nomem, tenv.mode);
79 set_ia32_am_support(res, ia32_am_Full);
80 set_ia32_commutative(res);
82 set_ia32_res_mode(res, tenv.mode);
84 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(tenv.cg, irn));
86 slots = get_ia32_slots(res);
89 /* exchange the add and the sub */
90 edges_reroute(irn, res, tenv.irg);
93 sched_add_before(irn, res);
95 /* remove the old sub */
97 arity = get_irn_arity(irn);
98 for(i = 0; i < arity; ++i) {
99 set_irn_n(irn, i, new_Bad());
102 DBG_OPT_SUB2NEGADD(irn, res);
106 * Transforms a LEA into an Add if possible
107 * THIS FUNCTIONS MUST BE CALLED AFTER REGISTER ALLOCATION.
109 static void ia32_transform_lea_to_add(ir_node *irn, ia32_code_gen_t *cg) {
110 ia32_am_flavour_t am_flav;
113 ir_node *nomem, *noreg, *base, *index, *op1, *op2;
114 const char *offs = NULL;
115 ia32_transform_env_t tenv;
116 const arch_register_t *out_reg, *base_reg, *index_reg;
117 int imm_tp = ia32_ImmConst;
120 if (! is_ia32_Lea(irn))
123 am_flav = get_ia32_am_flavour(irn);
125 if (get_ia32_am_sc(irn))
128 /* only some LEAs can be transformed to an Add */
129 if (am_flav != ia32_am_B && am_flav != ia32_am_OB && am_flav != ia32_am_OI && am_flav != ia32_am_BI)
132 noreg = ia32_new_NoReg_gp(cg);
133 nomem = new_rd_NoMem(cg->irg);
136 base = get_irn_n(irn, 0);
137 index = get_irn_n(irn,1);
139 if (am_flav & ia32_O) {
140 offs = get_ia32_am_offs(irn);
143 ident *id = get_ia32_am_sc(irn);
146 offs = get_id_str(id);
147 imm_tp = ia32_ImmSymConst;
149 /* offset has a explicit sign -> we need to skip + */
150 else if (offs[0] == '+')
154 out_reg = arch_get_irn_register(cg->arch_env, irn);
155 base_reg = arch_get_irn_register(cg->arch_env, base);
156 index_reg = arch_get_irn_register(cg->arch_env, index);
158 tenv.block = get_nodes_block(irn);
159 tenv.dbg = get_irn_dbg_info(irn);
162 DEBUG_ONLY(tenv.mod = cg->mod;)
163 tenv.mode = get_irn_mode(irn);
166 switch(get_ia32_am_flavour(irn)) {
168 /* out register must be same as base register */
169 if (! REGS_ARE_EQUAL(out_reg, base_reg))
175 /* out register must be same as base register */
176 if (! REGS_ARE_EQUAL(out_reg, base_reg))
183 /* out register must be same as index register */
184 if (! REGS_ARE_EQUAL(out_reg, index_reg))
191 /* out register must be same as one in register */
192 if (REGS_ARE_EQUAL(out_reg, base_reg)) {
196 else if (REGS_ARE_EQUAL(out_reg, index_reg)) {
201 /* in registers a different from out -> no Add possible */
208 res = new_rd_ia32_Add(tenv.dbg, tenv.irg, tenv.block, noreg, noreg, op1, op2, nomem, tenv.mode);
209 arch_set_irn_register(cg->arch_env, res, out_reg);
210 set_ia32_op_type(res, ia32_Normal);
211 set_ia32_commutative(res);
212 set_ia32_res_mode(res, tenv.mode);
215 set_ia32_cnst(res, offs);
216 set_ia32_immop_type(res, imm_tp);
219 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(cg, irn));
221 /* add Add to schedule */
222 sched_add_before(irn, res);
224 DBG_OPT_LEA2ADD(irn, res);
226 /* remove the old LEA */
229 /* exchange the Add and the LEA */
233 static INLINE int need_constraint_copy(ir_node *irn) {
235 ! is_ia32_Lea(irn) && \
236 ! is_ia32_Conv_I2I(irn) && \
237 ! is_ia32_Conv_I2I8Bit(irn) && \
238 ! is_ia32_CmpCMov(irn) && \
239 ! is_ia32_PsiCondCMov(irn) && \
240 ! is_ia32_CmpSet(irn);
244 * Insert copies for all ia32 nodes where the should_be_same requirement
246 * Transform Sub into Neg -- Add if IN2 == OUT
248 static void ia32_finish_node(ir_node *irn, void *env) {
249 ia32_code_gen_t *cg = env;
250 const ia32_register_req_t **reqs;
251 const arch_register_t *out_reg, *in_reg, *in2_reg;
253 ir_node *copy, *in_node, *block, *in2_node;
254 ia32_op_type_t op_tp;
256 if (is_ia32_irn(irn)) {
257 /* AM Dest nodes don't produce any values */
258 op_tp = get_ia32_op_type(irn);
259 if (op_tp == ia32_AddrModeD)
262 reqs = get_ia32_out_req_all(irn);
263 n_res = get_ia32_n_res(irn);
264 block = get_nodes_block(irn);
266 /* check all OUT requirements, if there is a should_be_same */
267 if ((op_tp == ia32_Normal || op_tp == ia32_AddrModeS) && need_constraint_copy(irn))
269 for (i = 0; i < n_res; i++) {
270 if (arch_register_req_is(&(reqs[i]->req), should_be_same)) {
271 /* get in and out register */
272 out_reg = get_ia32_out_reg(irn, i);
273 in_node = get_irn_n(irn, reqs[i]->same_pos);
274 in_reg = arch_get_irn_register(cg->arch_env, in_node);
276 /* don't copy ignore nodes */
277 if (arch_irn_is(cg->arch_env, in_node, ignore) && is_Proj(in_node))
280 /* check if in and out register are equal */
281 if (! REGS_ARE_EQUAL(out_reg, in_reg)) {
282 /* in case of a commutative op: just exchange the in's */
283 /* beware: the current op could be everything, so test for ia32 */
284 /* commutativity first before getting the second in */
285 if (is_ia32_commutative(irn)) {
286 in2_node = get_irn_n(irn, reqs[i]->same_pos ^ 1);
287 in2_reg = arch_get_irn_register(cg->arch_env, in2_node);
289 if (REGS_ARE_EQUAL(out_reg, in2_reg)) {
290 set_irn_n(irn, reqs[i]->same_pos, in2_node);
291 set_irn_n(irn, reqs[i]->same_pos ^ 1, in_node);
298 DBG((cg->mod, LEVEL_1, "inserting copy for %+F in_pos %d\n", irn, reqs[i]->same_pos));
299 /* create copy from in register */
300 copy = be_new_Copy(arch_register_get_class(in_reg), cg->irg, block, in_node);
302 DBG_OPT_2ADDRCPY(copy);
304 /* destination is the out register */
305 arch_set_irn_register(cg->arch_env, copy, out_reg);
307 /* insert copy before the node into the schedule */
308 sched_add_before(irn, copy);
311 set_irn_n(irn, reqs[i]->same_pos, copy);
318 /* check xCmp: try to avoid unordered cmp */
319 if ((is_ia32_xCmp(irn) || is_ia32_xCmpCMov(irn) || is_ia32_xCmpSet(irn)) &&
320 op_tp == ia32_Normal &&
321 ! is_ia32_ImmConst(irn) && ! is_ia32_ImmSymConst(irn))
323 long pnc = get_ia32_pncode(irn);
325 if (pnc & pn_Cmp_Uo) {
327 int idx1 = 2, idx2 = 3;
329 if (is_ia32_xCmpCMov(irn)) {
334 tmp = get_irn_n(irn, idx1);
335 set_irn_n(irn, idx1, get_irn_n(irn, idx2));
336 set_irn_n(irn, idx2, tmp);
338 set_ia32_pncode(irn, get_negated_pnc(pnc, mode_D));
343 If we have a CondJmp/CmpSet/xCmpSet with immediate,
344 we need to check if it's the right operand, otherwise
345 we have to change it, as CMP doesn't support immediate
349 if ((is_ia32_CondJmp(irn) || is_ia32_CmpSet(irn) || is_ia32_xCmpSet(irn)) &&
350 (is_ia32_ImmConst(irn) || is_ia32_ImmSymConst(irn)) &&
351 op_tp == ia32_AddrModeS)
353 set_ia32_op_type(irn, ia32_AddrModeD);
354 set_ia32_pncode(irn, get_inversed_pnc(get_ia32_pncode(irn)));
363 * We have a source address mode node with base or index register equal to
364 * result register. The constraint handler will insert a copy from the
365 * remaining input operand to the result register -> base or index is
367 * Solution: Turn back this address mode into explicit Load + Operation.
369 static void fix_am_source(ir_node *irn, void *env) {
370 ia32_code_gen_t *cg = env;
371 ir_node *base, *index, *noreg;
372 const arch_register_t *reg_base, *reg_index;
373 const ia32_register_req_t **reqs;
376 /* check only ia32 nodes with source address mode */
377 if (! is_ia32_irn(irn) || get_ia32_op_type(irn) != ia32_AddrModeS)
379 /* no need to fix unary operations */
380 if (get_irn_arity(irn) == 4)
383 base = get_irn_n(irn, 0);
384 index = get_irn_n(irn, 1);
386 reg_base = arch_get_irn_register(cg->arch_env, base);
387 reg_index = arch_get_irn_register(cg->arch_env, index);
388 reqs = get_ia32_out_req_all(irn);
390 noreg = ia32_new_NoReg_gp(cg);
392 n_res = get_ia32_n_res(irn);
394 for (i = 0; i < n_res; i++) {
395 if (arch_register_req_is(&(reqs[i]->req), should_be_same)) {
396 /* get in and out register */
397 const arch_register_t *out_reg = get_ia32_out_reg(irn, i);
400 there is a constraint for the remaining operand
401 and the result register is equal to base or index register
403 if (reqs[i]->same_pos == 2 &&
404 (REGS_ARE_EQUAL(out_reg, reg_base) || REGS_ARE_EQUAL(out_reg, reg_index)))
406 /* turn back address mode */
407 ir_node *in_node = get_irn_n(irn, 2);
408 const arch_register_t *in_reg = arch_get_irn_register(cg->arch_env, in_node);
409 ir_node *block = get_nodes_block(irn);
410 ir_mode *ls_mode = get_ia32_ls_mode(irn);
414 if (arch_register_get_class(in_reg) == &ia32_reg_classes[CLASS_ia32_gp]) {
415 load = new_rd_ia32_Load(NULL, cg->irg, block, base, index, get_irn_n(irn, 4));
416 pnres = pn_ia32_Load_res;
418 else if (arch_register_get_class(in_reg) == &ia32_reg_classes[CLASS_ia32_xmm]) {
419 load = new_rd_ia32_xLoad(NULL, cg->irg, block, base, index, get_irn_n(irn, 4));
420 pnres = pn_ia32_xLoad_res;
423 assert(0 && "cannot turn back address mode for this register class");
426 /* copy address mode information to load */
427 set_ia32_ls_mode(load, ls_mode);
428 set_ia32_am_flavour(load, get_ia32_am_flavour(irn));
429 set_ia32_op_type(load, ia32_AddrModeS);
430 set_ia32_am_support(load, ia32_am_Source);
431 set_ia32_am_scale(load, get_ia32_am_scale(irn));
432 set_ia32_am_sc(load, get_ia32_am_sc(irn));
433 add_ia32_am_offs(load, get_ia32_am_offs(irn));
434 set_ia32_frame_ent(load, get_ia32_frame_ent(irn));
436 if (is_ia32_use_frame(irn))
437 set_ia32_use_frame(load);
439 /* insert the load into schedule */
440 sched_add_before(irn, load);
442 DBG((cg->mod, LEVEL_3, "irg %+F: build back AM source for node %+F, inserted load %+F\n", cg->irg, irn, load));
444 load = new_r_Proj(cg->irg, block, load, ls_mode, pnres);
445 arch_set_irn_register(cg->arch_env, load, out_reg);
447 /* insert the load result proj into schedule */
448 sched_add_before(irn, load);
450 /* set the new input operand */
451 set_irn_n(irn, 3, load);
453 /* this is a normal node now */
454 set_irn_n(irn, 0, noreg);
455 set_irn_n(irn, 1, noreg);
456 set_ia32_op_type(irn, ia32_Normal);
464 static void ia32_finish_irg_walker(ir_node *block, void *env) {
467 /* first: turn back AM source if necessary */
468 for (irn = sched_first(block); ! sched_is_end(irn); irn = next) {
469 next = sched_next(irn);
470 fix_am_source(irn, env);
473 for (irn = sched_first(block); ! sched_is_end(irn); irn = next) {
474 ia32_code_gen_t *cg = env;
476 next = sched_next(irn);
478 /* check if there is a sub which need to be transformed */
479 ia32_transform_sub_to_neg_add(irn, cg);
481 /* transform a LEA into an Add if possible */
482 ia32_transform_lea_to_add(irn, cg);
485 /* second: insert copies and finish irg */
486 for (irn = sched_first(block); ! sched_is_end(irn); irn = next) {
487 next = sched_next(irn);
488 ia32_finish_node(irn, env);
492 static void ia32_push_on_queue_walker(ir_node *block, void *env) {
494 waitq_put(wq, block);
499 * Add Copy nodes for not fulfilled should_be_equal constraints
501 void ia32_finish_irg(ir_graph *irg, ia32_code_gen_t *cg) {
502 waitq *wq = new_waitq();
504 /* Push the blocks on the waitq because ia32_finish_irg_walker starts more walks ... */
505 irg_block_walk_graph(irg, NULL, ia32_push_on_queue_walker, wq);
507 while (! waitq_empty(wq)) {
508 ir_node *block = waitq_get(wq);
509 ia32_finish_irg_walker(block, cg);