2 * Copyright (C) 1995-2007 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This file implements the ia32 node emitter.
23 * @author Christian Wuerdig, Matthias Braun
41 #include "iredges_t.h"
44 #include "raw_bitset.h"
46 #include "../besched_t.h"
47 #include "../benode_t.h"
49 #include "../be_dbgout.h"
50 #include "../beemitter.h"
51 #include "../begnuas.h"
52 #include "../beirg_t.h"
54 #include "ia32_emitter.h"
55 #include "gen_ia32_emitter.h"
56 #include "gen_ia32_regalloc_if.h"
57 #include "ia32_nodes_attr.h"
58 #include "ia32_new_nodes.h"
59 #include "ia32_map_regs.h"
60 #include "bearch_ia32_t.h"
62 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
64 #define BLOCK_PREFIX ".L"
66 #define SNPRINTF_BUF_LEN 128
69 * Returns the register at in position pos.
72 const arch_register_t *get_in_reg(ia32_emit_env_t *env, const ir_node *irn,
75 const arch_env_t *arch_env = env->arch_env;
77 const arch_register_t *reg = NULL;
79 assert(get_irn_arity(irn) > pos && "Invalid IN position");
81 /* The out register of the operator at position pos is the
82 in register we need. */
83 op = get_irn_n(irn, pos);
85 reg = arch_get_irn_register(arch_env, op);
87 assert(reg && "no in register found");
89 /* in case of a joker register: just return a valid register */
90 if (arch_register_type_is(reg, joker)) {
91 const arch_register_req_t *req;
93 /* ask for the requirements */
94 req = arch_get_register_req(arch_env, irn, pos);
96 if (arch_register_req_is(req, limited)) {
97 /* in case of limited requirements: get the first allowed register */
98 unsigned idx = rbitset_next(req->limited, 0, 1);
99 reg = arch_register_for_index(req->cls, idx);
101 /* otherwise get first register in class */
102 reg = arch_register_for_index(req->cls, 0);
110 * Returns the register at out position pos.
113 const arch_register_t *get_out_reg(ia32_emit_env_t *env, const ir_node *irn,
116 const arch_env_t *arch_env = env->arch_env;
118 const arch_register_t *reg = NULL;
120 /* 1st case: irn is not of mode_T, so it has only */
121 /* one OUT register -> good */
122 /* 2nd case: irn is of mode_T -> collect all Projs and ask the */
123 /* Proj with the corresponding projnum for the register */
125 if (get_irn_mode(irn) != mode_T) {
126 reg = arch_get_irn_register(arch_env, irn);
127 } else if (is_ia32_irn(irn)) {
128 reg = get_ia32_out_reg(irn, pos);
130 const ir_edge_t *edge;
132 foreach_out_edge(irn, edge) {
133 proj = get_edge_src_irn(edge);
134 assert(is_Proj(proj) && "non-Proj from mode_T node");
135 if (get_Proj_proj(proj) == pos) {
136 reg = arch_get_irn_register(arch_env, proj);
142 assert(reg && "no out register found");
147 * Determine the gnu assembler suffix that indicates a mode
150 char get_mode_suffix(const ir_mode *mode) {
151 if(mode_is_float(mode)) {
152 switch(get_mode_size_bits(mode)) {
162 assert(mode_is_int(mode) || mode_is_reference(mode) || mode_is_character(mode));
163 switch(get_mode_size_bits(mode)) {
174 panic("Can't output mode_suffix for %+F\n", mode);
178 int produces_result(const ir_node *node) {
180 !is_ia32_CmpSet(node) &&
181 !is_ia32_CondJmp(node) &&
183 !is_ia32_SwitchJmp(node) &&
184 !is_ia32_TestJmp(node) &&
185 !is_ia32_xCmpSet(node) &&
186 !is_ia32_xCondJmp(node);
190 const char *ia32_get_reg_name_for_mode(ia32_emit_env_t *env, ir_mode *mode,
191 const arch_register_t *reg) {
192 switch(get_mode_size_bits(mode)) {
194 return ia32_get_mapped_reg_name(env->isa->regs_8bit, reg);
196 return ia32_get_mapped_reg_name(env->isa->regs_16bit, reg);
198 return (char *)arch_register_get_name(reg);
203 * Add a number to a prefix. This number will not be used a second time.
206 char *get_unique_label(char *buf, size_t buflen, const char *prefix) {
207 static unsigned long id = 0;
208 snprintf(buf, buflen, "%s%lu", prefix, ++id);
212 /*************************************************************
214 * (_) | | / _| | | | |
215 * _ __ _ __ _ _ __ | |_| |_ | |__ ___| |_ __ ___ _ __
216 * | '_ \| '__| | '_ \| __| _| | '_ \ / _ \ | '_ \ / _ \ '__|
217 * | |_) | | | | | | | |_| | | | | | __/ | |_) | __/ |
218 * | .__/|_| |_|_| |_|\__|_| |_| |_|\___|_| .__/ \___|_|
221 *************************************************************/
223 // we have no C++ and can't define an implicit ia32_emit_env_t* cast to
224 // be_emit_env_t* so we cheat a bit...
225 #define be_emit_char(env,c) be_emit_char(env->emit,c)
226 #define be_emit_string(env,s) be_emit_string(env->emit,s)
227 #undef be_emit_cstring
228 #define be_emit_cstring(env,x) { be_emit_string_len(env->emit, x, sizeof(x)-1); }
229 #define be_emit_ident(env,i) be_emit_ident(env->emit,i)
230 #define be_emit_tarval(env,tv) be_emit_tarval(env->emit,tv)
231 #define be_emit_write_line(env) be_emit_write_line(env->emit)
232 #define be_emit_finish_line_gas(env,n) be_emit_finish_line_gas(env->emit,n)
233 #define be_emit_pad_comment(env) be_emit_pad_comment(env->emit)
235 void ia32_emit_source_register(ia32_emit_env_t *env, const ir_node *node, int pos)
237 const arch_register_t *reg = get_in_reg(env, node, pos);
238 const char *reg_name = arch_register_get_name(reg);
240 assert(pos < get_irn_arity(node));
242 be_emit_char(env, '%');
243 be_emit_string(env, reg_name);
246 void ia32_emit_dest_register(ia32_emit_env_t *env, const ir_node *node, int pos) {
247 const arch_register_t *reg = get_out_reg(env, node, pos);
248 const char *reg_name = arch_register_get_name(reg);
250 be_emit_char(env, '%');
251 be_emit_string(env, reg_name);
254 void ia32_emit_x87_name(ia32_emit_env_t *env, const ir_node *node, int pos)
256 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
259 be_emit_char(env, '%');
260 be_emit_string(env, attr->x87[pos]->name);
263 void ia32_emit_immediate(ia32_emit_env_t *env, const ir_node *node)
269 be_emit_char(env, '$');
271 switch(get_ia32_immop_type(node)) {
273 tv = get_ia32_Immop_tarval(node);
274 be_emit_tarval(env, tv);
276 case ia32_ImmSymConst:
277 ent = get_ia32_Immop_symconst(node);
278 set_entity_backend_marked(ent, 1);
279 id = get_entity_ld_ident(ent);
280 be_emit_ident(env, id);
287 be_emit_string(env, "BAD");
292 void ia32_emit_mode_suffix_mode(ia32_emit_env_t *env, const ir_mode *mode)
294 be_emit_char(env, get_mode_suffix(mode));
297 void ia32_emit_mode_suffix(ia32_emit_env_t *env, const ir_node *node)
299 ir_mode *mode = get_ia32_ls_mode(node);
303 ia32_emit_mode_suffix_mode(env, mode);
306 void ia32_emit_x87_mode_suffix(ia32_emit_env_t *env, const ir_node *node)
308 ir_mode *mode = get_ia32_ls_mode(node);
310 ia32_emit_mode_suffix_mode(env, mode);
314 char get_xmm_mode_suffix(ir_mode *mode)
316 assert(mode_is_float(mode));
317 switch(get_mode_size_bits(mode)) {
328 void ia32_emit_xmm_mode_suffix(ia32_emit_env_t *env, const ir_node *node)
330 ir_mode *mode = get_ia32_ls_mode(node);
331 assert(mode != NULL);
332 be_emit_char(env, 's');
333 be_emit_char(env, get_xmm_mode_suffix(mode));
336 void ia32_emit_xmm_mode_suffix_s(ia32_emit_env_t *env, const ir_node *node)
338 ir_mode *mode = get_ia32_ls_mode(node);
339 assert(mode != NULL);
340 be_emit_char(env, get_xmm_mode_suffix(mode));
343 void ia32_emit_extend_suffix(ia32_emit_env_t *env, const ir_mode *mode)
345 if(get_mode_size_bits(mode) == 32)
347 if(mode_is_signed(mode)) {
348 be_emit_char(env, 's');
350 be_emit_char(env, 'z');
355 void ia32_emit_function_object(ia32_emit_env_t *env, const char *name)
357 switch (be_gas_flavour) {
358 case GAS_FLAVOUR_NORMAL:
359 be_emit_cstring(env, "\t.type\t");
360 be_emit_string(env, name);
361 be_emit_cstring(env, ", @function\n");
362 be_emit_write_line(env);
364 case GAS_FLAVOUR_MINGW:
365 be_emit_cstring(env, "\t.def\t");
366 be_emit_string(env, name);
367 be_emit_cstring(env, ";\t.scl\t2;\t.type\t32;\t.endef\n");
368 be_emit_write_line(env);
376 void ia32_emit_function_size(ia32_emit_env_t *env, const char *name)
378 switch (be_gas_flavour) {
379 case GAS_FLAVOUR_NORMAL:
380 be_emit_cstring(env, "\t.size\t");
381 be_emit_string(env, name);
382 be_emit_cstring(env, ", .-");
383 be_emit_string(env, name);
384 be_emit_char(env, '\n');
385 be_emit_write_line(env);
394 void emit_ia32_Immediate(ia32_emit_env_t *env, const ir_node *node);
397 * Emits registers and/or address mode of a binary operation.
399 void ia32_emit_binop(ia32_emit_env_t *env, const ir_node *node) {
401 const ir_node *right_op;
403 switch(get_ia32_op_type(node)) {
405 right_op = get_irn_n(node, 3);
406 if(is_ia32_Immediate(right_op)) {
407 emit_ia32_Immediate(env, right_op);
408 be_emit_cstring(env, ", ");
409 ia32_emit_source_register(env, node, 2);
411 } else if (is_ia32_ImmConst(node) || is_ia32_ImmSymConst(node)) {
412 ia32_emit_immediate(env, node);
413 be_emit_cstring(env, ", ");
414 ia32_emit_source_register(env, node, 2);
416 const arch_register_t *in1 = get_in_reg(env, node, 2);
417 const arch_register_t *in2 = get_in_reg(env, node, 3);
418 const arch_register_t *out = produces_result(node) ? get_out_reg(env, node, 0) : NULL;
419 const arch_register_t *in;
422 in = out ? (REGS_ARE_EQUAL(out, in2) ? in1 : in2) : in2;
423 out = out ? out : in1;
424 in_name = arch_register_get_name(in);
426 if (is_ia32_emit_cl(node)) {
427 assert(REGS_ARE_EQUAL(&ia32_gp_regs[REG_ECX], in) && "shift operation needs ecx");
431 be_emit_char(env, '%');
432 be_emit_string(env, in_name);
433 be_emit_cstring(env, ", %");
434 be_emit_string(env, arch_register_get_name(out));
438 ia32_emit_am(env, node);
439 be_emit_cstring(env, ", ");
440 if (is_ia32_ImmConst(node) || is_ia32_ImmSymConst(node)) {
441 assert(!produces_result(node) && "Source AM with Const must not produce result");
442 ia32_emit_immediate(env, node);
443 } else if (produces_result(node)) {
444 ia32_emit_dest_register(env, node, 0);
446 ia32_emit_source_register(env, node, 2);
450 right_pos = get_irn_arity(node) == 5 ? 3 : 2;
451 right_op = get_irn_n(node, right_pos);
452 if(is_ia32_Immediate(right_op)) {
453 emit_ia32_Immediate(env, right_op);
454 be_emit_cstring(env, ", ");
455 ia32_emit_am(env, node);
457 } else if (is_ia32_ImmConst(node) || is_ia32_ImmSymConst(node)) {
458 ia32_emit_immediate(env, node);
459 be_emit_cstring(env, ", ");
460 ia32_emit_am(env, node);
462 const arch_register_t *in1 = get_in_reg(env, node, right_pos);
463 ir_mode *mode = get_ia32_ls_mode(node);
466 in_name = ia32_get_reg_name_for_mode(env, mode, in1);
468 if (is_ia32_emit_cl(node)) {
469 assert(REGS_ARE_EQUAL(&ia32_gp_regs[REG_ECX], in1) && "shift operation needs ecx");
473 be_emit_char(env, '%');
474 be_emit_string(env, in_name);
475 be_emit_cstring(env, ", ");
476 ia32_emit_am(env, node);
480 assert(0 && "unsupported op type");
485 * Emits registers and/or address mode of a binary operation.
487 void ia32_emit_x87_binop(ia32_emit_env_t *env, const ir_node *node) {
488 switch(get_ia32_op_type(node)) {
490 if (is_ia32_ImmConst(node) || is_ia32_ImmSymConst(node)) {
491 // should not happen...
494 const ia32_x87_attr_t *x87_attr = get_ia32_x87_attr_const(node);
495 const arch_register_t *in1 = x87_attr->x87[0];
496 const arch_register_t *in2 = x87_attr->x87[1];
497 const arch_register_t *out = x87_attr->x87[2];
498 const arch_register_t *in;
500 in = out ? (REGS_ARE_EQUAL(out, in2) ? in1 : in2) : in2;
501 out = out ? out : in1;
503 be_emit_char(env, '%');
504 be_emit_string(env, arch_register_get_name(in));
505 be_emit_cstring(env, ", %");
506 be_emit_string(env, arch_register_get_name(out));
511 ia32_emit_am(env, node);
514 assert(0 && "unsupported op type");
518 void ia32_emit_am_or_dest_register(ia32_emit_env_t *env, const ir_node *node,
520 if(get_ia32_op_type(node) == ia32_Normal) {
521 ia32_emit_dest_register(env, node, pos);
523 assert(get_ia32_op_type(node) == ia32_AddrModeD);
524 ia32_emit_am(env, node);
529 * Emits registers and/or address mode of a unary operation.
531 void ia32_emit_unop(ia32_emit_env_t *env, const ir_node *node, int pos) {
534 switch(get_ia32_op_type(node)) {
536 op = get_irn_n(node, pos);
537 if (is_ia32_Immediate(op)) {
538 emit_ia32_Immediate(env, op);
539 } else if (is_ia32_ImmConst(node) || is_ia32_ImmSymConst(node)) {
540 ia32_emit_immediate(env, node);
542 ia32_emit_source_register(env, node, pos);
547 ia32_emit_am(env, node);
550 assert(0 && "unsupported op type");
555 * Emits address mode.
557 void ia32_emit_am(ia32_emit_env_t *env, const ir_node *node) {
558 ir_entity *ent = get_ia32_am_sc(node);
559 int offs = get_ia32_am_offs_int(node);
560 ir_node *base = get_irn_n(node, 0);
561 int has_base = !is_ia32_NoReg_GP(base);
562 ir_node *index = get_irn_n(node, 1);
563 int has_index = !is_ia32_NoReg_GP(index);
565 /* just to be sure... */
566 assert(!is_ia32_use_frame(node) || get_ia32_frame_ent(node) != NULL);
572 set_entity_backend_marked(ent, 1);
573 id = get_entity_ld_ident(ent);
574 if (is_ia32_am_sc_sign(node))
575 be_emit_char(env, '-');
576 be_emit_ident(env, id);
578 if(get_entity_owner(ent) == get_tls_type()) {
579 if (get_entity_visibility(ent) == visibility_external_allocated) {
580 be_emit_cstring(env, "@INDNTPOFF");
582 be_emit_cstring(env, "@NTPOFF");
589 be_emit_irprintf(env->emit, "%+d", offs);
591 be_emit_irprintf(env->emit, "%d", offs);
595 if (has_base || has_index) {
596 be_emit_char(env, '(');
600 ia32_emit_source_register(env, node, 0);
603 /* emit index + scale */
606 be_emit_char(env, ',');
607 ia32_emit_source_register(env, node, 1);
609 scale = get_ia32_am_scale(node);
611 be_emit_irprintf(env->emit, ",%d", 1 << get_ia32_am_scale(node));
614 be_emit_char(env, ')');
618 /*************************************************
621 * ___ _ __ ___ _| |_ ___ ___ _ __ __| |
622 * / _ \ '_ ` _ \| | __| / __/ _ \| '_ \ / _` |
623 * | __/ | | | | | | |_ | (_| (_) | | | | (_| |
624 * \___|_| |_| |_|_|\__| \___\___/|_| |_|\__,_|
626 *************************************************/
629 #define IA32_DO_EMIT(irn) ia32_fprintf_format(F, irn, cmd_buf, cmnt_buf)
632 * coding of conditions
634 struct cmp2conditon_t {
640 * positive conditions for signed compares
643 const struct cmp2conditon_t cmp2condition_s[] = {
644 { NULL, pn_Cmp_False }, /* always false */
645 { "e", pn_Cmp_Eq }, /* == */
646 { "l", pn_Cmp_Lt }, /* < */
647 { "le", pn_Cmp_Le }, /* <= */
648 { "g", pn_Cmp_Gt }, /* > */
649 { "ge", pn_Cmp_Ge }, /* >= */
650 { "ne", pn_Cmp_Lg }, /* != */
651 { NULL, pn_Cmp_Leg}, /* Floating point: ordered */
652 { NULL, pn_Cmp_Uo }, /* Floating point: unordered */
653 { "e", pn_Cmp_Ue }, /* Floating point: unordered or == */
654 { "b", pn_Cmp_Ul }, /* Floating point: unordered or < */
655 { "be", pn_Cmp_Ule }, /* Floating point: unordered or <= */
656 { "a", pn_Cmp_Ug }, /* Floating point: unordered or > */
657 { "ae", pn_Cmp_Uge }, /* Floating point: unordered or >= */
658 { "ne", pn_Cmp_Ne }, /* Floating point: unordered or != */
659 { NULL, pn_Cmp_True }, /* always true */
663 * positive conditions for unsigned compares
666 const struct cmp2conditon_t cmp2condition_u[] = {
667 { NULL, pn_Cmp_False }, /* always false */
668 { "e", pn_Cmp_Eq }, /* == */
669 { "b", pn_Cmp_Lt }, /* < */
670 { "be", pn_Cmp_Le }, /* <= */
671 { "a", pn_Cmp_Gt }, /* > */
672 { "ae", pn_Cmp_Ge }, /* >= */
673 { "ne", pn_Cmp_Lg }, /* != */
674 { NULL, pn_Cmp_True }, /* always true */
678 * returns the condition code
681 const char *get_cmp_suffix(pn_Cmp cmp_code)
683 assert( (cmp2condition_s[cmp_code & 15].num) == (cmp_code & 15));
684 assert( (cmp2condition_u[cmp_code & 7].num) == (cmp_code & 7));
686 if((cmp_code & ia32_pn_Cmp_Unsigned)) {
687 return cmp2condition_u[cmp_code & 7].name;
689 return cmp2condition_s[cmp_code & 15].name;
693 void ia32_emit_cmp_suffix(ia32_emit_env_t *env, long pnc)
695 be_emit_string(env, get_cmp_suffix(pnc));
700 * Returns the target block for a control flow node.
703 ir_node *get_cfop_target_block(const ir_node *irn) {
704 return get_irn_link(irn);
708 * Emits a block label for the given block.
711 void ia32_emit_block_name(ia32_emit_env_t *env, const ir_node *block)
713 be_emit_cstring(env, BLOCK_PREFIX);
714 be_emit_irprintf(env->emit, "%d", get_irn_node_nr(block));
718 * Emits the target label for a control flow node.
721 void ia32_emit_cfop_target(ia32_emit_env_t * env, const ir_node *node) {
722 ir_node *block = get_cfop_target_block(node);
724 ia32_emit_block_name(env, block);
727 /** Return the next block in Block schedule */
728 static ir_node *next_blk_sched(const ir_node *block) {
729 return get_irn_link(block);
733 * Returns the Proj with projection number proj and NOT mode_M
736 ir_node *get_proj(const ir_node *node, long proj) {
737 const ir_edge_t *edge;
740 assert(get_irn_mode(node) == mode_T && "expected mode_T node");
742 foreach_out_edge(node, edge) {
743 src = get_edge_src_irn(edge);
745 assert(is_Proj(src) && "Proj expected");
746 if (get_irn_mode(src) == mode_M)
749 if (get_Proj_proj(src) == proj)
756 * Emits the jump sequence for a conditional jump (cmp + jmp_true + jmp_false)
759 void finish_CondJmp(ia32_emit_env_t *env, const ir_node *node, ir_mode *mode,
761 const ir_node *proj_true;
762 const ir_node *proj_false;
763 const ir_node *block;
764 const ir_node *next_block;
767 /* get both Proj's */
768 proj_true = get_proj(node, pn_Cond_true);
769 assert(proj_true && "CondJmp without true Proj");
771 proj_false = get_proj(node, pn_Cond_false);
772 assert(proj_false && "CondJmp without false Proj");
774 /* for now, the code works for scheduled and non-schedules blocks */
775 block = get_nodes_block(node);
777 /* we have a block schedule */
778 next_block = next_blk_sched(block);
780 if (get_cfop_target_block(proj_true) == next_block) {
781 /* exchange both proj's so the second one can be omitted */
782 const ir_node *t = proj_true;
784 proj_true = proj_false;
787 pnc = get_negated_pnc(pnc, mode);
790 /* in case of unordered compare, check for parity */
791 if (pnc & pn_Cmp_Uo) {
792 be_emit_cstring(env, "\tjp ");
793 ia32_emit_cfop_target(env, proj_true);
794 be_emit_finish_line_gas(env, proj_true);
797 be_emit_cstring(env, "\tj");
798 ia32_emit_cmp_suffix(env, pnc);
799 be_emit_char(env, ' ');
800 ia32_emit_cfop_target(env, proj_true);
801 be_emit_finish_line_gas(env, proj_true);
803 /* the second Proj might be a fallthrough */
804 if (get_cfop_target_block(proj_false) != next_block) {
805 be_emit_cstring(env, "\tjmp ");
806 ia32_emit_cfop_target(env, proj_false);
807 be_emit_finish_line_gas(env, proj_false);
809 be_emit_cstring(env, "\t/* fallthrough to ");
810 ia32_emit_cfop_target(env, proj_false);
811 be_emit_cstring(env, " */");
812 be_emit_finish_line_gas(env, proj_false);
817 * Emits code for conditional jump.
820 void CondJmp_emitter(ia32_emit_env_t *env, const ir_node *node) {
821 be_emit_cstring(env, "\tcmp ");
822 ia32_emit_binop(env, node);
823 be_emit_finish_line_gas(env, node);
825 finish_CondJmp(env, node, mode_Iu, get_ia32_pncode(node));
829 * Emits code for conditional jump with two variables.
832 void emit_ia32_CondJmp(ia32_emit_env_t *env, const ir_node *node) {
833 CondJmp_emitter(env, node);
837 * Emits code for conditional test and jump.
840 void TestJmp_emitter(ia32_emit_env_t *env, const ir_node *node) {
841 be_emit_cstring(env, "\ttest ");
842 ia32_emit_binop(env, node);
843 be_emit_finish_line_gas(env, node);
845 finish_CondJmp(env, node, mode_Iu, get_ia32_pncode(node));
849 * Emits code for conditional test and jump with two variables.
852 void emit_ia32_TestJmp(ia32_emit_env_t *env, const ir_node *node) {
853 TestJmp_emitter(env, node);
857 void emit_ia32_CJmp(ia32_emit_env_t *env, const ir_node *node) {
858 be_emit_cstring(env, "/* omitted redundant test */");
859 be_emit_finish_line_gas(env, node);
861 finish_CondJmp(env, node, mode_Is, get_ia32_pncode(node));
865 void emit_ia32_CJmpAM(ia32_emit_env_t *env, const ir_node *node) {
866 be_emit_cstring(env, "/* omitted redundant test/cmp */");
867 be_emit_finish_line_gas(env, node);
869 finish_CondJmp(env, node, mode_Is, get_ia32_pncode(node));
873 * Emits code for conditional SSE floating point jump with two variables.
876 void emit_ia32_xCondJmp(ia32_emit_env_t *env, const ir_node *node) {
877 be_emit_cstring(env, "\tucomi");
878 ia32_emit_xmm_mode_suffix(env, node);
879 be_emit_char(env, ' ');
880 ia32_emit_binop(env, node);
881 be_emit_finish_line_gas(env, node);
883 finish_CondJmp(env, node, mode_F, get_ia32_pncode(node));
887 * Emits code for conditional x87 floating point jump with two variables.
890 void emit_ia32_x87CondJmp(ia32_emit_env_t *env, const ir_node *node) {
891 const ia32_x87_attr_t *x87_attr = get_ia32_x87_attr_const(node);
892 const char *reg = x87_attr->x87[1]->name;
893 long pnc = get_ia32_pncode(node);
895 switch (get_ia32_irn_opcode(node)) {
896 case iro_ia32_fcomrJmp:
897 pnc = get_inversed_pnc(pnc);
898 reg = x87_attr->x87[0]->name;
899 case iro_ia32_fcomJmp:
901 be_emit_cstring(env, "\tfucom ");
903 case iro_ia32_fcomrpJmp:
904 pnc = get_inversed_pnc(pnc);
905 reg = x87_attr->x87[0]->name;
906 case iro_ia32_fcompJmp:
907 be_emit_cstring(env, "\tfucomp ");
909 case iro_ia32_fcomrppJmp:
910 pnc = get_inversed_pnc(pnc);
911 case iro_ia32_fcomppJmp:
912 be_emit_cstring(env, "\tfucompp ");
918 be_emit_char(env, '%');
919 be_emit_string(env, reg);
921 be_emit_finish_line_gas(env, node);
923 be_emit_cstring(env, "\tfnstsw %ax");
924 be_emit_finish_line_gas(env, node);
925 be_emit_cstring(env, "\tsahf");
926 be_emit_finish_line_gas(env, node);
928 finish_CondJmp(env, node, mode_E, pnc);
932 void emit_register_or_immediate(ia32_emit_env_t *env, const ir_node *node,
935 ir_node *op = get_irn_n(node, pos);
936 if(is_ia32_Immediate(op)) {
937 emit_ia32_Immediate(env, op);
939 ia32_emit_source_register(env, node, pos);
944 int is_ia32_Immediate_0(const ir_node *node)
946 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(node);
948 return attr->offset == 0 && attr->symconst == NULL;
952 void CMov_emitter(ia32_emit_env_t *env, const ir_node *node)
954 long pnc = get_ia32_pncode(node);
955 const arch_register_t *in1, *in2, *out;
957 out = arch_get_irn_register(env->arch_env, node);
958 in1 = arch_get_irn_register(env->arch_env, get_irn_n(node, 2));
959 in2 = arch_get_irn_register(env->arch_env, get_irn_n(node, 3));
961 /* we have to emit the cmp first, because the destination register */
962 /* could be one of the compare registers */
963 if (is_ia32_CmpCMov(node)) {
964 long pncr = pnc & ~ia32_pn_Cmp_Unsigned;
965 ir_node *cmp_right = get_irn_n(node, 1);
967 if( (pncr == pn_Cmp_Eq || pncr == pn_Cmp_Lg)
968 && is_ia32_Immediate(cmp_right)
969 && is_ia32_Immediate_0(cmp_right)) {
970 be_emit_cstring(env, "\ttest ");
971 ia32_emit_source_register(env, node, 0);
972 be_emit_cstring(env, ", ");
973 ia32_emit_source_register(env, node, 0);
975 be_emit_cstring(env, "\tcmp ");
976 emit_register_or_immediate(env, node, 1);
977 be_emit_cstring(env, ", ");
978 ia32_emit_source_register(env, node, 0);
980 } else if (is_ia32_xCmpCMov(node)) {
981 be_emit_cstring(env, "\tucomis");
982 ia32_emit_mode_suffix_mode(env, get_irn_mode(node));
983 be_emit_char(env, ' ');
984 ia32_emit_source_register(env, node, 1);
985 be_emit_cstring(env, ", ");
986 ia32_emit_source_register(env, node, 0);
988 assert(0 && "unsupported CMov");
990 be_emit_finish_line_gas(env, node);
992 if (REGS_ARE_EQUAL(out, in2)) {
993 /* best case: default in == out -> do nothing */
994 } else if (REGS_ARE_EQUAL(out, in1)) {
995 ir_node *n = (ir_node*) node;
996 /* true in == out -> need complement compare and exchange true and default in */
997 ir_node *t = get_irn_n(n, 2);
998 set_irn_n(n, 2, get_irn_n(n, 3));
1001 pnc = get_negated_pnc(pnc, get_irn_mode(node));
1003 /* out is different from in: need copy default -> out */
1004 be_emit_cstring(env, "\tmovl ");
1005 ia32_emit_source_register(env, node, n_ia32_CmpCMov_val_false);
1006 be_emit_cstring(env, ", ");
1007 ia32_emit_dest_register(env, node, 0);
1008 be_emit_finish_line_gas(env, node);
1011 be_emit_cstring(env, "\tcmov");
1012 ia32_emit_cmp_suffix(env, pnc);
1013 be_emit_cstring(env, "l ");
1014 ia32_emit_source_register(env, node, n_ia32_CmpCMov_val_true);
1015 be_emit_cstring(env, ", ");
1016 ia32_emit_dest_register(env, node, 0);
1017 be_emit_finish_line_gas(env, node);
1021 void emit_ia32_CmpCMov(ia32_emit_env_t *env, const ir_node *node)
1023 CMov_emitter(env, node);
1027 void emit_ia32_xCmpCMov(ia32_emit_env_t *env, const ir_node *node)
1029 CMov_emitter(env, node);
1033 void Set_emitter(ia32_emit_env_t *env, const ir_node *node)
1035 long pnc = get_ia32_pncode(node);
1036 const char *reg8bit;
1037 const arch_register_t *out;
1039 out = arch_get_irn_register(env->arch_env, node);
1040 reg8bit = ia32_get_mapped_reg_name(env->isa->regs_8bit, out);
1042 if (is_ia32_CmpSet(node)) {
1043 long pncr = pnc & ~ia32_pn_Cmp_Unsigned;
1044 ir_node *cmp_right = get_irn_n(node, n_ia32_CmpSet_cmp_right);
1046 if( (pncr == pn_Cmp_Eq || pncr == pn_Cmp_Lg)
1047 && is_ia32_Immediate(cmp_right)
1048 && is_ia32_Immediate_0(cmp_right)) {
1049 be_emit_cstring(env, "\ttest ");
1050 ia32_emit_source_register(env, node, n_ia32_CmpSet_cmp_left);
1051 be_emit_cstring(env, ", ");
1052 ia32_emit_source_register(env, node, n_ia32_CmpSet_cmp_left);
1054 be_emit_cstring(env, "\tcmp ");
1055 ia32_emit_binop(env, node);
1057 } else if (is_ia32_xCmpSet(node)) {
1058 be_emit_cstring(env, "\tucomis");
1059 ia32_emit_mode_suffix_mode(env, get_irn_mode(get_irn_n(node, 2)));
1060 be_emit_char(env, ' ');
1061 ia32_emit_binop(env, node);
1063 assert(0 && "unsupported Set");
1065 be_emit_finish_line_gas(env, node);
1067 /* use mov to clear target because it doesn't affect the eflags */
1068 be_emit_cstring(env, "\tmovl $0, %");
1069 be_emit_string(env, arch_register_get_name(out));
1070 be_emit_finish_line_gas(env, node);
1072 be_emit_cstring(env, "\tset");
1073 ia32_emit_cmp_suffix(env, pnc);
1074 be_emit_cstring(env, " %");
1075 be_emit_string(env, reg8bit);
1076 be_emit_finish_line_gas(env, node);
1080 void emit_ia32_CmpSet(ia32_emit_env_t *env, const ir_node *node) {
1081 Set_emitter(env, node);
1085 void emit_ia32_xCmpSet(ia32_emit_env_t *env, const ir_node *node) {
1086 Set_emitter(env, node);
1090 void emit_ia32_xCmp(ia32_emit_env_t *env, const ir_node *node) {
1092 long pnc = get_ia32_pncode(node);
1093 long unord = pnc & pn_Cmp_Uo;
1095 assert( (pnc & ia32_pn_Cmp_Unsigned) == 0);
1098 case pn_Cmp_Leg: /* odered */
1101 case pn_Cmp_Uo: /* unordered */
1105 case pn_Cmp_Eq: /* == */
1109 case pn_Cmp_Lt: /* < */
1113 case pn_Cmp_Le: /* <= */
1117 case pn_Cmp_Gt: /* > */
1121 case pn_Cmp_Ge: /* >= */
1125 case pn_Cmp_Lg: /* != */
1130 assert(sse_pnc >= 0 && "unsupported compare");
1132 if (unord && sse_pnc != 3) {
1134 We need a separate compare against unordered.
1135 Quick and Dirty solution:
1136 - get some memory on stack
1140 - and result and stored result
1143 be_emit_cstring(env, "\tsubl $8, %esp");
1144 be_emit_finish_line_gas(env, node);
1146 be_emit_cstring(env, "\tcmpsd $3, ");
1147 ia32_emit_binop(env, node);
1148 be_emit_finish_line_gas(env, node);
1150 be_emit_cstring(env, "\tmovsd ");
1151 ia32_emit_dest_register(env, node, 0);
1152 be_emit_cstring(env, ", (%esp)");
1153 be_emit_finish_line_gas(env, node);
1156 be_emit_cstring(env, "\tcmpsd ");
1157 be_emit_irprintf(env->emit, "%d, ", sse_pnc);
1158 ia32_emit_binop(env, node);
1159 be_emit_finish_line_gas(env, node);
1161 if (unord && sse_pnc != 3) {
1162 be_emit_cstring(env, "\tandpd (%esp), ");
1163 ia32_emit_dest_register(env, node, 0);
1164 be_emit_finish_line_gas(env, node);
1166 be_emit_cstring(env, "\taddl $8, %esp");
1167 be_emit_finish_line_gas(env, node);
1171 /*********************************************************
1174 * ___ _ __ ___ _| |_ _ _ _ _ __ ___ _ __ ___
1175 * / _ \ '_ ` _ \| | __| | | | | | '_ ` _ \| '_ \/ __|
1176 * | __/ | | | | | | |_ | | |_| | | | | | | |_) \__ \
1177 * \___|_| |_| |_|_|\__| | |\__,_|_| |_| |_| .__/|___/
1180 *********************************************************/
1182 /* jump table entry (target and corresponding number) */
1183 typedef struct _branch_t {
1188 /* jump table for switch generation */
1189 typedef struct _jmp_tbl_t {
1190 ir_node *defProj; /**< default target */
1191 long min_value; /**< smallest switch case */
1192 long max_value; /**< largest switch case */
1193 long num_branches; /**< number of jumps */
1194 char *label; /**< label of the jump table */
1195 branch_t *branches; /**< jump array */
1199 * Compare two variables of type branch_t. Used to sort all switch cases
1202 int ia32_cmp_branch_t(const void *a, const void *b) {
1203 branch_t *b1 = (branch_t *)a;
1204 branch_t *b2 = (branch_t *)b;
1206 if (b1->value <= b2->value)
1213 * Emits code for a SwitchJmp (creates a jump table if
1214 * possible otherwise a cmp-jmp cascade). Port from
1218 void emit_ia32_SwitchJmp(ia32_emit_env_t *env, const ir_node *node) {
1219 unsigned long interval;
1224 const ir_edge_t *edge;
1226 /* fill the table structure */
1227 tbl.label = xmalloc(SNPRINTF_BUF_LEN);
1228 tbl.label = get_unique_label(tbl.label, SNPRINTF_BUF_LEN, ".TBL_");
1230 tbl.num_branches = get_irn_n_edges(node);
1231 tbl.branches = xcalloc(tbl.num_branches, sizeof(tbl.branches[0]));
1232 tbl.min_value = INT_MAX;
1233 tbl.max_value = INT_MIN;
1236 /* go over all proj's and collect them */
1237 foreach_out_edge(node, edge) {
1238 proj = get_edge_src_irn(edge);
1239 assert(is_Proj(proj) && "Only proj allowed at SwitchJmp");
1241 pnc = get_Proj_proj(proj);
1243 /* create branch entry */
1244 tbl.branches[i].target = proj;
1245 tbl.branches[i].value = pnc;
1247 tbl.min_value = pnc < tbl.min_value ? pnc : tbl.min_value;
1248 tbl.max_value = pnc > tbl.max_value ? pnc : tbl.max_value;
1250 /* check for default proj */
1251 if (pnc == get_ia32_pncode(node)) {
1252 assert(tbl.defProj == NULL && "found two defProjs at SwitchJmp");
1259 /* sort the branches by their number */
1260 qsort(tbl.branches, tbl.num_branches, sizeof(tbl.branches[0]), ia32_cmp_branch_t);
1262 /* two-complement's magic make this work without overflow */
1263 interval = tbl.max_value - tbl.min_value;
1265 /* emit the table */
1266 be_emit_cstring(env, "\tcmpl $");
1267 be_emit_irprintf(env->emit, "%u, ", interval);
1268 ia32_emit_source_register(env, node, 0);
1269 be_emit_finish_line_gas(env, node);
1271 be_emit_cstring(env, "\tja ");
1272 ia32_emit_cfop_target(env, tbl.defProj);
1273 be_emit_finish_line_gas(env, node);
1275 if (tbl.num_branches > 1) {
1277 be_emit_cstring(env, "\tjmp *");
1278 be_emit_string(env, tbl.label);
1279 be_emit_cstring(env, "(,");
1280 ia32_emit_source_register(env, node, 0);
1281 be_emit_cstring(env, ",4)");
1282 be_emit_finish_line_gas(env, node);
1284 be_gas_emit_switch_section(env->emit, GAS_SECTION_RODATA);
1285 be_emit_cstring(env, "\t.align 4\n");
1286 be_emit_write_line(env);
1288 be_emit_string(env, tbl.label);
1289 be_emit_cstring(env, ":\n");
1290 be_emit_write_line(env);
1292 be_emit_cstring(env, ".long ");
1293 ia32_emit_cfop_target(env, tbl.branches[0].target);
1294 be_emit_finish_line_gas(env, NULL);
1296 last_value = tbl.branches[0].value;
1297 for (i = 1; i < tbl.num_branches; ++i) {
1298 while (++last_value < tbl.branches[i].value) {
1299 be_emit_cstring(env, ".long ");
1300 ia32_emit_cfop_target(env, tbl.defProj);
1301 be_emit_finish_line_gas(env, NULL);
1303 be_emit_cstring(env, ".long ");
1304 ia32_emit_cfop_target(env, tbl.branches[i].target);
1305 be_emit_finish_line_gas(env, NULL);
1307 be_gas_emit_switch_section(env->emit, GAS_SECTION_TEXT);
1309 /* one jump is enough */
1310 be_emit_cstring(env, "\tjmp ");
1311 ia32_emit_cfop_target(env, tbl.branches[0].target);
1312 be_emit_finish_line_gas(env, node);
1322 * Emits code for a unconditional jump.
1325 void emit_Jmp(ia32_emit_env_t *env, const ir_node *node) {
1326 ir_node *block, *next_block;
1328 /* for now, the code works for scheduled and non-schedules blocks */
1329 block = get_nodes_block(node);
1331 /* we have a block schedule */
1332 next_block = next_blk_sched(block);
1333 if (get_cfop_target_block(node) != next_block) {
1334 be_emit_cstring(env, "\tjmp ");
1335 ia32_emit_cfop_target(env, node);
1337 be_emit_cstring(env, "\t/* fallthrough to ");
1338 ia32_emit_cfop_target(env, node);
1339 be_emit_cstring(env, " */");
1341 be_emit_finish_line_gas(env, node);
1345 void emit_ia32_Immediate(ia32_emit_env_t *env, const ir_node *node)
1347 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(node);
1349 be_emit_char(env, '$');
1350 if(attr->symconst != NULL) {
1351 ident *id = get_entity_ld_ident(attr->symconst);
1353 if(attr->attr.data.am_sc_sign)
1354 be_emit_char(env, '-');
1355 be_emit_ident(env, id);
1357 if(attr->symconst == NULL || attr->offset != 0) {
1358 if(attr->symconst != NULL)
1359 be_emit_char(env, '+');
1360 be_emit_irprintf(env->emit, "%d", attr->offset);
1365 const char* emit_asm_operand(ia32_emit_env_t *env, const ir_node *node,
1368 const arch_register_t *reg;
1369 const char *reg_name;
1373 const ia32_attr_t *attr;
1380 /* parse modifiers */
1383 ir_fprintf(stderr, "Warning: asm text (%+F) ends with %\n", node);
1384 be_emit_char(env, '%');
1387 be_emit_char(env, '%');
1407 ir_fprintf(stderr, "Warning: asm text (%+F) contains unknown modifier "
1408 "'%c' for asm op\n", node, c);
1414 sscanf(s, "%d%n", &num, &p);
1416 ir_fprintf(stderr, "Warning: Couldn't parse assembler operand (%+F)\n",
1424 attr = get_ia32_attr_const(node);
1425 n_outs = ARR_LEN(attr->slots);
1427 reg = get_out_reg(env, node, num);
1430 int in = num - n_outs;
1431 if(in >= get_irn_arity(node)) {
1432 ir_fprintf(stderr, "Warning: Invalid input %d specified in asm "
1433 "op (%+F)\n", num, node);
1436 pred = get_irn_n(node, in);
1437 /* might be an immediate value */
1438 if(is_ia32_Immediate(pred)) {
1439 emit_ia32_Immediate(env, pred);
1442 reg = get_in_reg(env, node, in);
1445 ir_fprintf(stderr, "Warning: no register assigned for %d asm op "
1446 "(%+F)\n", num, node);
1451 be_emit_char(env, '%');
1454 reg_name = arch_register_get_name(reg);
1457 reg_name = ia32_get_mapped_reg_name(env->isa->regs_8bit, reg);
1460 reg_name = ia32_get_mapped_reg_name(env->isa->regs_8bit_high, reg);
1463 reg_name = ia32_get_mapped_reg_name(env->isa->regs_16bit, reg);
1466 panic("Invalid asm op modifier");
1468 be_emit_string(env, reg_name);
1474 * Emits code for an ASM pseudo op.
1477 void emit_ia32_Asm(ia32_emit_env_t *env, const ir_node *node)
1479 const void *gen_attr = get_irn_generic_attr_const(node);
1480 const ia32_asm_attr_t *attr
1481 = CONST_CAST_IA32_ATTR(ia32_asm_attr_t, gen_attr);
1482 ident *asm_text = attr->asm_text;
1483 const char *s = get_id_str(asm_text);
1485 be_emit_cstring(env, "# Begin ASM \t");
1486 be_emit_finish_line_gas(env, node);
1489 be_emit_char(env, '\t');
1493 s = emit_asm_operand(env, node, s);
1496 be_emit_char(env, *s);
1501 be_emit_char(env, '\n');
1502 be_emit_write_line(env);
1504 be_emit_cstring(env, "# End ASM\n");
1505 be_emit_write_line(env);
1508 /**********************************
1511 * | | ___ _ __ _ _| |_) |
1512 * | | / _ \| '_ \| | | | _ <
1513 * | |___| (_) | |_) | |_| | |_) |
1514 * \_____\___/| .__/ \__, |____/
1517 **********************************/
1520 * Emit movsb/w instructions to make mov count divideable by 4
1523 void emit_CopyB_prolog(ia32_emit_env_t *env, int rem) {
1524 be_emit_cstring(env, "\tcld");
1525 be_emit_finish_line_gas(env, NULL);
1529 be_emit_cstring(env, "\tmovsb");
1530 be_emit_finish_line_gas(env, NULL);
1533 be_emit_cstring(env, "\tmovsw");
1534 be_emit_finish_line_gas(env, NULL);
1537 be_emit_cstring(env, "\tmovsb");
1538 be_emit_finish_line_gas(env, NULL);
1539 be_emit_cstring(env, "\tmovsw");
1540 be_emit_finish_line_gas(env, NULL);
1546 * Emit rep movsd instruction for memcopy.
1549 void emit_ia32_CopyB(ia32_emit_env_t *env, const ir_node *node) {
1550 tarval *tv = get_ia32_Immop_tarval(node);
1551 int rem = get_tarval_long(tv);
1553 emit_CopyB_prolog(env, rem);
1555 be_emit_cstring(env, "\trep movsd");
1556 be_emit_finish_line_gas(env, node);
1560 * Emits unrolled memcopy.
1563 void emit_ia32_CopyB_i(ia32_emit_env_t *env, const ir_node *node) {
1564 tarval *tv = get_ia32_Immop_tarval(node);
1565 int size = get_tarval_long(tv);
1567 emit_CopyB_prolog(env, size & 0x3);
1571 be_emit_cstring(env, "\tmovsd");
1572 be_emit_finish_line_gas(env, NULL);
1578 /***************************
1582 * | | / _ \| '_ \ \ / /
1583 * | |___| (_) | | | \ V /
1584 * \_____\___/|_| |_|\_/
1586 ***************************/
1589 * Emit code for conversions (I, FP), (FP, I) and (FP, FP).
1592 void emit_ia32_Conv_with_FP(ia32_emit_env_t *env, const ir_node *node) {
1593 ir_mode *ls_mode = get_ia32_ls_mode(node);
1594 int ls_bits = get_mode_size_bits(ls_mode);
1596 be_emit_cstring(env, "\tcvt");
1598 if(is_ia32_Conv_I2FP(node)) {
1600 be_emit_cstring(env, "si2ss");
1602 be_emit_cstring(env, "si2sd");
1604 } else if(is_ia32_Conv_FP2I(node)) {
1606 be_emit_cstring(env, "ss2si");
1608 be_emit_cstring(env, "sd2si");
1611 assert(is_ia32_Conv_FP2FP(node));
1613 be_emit_cstring(env, "sd2ss");
1615 be_emit_cstring(env, "ss2sd");
1618 be_emit_char(env, ' ');
1620 switch(get_ia32_op_type(node)) {
1622 ia32_emit_source_register(env, node, 2);
1623 be_emit_cstring(env, ", ");
1624 ia32_emit_dest_register(env, node, 0);
1626 case ia32_AddrModeS:
1627 ia32_emit_dest_register(env, node, 0);
1628 be_emit_cstring(env, ", ");
1629 ia32_emit_am(env, node);
1632 assert(0 && "unsupported op type for Conv");
1634 be_emit_finish_line_gas(env, node);
1638 void emit_ia32_Conv_I2FP(ia32_emit_env_t *env, const ir_node *node) {
1639 emit_ia32_Conv_with_FP(env, node);
1643 void emit_ia32_Conv_FP2I(ia32_emit_env_t *env, const ir_node *node) {
1644 emit_ia32_Conv_with_FP(env, node);
1648 void emit_ia32_Conv_FP2FP(ia32_emit_env_t *env, const ir_node *node) {
1649 emit_ia32_Conv_with_FP(env, node);
1653 * Emits code for an Int conversion.
1656 void emit_ia32_Conv_I2I(ia32_emit_env_t *env, const ir_node *node) {
1657 const char *sign_suffix;
1658 ir_mode *smaller_mode = get_ia32_ls_mode(node);
1659 int smaller_bits = get_mode_size_bits(smaller_mode);
1661 const arch_register_t *in_reg, *out_reg;
1663 assert(!mode_is_float(smaller_mode));
1664 assert(smaller_bits == 8 || smaller_bits == 16 || smaller_bits == 32);
1666 signed_mode = mode_is_signed(smaller_mode);
1667 if(smaller_bits == 32) {
1668 // this should not happen as it's no convert
1672 sign_suffix = signed_mode ? "s" : "z";
1675 switch(get_ia32_op_type(node)) {
1677 in_reg = get_in_reg(env, node, 2);
1678 out_reg = get_out_reg(env, node, 0);
1680 if (REGS_ARE_EQUAL(in_reg, &ia32_gp_regs[REG_EAX]) &&
1681 REGS_ARE_EQUAL(out_reg, in_reg) &&
1685 /* argument and result are both in EAX and */
1686 /* signedness is ok: -> use the smaller cwtl opcode */
1687 be_emit_cstring(env, "\tcwtl");
1689 const char *sreg = ia32_get_reg_name_for_mode(env, smaller_mode, in_reg);
1691 be_emit_cstring(env, "\tmov");
1692 be_emit_string(env, sign_suffix);
1693 ia32_emit_mode_suffix_mode(env, smaller_mode);
1694 be_emit_cstring(env, "l %");
1695 be_emit_string(env, sreg);
1696 be_emit_cstring(env, ", ");
1697 ia32_emit_dest_register(env, node, 0);
1700 case ia32_AddrModeS: {
1701 be_emit_cstring(env, "\tmov");
1702 be_emit_string(env, sign_suffix);
1703 ia32_emit_mode_suffix_mode(env, smaller_mode);
1704 be_emit_cstring(env, "l %");
1705 ia32_emit_am(env, node);
1706 be_emit_cstring(env, ", ");
1707 ia32_emit_dest_register(env, node, 0);
1711 assert(0 && "unsupported op type for Conv");
1713 be_emit_finish_line_gas(env, node);
1717 * Emits code for an 8Bit Int conversion.
1719 void emit_ia32_Conv_I2I8Bit(ia32_emit_env_t *env, const ir_node *node) {
1720 emit_ia32_Conv_I2I(env, node);
1724 /*******************************************
1727 * | |__ ___ _ __ ___ __| | ___ ___
1728 * | '_ \ / _ \ '_ \ / _ \ / _` |/ _ \/ __|
1729 * | |_) | __/ | | | (_) | (_| | __/\__ \
1730 * |_.__/ \___|_| |_|\___/ \__,_|\___||___/
1732 *******************************************/
1735 * Emits a backend call
1738 void emit_be_Call(ia32_emit_env_t *env, const ir_node *node) {
1739 ir_entity *ent = be_Call_get_entity(node);
1741 be_emit_cstring(env, "\tcall ");
1743 set_entity_backend_marked(ent, 1);
1744 be_emit_string(env, get_entity_ld_name(ent));
1746 be_emit_char(env, '*');
1747 ia32_emit_dest_register(env, get_irn_n(node, be_pos_Call_ptr), 0);
1749 be_emit_finish_line_gas(env, node);
1753 * Emits code to increase stack pointer.
1756 void emit_be_IncSP(ia32_emit_env_t *env, const ir_node *node) {
1757 int offs = be_get_IncSP_offset(node);
1763 be_emit_cstring(env, "\tsubl $");
1764 be_emit_irprintf(env->emit, "%u, ", offs);
1765 ia32_emit_source_register(env, node, 0);
1767 be_emit_cstring(env, "\taddl $");
1768 be_emit_irprintf(env->emit, "%u, ", -offs);
1769 ia32_emit_source_register(env, node, 0);
1771 be_emit_finish_line_gas(env, node);
1775 * Emits code to set stack pointer.
1778 void emit_be_SetSP(ia32_emit_env_t *env, const ir_node *node) {
1779 be_emit_cstring(env, "\tmovl ");
1780 ia32_emit_source_register(env, node, 2);
1781 be_emit_cstring(env, ", ");
1782 ia32_emit_dest_register(env, node, 0);
1783 be_emit_finish_line_gas(env, node);
1787 * Emits code for Copy/CopyKeep.
1790 void Copy_emitter(ia32_emit_env_t *env, const ir_node *node, const ir_node *op)
1792 const arch_env_t *aenv = env->arch_env;
1795 if (REGS_ARE_EQUAL(arch_get_irn_register(aenv, node), arch_get_irn_register(aenv, op)) ||
1796 arch_register_type_is(arch_get_irn_register(aenv, op), virtual))
1799 mode = get_irn_mode(node);
1800 if (mode == mode_E) {
1801 be_emit_cstring(env, "\tmovsd ");
1802 ia32_emit_source_register(env, node, 0);
1803 be_emit_cstring(env, ", ");
1804 ia32_emit_dest_register(env, node, 0);
1806 be_emit_cstring(env, "\tmovl ");
1807 ia32_emit_source_register(env, node, 0);
1808 be_emit_cstring(env, ", ");
1809 ia32_emit_dest_register(env, node, 0);
1811 be_emit_finish_line_gas(env, node);
1815 void emit_be_Copy(ia32_emit_env_t *env, const ir_node *node) {
1816 Copy_emitter(env, node, be_get_Copy_op(node));
1820 void emit_be_CopyKeep(ia32_emit_env_t *env, const ir_node *node) {
1821 Copy_emitter(env, node, be_get_CopyKeep_op(node));
1825 * Emits code for exchange.
1828 void emit_be_Perm(ia32_emit_env_t *env, const ir_node *node) {
1829 const arch_register_t *in1, *in2;
1830 const arch_register_class_t *cls1, *cls2;
1832 in1 = arch_get_irn_register(env->arch_env, get_irn_n(node, 0));
1833 in2 = arch_get_irn_register(env->arch_env, get_irn_n(node, 1));
1835 cls1 = arch_register_get_class(in1);
1836 cls2 = arch_register_get_class(in2);
1838 assert(cls1 == cls2 && "Register class mismatch at Perm");
1840 if (cls1 == &ia32_reg_classes[CLASS_ia32_gp]) {
1841 be_emit_cstring(env, "\txchg ");
1842 ia32_emit_source_register(env, node, 1);
1843 be_emit_cstring(env, ", ");
1844 ia32_emit_source_register(env, node, 0);
1845 be_emit_finish_line_gas(env, node);
1846 } else if (cls1 == &ia32_reg_classes[CLASS_ia32_xmm]) {
1847 be_emit_cstring(env, "\txorpd ");
1848 ia32_emit_source_register(env, node, 1);
1849 be_emit_cstring(env, ", ");
1850 ia32_emit_source_register(env, node, 0);
1851 be_emit_finish_line_gas(env, NULL);
1853 be_emit_cstring(env, "\txorpd ");
1854 ia32_emit_source_register(env, node, 0);
1855 be_emit_cstring(env, ", ");
1856 ia32_emit_source_register(env, node, 1);
1857 be_emit_finish_line_gas(env, NULL);
1859 be_emit_cstring(env, "\txorpd ");
1860 ia32_emit_source_register(env, node, 1);
1861 be_emit_cstring(env, ", ");
1862 ia32_emit_source_register(env, node, 0);
1863 be_emit_finish_line_gas(env, node);
1864 } else if (cls1 == &ia32_reg_classes[CLASS_ia32_vfp]) {
1866 } else if (cls1 == &ia32_reg_classes[CLASS_ia32_st]) {
1872 * Emits code for Constant loading.
1875 void emit_ia32_Const(ia32_emit_env_t *env, const ir_node *node) {
1876 ia32_immop_type_t imm_tp = get_ia32_immop_type(node);
1878 if (imm_tp == ia32_ImmSymConst) {
1879 be_emit_cstring(env, "\tmovl ");
1880 ia32_emit_immediate(env, node);
1881 be_emit_cstring(env, ", ");
1882 ia32_emit_dest_register(env, node, 0);
1884 tarval *tv = get_ia32_Immop_tarval(node);
1885 assert(get_irn_mode(node) == mode_Iu);
1886 /* beware: in some rare cases mode is mode_b which has no tarval_null() */
1887 if (tarval_is_null(tv)) {
1888 if (env->isa->opt_arch == arch_pentium_4) {
1889 /* P4 prefers sub r, r, others xor r, r */
1890 be_emit_cstring(env, "\tsubl ");
1892 be_emit_cstring(env, "\txorl ");
1894 ia32_emit_dest_register(env, node, 0);
1895 be_emit_cstring(env, ", ");
1896 ia32_emit_dest_register(env, node, 0);
1898 be_emit_cstring(env, "\tmovl ");
1899 ia32_emit_immediate(env, node);
1900 be_emit_cstring(env, ", ");
1901 ia32_emit_dest_register(env, node, 0);
1904 be_emit_finish_line_gas(env, node);
1908 * Emits code to load the TLS base
1911 void emit_ia32_LdTls(ia32_emit_env_t *env, const ir_node *node) {
1912 be_emit_cstring(env, "\tmovl %gs:0, ");
1913 ia32_emit_dest_register(env, node, 0);
1914 be_emit_finish_line_gas(env, node);
1918 void emit_be_Return(ia32_emit_env_t *env, const ir_node *node)
1920 be_emit_cstring(env, "\tret");
1921 be_emit_finish_line_gas(env, node);
1925 void emit_Nothing(ia32_emit_env_t *env, const ir_node *node)
1932 /***********************************************************************************
1935 * _ __ ___ __ _ _ _ __ | |_ _ __ __ _ _ __ ___ _____ _____ _ __| | __
1936 * | '_ ` _ \ / _` | | '_ \ | _| '__/ _` | '_ ` _ \ / _ \ \ /\ / / _ \| '__| |/ /
1937 * | | | | | | (_| | | | | | | | | | | (_| | | | | | | __/\ V V / (_) | | | <
1938 * |_| |_| |_|\__,_|_|_| |_| |_| |_| \__,_|_| |_| |_|\___| \_/\_/ \___/|_| |_|\_\
1940 ***********************************************************************************/
1943 * Enters the emitter functions for handled nodes into the generic
1944 * pointer of an opcode.
1947 void ia32_register_emitters(void) {
1949 #define IA32_EMIT2(a,b) op_ia32_##a->ops.generic = (op_func)emit_ia32_##b
1950 #define IA32_EMIT(a) IA32_EMIT2(a,a)
1951 #define EMIT(a) op_##a->ops.generic = (op_func)emit_##a
1952 #define IGN(a) op_##a->ops.generic = (op_func)emit_Nothing
1953 #define BE_EMIT(a) op_be_##a->ops.generic = (op_func)emit_be_##a
1954 #define BE_IGN(a) op_be_##a->ops.generic = (op_func)emit_Nothing
1956 /* first clear the generic function pointer for all ops */
1957 clear_irp_opcodes_generic_func();
1959 /* register all emitter functions defined in spec */
1960 ia32_register_spec_emitters();
1962 /* other ia32 emitter functions */
1970 IA32_EMIT(SwitchJmp);
1973 IA32_EMIT(Conv_I2FP);
1974 IA32_EMIT(Conv_FP2I);
1975 IA32_EMIT(Conv_FP2FP);
1976 IA32_EMIT(Conv_I2I);
1977 IA32_EMIT(Conv_I2I8Bit);
1982 IA32_EMIT(xCmpCMov);
1983 IA32_EMIT(xCondJmp);
1984 IA32_EMIT2(fcomJmp, x87CondJmp);
1985 IA32_EMIT2(fcompJmp, x87CondJmp);
1986 IA32_EMIT2(fcomppJmp, x87CondJmp);
1987 IA32_EMIT2(fcomrJmp, x87CondJmp);
1988 IA32_EMIT2(fcomrpJmp, x87CondJmp);
1989 IA32_EMIT2(fcomrppJmp, x87CondJmp);
1991 /* benode emitter */
2017 static const char *last_name = NULL;
2018 static unsigned last_line = -1;
2019 static unsigned num = -1;
2022 * Emit the debug support for node node.
2025 void ia32_emit_dbg(ia32_emit_env_t *env, const ir_node *node) {
2026 dbg_info *db = get_irn_dbg_info(node);
2028 const char *fname = be_retrieve_dbg_info(db, &lineno);
2030 if (! env->cg->birg->main_env->options->stabs_debug_support)
2034 if (last_name != fname) {
2036 be_dbg_include_begin(env->cg->birg->main_env->db_handle, fname);
2039 if (last_line != lineno) {
2042 snprintf(name, sizeof(name), ".LM%u", ++num);
2044 be_dbg_line(env->cg->birg->main_env->db_handle, lineno, name);
2045 be_emit_string(env, name);
2046 be_emit_cstring(env, ":\n");
2047 be_emit_write_line(env);
2052 typedef void (*emit_func_ptr) (ia32_emit_env_t *, const ir_node *);
2055 * Emits code for a node.
2058 void ia32_emit_node(ia32_emit_env_t *env, const ir_node *node) {
2059 ir_op *op = get_irn_op(node);
2061 DBG((dbg, LEVEL_1, "emitting code for %+F\n", node));
2063 if (op->ops.generic) {
2064 emit_func_ptr func = (emit_func_ptr) op->ops.generic;
2065 ia32_emit_dbg(env, node);
2066 (*func) (env, node);
2068 emit_Nothing(env, node);
2069 ir_fprintf(stderr, "Warning: No emit handler for node %+F (%+G)\n", node, node);
2074 * Emits gas alignment directives
2077 void ia32_emit_alignment(ia32_emit_env_t *env, unsigned align, unsigned skip) {
2078 be_emit_cstring(env, "\t.p2align ");
2079 be_emit_irprintf(env->emit, "%u,,%u\n", align, skip);
2080 be_emit_write_line(env);
2084 * Emits gas alignment directives for Functions depended on cpu architecture.
2087 void ia32_emit_align_func(ia32_emit_env_t *env, cpu_support cpu) {
2089 unsigned maximum_skip;
2104 maximum_skip = (1 << align) - 1;
2105 ia32_emit_alignment(env, align, maximum_skip);
2109 * Emits gas alignment directives for Labels depended on cpu architecture.
2112 void ia32_emit_align_label(ia32_emit_env_t *env, cpu_support cpu) {
2113 unsigned align; unsigned maximum_skip;
2128 maximum_skip = (1 << align) - 1;
2129 ia32_emit_alignment(env, align, maximum_skip);
2133 * Test wether a block should be aligned.
2134 * For cpus in the P4/Athlon class it is usefull to align jump labels to
2135 * 16 bytes. However we should only do that if the alignment nops before the
2136 * label aren't executed more often than we have jumps to the label.
2139 int should_align_block(ia32_emit_env_t *env, ir_node *block, ir_node *prev) {
2140 static const double DELTA = .0001;
2141 ir_exec_freq *exec_freq = env->cg->birg->exec_freq;
2143 double prev_freq = 0; /**< execfreq of the fallthrough block */
2144 double jmp_freq = 0; /**< execfreq of all non-fallthrough blocks */
2145 cpu_support cpu = env->isa->opt_arch;
2148 if(exec_freq == NULL)
2150 if(cpu == arch_i386 || cpu == arch_i486)
2153 block_freq = get_block_execfreq(exec_freq, block);
2154 if(block_freq < DELTA)
2157 n_cfgpreds = get_Block_n_cfgpreds(block);
2158 for(i = 0; i < n_cfgpreds; ++i) {
2159 ir_node *pred = get_Block_cfgpred_block(block, i);
2160 double pred_freq = get_block_execfreq(exec_freq, pred);
2163 prev_freq += pred_freq;
2165 jmp_freq += pred_freq;
2169 if(prev_freq < DELTA && !(jmp_freq < DELTA))
2172 jmp_freq /= prev_freq;
2176 case arch_athlon_64:
2178 return jmp_freq > 3;
2180 return jmp_freq > 2;
2185 void ia32_emit_block_header(ia32_emit_env_t *env, ir_node *block, ir_node *prev)
2190 ir_exec_freq *exec_freq = env->cg->birg->exec_freq;
2193 n_cfgpreds = get_Block_n_cfgpreds(block);
2194 if (n_cfgpreds == 0) {
2196 } else if (n_cfgpreds == 1) {
2197 ir_node *pred = get_Block_cfgpred(block, 0);
2198 ir_node *pred_block = get_nodes_block(pred);
2200 /* we don't need labels for fallthrough blocks, however switch-jmps
2201 * are no fallthroughs */
2202 if(pred_block == prev &&
2203 !(is_Proj(pred) && is_ia32_SwitchJmp(get_Proj_pred(pred)))) {
2212 if (should_align_block(env, block, prev)) {
2214 ia32_emit_align_label(env, env->isa->opt_arch);
2218 ia32_emit_block_name(env, block);
2219 be_emit_char(env, ':');
2221 be_emit_pad_comment(env);
2222 be_emit_cstring(env, " /* preds:");
2224 /* emit list of pred blocks in comment */
2225 arity = get_irn_arity(block);
2226 for (i = 0; i < arity; ++i) {
2227 ir_node *predblock = get_Block_cfgpred_block(block, i);
2228 be_emit_irprintf(env->emit, " %d", get_irn_node_nr(predblock));
2231 be_emit_cstring(env, "\t/* ");
2232 ia32_emit_block_name(env, block);
2233 be_emit_cstring(env, ": ");
2235 if (exec_freq != NULL) {
2236 be_emit_irprintf(env->emit, " freq: %f",
2237 get_block_execfreq(exec_freq, block));
2239 be_emit_cstring(env, " */\n");
2240 be_emit_write_line(env);
2244 * Walks over the nodes in a block connected by scheduling edges
2245 * and emits code for each node.
2248 void ia32_gen_block(ia32_emit_env_t *env, ir_node *block, ir_node *last_block)
2250 const ir_node *node;
2252 ia32_emit_block_header(env, block, last_block);
2254 /* emit the contents of the block */
2255 ia32_emit_dbg(env, block);
2256 sched_foreach(block, node) {
2257 ia32_emit_node(env, node);
2262 * Emits code for function start.
2265 void ia32_emit_func_prolog(ia32_emit_env_t *env, ir_graph *irg) {
2266 ir_entity *irg_ent = get_irg_entity(irg);
2267 const char *irg_name = get_entity_ld_name(irg_ent);
2268 cpu_support cpu = env->isa->opt_arch;
2269 const be_irg_t *birg = env->cg->birg;
2271 be_emit_write_line(env);
2272 be_gas_emit_switch_section(env->emit, GAS_SECTION_TEXT);
2273 be_dbg_method_begin(birg->main_env->db_handle, irg_ent, be_abi_get_stack_layout(birg->abi));
2274 ia32_emit_align_func(env, cpu);
2275 if (get_entity_visibility(irg_ent) == visibility_external_visible) {
2276 be_emit_cstring(env, ".global ");
2277 be_emit_string(env, irg_name);
2278 be_emit_char(env, '\n');
2279 be_emit_write_line(env);
2281 ia32_emit_function_object(env, irg_name);
2282 be_emit_string(env, irg_name);
2283 be_emit_cstring(env, ":\n");
2284 be_emit_write_line(env);
2288 * Emits code for function end
2291 void ia32_emit_func_epilog(ia32_emit_env_t *env, ir_graph *irg) {
2292 const char *irg_name = get_entity_ld_name(get_irg_entity(irg));
2293 const be_irg_t *birg = env->cg->birg;
2295 ia32_emit_function_size(env, irg_name);
2296 be_dbg_method_end(birg->main_env->db_handle);
2297 be_emit_char(env, '\n');
2298 be_emit_write_line(env);
2303 * Sets labels for control flow nodes (jump target)
2306 void ia32_gen_labels(ir_node *block, void *data)
2309 int n = get_Block_n_cfgpreds(block);
2312 for (n--; n >= 0; n--) {
2313 pred = get_Block_cfgpred(block, n);
2314 set_irn_link(pred, block);
2319 * Emit an exception label if the current instruction can fail.
2321 void ia32_emit_exc_label(ia32_emit_env_t *env, const ir_node *node) {
2322 if (get_ia32_exc_label(node)) {
2323 be_emit_irprintf(env->emit, ".EXL%u\n", 0);
2324 be_emit_write_line(env);
2329 * Main driver. Emits the code for one routine.
2331 void ia32_gen_routine(ia32_code_gen_t *cg, ir_graph *irg) {
2332 ia32_emit_env_t env;
2334 ir_node *last_block = NULL;
2337 env.isa = (ia32_isa_t *)cg->arch_env->isa;
2338 env.emit = &env.isa->emit;
2339 env.arch_env = cg->arch_env;
2342 ia32_register_emitters();
2344 ia32_emit_func_prolog(&env, irg);
2345 irg_block_walk_graph(irg, ia32_gen_labels, NULL, &env);
2347 n = ARR_LEN(cg->blk_sched);
2348 for (i = 0; i < n;) {
2351 block = cg->blk_sched[i];
2353 next_bl = i < n ? cg->blk_sched[i] : NULL;
2355 /* set here the link. the emitter expects to find the next block here */
2356 set_irn_link(block, next_bl);
2357 ia32_gen_block(&env, block, last_block);
2361 ia32_emit_func_epilog(&env, irg);
2364 void ia32_init_emitter(void)
2366 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.emitter");