2 * This file implements the node emitter.
3 * @author Christian Wuerdig
22 #include "iredges_t.h"
25 #include "../besched_t.h"
26 #include "../benode_t.h"
28 #include "../be_dbgout.h"
30 #include "ia32_emitter.h"
31 #include "gen_ia32_emitter.h"
32 #include "gen_ia32_regalloc_if.h"
33 #include "ia32_nodes_attr.h"
34 #include "ia32_new_nodes.h"
35 #include "ia32_map_regs.h"
36 #include "bearch_ia32_t.h"
38 #define BLOCK_PREFIX(x) ".L" x
40 #define SNPRINTF_BUF_LEN 128
42 /* global arch_env for lc_printf functions */
43 static const arch_env_t *arch_env = NULL;
45 /** by default, we generate assembler code for the Linux gas */
46 asm_flavour_t asm_flavour = ASM_LINUX_GAS;
49 * Switch to a new section
51 void ia32_switch_section(FILE *F, section_t sec) {
52 static section_t curr_sec = NO_SECTION;
53 static const char *text[ASM_MAX][SECTION_MAX] = {
59 ".section\t.tbss,\"awT\",@nobits",
60 ".section\t.ctors,\"aw\",@progbits"
65 ".section .rdata,\"dr\"",
67 ".section\t.tbss,\"awT\",@nobits",
68 ".section\t.ctors,\"aw\",@progbits"
87 fprintf(F, "\t%s\n", text[asm_flavour][sec]);
95 static void ia32_dump_function_object(FILE *F, const char *name)
97 switch (asm_flavour) {
99 fprintf(F, "\t.type\t%s, @function\n", name);
102 fprintf(F, "\t.def\t%s;\t.scl\t2;\t.type\t32;\t.endef\n", name);
109 static void ia32_dump_function_size(FILE *F, const char *name)
111 switch (asm_flavour) {
113 fprintf(F, "\t.size\t%s, .-%s\n", name, name);
120 /*************************************************************
122 * (_) | | / _| | | | |
123 * _ __ _ __ _ _ __ | |_| |_ | |__ ___| |_ __ ___ _ __
124 * | '_ \| '__| | '_ \| __| _| | '_ \ / _ \ | '_ \ / _ \ '__|
125 * | |_) | | | | | | | |_| | | | | | __/ | |_) | __/ |
126 * | .__/|_| |_|_| |_|\__|_| |_| |_|\___|_| .__/ \___|_|
129 *************************************************************/
131 /* We always pass the ir_node which is a pointer. */
132 static int ia32_get_arg_type(const lc_arg_occ_t *occ) {
133 return lc_arg_type_ptr;
138 * Returns the register at in position pos.
140 static const arch_register_t *get_in_reg(const ir_node *irn, int pos) {
142 const arch_register_t *reg = NULL;
144 assert(get_irn_arity(irn) > pos && "Invalid IN position");
146 /* The out register of the operator at position pos is the
147 in register we need. */
148 op = get_irn_n(irn, pos);
150 reg = arch_get_irn_register(arch_env, op);
152 assert(reg && "no in register found");
154 /* in case of a joker register: just return a valid register */
155 if (arch_register_type_is(reg, joker)) {
156 arch_register_req_t req;
157 const arch_register_req_t *p_req;
159 /* ask for the requirements */
160 p_req = arch_get_register_req(arch_env, &req, irn, pos);
162 if (arch_register_req_is(p_req, limited)) {
163 /* in case of limited requirements: get the first allowed register */
165 bitset_t *bs = bitset_alloca(arch_register_class_n_regs(p_req->cls));
168 p_req->limited(p_req->limited_env, bs);
169 idx = bitset_next_set(bs, 0);
170 reg = arch_register_for_index(p_req->cls, idx);
173 /* otherwise get first register in class */
174 reg = arch_register_for_index(p_req->cls, 0);
182 * Returns the register at out position pos.
184 static const arch_register_t *get_out_reg(const ir_node *irn, int pos) {
186 const arch_register_t *reg = NULL;
188 /* 1st case: irn is not of mode_T, so it has only */
189 /* one OUT register -> good */
190 /* 2nd case: irn is of mode_T -> collect all Projs and ask the */
191 /* Proj with the corresponding projnum for the register */
193 if (get_irn_mode(irn) != mode_T) {
194 reg = arch_get_irn_register(arch_env, irn);
196 else if (is_ia32_irn(irn)) {
197 reg = get_ia32_out_reg(irn, pos);
200 const ir_edge_t *edge;
202 foreach_out_edge(irn, edge) {
203 proj = get_edge_src_irn(edge);
204 assert(is_Proj(proj) && "non-Proj from mode_T node");
205 if (get_Proj_proj(proj) == pos) {
206 reg = arch_get_irn_register(arch_env, proj);
212 assert(reg && "no out register found");
222 * Returns the name of the in register at position pos.
224 static const char *get_ia32_reg_name(ir_node *irn, int pos, enum io_direction in_out) {
225 const arch_register_t *reg;
227 if (in_out == IN_REG) {
228 reg = get_in_reg(irn, pos);
230 if (reg->reg_class == &ia32_reg_classes[CLASS_ia32_vfp]) {
231 /* FIXME: works for binop only */
232 assert(2 <= pos && pos <= 3);
233 reg = get_ia32_attr(irn)->x87[pos - 2];
237 /* destination address mode nodes don't have outputs */
238 if (is_ia32_irn(irn) && get_ia32_op_type(irn) == ia32_AddrModeD) {
242 reg = get_out_reg(irn, pos);
243 if (reg->reg_class == &ia32_reg_classes[CLASS_ia32_vfp])
244 reg = get_ia32_attr(irn)->x87[pos + 2];
246 return arch_register_get_name(reg);
250 * Get the register name for a node.
252 static int ia32_get_reg_name(lc_appendable_t *app,
253 const lc_arg_occ_t *occ, const lc_arg_value_t *arg)
256 ir_node *irn = arg->v_ptr;
257 int nr = occ->width - 1;
260 return lc_appendable_snadd(app, "(null)", 6);
262 buf = get_ia32_reg_name(irn, nr, occ->conversion == 'S' ? IN_REG : OUT_REG);
264 /* append the stupid % to register names */
265 lc_appendable_chadd(app, '%');
266 return lc_appendable_snadd(app, buf, strlen(buf));
270 * Get the x87 register name for a node.
272 static int ia32_get_x87_name(lc_appendable_t *app,
273 const lc_arg_occ_t *occ, const lc_arg_value_t *arg)
276 ir_node *irn = arg->v_ptr;
277 int nr = occ->width - 1;
283 return lc_appendable_snadd(app, "(null)", 6);
285 attr = get_ia32_attr(irn);
286 buf = attr->x87[nr]->name;
288 res += lc_appendable_chadd(app, '%');
291 /* just omit 'st' (skip the 0) */
292 res += lc_appendable_snadd(app, buf, strlen(buf) - 1);
295 res += lc_appendable_snadd(app, "st(", 3);
296 res += lc_appendable_chadd(app, buf[2]);
297 res += lc_appendable_chadd(app, ')');
304 * Returns the tarval, offset or scale of an ia32 as a string.
306 static int ia32_const_to_str(lc_appendable_t *app,
307 const lc_arg_occ_t *occ, const lc_arg_value_t *arg)
310 ir_node *irn = arg->v_ptr;
313 return lc_arg_append(app, occ, "(null)", 6);
315 if (occ->conversion == 'C') {
316 buf = get_ia32_cnst(irn);
319 buf = get_ia32_am_offs(irn);
322 return buf ? lc_appendable_snadd(app, buf, strlen(buf)) : 0;
326 * Determines the SSE suffix depending on the mode.
328 static int ia32_get_mode_suffix(lc_appendable_t *app,
329 const lc_arg_occ_t *occ, const lc_arg_value_t *arg)
331 ir_node *irn = arg->v_ptr;
332 ir_mode *mode = get_irn_mode(irn);
334 if (mode == mode_T) {
335 mode = get_ia32_res_mode(irn);
337 mode = get_ia32_ls_mode(irn);
341 return lc_arg_append(app, occ, "(null)", 6);
343 if (mode_is_float(mode)) {
344 return lc_appendable_chadd(app, get_mode_size_bits(mode) == 32 ? 's' : 'd');
347 return lc_appendable_chadd(app, mode_is_signed(mode) ? 's' : 'z');
352 * Return the ia32 printf arg environment.
353 * We use the firm environment with some additional handlers.
355 const lc_arg_env_t *ia32_get_arg_env(void) {
356 static lc_arg_env_t *env = NULL;
358 static const lc_arg_handler_t ia32_reg_handler = { ia32_get_arg_type, ia32_get_reg_name };
359 static const lc_arg_handler_t ia32_const_handler = { ia32_get_arg_type, ia32_const_to_str };
360 static const lc_arg_handler_t ia32_mode_handler = { ia32_get_arg_type, ia32_get_mode_suffix };
361 static const lc_arg_handler_t ia32_x87_handler = { ia32_get_arg_type, ia32_get_x87_name };
364 /* extend the firm printer */
365 env = firm_get_arg_env();
367 lc_arg_register(env, "ia32:sreg", 'S', &ia32_reg_handler);
368 lc_arg_register(env, "ia32:dreg", 'D', &ia32_reg_handler);
369 lc_arg_register(env, "ia32:cnst", 'C', &ia32_const_handler);
370 lc_arg_register(env, "ia32:offs", 'O', &ia32_const_handler);
371 lc_arg_register(env, "ia32:mode", 'M', &ia32_mode_handler);
372 lc_arg_register(env, "ia32:x87", 'X', &ia32_x87_handler);
378 static const char *ia32_get_reg_name_for_mode(ia32_emit_env_t *env, ir_mode *mode, const arch_register_t *reg) {
379 switch(get_mode_size_bits(mode)) {
381 return ia32_get_mapped_reg_name(env->isa->regs_8bit, reg);
383 return ia32_get_mapped_reg_name(env->isa->regs_16bit, reg);
385 return (char *)arch_register_get_name(reg);
390 * Emits registers and/or address mode of a binary operation.
392 const char *ia32_emit_binop(const ir_node *n, ia32_emit_env_t *env) {
393 static char *buf = NULL;
395 /* verify that this function is never called on non-AM supporting operations */
396 //assert(get_ia32_am_support(n) != ia32_am_None && "emit binop expects addressmode support");
398 #define PRODUCES_RESULT(n) \
399 (!(is_ia32_St(n) || \
400 is_ia32_Store8Bit(n) || \
401 is_ia32_CondJmp(n) || \
402 is_ia32_xCondJmp(n) || \
403 is_ia32_CmpSet(n) || \
404 is_ia32_xCmpSet(n) || \
405 is_ia32_SwitchJmp(n)))
408 buf = xcalloc(1, SNPRINTF_BUF_LEN);
411 memset(buf, 0, SNPRINTF_BUF_LEN);
414 switch(get_ia32_op_type(n)) {
416 if (is_ia32_ImmConst(n)) {
417 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%3S, %s", n, get_ia32_cnst(n));
419 else if (is_ia32_ImmSymConst(n)) {
420 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%3S, OFFSET FLAT:%s", n, get_ia32_cnst(n));
423 const arch_register_t *in1 = get_in_reg(n, 2);
424 const arch_register_t *in2 = get_in_reg(n, 3);
425 const arch_register_t *out = PRODUCES_RESULT(n) ? get_out_reg(n, 0) : NULL;
426 const arch_register_t *in;
429 in = out ? (REGS_ARE_EQUAL(out, in2) ? in1 : in2) : in2;
430 out = out ? out : in1;
431 in_name = arch_register_get_name(in);
433 if (is_ia32_emit_cl(n)) {
434 assert(REGS_ARE_EQUAL(&ia32_gp_regs[REG_ECX], in) && "shift operation needs ecx");
438 snprintf(buf, SNPRINTF_BUF_LEN, "%%%s, %%%s", arch_register_get_name(out), in_name);
442 if (is_ia32_ImmConst(n) || is_ia32_ImmSymConst(n)) {
443 assert(! PRODUCES_RESULT(n) && "Source AM with Const must not produce result");
444 snprintf(buf, SNPRINTF_BUF_LEN, "%s, %s", get_ia32_cnst(n), ia32_emit_am(n, env));
447 if (PRODUCES_RESULT(n)) {
448 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%1D, %s", n, ia32_emit_am(n, env));
451 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%3S, %s", n, ia32_emit_am(n, env));
456 if (is_ia32_ImmConst(n) || is_ia32_ImmSymConst(n)) {
457 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%s,%s%s",
458 ia32_emit_am(n, env),
459 is_ia32_ImmSymConst(n) ? " OFFSET FLAT:" : " ", /* In case of a symconst we must add OFFSET to */
460 get_ia32_cnst(n)); /* tell the assembler to store it's address. */
463 const arch_register_t *in1 = get_in_reg(n, get_irn_arity(n) == 5 ? 3 : 2);
464 ir_mode *mode = get_ia32_res_mode(n);
467 mode = mode ? mode : get_ia32_ls_mode(n);
468 in_name = ia32_get_reg_name_for_mode(env, mode, in1);
470 if (is_ia32_emit_cl(n)) {
471 assert(REGS_ARE_EQUAL(&ia32_gp_regs[REG_ECX], in1) && "shift operation needs ecx");
475 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%s, %%%s", ia32_emit_am(n, env), in_name);
479 assert(0 && "unsupported op type");
482 #undef PRODUCES_RESULT
488 * Returns the xxx PTR string for a given mode
490 * @param mode the mode
491 * @param x87_insn if non-zero returns the string for a x87 instruction
492 * else for a SSE instruction
494 static const char *pointer_size(ir_mode *mode, int x87_insn)
497 switch (get_mode_size_bits(mode)) {
498 case 8: return "BYTE PTR";
499 case 16: return "WORD PTR";
500 case 32: return "DWORD PTR";
506 case 96: return "XWORD PTR";
507 default: return NULL;
514 * Translate the stx names into %st(x).
516 static char *get_x87_reg_name(const arch_register_t *reg, char *buf) {
517 const char *name = arch_register_get_name(reg);
536 * Emits registers and/or address mode of a binary operation.
538 const char *ia32_emit_x87_binop(const ir_node *n, ia32_emit_env_t *env) {
539 static char *buf = NULL;
541 /* verify that this function is never called on non-AM supporting operations */
542 //assert(get_ia32_am_support(n) != ia32_am_None && "emit binop expects addressmode support");
545 buf = xcalloc(1, SNPRINTF_BUF_LEN);
548 memset(buf, 0, SNPRINTF_BUF_LEN);
551 switch(get_ia32_op_type(n)) {
553 if (is_ia32_ImmConst(n) || is_ia32_ImmSymConst(n)) {
554 ir_mode *mode = get_ia32_ls_mode(n);
555 const char *p = pointer_size(mode, 1);
556 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%s %s", p, get_ia32_cnst(n));
559 ia32_attr_t *attr = get_ia32_attr(n);
560 const arch_register_t *in1 = attr->x87[0];
561 const arch_register_t *in2 = attr->x87[1];
562 const arch_register_t *out = attr->x87[2];
563 const arch_register_t *in;
564 char buf1[7], buf2[7];
566 in = out ? (REGS_ARE_EQUAL(out, in2) ? in1 : in2) : in2;
567 out = out ? out : in1;
569 snprintf(buf, SNPRINTF_BUF_LEN, "%s, %s", get_x87_reg_name(out, buf1), get_x87_reg_name(in, buf2));
574 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%s", ia32_emit_am(n, env));
577 assert(0 && "unsupported op type");
584 * Emits registers and/or address mode of a unary operation.
586 const char *ia32_emit_unop(const ir_node *n, ia32_emit_env_t *env) {
587 static char *buf = NULL;
590 buf = xcalloc(1, SNPRINTF_BUF_LEN);
593 memset(buf, 0, SNPRINTF_BUF_LEN);
596 switch(get_ia32_op_type(n)) {
598 if (is_ia32_ImmConst(n)) {
599 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%C", n);
601 else if (is_ia32_ImmSymConst(n)) {
602 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "OFFSET FLAT:%C", n);
605 if (is_ia32_MulS(n) || is_ia32_Mulh(n)) {
606 /* MulS and Mulh implicitly multiply by EAX */
607 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%4S", n);
608 } else if(is_ia32_Push(n)) {
609 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%3S", n);
611 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%1D", n);
616 assert(!is_ia32_Push(n));
617 snprintf(buf, SNPRINTF_BUF_LEN, "%s", ia32_emit_am(n, env));
621 Mulh is emitted via emit_unop
622 imul [MEM] means EDX:EAX <- EAX * [MEM]
624 assert((is_ia32_Mulh(n) || is_ia32_MulS(n) || is_ia32_Push(n)) && "Only MulS and Mulh can have AM source as unop");
625 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%s", ia32_emit_am(n, env));
628 assert(0 && "unsupported op type");
635 * Emits address mode.
637 const char *ia32_emit_am(const ir_node *n, ia32_emit_env_t *env) {
638 ia32_am_flavour_t am_flav = get_ia32_am_flavour(n);
642 static struct obstack *obst = NULL;
643 ir_mode *mode = get_ia32_ls_mode(n);
645 if (! is_ia32_Lea(n))
646 assert(mode && "AM node must have ls_mode attribute set.");
649 obst = xcalloc(1, sizeof(*obst));
652 obstack_free(obst, NULL);
655 /* obstack_free with NULL results in an uninitialized obstack */
658 p = pointer_size(mode, ia32_has_x87_register(n) || is_ia32_GetST0(n) || is_ia32_SetST0(n));
660 obstack_printf(obst, "%s ", p);
662 /* emit address mode symconst */
663 if (get_ia32_am_sc(n)) {
664 if (is_ia32_am_sc_sign(n))
665 obstack_printf(obst, "-");
666 obstack_printf(obst, "%s", get_id_str(get_ia32_am_sc(n)));
669 if (am_flav & ia32_B) {
670 obstack_printf(obst, "[");
671 lc_eoprintf(ia32_get_arg_env(), obst, "%1S", n);
675 if (am_flav & ia32_I) {
677 obstack_printf(obst, "+");
680 obstack_printf(obst, "[");
683 lc_eoprintf(ia32_get_arg_env(), obst, "%2S", n);
685 if (am_flav & ia32_S) {
686 obstack_printf(obst, "*%d", 1 << get_ia32_am_scale(n));
692 if (am_flav & ia32_O) {
693 int offs = get_ia32_am_offs_int(n);
696 /* omit explicit + if there was no base or index */
698 obstack_printf(obst, "[%d", offs);
700 obstack_printf(obst, "%+d", offs);
708 obstack_printf(obst, "] ");
710 obstack_1grow(obst, '\0');
711 s = obstack_finish(obst);
719 const char *ia32_emit_adr(const ir_node *irn, ia32_emit_env_t *env)
721 static char buf[SNPRINTF_BUF_LEN];
722 ir_mode *mode = get_ia32_ls_mode(irn);
723 const char *adr = get_ia32_cnst(irn);
724 const char *pref = pointer_size(mode, ia32_has_x87_register(irn));
726 snprintf(buf, SNPRINTF_BUF_LEN, "%s %s", pref ? pref : "", adr);
731 * Formated print of commands and comments.
733 static void ia32_fprintf_format(FILE *F, const ir_node *irn, char *cmd_buf, char *cmnt_buf) {
735 const char *name = irn ? be_retrieve_dbg_info(get_irn_dbg_info((ir_node *)irn), &lineno) : NULL;
738 fprintf(F, "\t%-35s %-60s /* %s:%u */\n", cmd_buf, cmnt_buf, name, lineno);
740 fprintf(F, "\t%-35s %-60s\n", cmd_buf, cmnt_buf);
746 * Add a number to a prefix. This number will not be used a second time.
748 static char *get_unique_label(char *buf, size_t buflen, const char *prefix) {
749 static unsigned long id = 0;
750 snprintf(buf, buflen, "%s%lu", prefix, ++id);
756 /*************************************************
759 * ___ _ __ ___ _| |_ ___ ___ _ __ __| |
760 * / _ \ '_ ` _ \| | __| / __/ _ \| '_ \ / _` |
761 * | __/ | | | | | | |_ | (_| (_) | | | | (_| |
762 * \___|_| |_| |_|_|\__| \___\___/|_| |_|\__,_|
764 *************************************************/
767 #define IA32_DO_EMIT(irn) ia32_fprintf_format(F, irn, cmd_buf, cmnt_buf)
770 * coding of conditions
772 struct cmp2conditon_t {
778 * positive conditions for signed compares
780 static const struct cmp2conditon_t cmp2condition_s[] = {
781 { NULL, pn_Cmp_False }, /* always false */
782 { "e", pn_Cmp_Eq }, /* == */
783 { "l", pn_Cmp_Lt }, /* < */
784 { "le", pn_Cmp_Le }, /* <= */
785 { "g", pn_Cmp_Gt }, /* > */
786 { "ge", pn_Cmp_Ge }, /* >= */
787 { "ne", pn_Cmp_Lg }, /* != */
788 { "ordered", pn_Cmp_Leg }, /* Floating point: ordered */
789 { "unordered", pn_Cmp_Uo }, /* FLoting point: unordered */
790 { "e", pn_Cmp_Ue }, /* Floating point: unordered or == */
791 { "b", pn_Cmp_Ul }, /* Floating point: unordered or < */
792 { "be", pn_Cmp_Ule }, /* Floating point: unordered or <= */
793 { "a", pn_Cmp_Ug }, /* Floating point: unordered or > */
794 { "ae", pn_Cmp_Uge }, /* Floating point: unordered or >= */
795 { "ne", pn_Cmp_Ne }, /* Floating point: unordered or != */
796 { NULL, pn_Cmp_True }, /* always true */
800 * positive conditions for unsigned compares
802 static const struct cmp2conditon_t cmp2condition_u[] = {
803 { NULL, pn_Cmp_False }, /* always false */
804 { "e", pn_Cmp_Eq }, /* == */
805 { "b", pn_Cmp_Lt }, /* < */
806 { "be", pn_Cmp_Le }, /* <= */
807 { "a", pn_Cmp_Gt }, /* > */
808 { "ae", pn_Cmp_Ge }, /* >= */
809 { "ne", pn_Cmp_Lg }, /* != */
810 { "ordered", pn_Cmp_Leg }, /* Floating point: ordered */
811 { "unordered", pn_Cmp_Uo }, /* FLoting point: unordered */
812 { "e", pn_Cmp_Ue }, /* Floating point: unordered or == */
813 { "b", pn_Cmp_Ul }, /* Floating point: unordered or < */
814 { "be", pn_Cmp_Ule }, /* Floating point: unordered or <= */
815 { "a", pn_Cmp_Ug }, /* Floating point: unordered or > */
816 { "ae", pn_Cmp_Uge }, /* Floating point: unordered or >= */
817 { "ne", pn_Cmp_Ne }, /* Floating point: unordered or != */
818 { NULL, pn_Cmp_True }, /* always true */
822 * returns the condition code
824 static const char *get_cmp_suffix(int cmp_code, int unsigned_cmp)
826 assert(cmp2condition_s[cmp_code].num == cmp_code);
827 assert(cmp2condition_u[cmp_code].num == cmp_code);
829 return unsigned_cmp ? cmp2condition_u[cmp_code & 7].name : cmp2condition_s[cmp_code & 7].name;
833 * Returns the target block for a control flow node.
835 static ir_node *get_cfop_target_block(const ir_node *irn) {
836 return get_irn_link(irn);
840 * Returns the target label for a control flow node.
842 static char *get_cfop_target(const ir_node *irn, char *buf) {
843 ir_node *bl = get_cfop_target_block(irn);
845 snprintf(buf, SNPRINTF_BUF_LEN, BLOCK_PREFIX("%ld"), get_irn_node_nr(bl));
849 /** Return the next block in Block schedule */
850 static ir_node *next_blk_sched(const ir_node *block) {
851 return get_irn_link(block);
855 * Returns the Proj with projection number proj and NOT mode_M
857 static ir_node *get_proj(const ir_node *irn, long proj) {
858 const ir_edge_t *edge;
861 assert(get_irn_mode(irn) == mode_T && "expected mode_T node");
863 foreach_out_edge(irn, edge) {
864 src = get_edge_src_irn(edge);
866 assert(is_Proj(src) && "Proj expected");
867 if (get_irn_mode(src) == mode_M)
870 if (get_Proj_proj(src) == proj)
877 * Emits the jump sequence for a conditional jump (cmp + jmp_true + jmp_false)
879 static void finish_CondJmp(FILE *F, const ir_node *irn, ir_mode *mode) {
880 const ir_node *proj_true;
881 const ir_node *proj_false;
882 const ir_node *block;
883 const ir_node *next_block;
884 char buf[SNPRINTF_BUF_LEN];
885 char cmd_buf[SNPRINTF_BUF_LEN];
886 char cmnt_buf[SNPRINTF_BUF_LEN];
891 /* get both Proj's */
892 proj_true = get_proj(irn, pn_Cond_true);
893 assert(proj_true && "CondJmp without true Proj");
895 proj_false = get_proj(irn, pn_Cond_false);
896 assert(proj_false && "CondJmp without false Proj");
898 pnc = get_ia32_pncode(irn);
900 /* for now, the code works for scheduled and non-schedules blocks */
901 block = get_nodes_block(irn);
903 /* we have a block schedule */
904 next_block = next_blk_sched(block);
906 if (get_cfop_target_block(proj_true) == next_block) {
907 /* exchange both proj's so the second one can be omitted */
908 const ir_node *t = proj_true;
910 proj_true = proj_false;
913 pnc = get_negated_pnc(pnc, mode);
916 /* the first Proj must always be created */
917 is_unsigned = mode_is_float(mode) || ! mode_is_signed(mode);
919 /* in case of unordered compare, check for parity */
920 if (pnc & pn_Cmp_Uo) {
921 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "jp %s", get_cfop_target(proj_true, buf));
922 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* jump to false if result is unordered */");
926 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "j%s %s",
927 get_cmp_suffix(pnc, is_unsigned),
928 get_cfop_target(proj_true, buf));
929 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* %s(a, b) %s*/",
930 get_pnc_string(pnc), flipped ? "(was flipped)" : "");
933 /* the second Proj might be a fallthrough */
934 if (get_cfop_target_block(proj_false) != next_block) {
935 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "jmp %s", get_cfop_target(proj_false, buf));
936 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* otherwise */");
940 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* fallthrough %s */", get_cfop_target(proj_false, buf));
946 * Emits code for conditional jump.
948 static void CondJmp_emitter(const ir_node *irn, ia32_emit_env_t *env) {
950 char cmd_buf[SNPRINTF_BUF_LEN];
951 char cmnt_buf[SNPRINTF_BUF_LEN];
953 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "cmp %s", ia32_emit_binop(irn, env));
954 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F */", irn);
956 finish_CondJmp(F, irn, get_ia32_res_mode(irn));
960 * Emits code for conditional jump with two variables.
962 static void emit_ia32_CondJmp(const ir_node *irn, ia32_emit_env_t *env) {
963 CondJmp_emitter(irn, env);
967 * Emits code for conditional test and jump.
969 static void TestJmp_emitter(const ir_node *irn, ia32_emit_env_t *env) {
971 #define IA32_IS_IMMOP (is_ia32_ImmConst(irn) || is_ia32_ImmSymConst(irn))
974 const char *op1 = arch_register_get_name(get_in_reg(irn, 0));
975 const char *op2 = IA32_IS_IMMOP ? get_ia32_cnst(irn) : NULL;
976 char cmd_buf[SNPRINTF_BUF_LEN];
977 char cmnt_buf[SNPRINTF_BUF_LEN];
980 op2 = arch_register_get_name(get_in_reg(irn, 1));
982 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "test %%%s,%s%s ", op1, IA32_IS_IMMOP ? " " : " %", op2);
983 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F */", irn);
986 finish_CondJmp(F, irn, get_ia32_res_mode(irn));
992 * Emits code for conditional test and jump with two variables.
994 static void emit_ia32_TestJmp(const ir_node *irn, ia32_emit_env_t *env) {
995 TestJmp_emitter(irn, env);
998 static void emit_ia32_CJmp(const ir_node *irn, ia32_emit_env_t *env) {
1000 char cmd_buf[SNPRINTF_BUF_LEN];
1001 char cmnt_buf[SNPRINTF_BUF_LEN];
1003 snprintf(cmd_buf, SNPRINTF_BUF_LEN, " ");
1004 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F omitted redundant test */", irn);
1006 finish_CondJmp(F, irn, get_ia32_res_mode(irn));
1009 static void emit_ia32_CJmpAM(const ir_node *irn, ia32_emit_env_t *env) {
1011 char cmd_buf[SNPRINTF_BUF_LEN];
1012 char cmnt_buf[SNPRINTF_BUF_LEN];
1014 snprintf(cmd_buf, SNPRINTF_BUF_LEN, " ");
1015 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F omitted redundant test/cmp */", irn);
1017 finish_CondJmp(F, irn, get_ia32_res_mode(irn));
1021 * Emits code for conditional SSE floating point jump with two variables.
1023 static void emit_ia32_xCondJmp(ir_node *irn, ia32_emit_env_t *env) {
1025 char cmd_buf[SNPRINTF_BUF_LEN];
1026 char cmnt_buf[SNPRINTF_BUF_LEN];
1027 const lc_arg_env_t *arg_env = ia32_get_arg_env();
1029 lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "ucomis%M %s", irn, ia32_emit_binop(irn, env));
1030 lc_esnprintf(arg_env, cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F */", irn);
1033 finish_CondJmp(F, irn, mode_F);
1037 * Emits code for conditional x87 floating point jump with two variables.
1039 static void emit_ia32_x87CondJmp(ir_node *irn, ia32_emit_env_t *env) {
1041 char cmd_buf[SNPRINTF_BUF_LEN];
1042 char cmnt_buf[SNPRINTF_BUF_LEN];
1043 ia32_attr_t *attr = get_ia32_attr(irn);
1044 const char *reg = attr->x87[1]->name;
1045 const char *instr = "fcom";
1048 switch (get_ia32_irn_opcode(irn)) {
1049 case iro_ia32_fcomrJmp:
1051 case iro_ia32_fcomJmp:
1055 case iro_ia32_fcomrpJmp:
1057 case iro_ia32_fcompJmp:
1060 case iro_ia32_fcomrppJmp:
1062 case iro_ia32_fcomppJmp:
1069 set_ia32_pncode(irn, (long)get_inversed_pnc(get_ia32_pncode(irn)));
1071 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "%s %s%s", instr, reg[0] == '\0' ? "" : "%", reg);
1072 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F */", irn);
1074 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "fnstsw %%ax", irn);
1075 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* Store x87 FPU Control Word */");
1077 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "sahf");
1078 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* Store ah into flags */");
1081 /* the compare flags must be evaluated using carry , ie unsigned */
1082 finish_CondJmp(F, irn, mode_Iu);
1085 static void CMov_emitter(ir_node *irn, ia32_emit_env_t *env) {
1087 const lc_arg_env_t *arg_env = ia32_get_arg_env();
1088 ir_mode *mode = get_irn_mode(get_irn_n(irn, 0));
1089 int is_unsigned = mode_is_float(mode) || ! mode_is_signed(mode);
1090 const char *cmp_suffix = get_cmp_suffix(get_ia32_pncode(irn), is_unsigned);
1091 int is_PsiCondCMov = is_ia32_PsiCondCMov(irn);
1092 int idx_left = 2 - is_PsiCondCMov;
1093 int idx_right = 3 - is_PsiCondCMov;
1095 char cmd_buf[SNPRINTF_BUF_LEN];
1096 char cmnt_buf[SNPRINTF_BUF_LEN];
1097 const arch_register_t *in1, *in2, *out;
1099 out = arch_get_irn_register(env->arch_env, irn);
1100 in1 = arch_get_irn_register(env->arch_env, get_irn_n(irn, idx_left));
1101 in2 = arch_get_irn_register(env->arch_env, get_irn_n(irn, idx_right));
1103 /* we have to emit the cmp first, because the destination register */
1104 /* could be one of the compare registers */
1105 if (is_ia32_CmpCMov(irn)) {
1106 lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "cmp %1S, %2S", irn, irn);
1108 else if (is_ia32_xCmpCMov(irn)) {
1109 lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "ucomis%M %1S, %2S", get_irn_n(irn, 0), irn, irn);
1111 else if (is_PsiCondCMov) {
1112 /* omit compare because flags are already set by And/Or */
1113 lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "test %1S, %1S", irn, irn);
1116 assert(0 && "unsupported CMov");
1118 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* Psi condition */" );
1121 if (REGS_ARE_EQUAL(out, in2)) {
1122 /* best case: default in == out -> do nothing */
1124 else if (REGS_ARE_EQUAL(out, in1)) {
1125 /* true in == out -> need complement compare and exchange true and default in */
1126 ir_node *t = get_irn_n(irn, idx_left);
1127 set_irn_n(irn, idx_left, get_irn_n(irn, idx_right));
1128 set_irn_n(irn, idx_right, t);
1130 cmp_suffix = get_cmp_suffix(get_negated_pnc(get_ia32_pncode(irn), get_irn_mode(irn)), is_unsigned);
1134 /* out is different from in: need copy default -> out */
1136 lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "mov %1D, %3S", irn, irn);
1138 lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "mov %1D, %4S", irn, irn);
1140 lc_esnprintf(arg_env, cmnt_buf, SNPRINTF_BUF_LEN, "/* copy default -> out */" );
1145 lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "cmov%s %1D, %2S", cmp_suffix, irn, irn);
1147 lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "cmov%s %1D, %3S", cmp_suffix, irn, irn);
1149 lc_esnprintf(arg_env, cmnt_buf, SNPRINTF_BUF_LEN, "/* condition is true case */" );
1153 static void emit_ia32_CmpCMov(ir_node *irn, ia32_emit_env_t *env) {
1154 CMov_emitter(irn, env);
1157 static void emit_ia32_PsiCondCMov(ir_node *irn, ia32_emit_env_t *env) {
1158 CMov_emitter(irn, env);
1161 static void emit_ia32_xCmpCMov(ir_node *irn, ia32_emit_env_t *env) {
1162 CMov_emitter(irn, env);
1165 static void Set_emitter(ir_node *irn, ir_mode *mode, ia32_emit_env_t *env) {
1167 const lc_arg_env_t *arg_env = ia32_get_arg_env();
1168 int is_unsigned = mode_is_float(mode) || ! mode_is_signed(mode);
1169 const char *cmp_suffix = get_cmp_suffix(get_ia32_pncode(irn), is_unsigned);
1170 const char *reg8bit;
1172 char cmd_buf[SNPRINTF_BUF_LEN];
1173 char cmnt_buf[SNPRINTF_BUF_LEN];
1174 const arch_register_t *out;
1176 out = arch_get_irn_register(env->arch_env, irn);
1177 reg8bit = ia32_get_mapped_reg_name(env->isa->regs_8bit, out);
1179 if (is_ia32_CmpSet(irn)) {
1180 lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "cmp %s", ia32_emit_binop(irn, env));
1182 else if (is_ia32_xCmpSet(irn)) {
1183 lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "ucomis%M %s", get_irn_n(irn, 2), ia32_emit_binop(irn, env));
1185 else if (is_ia32_PsiCondSet(irn)) {
1186 /* omit compare because flags are already set by And/Or */
1187 snprintf(cmd_buf, SNPRINTF_BUF_LEN, " ");
1190 assert(0 && "unsupported Set");
1192 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* calculate Psi condition */" );
1195 /* use mov to clear target because it doesn't affect the eflags */
1196 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "mov %%%s, 0", arch_register_get_name(out));
1197 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* clear target as set modifies only lower 8 bit */");
1200 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "set%s %%%s", cmp_suffix, reg8bit);
1201 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* set 1 iff true, 0 otherweise */" );
1205 static void emit_ia32_CmpSet(ir_node *irn, ia32_emit_env_t *env) {
1206 Set_emitter(irn, get_irn_mode(get_irn_n(irn, 2)), env);
1209 static void emit_ia32_PsiCondSet(ir_node *irn, ia32_emit_env_t *env) {
1210 Set_emitter(irn, get_irn_mode(get_irn_n(irn, 0)), env);
1213 static void emit_ia32_xCmpSet(ir_node *irn, ia32_emit_env_t *env) {
1214 Set_emitter(irn, get_irn_mode(get_irn_n(irn, 2)), env);
1217 static void emit_ia32_xCmp(ir_node *irn, ia32_emit_env_t *env) {
1219 const lc_arg_env_t *arg_env = ia32_get_arg_env();
1221 long pnc = get_ia32_pncode(irn);
1222 long unord = pnc & pn_Cmp_Uo;
1223 char cmd_buf[SNPRINTF_BUF_LEN];
1224 char cmnt_buf[SNPRINTF_BUF_LEN];
1227 case pn_Cmp_Leg: /* odered */
1230 case pn_Cmp_Uo: /* unordered */
1234 case pn_Cmp_Eq: /* == */
1238 case pn_Cmp_Lt: /* < */
1242 case pn_Cmp_Le: /* <= */
1246 case pn_Cmp_Gt: /* > */
1250 case pn_Cmp_Ge: /* >= */
1254 case pn_Cmp_Lg: /* != */
1259 assert(sse_pnc >= 0 && "unsupported compare");
1261 if (unord && sse_pnc != 3) {
1263 We need a separate compare against unordered.
1264 Quick and Dirty solution:
1265 - get some memory on stack
1269 - and result and stored result
1272 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "sub %%esp, 8");
1273 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* reserve some space for unordered compare result */");
1275 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "cmpsd %s, 3", ia32_emit_binop(irn, env));
1276 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* SSE compare: unordered */");
1278 lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "movsd [%%esp], %1D", irn);
1279 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* store compare result */");
1283 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "cmpsd %s, %d", ia32_emit_binop(irn, env), sse_pnc);
1284 lc_esnprintf(arg_env, cmnt_buf, SNPRINTF_BUF_LEN, "/* SSE compare (%+F) with result in %1D */", irn, irn);
1287 if (unord && sse_pnc != 3) {
1288 lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "andpd %1D, [%%esp]", irn);
1289 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* build the final result */");
1291 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "add %%esp, 8");
1292 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* free allocated space */");
1297 /*********************************************************
1300 * ___ _ __ ___ _| |_ _ _ _ _ __ ___ _ __ ___
1301 * / _ \ '_ ` _ \| | __| | | | | | '_ ` _ \| '_ \/ __|
1302 * | __/ | | | | | | |_ | | |_| | | | | | | |_) \__ \
1303 * \___|_| |_| |_|_|\__| | |\__,_|_| |_| |_| .__/|___/
1306 *********************************************************/
1308 /* jump table entry (target and corresponding number) */
1309 typedef struct _branch_t {
1314 /* jump table for switch generation */
1315 typedef struct _jmp_tbl_t {
1316 ir_node *defProj; /**< default target */
1317 int min_value; /**< smallest switch case */
1318 int max_value; /**< largest switch case */
1319 int num_branches; /**< number of jumps */
1320 char *label; /**< label of the jump table */
1321 branch_t *branches; /**< jump array */
1325 * Compare two variables of type branch_t. Used to sort all switch cases
1327 static int ia32_cmp_branch_t(const void *a, const void *b) {
1328 branch_t *b1 = (branch_t *)a;
1329 branch_t *b2 = (branch_t *)b;
1331 if (b1->value <= b2->value)
1338 * Emits code for a SwitchJmp (creates a jump table if
1339 * possible otherwise a cmp-jmp cascade). Port from
1342 static void emit_ia32_SwitchJmp(const ir_node *irn, ia32_emit_env_t *emit_env) {
1343 unsigned long interval;
1344 char buf[SNPRINTF_BUF_LEN];
1345 int last_value, i, pn;
1348 const ir_edge_t *edge;
1349 const lc_arg_env_t *env = ia32_get_arg_env();
1350 FILE *F = emit_env->out;
1351 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1353 /* fill the table structure */
1354 tbl.label = xmalloc(SNPRINTF_BUF_LEN);
1355 tbl.label = get_unique_label(tbl.label, SNPRINTF_BUF_LEN, ".TBL_");
1357 tbl.num_branches = get_irn_n_edges(irn);
1358 tbl.branches = xcalloc(tbl.num_branches, sizeof(tbl.branches[0]));
1359 tbl.min_value = INT_MAX;
1360 tbl.max_value = INT_MIN;
1363 /* go over all proj's and collect them */
1364 foreach_out_edge(irn, edge) {
1365 proj = get_edge_src_irn(edge);
1366 assert(is_Proj(proj) && "Only proj allowed at SwitchJmp");
1368 pn = get_Proj_proj(proj);
1370 /* create branch entry */
1371 tbl.branches[i].target = proj;
1372 tbl.branches[i].value = pn;
1374 tbl.min_value = pn < tbl.min_value ? pn : tbl.min_value;
1375 tbl.max_value = pn > tbl.max_value ? pn : tbl.max_value;
1377 /* check for default proj */
1378 if (pn == get_ia32_pncode(irn)) {
1379 assert(tbl.defProj == NULL && "found two defProjs at SwitchJmp");
1386 /* sort the branches by their number */
1387 qsort(tbl.branches, tbl.num_branches, sizeof(tbl.branches[0]), ia32_cmp_branch_t);
1389 /* two-complement's magic make this work without overflow */
1390 interval = tbl.max_value - tbl.min_value;
1392 /* emit the table */
1393 lc_esnprintf(env, cmd_buf, SNPRINTF_BUF_LEN, "cmp %1S, %u", irn, interval);
1394 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* compare for switch */");
1397 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "ja %s", get_cfop_target(tbl.defProj, buf));
1398 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* default jump if out of range */");
1401 if (tbl.num_branches > 1) {
1404 lc_esnprintf(env, cmd_buf, SNPRINTF_BUF_LEN, "jmp %s[%1S*4]", tbl.label, irn);
1405 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* get jump table entry as target */");
1408 ia32_switch_section(F, SECTION_RODATA);
1409 fprintf(F, "\t.align 4\n");
1411 fprintf(F, "%s:\n", tbl.label);
1413 snprintf(cmd_buf, SNPRINTF_BUF_LEN, ".long %s", get_cfop_target(tbl.branches[0].target, buf));
1414 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* case %d */", tbl.branches[0].value);
1417 last_value = tbl.branches[0].value;
1418 for (i = 1; i < tbl.num_branches; ++i) {
1419 while (++last_value < tbl.branches[i].value) {
1420 snprintf(cmd_buf, SNPRINTF_BUF_LEN, ".long %s", get_cfop_target(tbl.defProj, buf));
1421 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* default case */");
1424 snprintf(cmd_buf, SNPRINTF_BUF_LEN, ".long %s", get_cfop_target(tbl.branches[i].target, buf));
1425 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* case %d */", last_value);
1428 ia32_switch_section(F, SECTION_TEXT);
1431 /* one jump is enough */
1432 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "jmp %s", get_cfop_target(tbl.branches[0].target, buf));
1433 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* only one case given */");
1444 * Emits code for a unconditional jump.
1446 static void emit_Jmp(const ir_node *irn, ia32_emit_env_t *env) {
1447 ir_node *block, *next_bl;
1449 char buf[SNPRINTF_BUF_LEN], cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1451 /* for now, the code works for scheduled and non-schedules blocks */
1452 block = get_nodes_block(irn);
1454 /* we have a block schedule */
1455 next_bl = next_blk_sched(block);
1456 if (get_cfop_target_block(irn) != next_bl) {
1457 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "jmp %s", get_cfop_target(irn, buf));
1458 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F(%+F) */", irn, get_cfop_target_block(irn));
1462 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* fallthrough %s */", get_cfop_target(irn, buf));
1467 /****************************
1470 * _ __ _ __ ___ _ ___
1471 * | '_ \| '__/ _ \| |/ __|
1472 * | |_) | | | (_) | |\__ \
1473 * | .__/|_| \___/| ||___/
1476 ****************************/
1479 * Emits code for a proj -> node
1481 static void emit_Proj(const ir_node *irn, ia32_emit_env_t *env) {
1482 ir_node *pred = get_Proj_pred(irn);
1484 if (get_irn_op(pred) == op_Start) {
1485 switch(get_Proj_proj(irn)) {
1486 case pn_Start_X_initial_exec:
1495 /**********************************
1498 * | | ___ _ __ _ _| |_) |
1499 * | | / _ \| '_ \| | | | _ <
1500 * | |___| (_) | |_) | |_| | |_) |
1501 * \_____\___/| .__/ \__, |____/
1504 **********************************/
1507 * Emit movsb/w instructions to make mov count divideable by 4
1509 static void emit_CopyB_prolog(FILE *F, const ir_node *irn, int rem) {
1510 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1512 ir_fprintf(F, "\t/* memcopy prolog %+F */\n", irn);
1514 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "cld");
1515 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* copy direction forward */");
1520 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "movsb");
1521 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* memcopy remainder 1 */");
1525 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "movsw");
1526 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* memcopy remainder 2 */");
1530 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "movsb");
1531 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* memcopy remainder 3 */");
1533 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "movsw");
1534 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* memcopy remainder 3 */");
1542 * Emit rep movsd instruction for memcopy.
1544 static void emit_ia32_CopyB(const ir_node *irn, ia32_emit_env_t *emit_env) {
1545 FILE *F = emit_env->out;
1546 tarval *tv = get_ia32_Immop_tarval(irn);
1547 int rem = get_tarval_long(tv);
1548 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1550 emit_CopyB_prolog(F, irn, rem);
1552 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "rep movsd");
1553 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* memcopy */");
1558 * Emits unrolled memcopy.
1560 static void emit_ia32_CopyB_i(const ir_node *irn, ia32_emit_env_t *emit_env) {
1561 tarval *tv = get_ia32_Immop_tarval(irn);
1562 int size = get_tarval_long(tv);
1563 FILE *F = emit_env->out;
1564 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1566 emit_CopyB_prolog(F, irn, size & 0x3);
1570 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "movsd");
1571 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* memcopy unrolled */");
1578 /***************************
1582 * | | / _ \| '_ \ \ / /
1583 * | |___| (_) | | | \ V /
1584 * \_____\___/|_| |_|\_/
1586 ***************************/
1589 * Emit code for conversions (I, FP), (FP, I) and (FP, FP).
1591 static void emit_ia32_Conv_with_FP(const ir_node *irn, ia32_emit_env_t *emit_env) {
1592 FILE *F = emit_env->out;
1593 const lc_arg_env_t *env = ia32_get_arg_env();
1594 ir_mode *src_mode = get_ia32_src_mode(irn);
1595 ir_mode *tgt_mode = get_ia32_tgt_mode(irn);
1596 char *from, *to, buf[64];
1597 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1599 from = mode_is_float(src_mode) ? (get_mode_size_bits(src_mode) == 32 ? "ss" : "sd") : "si";
1600 to = mode_is_float(tgt_mode) ? (get_mode_size_bits(tgt_mode) == 32 ? "ss" : "sd") : "si";
1602 switch(get_ia32_op_type(irn)) {
1604 lc_esnprintf(env, buf, sizeof(buf), "%1D, %3S", irn, irn);
1606 case ia32_AddrModeS:
1607 lc_esnprintf(env, buf, sizeof(buf), "%1D, %s", irn, ia32_emit_am(irn, emit_env));
1610 assert(0 && "unsupported op type for Conv");
1613 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "cvt%s2%s %s", from, to, buf);
1614 lc_esnprintf(env, cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F(%+F, %+F) */", irn, src_mode, tgt_mode);
1618 static void emit_ia32_Conv_I2FP(const ir_node *irn, ia32_emit_env_t *emit_env) {
1619 emit_ia32_Conv_with_FP(irn, emit_env);
1622 static void emit_ia32_Conv_FP2I(const ir_node *irn, ia32_emit_env_t *emit_env) {
1623 emit_ia32_Conv_with_FP(irn, emit_env);
1626 static void emit_ia32_Conv_FP2FP(const ir_node *irn, ia32_emit_env_t *emit_env) {
1627 emit_ia32_Conv_with_FP(irn, emit_env);
1631 * Emits code for an Int conversion.
1633 static void emit_ia32_Conv_I2I(const ir_node *irn, ia32_emit_env_t *emit_env) {
1634 FILE *F = emit_env->out;
1635 const lc_arg_env_t *env = ia32_get_arg_env();
1636 char *move_cmd = "movzx";
1637 char *conv_cmd = NULL;
1638 ir_mode *src_mode = get_ia32_src_mode(irn);
1639 ir_mode *tgt_mode = get_ia32_tgt_mode(irn);
1642 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1643 const arch_register_t *in_reg, *out_reg;
1645 n = get_mode_size_bits(src_mode);
1646 m = get_mode_size_bits(tgt_mode);
1648 assert(n == 8 || n == 16 || n == 32);
1649 assert(m == 8 || m == 16 || m == 32);
1652 signed_mode = mode_is_signed(n < m ? src_mode : tgt_mode);
1657 switch(get_ia32_op_type(irn)) {
1659 in_reg = get_in_reg(irn, 2);
1660 out_reg = get_out_reg(irn, 0);
1662 if (REGS_ARE_EQUAL(in_reg, &ia32_gp_regs[REG_EAX]) &&
1663 REGS_ARE_EQUAL(out_reg, in_reg) &&
1666 if (n == 8 || m == 8)
1668 else if (n == 16 || m == 16)
1671 /* argument and result are both in EAX and */
1672 /* signedness is ok: -> use converts */
1673 lc_esnprintf(env, cmd_buf, SNPRINTF_BUF_LEN, "%s", conv_cmd);
1675 else if (REGS_ARE_EQUAL(out_reg, in_reg) && ! signed_mode)
1677 /* argument and result are in the same register */
1678 /* and signedness is ok: -> use and with mask */
1679 int mask = (1 << (n < m ? n : m)) - 1;
1680 lc_esnprintf(env, cmd_buf, SNPRINTF_BUF_LEN, "and %1D, 0x%x", irn, mask);
1683 /* use move w/o sign extension */
1684 lc_esnprintf(env, cmd_buf, SNPRINTF_BUF_LEN, "%s %1D, %%%s",
1685 move_cmd, irn, ia32_get_reg_name_for_mode(emit_env, n < m ? src_mode : tgt_mode, in_reg));
1689 case ia32_AddrModeS:
1690 lc_esnprintf(env, cmd_buf, SNPRINTF_BUF_LEN, "%s %1D, %s",
1691 move_cmd, irn, ia32_emit_am(irn, emit_env));
1694 assert(0 && "unsupported op type for Conv");
1697 lc_esnprintf(env, cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F(%d Bit mode_%F -> %d Bit mode_%F) */",
1698 irn, n, src_mode, m, tgt_mode);
1704 * Emits code for an 8Bit Int conversion.
1706 void emit_ia32_Conv_I2I8Bit(const ir_node *irn, ia32_emit_env_t *emit_env) {
1707 emit_ia32_Conv_I2I(irn, emit_env);
1711 /*******************************************
1714 * | |__ ___ _ __ ___ __| | ___ ___
1715 * | '_ \ / _ \ '_ \ / _ \ / _` |/ _ \/ __|
1716 * | |_) | __/ | | | (_) | (_| | __/\__ \
1717 * |_.__/ \___|_| |_|\___/ \__,_|\___||___/
1719 *******************************************/
1722 * Emits a backend call
1724 static void emit_be_Call(const ir_node *irn, ia32_emit_env_t *emit_env) {
1725 FILE *F = emit_env->out;
1726 entity *ent = be_Call_get_entity(irn);
1727 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1730 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "call %s", get_entity_ld_name(ent));
1733 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "call %1D", get_irn_n(irn, be_pos_Call_ptr));
1736 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F (be_Call) */", irn);
1742 * Emits code to increase stack pointer.
1744 static void emit_be_IncSP(const ir_node *irn, ia32_emit_env_t *emit_env) {
1745 FILE *F = emit_env->out;
1746 int offs = be_get_IncSP_offset(irn);
1747 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1751 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "sub %1S, %u", irn, offs);
1753 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "add %1S, %u", irn, -offs);
1754 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F (IncSP) */", irn);
1757 snprintf(cmd_buf, SNPRINTF_BUF_LEN, " ");
1758 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* omitted %+F (IncSP) with 0 */", irn);
1765 * Emits code to set stack pointer.
1767 static void emit_be_SetSP(const ir_node *irn, ia32_emit_env_t *emit_env) {
1768 FILE *F = emit_env->out;
1769 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1771 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "mov %1D, %3S", irn, irn);
1772 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F (restore SP) */", irn);
1777 * Emits code for Copy/CopyKeep.
1779 static void Copy_emitter(const ir_node *irn, ir_node *op, ia32_emit_env_t *emit_env) {
1780 FILE *F = emit_env->out;
1781 const arch_env_t *aenv = emit_env->arch_env;
1782 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1784 if (REGS_ARE_EQUAL(arch_get_irn_register(aenv, irn), arch_get_irn_register(aenv, op)) ||
1785 arch_register_type_is(arch_get_irn_register(aenv, op), virtual))
1788 if (mode_is_float(get_irn_mode(irn)))
1789 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "movs%M %1D, %1S", irn, irn, irn);
1791 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "mov %1D, %1S", irn, irn);
1792 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F */", irn);
1796 static void emit_be_Copy(const ir_node *irn, ia32_emit_env_t *emit_env) {
1797 Copy_emitter(irn, be_get_Copy_op(irn), emit_env);
1800 static void emit_be_CopyKeep(const ir_node *irn, ia32_emit_env_t *emit_env) {
1801 Copy_emitter(irn, be_get_CopyKeep_op(irn), emit_env);
1805 * Emits code for exchange.
1807 static void emit_be_Perm(const ir_node *irn, ia32_emit_env_t *emit_env) {
1808 FILE *F = emit_env->out;
1809 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1810 const arch_register_t *in1, *in2;
1811 const arch_register_class_t *cls1, *cls2;
1813 in1 = arch_get_irn_register(emit_env->arch_env, get_irn_n(irn, 0));
1814 in2 = arch_get_irn_register(emit_env->arch_env, get_irn_n(irn, 1));
1816 cls1 = arch_register_get_class(in1);
1817 cls2 = arch_register_get_class(in2);
1819 assert(cls1 == cls2 && "Register class mismatch at Perm");
1821 if (cls1 == &ia32_reg_classes[CLASS_ia32_gp]) {
1822 if(emit_env->isa->opt_arch == arch_athlon) {
1823 // xchg commands are Vector path on athlons and therefore stall the DirectPath pipeline
1824 // it is nearly always beneficial to use the 3 xor trick instead of an xchg
1826 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "xor %1S, %2S", irn, irn);
1828 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "xor %2S, %1S", irn, irn);
1830 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "xor %1S, %2S", irn, irn);
1832 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "xchg %1S, %2S", irn, irn);
1835 else if (cls1 == &ia32_reg_classes[CLASS_ia32_xmm]) {
1836 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN,
1837 "pxor %1S, %2S\n\tpxor %2S, %1S\n\tpxor %1S, %2S", irn, irn, irn, irn, irn, irn);
1839 else if (cls1 == &ia32_reg_classes[CLASS_ia32_vfp]) {
1843 else if (cls1 == &ia32_reg_classes[CLASS_ia32_st]) {
1848 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F(%1A, %2A) */", irn, irn, irn);
1853 * Emits code for Constant loading.
1855 static void emit_ia32_Const(const ir_node *n, ia32_emit_env_t *env) {
1857 char cmd_buf[256], cmnt_buf[256];
1858 const lc_arg_env_t *arg_env = ia32_get_arg_env();
1859 ir_mode *mode = get_irn_mode(n);
1860 tarval *tv = get_ia32_Immop_tarval(n);
1862 if (get_ia32_op_type(n) == ia32_SymConst) {
1863 lc_esnprintf(arg_env, cmd_buf, 256, "mov %1D, OFFSET FLAT:%C ", n, n);
1864 lc_esnprintf(arg_env, cmnt_buf, 256, "/* Move address of SymConst into register */");
1866 assert(mode == get_tarval_mode(tv) || (mode_is_reference(get_tarval_mode(tv)) && mode == mode_Iu));
1867 /* beware: in some rare cases mode is mode_b which has no tarval_null() */
1868 if (tv == get_tarval_b_false() || tv == get_tarval_null(mode)) {
1869 const char *instr = "xor";
1870 if (env->isa->opt_arch == arch_pentium_4) {
1871 /* P4 prefers sub r, r, others xor r, r */
1874 lc_esnprintf(arg_env, cmd_buf, 256, "%s %1D, %1D ", instr, n, n);
1875 lc_esnprintf(arg_env, cmnt_buf, 256, "/* optimized mov 0 to register */");
1877 lc_esnprintf(arg_env, cmd_buf, 256, "mov %1D, %C ", n, n);
1878 lc_esnprintf(arg_env, cmnt_buf, 256, "/* Mov Const into register */");
1881 lc_efprintf(arg_env, F, "\t%-35s %-60s /* %+F (%+G) */\n", cmd_buf, cmnt_buf, n, n);
1885 * Emits code to increase stack pointer.
1887 static void emit_ia32_AddSP(const ir_node *irn, ia32_emit_env_t *emit_env) {
1888 FILE *F = emit_env->out;
1889 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1891 if (is_ia32_ImmConst(irn)) {
1892 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "sub %1D, %C", irn, irn);
1894 else if (is_ia32_ImmSymConst(irn)) {
1895 if (get_ia32_op_type(irn) == ia32_Normal)
1896 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "sub %1D, OFFSET_FLAT:%C", irn, irn);
1897 else /* source address mode */
1898 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "sub %1D, [%s%s]", irn, get_id_str(get_ia32_am_sc(irn)), get_ia32_am_offs(irn));
1901 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "sub %1D, %2S", irn, irn);
1903 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* reserve space on stack */");
1909 * Emits code to increase stack pointer.
1911 static void emit_ia32_SubSP(const ir_node *irn, ia32_emit_env_t *emit_env) {
1912 FILE *F = emit_env->out;
1913 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1915 if (is_ia32_ImmConst(irn)) {
1916 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "add %1D, %C", irn, irn);
1918 else if (is_ia32_ImmSymConst(irn)) {
1919 if (get_ia32_op_type(irn) == ia32_Normal)
1920 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "add %1D, OFFSET_FLAT:%C", irn, irn);
1921 else /* source address mode */
1922 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "add %1D, [%s%s]", irn, get_id_str(get_ia32_am_sc(irn)), get_ia32_am_offs(irn));
1925 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "add %1D, %2S", irn, irn);
1927 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* free space on stack */");
1933 * Emits code to load the TLS base
1935 static void emit_ia32_LdTls(const ir_node *irn, ia32_emit_env_t *emit_env) {
1936 FILE *F = emit_env->out;
1937 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1939 switch (asm_flavour) {
1941 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "mov %1D, DWORD PTR %%gs:0", irn);
1944 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "mov %1D, DWORD PTR %%gs:0", irn);
1947 assert(0 && "unsupported TLS");
1950 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* get thread local storage base */");
1955 static void emit_be_Return(const ir_node *n, ia32_emit_env_t *env) {
1957 const lc_arg_env_t *arg_env = ia32_get_arg_env();
1959 lc_efprintf(arg_env, F, "\t%-35s %-60s /* %+F (%+G) */\n", "ret", "/* be_Return */", n, n);
1962 static void emit_Nothing(const ir_node *n, ia32_emit_env_t *env) {
1965 ir_fprintf(F, "\t%35s /* %+F (%+G) */\n", " ", n, n);
1969 /***********************************************************************************
1972 * _ __ ___ __ _ _ _ __ | |_ _ __ __ _ _ __ ___ _____ _____ _ __| | __
1973 * | '_ ` _ \ / _` | | '_ \ | _| '__/ _` | '_ ` _ \ / _ \ \ /\ / / _ \| '__| |/ /
1974 * | | | | | | (_| | | | | | | | | | | (_| | | | | | | __/\ V V / (_) | | | <
1975 * |_| |_| |_|\__,_|_|_| |_| |_| |_| \__,_|_| |_| |_|\___| \_/\_/ \___/|_| |_|\_\
1977 ***********************************************************************************/
1980 * Enters the emitter functions for handled nodes into the generic
1981 * pointer of an opcode.
1983 static void ia32_register_emitters(void) {
1985 #define IA32_EMIT2(a,b) op_ia32_##a->ops.generic = (op_func)emit_ia32_##b
1986 #define IA32_EMIT(a) IA32_EMIT2(a,a)
1987 #define EMIT(a) op_##a->ops.generic = (op_func)emit_##a
1988 #define IGN(a) op_##a->ops.generic = (op_func)emit_Nothing
1989 #define BE_EMIT(a) op_be_##a->ops.generic = (op_func)emit_be_##a
1990 #define BE_IGN(a) op_be_##a->ops.generic = (op_func)emit_Nothing
1992 /* first clear the generic function pointer for all ops */
1993 clear_irp_opcodes_generic_func();
1995 /* register all emitter functions defined in spec */
1996 ia32_register_spec_emitters();
1998 /* other ia32 emitter functions */
2004 IA32_EMIT(PsiCondCMov);
2006 IA32_EMIT(PsiCondSet);
2007 IA32_EMIT(SwitchJmp);
2010 IA32_EMIT(Conv_I2FP);
2011 IA32_EMIT(Conv_FP2I);
2012 IA32_EMIT(Conv_FP2FP);
2013 IA32_EMIT(Conv_I2I);
2014 IA32_EMIT(Conv_I2I8Bit);
2021 IA32_EMIT(xCmpCMov);
2022 IA32_EMIT(xCondJmp);
2023 IA32_EMIT2(fcomJmp, x87CondJmp);
2024 IA32_EMIT2(fcompJmp, x87CondJmp);
2025 IA32_EMIT2(fcomppJmp, x87CondJmp);
2026 IA32_EMIT2(fcomrJmp, x87CondJmp);
2027 IA32_EMIT2(fcomrpJmp, x87CondJmp);
2028 IA32_EMIT2(fcomrppJmp, x87CondJmp);
2030 /* benode emitter */
2056 static const char *last_name = NULL;
2057 static unsigned last_line = -1;
2058 static unsigned num = -1;
2061 * Emit the debug support for node irn.
2063 static void ia32_emit_dbg(const ir_node *irn, ia32_emit_env_t *env) {
2064 dbg_info *db = get_irn_dbg_info(irn);
2066 const char *fname = be_retrieve_dbg_info(db, &lineno);
2068 if (! env->cg->birg->main_env->options->stabs_debug_support)
2072 if (last_name != fname) {
2074 be_dbg_include_begin(env->cg->birg->main_env->db_handle, fname);
2077 if (last_line != lineno) {
2081 snprintf(name, sizeof(name), ".LM%u", ++num);
2083 be_dbg_line(env->cg->birg->main_env->db_handle, lineno, name);
2084 fprintf(F, "%s:\n", name);
2090 * Emits code for a node.
2092 static void ia32_emit_node(const ir_node *irn, void *env) {
2093 ia32_emit_env_t *emit_env = env;
2094 ir_op *op = get_irn_op(irn);
2095 DEBUG_ONLY(firm_dbg_module_t *mod = emit_env->mod;)
2097 DBG((mod, LEVEL_1, "emitting code for %+F\n", irn));
2099 if (op->ops.generic) {
2100 void (*emit)(const ir_node *, void *) = (void (*)(const ir_node *, void *))op->ops.generic;
2101 ia32_emit_dbg(irn, emit_env);
2105 emit_Nothing(irn, env);
2106 ir_fprintf(stderr, "Warning: No emit handler for node %+F (%+G)\n", irn, irn);
2111 * Emits gas alignment directives
2113 static void ia32_emit_alignment(FILE *F, unsigned align, unsigned skip) {
2114 fprintf(F, "\t.p2align %u,,%u\n", align, skip);
2118 * Emits gas alignment directives for Functions depended on cpu architecture.
2120 static void ia32_emit_align_func(FILE *F, cpu_support cpu) {
2122 unsigned maximum_skip;
2137 maximum_skip = (1 << align) - 1;
2138 ia32_emit_alignment(F, align, maximum_skip);
2142 * Emits gas alignment directives for Labels depended on cpu architecture.
2144 static void ia32_emit_align_label(FILE *F, cpu_support cpu) {
2145 unsigned align; unsigned maximum_skip;
2160 maximum_skip = (1 << align) - 1;
2161 ia32_emit_alignment(F, align, maximum_skip);
2164 static int is_first_loop_block(ir_node *block, ir_node *prev_block, ia32_emit_env_t *env) {
2165 ir_exec_freq *execfreqs = env->cg->birg->execfreqs;
2166 double block_freq, prev_freq;
2167 static const double DELTA = .0001;
2168 cpu_support cpu = env->isa->opt_arch;
2170 if(execfreqs == NULL)
2172 if(cpu == arch_i386 || cpu == arch_i486)
2175 block_freq = get_block_execfreq(execfreqs, block);
2176 prev_freq = get_block_execfreq(execfreqs, prev_block);
2178 if(block_freq < DELTA || prev_freq < DELTA)
2181 block_freq /= prev_freq;
2185 case arch_athlon_64:
2187 return block_freq > 3;
2192 return block_freq > 2;
2196 * Walks over the nodes in a block connected by scheduling edges
2197 * and emits code for each node.
2199 static void ia32_gen_block(ir_node *block, ir_node *last_block, ia32_emit_env_t *env) {
2200 ir_graph *irg = get_irn_irg(block);
2201 ir_node *start_block = get_irg_start_block(irg);
2207 assert(is_Block(block));
2209 if (block == start_block)
2212 if (need_label && get_irn_arity(block) == 1) {
2213 ir_node *pred_block = get_Block_cfgpred_block(block, 0);
2215 if (pred_block == last_block && get_irn_n_edges_kind(pred_block, EDGE_KIND_BLOCK) <= 2)
2219 /* special case: if one of our cfg preds is a switch-jmp we need a label, */
2220 /* otherwise there might be jump table entries jumping to */
2221 /* non-existent (omitted) labels */
2222 for (i = get_Block_n_cfgpreds(block) - 1; i >= 0; --i) {
2223 ir_node *pred = get_Block_cfgpred(block, i);
2225 if (is_Proj(pred)) {
2226 assert(get_irn_mode(pred) == mode_X);
2227 if (is_ia32_SwitchJmp(get_Proj_pred(pred))) {
2234 /* special case because the start block contains no jump instruction */
2235 if (last_block == start_block) {
2236 const ir_edge_t *edge;
2237 ir_node *startsucc = NULL;
2239 foreach_block_succ(start_block, edge) {
2240 startsucc = get_edge_src_irn(edge);
2241 if (startsucc != start_block)
2244 assert(startsucc != NULL);
2246 /* if the last block was the start block and we are not inside the */
2247 /* start successor, emit a jump to the start successor */
2248 if (startsucc != block) {
2249 char buf[SNPRINTF_BUF_LEN];
2250 ir_snprintf(buf, sizeof(buf), BLOCK_PREFIX("%d"),
2251 get_irn_node_nr(startsucc));
2252 ir_fprintf(F, "\tjmp %s\n", buf);
2257 char cmd_buf[SNPRINTF_BUF_LEN];
2260 ir_exec_freq *execfreqs = env->cg->birg->execfreqs;
2262 /* align the loop headers */
2263 if (! is_first_loop_block(block, last_block, env)) {
2264 /* align blocks where the previous block has no fallthrough */
2265 arity = get_irn_arity(block);
2267 for (i = 0; i < arity; ++i) {
2268 ir_node *predblock = get_Block_cfgpred_block(block, i);
2270 if (predblock == last_block) {
2278 ia32_emit_align_label(env->out, env->isa->opt_arch);
2280 ir_snprintf(cmd_buf, sizeof(cmd_buf), BLOCK_PREFIX("%d:"),
2281 get_irn_node_nr(block));
2282 fprintf(F, "%-43s ", cmd_buf);
2284 /* emit list of pred blocks in comment */
2285 fprintf(F, "/* preds:");
2287 arity = get_irn_arity(block);
2288 for (i = 0; i < arity; ++i) {
2289 ir_node *predblock = get_Block_cfgpred_block(block, i);
2290 fprintf(F, " %ld", get_irn_node_nr(predblock));
2293 if (execfreqs != NULL) {
2294 fprintf(F, " freq: %f", get_block_execfreq(execfreqs, block));
2297 fprintf(F, " */\n");
2300 /* emit the contents of the block */
2301 ia32_emit_dbg(block, env);
2302 sched_foreach(block, irn) {
2303 ia32_emit_node(irn, env);
2308 * Emits code for function start.
2310 static void ia32_emit_func_prolog(FILE *F, ir_graph *irg, ia32_emit_env_t *emit_env) {
2311 entity *irg_ent = get_irg_entity(irg);
2312 const char *irg_name = get_entity_ld_name(irg_ent);
2313 cpu_support cpu = emit_env->isa->opt_arch;
2314 const be_irg_t *birg = emit_env->cg->birg;
2317 ia32_switch_section(F, SECTION_TEXT);
2318 be_dbg_method_begin(birg->main_env->db_handle, irg_ent, be_abi_get_stack_layout(birg->abi));
2319 ia32_emit_align_func(F, cpu);
2320 if (get_entity_visibility(irg_ent) == visibility_external_visible) {
2321 fprintf(F, ".globl %s\n", irg_name);
2323 ia32_dump_function_object(F, irg_name);
2324 fprintf(F, "%s:\n", irg_name);
2328 * Emits code for function end
2330 static void ia32_emit_func_epilog(FILE *F, ir_graph *irg, ia32_emit_env_t *emit_env) {
2331 const char *irg_name = get_entity_ld_name(get_irg_entity(irg));
2332 const be_irg_t *birg = emit_env->cg->birg;
2334 ia32_dump_function_size(F, irg_name);
2335 be_dbg_method_end(birg->main_env->db_handle);
2341 * Sets labels for control flow nodes (jump target)
2342 * TODO: Jump optimization
2344 static void ia32_gen_labels(ir_node *block, void *env) {
2346 int n = get_Block_n_cfgpreds(block);
2348 for (n--; n >= 0; n--) {
2349 pred = get_Block_cfgpred(block, n);
2350 set_irn_link(pred, block);
2355 * Main driver. Emits the code for one routine.
2357 void ia32_gen_routine(FILE *F, ir_graph *irg, const ia32_code_gen_t *cg) {
2358 ia32_emit_env_t emit_env;
2360 ir_node *last_block = NULL;
2363 emit_env.arch_env = cg->arch_env;
2365 emit_env.isa = (ia32_isa_t *)cg->arch_env->isa;
2366 FIRM_DBG_REGISTER(emit_env.mod, "firm.be.ia32.emitter");
2368 /* set the global arch_env (needed by print hooks) */
2369 arch_env = cg->arch_env;
2371 ia32_register_emitters();
2373 ia32_emit_func_prolog(F, irg, &emit_env);
2374 irg_block_walk_graph(irg, ia32_gen_labels, NULL, &emit_env);
2376 if ((cg->opt & IA32_OPT_EXTBB) && cg->blk_sched) {
2377 int i, n = ARR_LEN(cg->blk_sched);
2379 for (i = 0; i < n;) {
2382 block = cg->blk_sched[i];
2384 next_bl = i < n ? cg->blk_sched[i] : NULL;
2386 /* set here the link. the emitter expects to find the next block here */
2387 set_irn_link(block, next_bl);
2388 ia32_gen_block(block, last_block, &emit_env);
2393 /* "normal" block schedule: Note the get_next_block() returns the NUMBER of the block
2394 in the block schedule. As this number should NEVER be equal the next block,
2395 we does not need a clear block link here. */
2397 //irg_walk_blkwise_graph(irg, NULL, ia32_gen_block, &emit_env);
2401 ia32_emit_func_epilog(F, irg, &emit_env);