10 #include "../besched.h"
12 #include "ia32_emitter.h"
13 #include "gen_ia32_emitter.h"
14 #include "ia32_nodes_attr.h"
15 #include "ia32_new_nodes.h"
16 #include "ia32_map_regs.h"
18 #define SNPRINTF_BUF_LEN 128
20 static set *cur_reg_set = NULL;
23 /*************************************************************
25 * (_) | | / _| | | | |
26 * _ __ _ __ _ _ __ | |_| |_ | |__ ___| |_ __ ___ _ __
27 * | '_ \| '__| | '_ \| __| _| | '_ \ / _ \ | '_ \ / _ \ '__|
28 * | |_) | | | | | | | |_| | | | | | __/ | |_) | __/ |
29 * | .__/|_| |_|_| |_|\__|_| |_| |_|\___|_| .__/ \___|_|
32 *************************************************************/
35 * Return node's tarval as string.
37 const char *node_const_to_str(ir_node *n) {
39 tarval *tv = get_ia32_Immop_tarval(n);
42 buf = malloc(SNPRINTF_BUF_LEN);
43 tarval_snprintf(buf, SNPRINTF_BUF_LEN, tv);
46 else if (get_ia32_old_ir(n)) {
47 return get_sc_name(get_ia32_old_ir(n));
54 * Returns node's offset as string.
56 char *node_offset_to_str(ir_node *n) {
58 tarval *tv = get_ia32_offs(n);
61 buf = malloc(SNPRINTF_BUF_LEN);
62 tarval_snprintf(buf, SNPRINTF_BUF_LEN, tv);
69 /* We always pass the ir_node which is a pointer. */
70 static int ia32_get_arg_type(const lc_arg_occ_t *occ) {
71 return lc_arg_type_ptr;
76 * Returns the register at in position pos. If the IN node is not an
77 * ia32 node, we check for phi and proj.
79 static const arch_register_t *get_in_reg(ir_node *irn, int pos) {
81 const arch_register_t *reg = NULL;
82 const arch_register_t **slots;
84 assert(get_irn_arity(irn) > pos && "Invalid IN position");
86 /* The out register of the operator at position pos is the
87 in register we need. */
88 op = get_irn_n(irn, pos);
91 pos = (int)translate_proj_pos(op);
93 op = get_Proj_pred(op);
96 if (is_ia32_irn(op)) {
97 /* The operator is an ia32 node: this node has only one out */
98 slots = get_ia32_slots(op);
102 /* The operator is not an ia32 node: check for Phi or Proj */
104 /* Phi's getting register assigned */
105 reg = ia32_get_firm_reg(NULL, op, cur_reg_set);
106 assert(reg && "No register assigned to Phi node");
109 assert(0 && "Unsupported node for IN register");
117 * Returns the number of the in register at position pos.
119 int get_ia32_in_regnr(ir_node *irn, int pos) {
120 const arch_register_t *reg;
122 reg = get_in_reg(irn, pos);
123 assert(reg && "no in register");
128 * Returns the name of the in register at position pos.
130 const char *get_ia32_in_reg_name(ir_node *irn, int pos) {
131 const arch_register_t *reg;
133 reg = get_in_reg(irn, pos);
134 assert(reg && "no in register");
139 * Get the register name for a node.
141 static int ia32_get_reg_name(lc_appendable_t *app,
142 const lc_arg_occ_t *occ, const lc_arg_value_t *arg)
145 ir_node *X = arg->v_ptr;
146 int nr = occ->width - 1;
149 return lc_arg_append(app, occ, "(null)", 6);
151 if (occ->conversion == 's') {
152 buf = get_ia32_in_reg_name(X, nr);
155 buf = get_ia32_out_reg_name(X, nr);
158 return lc_arg_append(app, occ, buf, strlen(buf));
162 * Returns the tarval or offset of an ia32 as a string.
164 static int ia32_const_to_str(lc_appendable_t *app,
165 const lc_arg_occ_t *occ, const lc_arg_value_t *arg)
168 ir_node *X = arg->v_ptr;
171 return lc_arg_append(app, occ, "(null)", 6);
173 if (occ->conversion == 'c') {
174 buf = node_const_to_str(X);
177 buf = node_offset_to_str(X);
180 return lc_arg_append(app, occ, buf, strlen(buf));
184 * Determines the SSE suffix depending on the mode.
186 static int ia32_get_mode_suffix(lc_appendable_t *app,
187 const lc_arg_occ_t *occ, const lc_arg_value_t *arg)
189 ir_node *X = arg->v_ptr;
192 return lc_arg_append(app, occ, "(null)", 6);
194 if (get_mode_size_bits(get_irn_mode(X)) == 32)
195 return lc_appendable_chadd(app, 's');
197 return lc_appendable_chadd(app, 'd');
201 * Return the ia32 printf arg environment.
202 * We use the firm environment with some additional handlers.
204 const lc_arg_env_t *ia32_get_arg_env(void) {
205 static lc_arg_env_t *env = NULL;
207 static const lc_arg_handler_t ia32_reg_handler = { ia32_get_arg_type, ia32_get_reg_name };
208 static const lc_arg_handler_t ia32_const_handler = { ia32_get_arg_type, ia32_const_to_str };
209 static const lc_arg_handler_t ia32_mode_handler = { ia32_get_arg_type, ia32_get_mode_suffix };
212 env = firm_get_arg_env();
214 lc_arg_register(env, "ia32:sreg", 's', &ia32_reg_handler);
215 lc_arg_register(env, "ia32:dreg", 'd', &ia32_reg_handler);
216 lc_arg_register(env, "ia32:cnst", 'c', &ia32_const_handler);
217 lc_arg_register(env, "ia32:offs", 'o', &ia32_const_handler);
218 lc_arg_register(env, "ia32:mode", 'm', &ia32_mode_handler);
225 * For 2-address code we need to make sure the first src reg is equal to dest reg.
227 void equalize_dest_src(FILE *F, ir_node *n) {
228 if (get_ia32_in_regnr(n, 0) != get_ia32_out_regnr(n, 0)) {
229 if (get_irn_arity(n) > 1 && get_ia32_in_regnr(n, 1) == get_ia32_out_regnr(n, 0)) {
230 if (! is_op_commutative(get_irn_op(n))) {
231 /* we only need to echange for non-commutative ops */
232 lc_efprintf(ia32_get_arg_env(), F, "\txchg %1s, %2s\t\t\t/* xchg src1 <-> src2 for 2 address code */\n", n, n);
236 lc_efprintf(ia32_get_arg_env(), F, "\tmovl %1s, %1d\t\t\t/* src -> dest for 2 address code */\n", n, n);
242 * Add a number to a prefix. This number will not be used a second time.
244 char *get_unique_label(char *buf, size_t buflen, const char *prefix) {
245 static unsigned long id = 0;
246 snprintf(buf, buflen, "%s%lu", prefix, ++id);
251 * coding of conditions
253 struct cmp2conditon_t {
259 * positive conditions for signed compares
261 static const struct cmp2conditon_t cmp2condition_s[] = {
262 { NULL, pn_Cmp_False }, /* always false */
263 { "e", pn_Cmp_Eq }, /* == */
264 { "l", pn_Cmp_Lt }, /* < */
265 { "le", pn_Cmp_Le }, /* <= */
266 { "g", pn_Cmp_Gt }, /* > */
267 { "ge", pn_Cmp_Ge }, /* >= */
268 { "ne", pn_Cmp_Lg }, /* != */
269 { "ordered", pn_Cmp_Leg }, /* Floating point: ordered */
270 { "unordered", pn_Cmp_Uo }, /* FLoting point: unordered */
271 { "unordered or ==", pn_Cmp_Ue }, /* Floating point: unordered or == */
272 { "unordered or <", pn_Cmp_Ul }, /* Floating point: unordered or < */
273 { "unordered or <=", pn_Cmp_Ule }, /* Floating point: unordered or <= */
274 { "unordered or >", pn_Cmp_Ug }, /* Floating point: unordered or > */
275 { "unordered or >=", pn_Cmp_Uge }, /* Floating point: unordered or >= */
276 { "unordered or !=", pn_Cmp_Ne }, /* Floating point: unordered or != */
277 { NULL, pn_Cmp_True }, /* always true */
281 * positive conditions for unsigned compares
283 static const struct cmp2conditon_t cmp2condition_u[] = {
284 { NULL, pn_Cmp_False }, /* always false */
285 { "e", pn_Cmp_Eq }, /* == */
286 { "b", pn_Cmp_Lt }, /* < */
287 { "be", pn_Cmp_Le }, /* <= */
288 { "a", pn_Cmp_Gt }, /* > */
289 { "ae", pn_Cmp_Ge }, /* >= */
290 { "ne", pn_Cmp_Lg }, /* != */
291 { "ordered", pn_Cmp_Leg }, /* Floating point: ordered */
292 { "unordered", pn_Cmp_Uo }, /* FLoting point: unordered */
293 { "unordered or ==", pn_Cmp_Ue }, /* Floating point: unordered or == */
294 { "unordered or <", pn_Cmp_Ul }, /* Floating point: unordered or < */
295 { "unordered or <=", pn_Cmp_Ule }, /* Floating point: unordered or <= */
296 { "unordered or >", pn_Cmp_Ug }, /* Floating point: unordered or > */
297 { "unordered or >=", pn_Cmp_Uge }, /* Floating point: unordered or >= */
298 { "unordered or !=", pn_Cmp_Ne }, /* Floating point: unordered or != */
299 { NULL, pn_Cmp_True }, /* always true */
303 * returns the condition code
305 static const char *get_cmp_suffix(int cmp_code, int unsigned_cmp)
307 assert(cmp2condition_s[cmp_code].num == cmp_code);
308 assert(cmp2condition_u[cmp_code].num == cmp_code);
310 return unsigned_cmp ? cmp2condition_u[cmp_code & 7].name : cmp2condition_s[cmp_code & 7].name;
314 * Returns the target label for a control flow node.
316 static char *get_cfop_target(const ir_node *irn, char *buf) {
317 ir_node *bl = get_irn_link(irn);
319 snprintf(buf, SNPRINTF_BUF_LEN, "BLOCK_%ld", get_irn_node_nr(bl));
324 * Emits the jump sequence for a conditional jump (cmp + jmp_true + jmp_false)
326 static void finish_CondJmp(FILE *F, ir_node *irn) {
328 const ir_edge_t *edge;
329 char buf[SNPRINTF_BUF_LEN];
331 edge = get_irn_out_edge_first(irn);
332 proj = get_edge_src_irn(edge);
333 assert(is_Proj(proj) && "CondJmp with a non-Proj");
335 if (get_Proj_proj(proj) == 1) {
336 fprintf(F, "\tj%s %s\t\t\t/* cmp(a, b) == TRUE */\n",
337 get_cmp_suffix(get_ia32_pncode(irn), !mode_is_signed(get_irn_mode(get_irn_n(irn, 0)))),
338 get_cfop_target(proj, buf));
341 fprintf(F, "\tjn%s %s\t\t\t/* cmp(a, b) == FALSE */\n",
342 get_cmp_suffix(get_ia32_pncode(irn), !mode_is_signed(get_irn_mode(get_irn_n(irn, 0)))),
343 get_cfop_target(proj, buf));
346 edge = get_irn_out_edge_next(irn, edge);
348 proj = get_edge_src_irn(edge);
349 assert(is_Proj(proj) && "CondJmp with a non-Proj");
350 fprintf(F, "\tjmp %s\t\t\t/* otherwise */\n", get_cfop_target(proj, buf));
355 * Emits code for conditional jump with two variables.
357 static void emit_ia32_CondJmp(ir_node *irn, emit_env_t *env) {
360 lc_efprintf(ia32_get_arg_env(), F, "\tcmp %2s, %1s\t\t\t/* CondJmp(%+F, %+F) */\n", irn, irn,
361 get_irn_n(irn, 0), get_irn_n(irn, 1));
362 finish_CondJmp(F, irn);
366 * Emits code for conditional jump with immediate.
368 void emit_ia32_CondJmp_i(ir_node *irn, emit_env_t *env) {
371 lc_efprintf(ia32_get_arg_env(), F, "\tcmp %c, %1s\t\t\t/* CondJmp_i(%+F) */\n", irn, irn, get_irn_n(irn, 0));
372 finish_CondJmp(F, irn);
375 typedef struct _branch_t {
380 typedef struct _jmp_tbl_t {
389 /* Compare two variables of type branch_t */
390 static int ia32_cmp_branch_t(const void *a, const void *b) {
391 branch_t *b1 = (branch_t *)a;
392 branch_t *b2 = (branch_t *)b;
394 if (b1->value <= b2->value)
401 * Emits code for a SwitchJmp (creates a jump table if
402 * possible otherwise a cmp-jmp cascade). Port from
405 void emit_ia32_SwitchJmp(const ir_node *irn, emit_env_t *emit_env) {
406 unsigned long interval;
407 char buf[SNPRINTF_BUF_LEN];
408 int last_value, i, pn, do_jmp_tbl = 1;
411 const ir_edge_t *edge;
412 const lc_arg_env_t *env = ia32_get_arg_env();
413 FILE *F = emit_env->out;
415 /* fill the table structure */
416 tbl.label = malloc(SNPRINTF_BUF_LEN);
417 tbl.label = get_unique_label(tbl.label, SNPRINTF_BUF_LEN, "JMPTBL_");
419 tbl.num_branches = get_irn_n_edges(irn);
420 tbl.branches = calloc(tbl.num_branches, sizeof(*(tbl.branches)));
421 tbl.min_value = INT_MAX;
422 tbl.max_value = INT_MIN;
425 /* go over all proj's and collect them */
426 foreach_out_edge(irn, edge) {
427 proj = get_edge_src_irn(edge);
428 assert(is_Proj(proj) && "Only proj allowed at SwitchJmp");
430 pn = get_Proj_proj(proj);
432 /* create branch entry */
433 tbl.branches[i].target = proj;
434 tbl.branches[i].value = pn;
436 tbl.min_value = pn < tbl.min_value ? pn : tbl.min_value;
437 tbl.max_value = pn > tbl.max_value ? pn : tbl.max_value;
439 /* check for default proj */
440 if (pn == get_ia32_pncode(irn)) {
441 assert(tbl.defProj == NULL && "found two defProjs at SwitchJmp");
448 /* sort the branches by their number */
449 qsort(tbl.branches, tbl.num_branches, sizeof(*(tbl.branches)), ia32_cmp_branch_t);
451 /* two-complement's magic make this work without overflow */
452 interval = tbl.max_value - tbl.min_value;
454 /* check value interval */
455 if (interval > 16 * 1024) {
459 /* check ratio of value interval to number of branches */
460 if ((float)(interval + 1) / (float)tbl.num_branches > 8.0) {
466 if (tbl.min_value != 0) {
467 fprintf(F, "\tcmpl %lu, -%d", interval, tbl.min_value);
468 lc_efprintf(env, F, "(%1s)\t\t/* first switch value is not 0 */\n", irn);
471 fprintf(F, "\tcmpl %lu, ", interval);
472 lc_efprintf(env, F, "%1s\t\t\t/* compare for switch */\n", irn);
475 fprintf(F, "\tja %s\t\t\t/* default jump if out of range */\n", get_cfop_target(tbl.defProj, buf));
477 if (tbl.num_branches > 1) {
480 fprintf(F, "\tjmp *%s", tbl.label);
481 lc_efprintf(env, F, "(,%1s,4)\t\t/* get jump table entry as target */\n", irn);
483 fprintf(F, "\t.section\t.rodata\t\t/* start jump table */\n");
484 fprintf(F, "\t.align 4\n");
486 fprintf(F, "%s:\n", tbl.label);
487 fprintf(F, "\t.long %s\t\t\t/* case %d */\n", get_cfop_target(tbl.branches[0].target, buf), tbl.branches[0].value);
489 last_value = tbl.branches[0].value;
490 for (i = 1; i < tbl.num_branches; ++i) {
491 while (++last_value < tbl.branches[i].value) {
492 fprintf(F, "\t.long %s\t\t/* default case */\n", get_cfop_target(tbl.defProj, buf));
494 fprintf(F, "\t.long %s\t\t\t/* case %d */\n", get_cfop_target(tbl.branches[i].target, buf), last_value);
497 fprintf(F, "\t.text\t\t\t\t/* end of jump table */\n");
500 /* one jump is enough */
501 fprintf(F, "\tjmp %s\t\t/* only one case given */\n", get_cfop_target(tbl.branches[0].target, buf));
504 else { // no jump table
505 for (i = 0; i < tbl.num_branches; ++i) {
506 fprintf(F, "\tcmpl %d, ", tbl.branches[i].value);
507 lc_efprintf(env, F, "%1s", irn);
508 fprintf(F, "\t\t\t/* case %d */\n", tbl.branches[i].value);
509 fprintf(F, "\tje %s\n", get_cfop_target(tbl.branches[i].target, buf));
512 fprintf(F, "\tjmp %s\t\t\t/* default case */\n", get_cfop_target(tbl.defProj, buf));
520 * Emits code for a unconditional jump.
522 void emit_Jmp(ir_node *irn, emit_env_t *env) {
525 char buf[SNPRINTF_BUF_LEN];
526 ir_fprintf(F, "\tjmp %s\t\t\t/* Jmp(%+F) */\n", get_cfop_target(irn, buf), get_irn_link(irn));
530 * Emits code for a proj -> node
532 void emit_Proj(ir_node *irn, emit_env_t *env) {
533 ir_node *pred = get_Proj_pred(irn);
535 if (get_irn_opcode(pred) == iro_Start) {
536 switch(get_Proj_proj(irn)) {
537 case pn_Start_X_initial_exec:
547 * Main emitting function
549 void ia32_emit_node(ir_node *irn, void *env) {
550 emit_env_t *emit_env = env;
551 firm_dbg_module_t *mod = emit_env->mod;
552 FILE *F = emit_env->out;
554 DBG((mod, LEVEL_1, "emitting code for %+F\n", irn));
556 #define IA32_EMIT(a) if (is_ia32_##a(irn)) { emit_ia32_##a(irn, emit_env); return; }
557 #define EMIT(a) if (get_irn_opcode(irn) == iro_##a) { emit_##a(irn, emit_env); return; }
559 /* generated int emitter functions */
605 /* generated floating point emitter */
621 /* other emitter functions */
623 IA32_EMIT(CondJmp_i);
624 IA32_EMIT(SwitchJmp);
629 ir_fprintf(F, "\t\t\t\t\t/* %+F */\n", irn);
633 * Walks over the nodes in a block connected by scheduling edges
634 * and emits code for each node.
636 void ia32_gen_block(ir_node *block, void *env) {
639 fprintf(((emit_env_t *)env)->out, "BLOCK_%ld:\n", get_irn_node_nr(block));
640 sched_foreach(block, irn) {
641 ia32_emit_node(irn, env);
647 * Emits code for function start.
649 void ia32_emit_start(FILE *F, ir_graph *irg) {
650 const char *irg_name = get_entity_name(get_irg_entity(irg));
652 fprintf(F, "\t.text\n");
653 fprintf(F, ".globl %s\n", irg_name);
654 fprintf(F, "\t.type\t%s, @function\n", irg_name);
655 fprintf(F, "%s:\n", irg_name);
659 * Emits code for function end
661 void ia32_emit_end(FILE *F, ir_graph *irg) {
662 const char *irg_name = get_entity_name(get_irg_entity(irg));
664 fprintf(F, "\tret\n");
665 fprintf(F, "\t.size\t%s, .-%s\n\n", irg_name, irg_name);
669 * Sets labels for control flow nodes (jump target)
670 * TODO: Jump optimization
672 void ia32_gen_labels(ir_node *block, void *env) {
674 int n = get_Block_n_cfgpreds(block);
676 for (n--; n >= 0; n--) {
677 pred = get_Block_cfgpred(block, n);
678 set_irn_link(pred, block);
685 void ia32_gen_routine(FILE *F, ir_graph *irg, set *reg_set) {
688 emit_env.mod = firm_dbg_register("be.codegen.ia32");
690 emit_env.reg_set = reg_set;
692 cur_reg_set = reg_set;
694 ia32_emit_start(F, irg);
695 irg_block_walk_graph(irg, ia32_gen_labels, NULL, &emit_env);
696 irg_block_walk_graph(irg, NULL, ia32_gen_block, &emit_env);
697 ia32_emit_end(F, irg);