2 * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This file implements the ia32 node emitter.
23 * @author Christian Wuerdig, Matthias Braun
39 #include "iredges_t.h"
42 #include "raw_bitset.h"
45 #include "../besched_t.h"
46 #include "../benode_t.h"
48 #include "../be_dbgout.h"
49 #include "../beemitter.h"
50 #include "../begnuas.h"
51 #include "../beirg_t.h"
52 #include "../be_dbgout.h"
54 #include "ia32_emitter.h"
55 #include "gen_ia32_emitter.h"
56 #include "gen_ia32_regalloc_if.h"
57 #include "ia32_nodes_attr.h"
58 #include "ia32_new_nodes.h"
59 #include "ia32_map_regs.h"
60 #include "ia32_architecture.h"
61 #include "bearch_ia32_t.h"
63 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
65 #define BLOCK_PREFIX ".L"
67 #define SNPRINTF_BUF_LEN 128
69 static const ia32_isa_t *isa;
70 static ia32_code_gen_t *cg;
72 static char pic_base_label[128];
73 static ir_label_t exc_label_id;
74 static int mark_spill_reload = 0;
76 /** Return the next block in Block schedule */
77 static ir_node *get_prev_block_sched(const ir_node *block)
79 return get_irn_link(block);
82 /** Checks if the current block is a fall-through target. */
83 static int is_fallthrough(const ir_node *cfgpred)
87 if (!is_Proj(cfgpred))
89 pred = get_Proj_pred(cfgpred);
90 if (is_ia32_SwitchJmp(pred))
97 * returns non-zero if the given block needs a label
98 * because of being a jump-target (and not a fall-through)
100 static int block_needs_label(const ir_node *block)
103 int n_cfgpreds = get_Block_n_cfgpreds(block);
105 if (n_cfgpreds == 0) {
107 } else if (n_cfgpreds == 1) {
108 ir_node *cfgpred = get_Block_cfgpred(block, 0);
109 ir_node *cfgpred_block = get_nodes_block(cfgpred);
111 if (get_prev_block_sched(block) == cfgpred_block
112 && is_fallthrough(cfgpred)) {
121 * Returns the register at in position pos.
123 static const arch_register_t *get_in_reg(const ir_node *irn, int pos)
126 const arch_register_t *reg = NULL;
128 assert(get_irn_arity(irn) > pos && "Invalid IN position");
130 /* The out register of the operator at position pos is the
131 in register we need. */
132 op = get_irn_n(irn, pos);
134 reg = arch_get_irn_register(op);
136 assert(reg && "no in register found");
138 if (reg == &ia32_gp_regs[REG_GP_NOREG])
139 panic("trying to emit noreg for %+F input %d", irn, pos);
141 /* in case of unknown register: just return a valid register */
142 if (reg == &ia32_gp_regs[REG_GP_UKNWN]) {
143 const arch_register_req_t *req = arch_get_register_req(irn, pos);
145 if (arch_register_req_is(req, limited)) {
146 /* in case of limited requirements: get the first allowed register */
147 unsigned idx = rbitset_next(req->limited, 0, 1);
148 reg = arch_register_for_index(req->cls, idx);
150 /* otherwise get first register in class */
151 reg = arch_register_for_index(req->cls, 0);
159 * Returns the register at out position pos.
161 static const arch_register_t *get_out_reg(const ir_node *irn, int pos)
164 const arch_register_t *reg = NULL;
166 /* 1st case: irn is not of mode_T, so it has only */
167 /* one OUT register -> good */
168 /* 2nd case: irn is of mode_T -> collect all Projs and ask the */
169 /* Proj with the corresponding projnum for the register */
171 if (get_irn_mode(irn) != mode_T) {
173 reg = arch_get_irn_register(irn);
174 } else if (is_ia32_irn(irn)) {
175 reg = arch_irn_get_register(irn, pos);
177 const ir_edge_t *edge;
179 foreach_out_edge(irn, edge) {
180 proj = get_edge_src_irn(edge);
181 assert(is_Proj(proj) && "non-Proj from mode_T node");
182 if (get_Proj_proj(proj) == pos) {
183 reg = arch_get_irn_register(proj);
189 assert(reg && "no out register found");
194 * Add a number to a prefix. This number will not be used a second time.
196 static char *get_unique_label(char *buf, size_t buflen, const char *prefix)
198 static unsigned long id = 0;
199 snprintf(buf, buflen, "%s%lu", prefix, ++id);
203 /*************************************************************
205 * (_) | | / _| | | | |
206 * _ __ _ __ _ _ __ | |_| |_ | |__ ___| |_ __ ___ _ __
207 * | '_ \| '__| | '_ \| __| _| | '_ \ / _ \ | '_ \ / _ \ '__|
208 * | |_) | | | | | | | |_| | | | | | __/ | |_) | __/ |
209 * | .__/|_| |_|_| |_|\__|_| |_| |_|\___|_| .__/ \___|_|
212 *************************************************************/
214 static void emit_8bit_register(const arch_register_t *reg)
216 const char *reg_name = arch_register_get_name(reg);
219 be_emit_char(reg_name[1]);
223 static void emit_16bit_register(const arch_register_t *reg)
225 const char *reg_name = ia32_get_mapped_reg_name(isa->regs_16bit, reg);
228 be_emit_string(reg_name);
231 static void emit_register(const arch_register_t *reg, const ir_mode *mode)
233 const char *reg_name;
236 int size = get_mode_size_bits(mode);
238 case 8: emit_8bit_register(reg); return;
239 case 16: emit_16bit_register(reg); return;
241 assert(mode_is_float(mode) || size == 32);
244 reg_name = arch_register_get_name(reg);
247 be_emit_string(reg_name);
250 void ia32_emit_source_register(const ir_node *node, int pos)
252 const arch_register_t *reg = get_in_reg(node, pos);
254 emit_register(reg, NULL);
257 static void ia32_emit_entity(ir_entity *entity, int no_pic_adjust)
261 set_entity_backend_marked(entity, 1);
262 id = get_entity_ld_ident(entity);
265 if (get_entity_owner(entity) == get_tls_type()) {
266 if (get_entity_visibility(entity) == visibility_external_allocated) {
267 be_emit_cstring("@INDNTPOFF");
269 be_emit_cstring("@NTPOFF");
273 if (!no_pic_adjust && do_pic) {
274 /* TODO: only do this when necessary */
276 be_emit_string(pic_base_label);
280 static void emit_ia32_Immediate_no_prefix(const ir_node *node)
282 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(node);
284 if (attr->symconst != NULL) {
287 ia32_emit_entity(attr->symconst, 0);
289 if (attr->symconst == NULL || attr->offset != 0) {
290 if (attr->symconst != NULL) {
291 be_emit_irprintf("%+d", attr->offset);
293 be_emit_irprintf("0x%X", attr->offset);
298 static void emit_ia32_Immediate(const ir_node *node)
301 emit_ia32_Immediate_no_prefix(node);
304 void ia32_emit_8bit_source_register_or_immediate(const ir_node *node, int pos)
306 const arch_register_t *reg;
307 ir_node *in = get_irn_n(node, pos);
308 if (is_ia32_Immediate(in)) {
309 emit_ia32_Immediate(in);
313 reg = get_in_reg(node, pos);
314 emit_8bit_register(reg);
317 void ia32_emit_dest_register(const ir_node *node, int pos)
319 const arch_register_t *reg = get_out_reg(node, pos);
321 emit_register(reg, NULL);
324 void ia32_emit_8bit_dest_register(const ir_node *node, int pos)
326 const arch_register_t *reg = get_out_reg(node, pos);
328 emit_register(reg, mode_Bu);
331 void ia32_emit_x87_register(const ir_node *node, int pos)
333 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
337 be_emit_string(attr->x87[pos]->name);
340 static void ia32_emit_mode_suffix_mode(const ir_mode *mode)
342 assert(mode_is_int(mode) || mode_is_reference(mode));
343 switch (get_mode_size_bits(mode)) {
344 case 8: be_emit_char('b'); return;
345 case 16: be_emit_char('w'); return;
346 case 32: be_emit_char('l'); return;
347 /* gas docu says q is the suffix but gcc, objdump and icc use ll
349 case 64: be_emit_cstring("ll"); return;
351 panic("Can't output mode_suffix for %+F", mode);
354 void ia32_emit_mode_suffix(const ir_node *node)
356 ir_mode *mode = get_ia32_ls_mode(node);
360 ia32_emit_mode_suffix_mode(mode);
363 void ia32_emit_x87_mode_suffix(const ir_node *node)
367 /* we only need to emit the mode on address mode */
368 if (get_ia32_op_type(node) == ia32_Normal)
371 mode = get_ia32_ls_mode(node);
372 assert(mode != NULL);
374 if (mode_is_float(mode)) {
375 switch (get_mode_size_bits(mode)) {
376 case 32: be_emit_char('s'); return;
377 case 64: be_emit_char('l'); return;
379 case 96: be_emit_char('t'); return;
382 assert(mode_is_int(mode));
383 switch (get_mode_size_bits(mode)) {
384 case 16: be_emit_char('s'); return;
385 case 32: be_emit_char('l'); return;
386 /* gas docu says q is the suffix but gcc, objdump and icc use ll
388 case 64: be_emit_cstring("ll"); return;
391 panic("Can't output mode_suffix for %+F", mode);
394 static char get_xmm_mode_suffix(ir_mode *mode)
396 assert(mode_is_float(mode));
397 switch(get_mode_size_bits(mode)) {
400 default: panic("Invalid XMM mode");
404 void ia32_emit_xmm_mode_suffix(const ir_node *node)
406 ir_mode *mode = get_ia32_ls_mode(node);
407 assert(mode != NULL);
409 be_emit_char(get_xmm_mode_suffix(mode));
412 void ia32_emit_xmm_mode_suffix_s(const ir_node *node)
414 ir_mode *mode = get_ia32_ls_mode(node);
415 assert(mode != NULL);
416 be_emit_char(get_xmm_mode_suffix(mode));
419 void ia32_emit_extend_suffix(const ir_node *node)
421 ir_mode *mode = get_ia32_ls_mode(node);
422 if (get_mode_size_bits(mode) == 32)
424 be_emit_char(mode_is_signed(mode) ? 's' : 'z');
425 ia32_emit_mode_suffix_mode(mode);
428 void ia32_emit_source_register_or_immediate(const ir_node *node, int pos)
430 ir_node *in = get_irn_n(node, pos);
431 if (is_ia32_Immediate(in)) {
432 emit_ia32_Immediate(in);
434 const ir_mode *mode = get_ia32_ls_mode(node);
435 const arch_register_t *reg = get_in_reg(node, pos);
436 emit_register(reg, mode);
441 * Returns the target block for a control flow node.
443 static ir_node *get_cfop_target_block(const ir_node *irn)
445 assert(get_irn_mode(irn) == mode_X);
446 return get_irn_link(irn);
450 * Emits a block label for the given block.
452 static void ia32_emit_block_name(const ir_node *block)
454 if (has_Block_label(block)) {
455 be_emit_string(be_gas_block_label_prefix());
456 be_emit_irprintf("%lu", get_Block_label(block));
458 be_emit_cstring(BLOCK_PREFIX);
459 be_emit_irprintf("%ld", get_irn_node_nr(block));
464 * Emits the target label for a control flow node.
466 static void ia32_emit_cfop_target(const ir_node *node)
468 ir_node *block = get_cfop_target_block(node);
469 ia32_emit_block_name(block);
473 * positive conditions for signed compares
475 static const char *const cmp2condition_s[] = {
476 NULL, /* always false */
483 NULL /* always true */
487 * positive conditions for unsigned compares
489 static const char *const cmp2condition_u[] = {
490 NULL, /* always false */
497 NULL /* always true */
500 static void ia32_emit_cmp_suffix(int pnc)
504 if (pnc == ia32_pn_Cmp_parity) {
508 if (pnc & ia32_pn_Cmp_float || pnc & ia32_pn_Cmp_unsigned) {
509 str = cmp2condition_u[pnc & 7];
511 str = cmp2condition_s[pnc & 7];
517 typedef enum ia32_emit_mod_t {
518 EMIT_RESPECT_LS = 1U << 0,
519 EMIT_ALTERNATE_AM = 1U << 1,
524 * fmt parameter output
525 * ---- ---------------------- ---------------------------------------------
527 * %AM <node> address mode of the node
528 * %AR const arch_register_t* address mode of the node or register
529 * %ASx <node> address mode of the node or source register x
530 * %Dx <node> destination register x
531 * %I <node> immediate of the node
532 * %L <node> control flow target of the node
533 * %M <node> mode suffix of the node
534 * %P int condition code
535 * %R const arch_register_t* register
536 * %Sx <node> source register x
537 * %s const char* string
538 * %u unsigned int unsigned int
539 * %d signed int signed int
542 * # modifier for %ASx, %D and %S uses ls mode of node to alter register width
543 * * modifier does not prefix immediates with $, but AM with *
544 * l modifier for %lu and %ld
546 static void ia32_emitf(const ir_node *node, const char *fmt, ...)
552 const char *start = fmt;
553 ia32_emit_mod_t mod = 0;
555 while (*fmt != '%' && *fmt != '\n' && *fmt != '\0')
558 be_emit_string_len(start, fmt - start);
562 be_emit_finish_line_gas(node);
574 mod |= EMIT_ALTERNATE_AM;
579 mod |= EMIT_RESPECT_LS;
596 if (mod & EMIT_ALTERNATE_AM)
602 const arch_register_t *reg = va_arg(ap, const arch_register_t*);
603 if (mod & EMIT_ALTERNATE_AM)
605 if (get_ia32_op_type(node) == ia32_AddrModeS) {
608 emit_register(reg, NULL);
614 if (get_ia32_op_type(node) == ia32_AddrModeS) {
615 if (mod & EMIT_ALTERNATE_AM)
620 assert(get_ia32_op_type(node) == ia32_Normal);
625 default: goto unknown;
632 const arch_register_t *reg;
634 if (*fmt < '0' || '9' <= *fmt)
638 reg = get_out_reg(node, pos);
639 emit_register(reg, mod & EMIT_RESPECT_LS ? get_ia32_ls_mode(node) : NULL);
644 if (!(mod & EMIT_ALTERNATE_AM))
646 emit_ia32_Immediate_no_prefix(node);
650 ia32_emit_cfop_target(node);
654 ia32_emit_mode_suffix_mode(get_ia32_ls_mode(node));
659 int pnc = va_arg(ap, int);
660 ia32_emit_cmp_suffix(pnc);
665 const arch_register_t *reg = va_arg(ap, const arch_register_t*);
666 emit_register(reg, NULL);
675 if (*fmt < '0' || '9' <= *fmt)
679 in = get_irn_n(node, pos);
680 if (is_ia32_Immediate(in)) {
681 if (!(mod & EMIT_ALTERNATE_AM))
683 emit_ia32_Immediate_no_prefix(in);
685 const arch_register_t *reg;
687 if (mod & EMIT_ALTERNATE_AM)
689 reg = get_in_reg(node, pos);
690 emit_register(reg, mod & EMIT_RESPECT_LS ? get_ia32_ls_mode(node) : NULL);
696 const char *str = va_arg(ap, const char*);
702 if (mod & EMIT_LONG) {
703 unsigned long num = va_arg(ap, unsigned long);
704 be_emit_irprintf("%lu", num);
706 unsigned num = va_arg(ap, unsigned);
707 be_emit_irprintf("%u", num);
712 if (mod & EMIT_LONG) {
713 long num = va_arg(ap, long);
714 be_emit_irprintf("%ld", num);
716 int num = va_arg(ap, int);
717 be_emit_irprintf("%d", num);
723 panic("unknown format conversion in ia32_emitf()");
731 * Emits registers and/or address mode of a binary operation.
733 void ia32_emit_binop(const ir_node *node)
735 if (is_ia32_Immediate(get_irn_n(node, n_ia32_binary_right))) {
736 ia32_emitf(node, "%#S4, %#AS3");
738 ia32_emitf(node, "%#AS4, %#S3");
743 * Emits registers and/or address mode of a binary operation.
745 void ia32_emit_x87_binop(const ir_node *node)
747 switch(get_ia32_op_type(node)) {
750 const ia32_x87_attr_t *x87_attr = get_ia32_x87_attr_const(node);
751 const arch_register_t *in1 = x87_attr->x87[0];
752 const arch_register_t *in = x87_attr->x87[1];
753 const arch_register_t *out = x87_attr->x87[2];
757 } else if (out == in) {
762 be_emit_string(arch_register_get_name(in));
763 be_emit_cstring(", %");
764 be_emit_string(arch_register_get_name(out));
772 assert(0 && "unsupported op type");
777 * Emits registers and/or address mode of a unary operation.
779 void ia32_emit_unop(const ir_node *node, int pos)
783 ia32_emitf(node, fmt);
787 * Emits address mode.
789 void ia32_emit_am(const ir_node *node)
791 ir_entity *ent = get_ia32_am_sc(node);
792 int offs = get_ia32_am_offs_int(node);
793 ir_node *base = get_irn_n(node, n_ia32_base);
794 int has_base = !is_ia32_NoReg_GP(base);
795 ir_node *index = get_irn_n(node, n_ia32_index);
796 int has_index = !is_ia32_NoReg_GP(index);
798 /* just to be sure... */
799 assert(!is_ia32_use_frame(node) || get_ia32_frame_ent(node) != NULL);
803 if (is_ia32_am_sc_sign(node))
805 ia32_emit_entity(ent, 0);
808 /* also handle special case if nothing is set */
809 if (offs != 0 || (ent == NULL && !has_base && !has_index)) {
811 be_emit_irprintf("%+d", offs);
813 be_emit_irprintf("%d", offs);
817 if (has_base || has_index) {
822 const arch_register_t *reg = get_in_reg(node, n_ia32_base);
823 emit_register(reg, NULL);
826 /* emit index + scale */
828 const arch_register_t *reg = get_in_reg(node, n_ia32_index);
831 emit_register(reg, NULL);
833 scale = get_ia32_am_scale(node);
835 be_emit_irprintf(",%d", 1 << scale);
842 static void emit_ia32_IMul(const ir_node *node)
844 ir_node *left = get_irn_n(node, n_ia32_IMul_left);
845 const arch_register_t *out_reg = get_out_reg(node, pn_ia32_IMul_res);
847 /* do we need the 3-address form? */
848 if (is_ia32_NoReg_GP(left) ||
849 get_in_reg(node, n_ia32_IMul_left) != out_reg) {
850 ia32_emitf(node, "\timul%M %#S4, %#AS3, %#D0\n");
852 ia32_emitf(node, "\timul%M %#AS4, %#S3\n");
857 * walks up a tree of copies/perms/spills/reloads to find the original value
858 * that is moved around
860 static ir_node *find_original_value(ir_node *node)
862 if (irn_visited(node))
865 mark_irn_visited(node);
866 if (be_is_Copy(node)) {
867 return find_original_value(be_get_Copy_op(node));
868 } else if (be_is_CopyKeep(node)) {
869 return find_original_value(be_get_CopyKeep_op(node));
870 } else if (is_Proj(node)) {
871 ir_node *pred = get_Proj_pred(node);
872 if (be_is_Perm(pred)) {
873 return find_original_value(get_irn_n(pred, get_Proj_proj(node)));
874 } else if (be_is_MemPerm(pred)) {
875 return find_original_value(get_irn_n(pred, get_Proj_proj(node) + 1));
876 } else if (is_ia32_Load(pred)) {
877 return find_original_value(get_irn_n(pred, n_ia32_Load_mem));
881 } else if (is_ia32_Store(node)) {
882 return find_original_value(get_irn_n(node, n_ia32_Store_val));
883 } else if (is_Phi(node)) {
885 arity = get_irn_arity(node);
886 for (i = 0; i < arity; ++i) {
887 ir_node *in = get_irn_n(node, i);
888 ir_node *res = find_original_value(in);
899 static int determine_final_pnc(const ir_node *node, int flags_pos,
902 ir_node *flags = get_irn_n(node, flags_pos);
903 const ia32_attr_t *flags_attr;
904 flags = skip_Proj(flags);
906 if (is_ia32_Sahf(flags)) {
907 ir_node *cmp = get_irn_n(flags, n_ia32_Sahf_val);
908 if (!(is_ia32_FucomFnstsw(cmp) || is_ia32_FucompFnstsw(cmp)
909 || is_ia32_FucomppFnstsw(cmp) || is_ia32_FtstFnstsw(cmp))) {
910 inc_irg_visited(current_ir_graph);
911 cmp = find_original_value(cmp);
913 assert(is_ia32_FucomFnstsw(cmp) || is_ia32_FucompFnstsw(cmp)
914 || is_ia32_FucomppFnstsw(cmp) || is_ia32_FtstFnstsw(cmp));
917 flags_attr = get_ia32_attr_const(cmp);
918 if (flags_attr->data.ins_permuted)
919 pnc = get_mirrored_pnc(pnc);
920 pnc |= ia32_pn_Cmp_float;
921 } else if (is_ia32_Ucomi(flags) || is_ia32_Fucomi(flags)
922 || is_ia32_Fucompi(flags)) {
923 flags_attr = get_ia32_attr_const(flags);
925 if (flags_attr->data.ins_permuted)
926 pnc = get_mirrored_pnc(pnc);
927 pnc |= ia32_pn_Cmp_float;
929 flags_attr = get_ia32_attr_const(flags);
931 if (flags_attr->data.ins_permuted)
932 pnc = get_mirrored_pnc(pnc);
933 if (flags_attr->data.cmp_unsigned)
934 pnc |= ia32_pn_Cmp_unsigned;
940 static pn_Cmp ia32_get_negated_pnc(pn_Cmp pnc)
942 ir_mode *mode = pnc & ia32_pn_Cmp_float ? mode_F : mode_Iu;
943 return get_negated_pnc(pnc, mode);
946 void ia32_emit_cmp_suffix_node(const ir_node *node,
949 const ia32_attr_t *attr = get_ia32_attr_const(node);
951 pn_Cmp pnc = get_ia32_condcode(node);
953 pnc = determine_final_pnc(node, flags_pos, pnc);
954 if (attr->data.ins_permuted)
955 pnc = ia32_get_negated_pnc(pnc);
957 ia32_emit_cmp_suffix(pnc);
961 * Emits an exception label for a given node.
963 static void ia32_emit_exc_label(const ir_node *node)
965 be_emit_string(be_gas_insn_label_prefix());
966 be_emit_irprintf("%lu", get_ia32_exc_label_id(node));
970 * Returns the Proj with projection number proj and NOT mode_M
972 static ir_node *get_proj(const ir_node *node, long proj)
974 const ir_edge_t *edge;
977 assert(get_irn_mode(node) == mode_T && "expected mode_T node");
979 foreach_out_edge(node, edge) {
980 src = get_edge_src_irn(edge);
982 assert(is_Proj(src) && "Proj expected");
983 if (get_irn_mode(src) == mode_M)
986 if (get_Proj_proj(src) == proj)
992 static int can_be_fallthrough(const ir_node *node)
994 ir_node *target_block = get_cfop_target_block(node);
995 ir_node *block = get_nodes_block(node);
996 return get_prev_block_sched(target_block) == block;
1000 * Emits the jump sequence for a conditional jump (cmp + jmp_true + jmp_false)
1002 static void emit_ia32_Jcc(const ir_node *node)
1004 int need_parity_label = 0;
1005 const ir_node *proj_true;
1006 const ir_node *proj_false;
1007 const ir_node *block;
1008 pn_Cmp pnc = get_ia32_condcode(node);
1010 pnc = determine_final_pnc(node, 0, pnc);
1012 /* get both Projs */
1013 proj_true = get_proj(node, pn_ia32_Jcc_true);
1014 assert(proj_true && "Jcc without true Proj");
1016 proj_false = get_proj(node, pn_ia32_Jcc_false);
1017 assert(proj_false && "Jcc without false Proj");
1019 block = get_nodes_block(node);
1021 if (can_be_fallthrough(proj_true)) {
1022 /* exchange both proj's so the second one can be omitted */
1023 const ir_node *t = proj_true;
1025 proj_true = proj_false;
1027 pnc = ia32_get_negated_pnc(pnc);
1030 if (pnc & ia32_pn_Cmp_float) {
1031 /* Some floating point comparisons require a test of the parity flag,
1032 * which indicates that the result is unordered */
1035 ia32_emitf(proj_true, "\tjp %L\n");
1040 ia32_emitf(proj_true, "\tjnp %L\n");
1046 /* we need a local label if the false proj is a fallthrough
1047 * as the falseblock might have no label emitted then */
1048 if (can_be_fallthrough(proj_false)) {
1049 need_parity_label = 1;
1050 ia32_emitf(proj_false, "\tjp 1f\n");
1052 ia32_emitf(proj_false, "\tjp %L\n");
1059 ia32_emitf(proj_true, "\tjp %L\n");
1067 ia32_emitf(proj_true, "\tj%P %L\n", pnc);
1070 if (need_parity_label) {
1071 ia32_emitf(NULL, "1:\n");
1074 /* the second Proj might be a fallthrough */
1075 if (can_be_fallthrough(proj_false)) {
1076 ia32_emitf(proj_false, "\t/* fallthrough to %L */\n");
1078 ia32_emitf(proj_false, "\tjmp %L\n");
1082 static void emit_ia32_CMov(const ir_node *node)
1084 const ia32_attr_t *attr = get_ia32_attr_const(node);
1085 int ins_permuted = attr->data.ins_permuted;
1086 const arch_register_t *out = arch_irn_get_register(node, pn_ia32_res);
1087 pn_Cmp pnc = get_ia32_condcode(node);
1088 const arch_register_t *in_true;
1089 const arch_register_t *in_false;
1091 pnc = determine_final_pnc(node, n_ia32_CMov_eflags, pnc);
1093 in_true = arch_get_irn_register(get_irn_n(node, n_ia32_CMov_val_true));
1094 in_false = arch_get_irn_register(get_irn_n(node, n_ia32_CMov_val_false));
1096 /* should be same constraint fullfilled? */
1097 if (out == in_false) {
1098 /* yes -> nothing to do */
1099 } else if (out == in_true) {
1100 const arch_register_t *tmp;
1102 assert(get_ia32_op_type(node) == ia32_Normal);
1104 ins_permuted = !ins_permuted;
1111 ia32_emitf(node, "\tmovl %R, %R\n", in_false, out);
1115 pnc = ia32_get_negated_pnc(pnc);
1117 /* TODO: handling of Nans isn't correct yet */
1119 ia32_emitf(node, "\tcmov%P %#AR, %#R\n", pnc, in_true, out);
1122 /*********************************************************
1125 * ___ _ __ ___ _| |_ _ _ _ _ __ ___ _ __ ___
1126 * / _ \ '_ ` _ \| | __| | | | | | '_ ` _ \| '_ \/ __|
1127 * | __/ | | | | | | |_ | | |_| | | | | | | |_) \__ \
1128 * \___|_| |_| |_|_|\__| | |\__,_|_| |_| |_| .__/|___/
1131 *********************************************************/
1133 /* jump table entry (target and corresponding number) */
1134 typedef struct _branch_t {
1139 /* jump table for switch generation */
1140 typedef struct _jmp_tbl_t {
1141 ir_node *defProj; /**< default target */
1142 long min_value; /**< smallest switch case */
1143 long max_value; /**< largest switch case */
1144 long num_branches; /**< number of jumps */
1145 char *label; /**< label of the jump table */
1146 branch_t *branches; /**< jump array */
1150 * Compare two variables of type branch_t. Used to sort all switch cases
1152 static int ia32_cmp_branch_t(const void *a, const void *b)
1154 branch_t *b1 = (branch_t *)a;
1155 branch_t *b2 = (branch_t *)b;
1157 if (b1->value <= b2->value)
1164 * Emits code for a SwitchJmp (creates a jump table if
1165 * possible otherwise a cmp-jmp cascade). Port from
1168 static void emit_ia32_SwitchJmp(const ir_node *node)
1170 unsigned long interval;
1176 const ir_edge_t *edge;
1178 /* fill the table structure */
1179 tbl.label = XMALLOCN(char, SNPRINTF_BUF_LEN);
1180 tbl.label = get_unique_label(tbl.label, SNPRINTF_BUF_LEN, ".TBL_");
1182 tbl.num_branches = get_irn_n_edges(node) - 1;
1183 tbl.branches = XMALLOCNZ(branch_t, tbl.num_branches);
1184 tbl.min_value = INT_MAX;
1185 tbl.max_value = INT_MIN;
1187 default_pn = get_ia32_condcode(node);
1189 /* go over all proj's and collect them */
1190 foreach_out_edge(node, edge) {
1191 proj = get_edge_src_irn(edge);
1192 assert(is_Proj(proj) && "Only proj allowed at SwitchJmp");
1194 pnc = get_Proj_proj(proj);
1196 /* check for default proj */
1197 if (pnc == default_pn) {
1198 assert(tbl.defProj == NULL && "found two default Projs at SwitchJmp");
1201 tbl.min_value = pnc < tbl.min_value ? pnc : tbl.min_value;
1202 tbl.max_value = pnc > tbl.max_value ? pnc : tbl.max_value;
1204 /* create branch entry */
1205 tbl.branches[i].target = proj;
1206 tbl.branches[i].value = pnc;
1211 assert(i == tbl.num_branches);
1213 /* sort the branches by their number */
1214 qsort(tbl.branches, tbl.num_branches, sizeof(tbl.branches[0]), ia32_cmp_branch_t);
1216 /* two-complement's magic make this work without overflow */
1217 interval = tbl.max_value - tbl.min_value;
1219 /* emit the table */
1220 ia32_emitf(node, "\tcmpl $%u, %S0\n", interval);
1221 ia32_emitf(tbl.defProj, "\tja %L\n");
1223 if (tbl.num_branches > 1) {
1225 ia32_emitf(node, "\tjmp *%s(,%S0,4)\n", tbl.label);
1227 be_gas_emit_switch_section(GAS_SECTION_RODATA);
1228 ia32_emitf(NULL, "\t.align 4\n");
1229 ia32_emitf(NULL, "%s:\n", tbl.label);
1231 last_value = tbl.branches[0].value;
1232 for (i = 0; i != tbl.num_branches; ++i) {
1233 while (last_value != tbl.branches[i].value) {
1234 ia32_emitf(tbl.defProj, ".long %L\n");
1237 ia32_emitf(tbl.branches[i].target, ".long %L\n");
1240 be_gas_emit_switch_section(GAS_SECTION_TEXT);
1242 /* one jump is enough */
1243 ia32_emitf(tbl.branches[0].target, "\tjmp %L\n");
1253 * Emits code for a unconditional jump.
1255 static void emit_Jmp(const ir_node *node)
1259 /* for now, the code works for scheduled and non-schedules blocks */
1260 block = get_nodes_block(node);
1262 /* we have a block schedule */
1263 if (can_be_fallthrough(node)) {
1264 ia32_emitf(node, "\t/* fallthrough to %L */\n");
1266 ia32_emitf(node, "\tjmp %L\n");
1271 * Emit an inline assembler operand.
1273 * @param node the ia32_ASM node
1274 * @param s points to the operand (a %c)
1276 * @return pointer to the first char in s NOT in the current operand
1278 static const char* emit_asm_operand(const ir_node *node, const char *s)
1280 const ia32_attr_t *ia32_attr = get_ia32_attr_const(node);
1281 const ia32_asm_attr_t *attr = CONST_CAST_IA32_ATTR(ia32_asm_attr_t,
1283 const arch_register_t *reg;
1284 const ia32_asm_reg_t *asm_regs = attr->register_map;
1285 const ia32_asm_reg_t *asm_reg;
1286 const char *reg_name;
1295 /* parse modifiers */
1298 ir_fprintf(stderr, "Warning: asm text (%+F) ends with %%\n", node);
1323 "Warning: asm text (%+F) contains unknown modifier '%c' for asm op\n",
1330 sscanf(s, "%d%n", &num, &p);
1332 ir_fprintf(stderr, "Warning: Couldn't parse assembler operand (%+F)\n",
1339 if (num < 0 || ARR_LEN(asm_regs) <= num) {
1341 "Error: Custom assembler references invalid input/output (%+F)\n",
1345 asm_reg = & asm_regs[num];
1346 assert(asm_reg->valid);
1349 if (asm_reg->use_input == 0) {
1350 reg = get_out_reg(node, asm_reg->inout_pos);
1352 ir_node *pred = get_irn_n(node, asm_reg->inout_pos);
1354 /* might be an immediate value */
1355 if (is_ia32_Immediate(pred)) {
1356 emit_ia32_Immediate(pred);
1359 reg = get_in_reg(node, asm_reg->inout_pos);
1363 "Warning: no register assigned for %d asm op (%+F)\n",
1368 if (asm_reg->memory) {
1373 if (modifier != 0) {
1377 reg_name = ia32_get_mapped_reg_name(isa->regs_8bit, reg);
1380 reg_name = ia32_get_mapped_reg_name(isa->regs_8bit_high, reg);
1383 reg_name = ia32_get_mapped_reg_name(isa->regs_16bit, reg);
1386 panic("Invalid asm op modifier");
1388 be_emit_string(reg_name);
1390 emit_register(reg, asm_reg->mode);
1393 if (asm_reg->memory) {
1401 * Emits code for an ASM pseudo op.
1403 static void emit_ia32_Asm(const ir_node *node)
1405 const void *gen_attr = get_irn_generic_attr_const(node);
1406 const ia32_asm_attr_t *attr
1407 = CONST_CAST_IA32_ATTR(ia32_asm_attr_t, gen_attr);
1408 ident *asm_text = attr->asm_text;
1409 const char *s = get_id_str(asm_text);
1411 ia32_emitf(node, "#APP\t\n");
1418 s = emit_asm_operand(node, s);
1424 ia32_emitf(NULL, "\n#NO_APP\n");
1427 /**********************************
1430 * | | ___ _ __ _ _| |_) |
1431 * | | / _ \| '_ \| | | | _ <
1432 * | |___| (_) | |_) | |_| | |_) |
1433 * \_____\___/| .__/ \__, |____/
1436 **********************************/
1439 * Emit movsb/w instructions to make mov count divideable by 4
1441 static void emit_CopyB_prolog(unsigned size)
1444 ia32_emitf(NULL, "\tmovsb\n");
1446 ia32_emitf(NULL, "\tmovsw\n");
1450 * Emit rep movsd instruction for memcopy.
1452 static void emit_ia32_CopyB(const ir_node *node)
1454 unsigned size = get_ia32_copyb_size(node);
1456 emit_CopyB_prolog(size);
1457 ia32_emitf(node, "\trep movsd\n");
1461 * Emits unrolled memcopy.
1463 static void emit_ia32_CopyB_i(const ir_node *node)
1465 unsigned size = get_ia32_copyb_size(node);
1467 emit_CopyB_prolog(size);
1471 ia32_emitf(NULL, "\tmovsd\n");
1477 /***************************
1481 * | | / _ \| '_ \ \ / /
1482 * | |___| (_) | | | \ V /
1483 * \_____\___/|_| |_|\_/
1485 ***************************/
1488 * Emit code for conversions (I, FP), (FP, I) and (FP, FP).
1490 static void emit_ia32_Conv_with_FP(const ir_node *node, const char* conv_f,
1493 ir_mode *ls_mode = get_ia32_ls_mode(node);
1494 int ls_bits = get_mode_size_bits(ls_mode);
1495 const char *conv = ls_bits == 32 ? conv_f : conv_d;
1497 ia32_emitf(node, "\tcvt%s %AS3, %D0\n", conv);
1500 static void emit_ia32_Conv_I2FP(const ir_node *node)
1502 emit_ia32_Conv_with_FP(node, "si2ss", "si2sd");
1505 static void emit_ia32_Conv_FP2I(const ir_node *node)
1507 emit_ia32_Conv_with_FP(node, "ss2si", "sd2si");
1510 static void emit_ia32_Conv_FP2FP(const ir_node *node)
1512 emit_ia32_Conv_with_FP(node, "sd2ss", "ss2sd");
1516 * Emits code for an Int conversion.
1518 static void emit_ia32_Conv_I2I(const ir_node *node)
1520 ir_mode *smaller_mode = get_ia32_ls_mode(node);
1521 int signed_mode = mode_is_signed(smaller_mode);
1522 const char *sign_suffix;
1524 assert(!mode_is_float(smaller_mode));
1526 sign_suffix = signed_mode ? "s" : "z";
1527 ia32_emitf(node, "\tmov%s%Ml %#AS3, %D0\n", sign_suffix);
1533 static void emit_ia32_Call(const ir_node *node)
1535 /* Special case: Call must not have its immediates prefixed by $, instead
1536 * address mode is prefixed by *. */
1537 ia32_emitf(node, "\tcall %*AS3\n");
1541 /*******************************************
1544 * | |__ ___ _ __ ___ __| | ___ ___
1545 * | '_ \ / _ \ '_ \ / _ \ / _` |/ _ \/ __|
1546 * | |_) | __/ | | | (_) | (_| | __/\__ \
1547 * |_.__/ \___|_| |_|\___/ \__,_|\___||___/
1549 *******************************************/
1552 * Emits code to increase stack pointer.
1554 static void emit_be_IncSP(const ir_node *node)
1556 int offs = be_get_IncSP_offset(node);
1562 ia32_emitf(node, "\tsubl $%u, %D0\n", offs);
1564 ia32_emitf(node, "\taddl $%u, %D0\n", -offs);
1569 * Emits code for Copy/CopyKeep.
1571 static void Copy_emitter(const ir_node *node, const ir_node *op)
1573 const arch_register_t *in = arch_get_irn_register(op);
1574 const arch_register_t *out = arch_get_irn_register(node);
1579 if (is_unknown_reg(in))
1581 /* copies of vf nodes aren't real... */
1582 if (arch_register_get_class(in) == &ia32_reg_classes[CLASS_ia32_vfp])
1585 if (get_irn_mode(node) == mode_E) {
1586 ia32_emitf(node, "\tmovsd %R, %R\n", in, out);
1588 ia32_emitf(node, "\tmovl %R, %R\n", in, out);
1592 static void emit_be_Copy(const ir_node *node)
1594 Copy_emitter(node, be_get_Copy_op(node));
1597 static void emit_be_CopyKeep(const ir_node *node)
1599 Copy_emitter(node, be_get_CopyKeep_op(node));
1603 * Emits code for exchange.
1605 static void emit_be_Perm(const ir_node *node)
1607 const arch_register_t *in0, *in1;
1608 const arch_register_class_t *cls0, *cls1;
1610 in0 = arch_get_irn_register(get_irn_n(node, 0));
1611 in1 = arch_get_irn_register(get_irn_n(node, 1));
1613 cls0 = arch_register_get_class(in0);
1614 cls1 = arch_register_get_class(in1);
1616 assert(cls0 == cls1 && "Register class mismatch at Perm");
1618 if (cls0 == &ia32_reg_classes[CLASS_ia32_gp]) {
1619 ia32_emitf(node, "\txchg %R, %R\n", in1, in0);
1620 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_xmm]) {
1621 ia32_emitf(NULL, "\txorpd %R, %R\n", in1, in0);
1622 ia32_emitf(NULL, "\txorpd %R, %R\n", in0, in1);
1623 ia32_emitf(node, "\txorpd %R, %R\n", in1, in0);
1624 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_vfp]) {
1626 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_st]) {
1629 panic("unexpected register class in be_Perm (%+F)", node);
1634 * Emits code for Constant loading.
1636 static void emit_ia32_Const(const ir_node *node)
1638 ia32_emitf(node, "\tmovl %I, %D0\n");
1642 * Emits code to load the TLS base
1644 static void emit_ia32_LdTls(const ir_node *node)
1646 ia32_emitf(node, "\tmovl %%gs:0, %D0\n");
1649 /* helper function for emit_ia32_Minus64Bit */
1650 static void emit_mov(const ir_node* node, const arch_register_t *src, const arch_register_t *dst)
1652 ia32_emitf(node, "\tmovl %R, %R\n", src, dst);
1655 /* helper function for emit_ia32_Minus64Bit */
1656 static void emit_neg(const ir_node* node, const arch_register_t *reg)
1658 ia32_emitf(node, "\tnegl %R\n", reg);
1661 /* helper function for emit_ia32_Minus64Bit */
1662 static void emit_sbb0(const ir_node* node, const arch_register_t *reg)
1664 ia32_emitf(node, "\tsbbl $0, %R\n", reg);
1667 /* helper function for emit_ia32_Minus64Bit */
1668 static void emit_sbb(const ir_node* node, const arch_register_t *src, const arch_register_t *dst)
1670 ia32_emitf(node, "\tsbbl %R, %R\n", src, dst);
1673 /* helper function for emit_ia32_Minus64Bit */
1674 static void emit_xchg(const ir_node* node, const arch_register_t *src, const arch_register_t *dst)
1676 ia32_emitf(node, "\txchgl %R, %R\n", src, dst);
1679 /* helper function for emit_ia32_Minus64Bit */
1680 static void emit_zero(const ir_node* node, const arch_register_t *reg)
1682 ia32_emitf(node, "\txorl %R, %R\n", reg, reg);
1685 static void emit_ia32_Minus64Bit(const ir_node *node)
1687 const arch_register_t *in_lo = get_in_reg(node, 0);
1688 const arch_register_t *in_hi = get_in_reg(node, 1);
1689 const arch_register_t *out_lo = get_out_reg(node, 0);
1690 const arch_register_t *out_hi = get_out_reg(node, 1);
1692 if (out_lo == in_lo) {
1693 if (out_hi != in_hi) {
1694 /* a -> a, b -> d */
1697 /* a -> a, b -> b */
1700 } else if (out_lo == in_hi) {
1701 if (out_hi == in_lo) {
1702 /* a -> b, b -> a */
1703 emit_xchg(node, in_lo, in_hi);
1706 /* a -> b, b -> d */
1707 emit_mov(node, in_hi, out_hi);
1708 emit_mov(node, in_lo, out_lo);
1712 if (out_hi == in_lo) {
1713 /* a -> c, b -> a */
1714 emit_mov(node, in_lo, out_lo);
1716 } else if (out_hi == in_hi) {
1717 /* a -> c, b -> b */
1718 emit_mov(node, in_lo, out_lo);
1721 /* a -> c, b -> d */
1722 emit_mov(node, in_lo, out_lo);
1728 emit_neg( node, out_hi);
1729 emit_neg( node, out_lo);
1730 emit_sbb0(node, out_hi);
1734 emit_zero(node, out_hi);
1735 emit_neg( node, out_lo);
1736 emit_sbb( node, in_hi, out_hi);
1739 static void emit_ia32_GetEIP(const ir_node *node)
1741 ia32_emitf(node, "\tcall %s\n", pic_base_label);
1742 ia32_emitf(NULL, "%s:\n", pic_base_label);
1743 ia32_emitf(node, "\tpopl %D0\n");
1746 static void emit_ia32_ClimbFrame(const ir_node *node)
1748 const ia32_climbframe_attr_t *attr = get_ia32_climbframe_attr_const(node);
1750 ia32_emitf(node, "\tmovl %S0, %D0\n");
1751 ia32_emitf(node, "\tmovl $%u, %S1\n", attr->count);
1752 ia32_emitf(NULL, BLOCK_PREFIX "%ld:\n", get_irn_node_nr(node));
1753 ia32_emitf(node, "\tmovl (%D0), %D0\n");
1754 ia32_emitf(node, "\tdec %S1\n");
1755 ia32_emitf(node, "\tjnz " BLOCK_PREFIX "%ld\n", get_irn_node_nr(node));
1758 static void emit_be_Return(const ir_node *node)
1760 unsigned pop = be_Return_get_pop(node);
1762 if (pop > 0 || be_Return_get_emit_pop(node)) {
1763 ia32_emitf(node, "\tret $%u\n", pop);
1765 ia32_emitf(node, "\tret\n");
1769 static void emit_Nothing(const ir_node *node)
1775 /***********************************************************************************
1778 * _ __ ___ __ _ _ _ __ | |_ _ __ __ _ _ __ ___ _____ _____ _ __| | __
1779 * | '_ ` _ \ / _` | | '_ \ | _| '__/ _` | '_ ` _ \ / _ \ \ /\ / / _ \| '__| |/ /
1780 * | | | | | | (_| | | | | | | | | | | (_| | | | | | | __/\ V V / (_) | | | <
1781 * |_| |_| |_|\__,_|_|_| |_| |_| |_| \__,_|_| |_| |_|\___| \_/\_/ \___/|_| |_|\_\
1783 ***********************************************************************************/
1786 * Enters the emitter functions for handled nodes into the generic
1787 * pointer of an opcode.
1789 static void ia32_register_emitters(void)
1791 #define IA32_EMIT2(a,b) op_ia32_##a->ops.generic = (op_func)emit_ia32_##b
1792 #define IA32_EMIT(a) IA32_EMIT2(a,a)
1793 #define EMIT(a) op_##a->ops.generic = (op_func)emit_##a
1794 #define IGN(a) op_##a->ops.generic = (op_func)emit_Nothing
1795 #define BE_EMIT(a) op_be_##a->ops.generic = (op_func)emit_be_##a
1796 #define BE_IGN(a) op_be_##a->ops.generic = (op_func)emit_Nothing
1798 /* first clear the generic function pointer for all ops */
1799 clear_irp_opcodes_generic_func();
1801 /* register all emitter functions defined in spec */
1802 ia32_register_spec_emitters();
1804 /* other ia32 emitter functions */
1805 IA32_EMIT2(Conv_I2I8Bit, Conv_I2I);
1810 IA32_EMIT(Conv_FP2FP);
1811 IA32_EMIT(Conv_FP2I);
1812 IA32_EMIT(Conv_I2FP);
1813 IA32_EMIT(Conv_I2I);
1820 IA32_EMIT(Minus64Bit);
1821 IA32_EMIT(SwitchJmp);
1822 IA32_EMIT(ClimbFrame);
1824 /* benode emitter */
1847 typedef void (*emit_func_ptr) (const ir_node *);
1850 * Assign and emit an exception label if the current instruction can fail.
1852 static void ia32_assign_exc_label(ir_node *node)
1854 /* assign a new ID to the instruction */
1855 set_ia32_exc_label_id(node, ++exc_label_id);
1857 ia32_emit_exc_label(node);
1859 be_emit_pad_comment();
1860 be_emit_cstring("/* exception to Block ");
1861 ia32_emit_cfop_target(node);
1862 be_emit_cstring(" */\n");
1863 be_emit_write_line();
1867 * Emits code for a node.
1869 static void ia32_emit_node(ir_node *node)
1871 ir_op *op = get_irn_op(node);
1873 DBG((dbg, LEVEL_1, "emitting code for %+F\n", node));
1875 if (is_ia32_irn(node)) {
1876 if (get_ia32_exc_label(node)) {
1877 /* emit the exception label of this instruction */
1878 ia32_assign_exc_label(node);
1880 if (mark_spill_reload) {
1881 if (is_ia32_is_spill(node)) {
1882 ia32_emitf(NULL, "\txchg %ebx, %ebx /* spill mark */\n");
1884 if (is_ia32_is_reload(node)) {
1885 ia32_emitf(NULL, "\txchg %edx, %edx /* reload mark */\n");
1887 if (is_ia32_is_remat(node)) {
1888 ia32_emitf(NULL, "\txchg %ecx, %ecx /* remat mark */\n");
1892 if (op->ops.generic) {
1893 emit_func_ptr func = (emit_func_ptr) op->ops.generic;
1895 be_dbg_set_dbg_info(get_irn_dbg_info(node));
1900 ir_fprintf(stderr, "Error: No emit handler for node %+F (%+G, graph %+F)\n", node, node, current_ir_graph);
1906 * Emits gas alignment directives
1908 static void ia32_emit_alignment(unsigned align, unsigned skip)
1910 ia32_emitf(NULL, "\t.p2align %u,,%u\n", align, skip);
1914 * Emits gas alignment directives for Labels depended on cpu architecture.
1916 static void ia32_emit_align_label(void)
1918 unsigned align = ia32_cg_config.label_alignment;
1919 unsigned maximum_skip = ia32_cg_config.label_alignment_max_skip;
1920 ia32_emit_alignment(align, maximum_skip);
1924 * Test whether a block should be aligned.
1925 * For cpus in the P4/Athlon class it is useful to align jump labels to
1926 * 16 bytes. However we should only do that if the alignment nops before the
1927 * label aren't executed more often than we have jumps to the label.
1929 static int should_align_block(const ir_node *block)
1931 static const double DELTA = .0001;
1932 ir_exec_freq *exec_freq = cg->birg->exec_freq;
1933 ir_node *prev = get_prev_block_sched(block);
1935 double prev_freq = 0; /**< execfreq of the fallthrough block */
1936 double jmp_freq = 0; /**< execfreq of all non-fallthrough blocks */
1939 if (exec_freq == NULL)
1941 if (ia32_cg_config.label_alignment_factor <= 0)
1944 block_freq = get_block_execfreq(exec_freq, block);
1945 if (block_freq < DELTA)
1948 n_cfgpreds = get_Block_n_cfgpreds(block);
1949 for(i = 0; i < n_cfgpreds; ++i) {
1950 const ir_node *pred = get_Block_cfgpred_block(block, i);
1951 double pred_freq = get_block_execfreq(exec_freq, pred);
1954 prev_freq += pred_freq;
1956 jmp_freq += pred_freq;
1960 if (prev_freq < DELTA && !(jmp_freq < DELTA))
1963 jmp_freq /= prev_freq;
1965 return jmp_freq > ia32_cg_config.label_alignment_factor;
1969 * Emit the block header for a block.
1971 * @param block the block
1972 * @param prev_block the previous block
1974 static void ia32_emit_block_header(ir_node *block)
1976 ir_graph *irg = current_ir_graph;
1977 int need_label = block_needs_label(block);
1979 ir_exec_freq *exec_freq = cg->birg->exec_freq;
1981 if (block == get_irg_end_block(irg))
1984 if (ia32_cg_config.label_alignment > 0) {
1985 /* align the current block if:
1986 * a) if should be aligned due to its execution frequency
1987 * b) there is no fall-through here
1989 if (should_align_block(block)) {
1990 ia32_emit_align_label();
1992 /* if the predecessor block has no fall-through,
1993 we can always align the label. */
1995 int has_fallthrough = 0;
1997 for (i = get_Block_n_cfgpreds(block) - 1; i >= 0; --i) {
1998 ir_node *cfg_pred = get_Block_cfgpred(block, i);
1999 if (can_be_fallthrough(cfg_pred)) {
2000 has_fallthrough = 1;
2005 if (!has_fallthrough)
2006 ia32_emit_align_label();
2010 if (need_label || has_Block_label(block)) {
2011 ia32_emit_block_name(block);
2014 be_emit_pad_comment();
2015 be_emit_cstring(" /* ");
2017 be_emit_cstring("\t/* ");
2018 ia32_emit_block_name(block);
2019 be_emit_cstring(": ");
2022 be_emit_cstring("preds:");
2024 /* emit list of pred blocks in comment */
2025 arity = get_irn_arity(block);
2027 be_emit_cstring(" none");
2029 for (i = 0; i < arity; ++i) {
2030 ir_node *predblock = get_Block_cfgpred_block(block, i);
2031 be_emit_irprintf(" %d", get_irn_node_nr(predblock));
2034 if (exec_freq != NULL) {
2035 be_emit_irprintf(", freq: %f",
2036 get_block_execfreq(exec_freq, block));
2038 be_emit_cstring(" */\n");
2039 be_emit_write_line();
2043 * Walks over the nodes in a block connected by scheduling edges
2044 * and emits code for each node.
2046 static void ia32_gen_block(ir_node *block)
2050 ia32_emit_block_header(block);
2052 /* emit the contents of the block */
2053 be_dbg_set_dbg_info(get_irn_dbg_info(block));
2054 sched_foreach(block, node) {
2055 ia32_emit_node(node);
2059 typedef struct exc_entry {
2060 ir_node *exc_instr; /** The instruction that can issue an exception. */
2061 ir_node *block; /** The block to call then. */
2066 * Sets labels for control flow nodes (jump target).
2067 * Links control predecessors to there destination blocks.
2069 static void ia32_gen_labels(ir_node *block, void *data)
2071 exc_entry **exc_list = data;
2075 for (n = get_Block_n_cfgpreds(block) - 1; n >= 0; --n) {
2076 pred = get_Block_cfgpred(block, n);
2077 set_irn_link(pred, block);
2079 pred = skip_Proj(pred);
2080 if (is_ia32_irn(pred) && get_ia32_exc_label(pred)) {
2085 ARR_APP1(exc_entry, *exc_list, e);
2086 set_irn_link(pred, block);
2092 * Compare two exception_entries.
2094 static int cmp_exc_entry(const void *a, const void *b)
2096 const exc_entry *ea = a;
2097 const exc_entry *eb = b;
2099 if (get_ia32_exc_label_id(ea->exc_instr) < get_ia32_exc_label_id(eb->exc_instr))
2105 * Main driver. Emits the code for one routine.
2107 void ia32_gen_routine(ia32_code_gen_t *ia32_cg, ir_graph *irg)
2109 ir_entity *entity = get_irg_entity(irg);
2110 exc_entry *exc_list = NEW_ARR_F(exc_entry, 0);
2115 do_pic = cg->birg->main_env->options->pic;
2117 ia32_register_emitters();
2119 get_unique_label(pic_base_label, sizeof(pic_base_label), ".PIC_BASE");
2121 be_dbg_method_begin(entity, be_abi_get_stack_layout(cg->birg->abi));
2122 be_gas_emit_function_prolog(entity, ia32_cg_config.function_alignment);
2124 /* we use links to point to target blocks */
2125 ir_reserve_resources(irg, IR_RESOURCE_IRN_LINK);
2126 irg_block_walk_graph(irg, ia32_gen_labels, NULL, &exc_list);
2128 /* initialize next block links */
2129 n = ARR_LEN(cg->blk_sched);
2130 for (i = 0; i < n; ++i) {
2131 ir_node *block = cg->blk_sched[i];
2132 ir_node *prev = i > 0 ? cg->blk_sched[i-1] : NULL;
2134 set_irn_link(block, prev);
2137 for (i = 0; i < n; ++i) {
2138 ir_node *block = cg->blk_sched[i];
2140 ia32_gen_block(block);
2143 be_gas_emit_function_epilog(entity);
2144 be_dbg_method_end();
2146 be_emit_write_line();
2148 ir_free_resources(irg, IR_RESOURCE_IRN_LINK);
2150 /* Sort the exception table using the exception label id's.
2151 Those are ascending with ascending addresses. */
2152 qsort(exc_list, ARR_LEN(exc_list), sizeof(exc_list[0]), cmp_exc_entry);
2156 for (i = 0; i < ARR_LEN(exc_list); ++i) {
2157 be_emit_cstring("\t.long ");
2158 ia32_emit_exc_label(exc_list[i].exc_instr);
2160 be_emit_cstring("\t.long ");
2161 ia32_emit_block_name(exc_list[i].block);
2165 DEL_ARR_F(exc_list);
2168 static const lc_opt_table_entry_t ia32_emitter_options[] = {
2169 LC_OPT_ENT_BOOL("mark_spill_reload", "mark spills and reloads with ud opcodes", &mark_spill_reload),
2173 void ia32_init_emitter(void)
2175 lc_opt_entry_t *be_grp;
2176 lc_opt_entry_t *ia32_grp;
2178 be_grp = lc_opt_get_grp(firm_opt_get_root(), "be");
2179 ia32_grp = lc_opt_get_grp(be_grp, "ia32");
2181 lc_opt_add_table(ia32_grp, ia32_emitter_options);
2183 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.emitter");