2 * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This file implements the ia32 node emitter.
23 * @author Christian Wuerdig, Matthias Braun
39 #include "iredges_t.h"
43 #include "raw_bitset.h"
47 #include "../besched.h"
48 #include "../benode.h"
50 #include "../be_dbgout.h"
51 #include "../beemitter.h"
52 #include "../begnuas.h"
54 #include "../be_dbgout.h"
56 #include "ia32_emitter.h"
57 #include "gen_ia32_emitter.h"
58 #include "gen_ia32_regalloc_if.h"
59 #include "ia32_nodes_attr.h"
60 #include "ia32_new_nodes.h"
61 #include "ia32_map_regs.h"
62 #include "ia32_architecture.h"
63 #include "bearch_ia32_t.h"
65 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
67 #define BLOCK_PREFIX ".L"
69 #define SNPRINTF_BUF_LEN 128
71 static const ia32_isa_t *isa;
72 static ia32_code_gen_t *cg;
73 static char pic_base_label[128];
74 static ir_label_t exc_label_id;
75 static int mark_spill_reload = 0;
78 /** Return the next block in Block schedule */
79 static ir_node *get_prev_block_sched(const ir_node *block)
81 return get_irn_link(block);
84 /** Checks if the current block is a fall-through target. */
85 static int is_fallthrough(const ir_node *cfgpred)
89 if (!is_Proj(cfgpred))
91 pred = get_Proj_pred(cfgpred);
92 if (is_ia32_SwitchJmp(pred))
99 * returns non-zero if the given block needs a label
100 * because of being a jump-target (and not a fall-through)
102 static int block_needs_label(const ir_node *block)
105 int n_cfgpreds = get_Block_n_cfgpreds(block);
107 if (has_Block_entity(block))
110 if (n_cfgpreds == 0) {
112 } else if (n_cfgpreds == 1) {
113 ir_node *cfgpred = get_Block_cfgpred(block, 0);
114 ir_node *cfgpred_block = get_nodes_block(cfgpred);
116 if (get_prev_block_sched(block) == cfgpred_block
117 && is_fallthrough(cfgpred)) {
126 * Returns the register at in position pos.
128 static const arch_register_t *get_in_reg(const ir_node *irn, int pos)
131 const arch_register_t *reg = NULL;
133 assert(get_irn_arity(irn) > pos && "Invalid IN position");
135 /* The out register of the operator at position pos is the
136 in register we need. */
137 op = get_irn_n(irn, pos);
139 reg = arch_get_irn_register(op);
141 assert(reg && "no in register found");
143 if (reg == &ia32_gp_regs[REG_GP_NOREG])
144 panic("trying to emit noreg for %+F input %d", irn, pos);
146 /* in case of unknown register: just return a valid register */
147 if (reg == &ia32_gp_regs[REG_GP_UKNWN]) {
148 const arch_register_req_t *req = arch_get_register_req(irn, pos);
150 if (arch_register_req_is(req, limited)) {
151 /* in case of limited requirements: get the first allowed register */
152 unsigned idx = rbitset_next(req->limited, 0, 1);
153 reg = arch_register_for_index(req->cls, idx);
155 /* otherwise get first register in class */
156 reg = arch_register_for_index(req->cls, 0);
164 * Returns the register at out position pos.
166 static const arch_register_t *get_out_reg(const ir_node *irn, int pos)
169 const arch_register_t *reg = NULL;
171 /* 1st case: irn is not of mode_T, so it has only */
172 /* one OUT register -> good */
173 /* 2nd case: irn is of mode_T -> collect all Projs and ask the */
174 /* Proj with the corresponding projnum for the register */
176 if (get_irn_mode(irn) != mode_T) {
178 reg = arch_get_irn_register(irn);
179 } else if (is_ia32_irn(irn)) {
180 reg = arch_irn_get_register(irn, pos);
182 const ir_edge_t *edge;
184 foreach_out_edge(irn, edge) {
185 proj = get_edge_src_irn(edge);
186 assert(is_Proj(proj) && "non-Proj from mode_T node");
187 if (get_Proj_proj(proj) == pos) {
188 reg = arch_get_irn_register(proj);
194 assert(reg && "no out register found");
199 * Add a number to a prefix. This number will not be used a second time.
201 static char *get_unique_label(char *buf, size_t buflen, const char *prefix)
203 static unsigned long id = 0;
204 snprintf(buf, buflen, "%s%lu", prefix, ++id);
208 /*************************************************************
210 * (_) | | / _| | | | |
211 * _ __ _ __ _ _ __ | |_| |_ | |__ ___| |_ __ ___ _ __
212 * | '_ \| '__| | '_ \| __| _| | '_ \ / _ \ | '_ \ / _ \ '__|
213 * | |_) | | | | | | | |_| | | | | | __/ | |_) | __/ |
214 * | .__/|_| |_|_| |_|\__|_| |_| |_|\___|_| .__/ \___|_|
217 *************************************************************/
220 * Emit the name of the 8bit low register
222 static void emit_8bit_register(const arch_register_t *reg)
224 const char *reg_name = arch_register_get_name(reg);
227 be_emit_char(reg_name[1]);
232 * Emit the name of the 8bit high register
234 static void emit_8bit_register_high(const arch_register_t *reg)
236 const char *reg_name = arch_register_get_name(reg);
239 be_emit_char(reg_name[1]);
243 static void emit_16bit_register(const arch_register_t *reg)
245 const char *reg_name = ia32_get_mapped_reg_name(isa->regs_16bit, reg);
248 be_emit_string(reg_name);
252 * emit a register, possible shortened by a mode
254 * @param reg the register
255 * @param mode the mode of the register or NULL for full register
257 static void emit_register(const arch_register_t *reg, const ir_mode *mode)
259 const char *reg_name;
262 int size = get_mode_size_bits(mode);
264 case 8: emit_8bit_register(reg); return;
265 case 16: emit_16bit_register(reg); return;
267 assert(mode_is_float(mode) || size == 32);
270 reg_name = arch_register_get_name(reg);
273 be_emit_string(reg_name);
276 void ia32_emit_source_register(const ir_node *node, int pos)
278 const arch_register_t *reg = get_in_reg(node, pos);
280 emit_register(reg, NULL);
283 static void ia32_emit_entity(ir_entity *entity, int no_pic_adjust)
285 set_entity_backend_marked(entity, 1);
286 be_gas_emit_entity(entity);
288 if (get_entity_owner(entity) == get_tls_type()) {
289 if (get_entity_visibility(entity) == visibility_external_allocated) {
290 be_emit_cstring("@INDNTPOFF");
292 be_emit_cstring("@NTPOFF");
296 if (do_pic && !no_pic_adjust) {
298 be_emit_string(pic_base_label);
302 static void emit_ia32_Immediate_no_prefix(const ir_node *node)
304 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(node);
306 if (attr->symconst != NULL) {
309 ia32_emit_entity(attr->symconst, attr->no_pic_adjust);
311 if (attr->symconst == NULL || attr->offset != 0) {
312 if (attr->symconst != NULL) {
313 be_emit_irprintf("%+d", attr->offset);
315 be_emit_irprintf("0x%X", attr->offset);
320 static void emit_ia32_Immediate(const ir_node *node)
323 emit_ia32_Immediate_no_prefix(node);
326 void ia32_emit_8bit_source_register_or_immediate(const ir_node *node, int pos)
328 const arch_register_t *reg;
329 const ir_node *in = get_irn_n(node, pos);
330 if (is_ia32_Immediate(in)) {
331 emit_ia32_Immediate(in);
335 reg = get_in_reg(node, pos);
336 emit_8bit_register(reg);
339 void ia32_emit_8bit_high_source_register(const ir_node *node, int pos)
341 const arch_register_t *reg = get_in_reg(node, pos);
342 emit_8bit_register_high(reg);
345 void ia32_emit_16bit_source_register_or_immediate(const ir_node *node, int pos)
347 const arch_register_t *reg;
348 const ir_node *in = get_irn_n(node, pos);
349 if (is_ia32_Immediate(in)) {
350 emit_ia32_Immediate(in);
354 reg = get_in_reg(node, pos);
355 emit_16bit_register(reg);
358 void ia32_emit_dest_register(const ir_node *node, int pos)
360 const arch_register_t *reg = get_out_reg(node, pos);
362 emit_register(reg, NULL);
365 void ia32_emit_dest_register_size(const ir_node *node, int pos)
367 const arch_register_t *reg = get_out_reg(node, pos);
369 emit_register(reg, get_ia32_ls_mode(node));
372 void ia32_emit_8bit_dest_register(const ir_node *node, int pos)
374 const arch_register_t *reg = get_out_reg(node, pos);
376 emit_register(reg, mode_Bu);
379 void ia32_emit_x87_register(const ir_node *node, int pos)
381 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
385 be_emit_string(attr->x87[pos]->name);
388 static void ia32_emit_mode_suffix_mode(const ir_mode *mode)
390 assert(mode_is_int(mode) || mode_is_reference(mode));
391 switch (get_mode_size_bits(mode)) {
392 case 8: be_emit_char('b'); return;
393 case 16: be_emit_char('w'); return;
394 case 32: be_emit_char('l'); return;
395 /* gas docu says q is the suffix but gcc, objdump and icc use ll
397 case 64: be_emit_cstring("ll"); return;
399 panic("Can't output mode_suffix for %+F", mode);
402 void ia32_emit_mode_suffix(const ir_node *node)
404 ir_mode *mode = get_ia32_ls_mode(node);
408 ia32_emit_mode_suffix_mode(mode);
411 void ia32_emit_x87_mode_suffix(const ir_node *node)
415 /* we only need to emit the mode on address mode */
416 if (get_ia32_op_type(node) == ia32_Normal)
419 mode = get_ia32_ls_mode(node);
420 assert(mode != NULL);
422 if (mode_is_float(mode)) {
423 switch (get_mode_size_bits(mode)) {
424 case 32: be_emit_char('s'); return;
425 case 64: be_emit_char('l'); return;
427 case 96: be_emit_char('t'); return;
430 assert(mode_is_int(mode));
431 switch (get_mode_size_bits(mode)) {
432 case 16: be_emit_char('s'); return;
433 case 32: be_emit_char('l'); return;
434 /* gas docu says q is the suffix but gcc, objdump and icc use ll
436 case 64: be_emit_cstring("ll"); return;
439 panic("Can't output mode_suffix for %+F", mode);
442 static char get_xmm_mode_suffix(ir_mode *mode)
444 assert(mode_is_float(mode));
445 switch(get_mode_size_bits(mode)) {
448 default: panic("Invalid XMM mode");
452 void ia32_emit_xmm_mode_suffix(const ir_node *node)
454 ir_mode *mode = get_ia32_ls_mode(node);
455 assert(mode != NULL);
457 be_emit_char(get_xmm_mode_suffix(mode));
460 void ia32_emit_xmm_mode_suffix_s(const ir_node *node)
462 ir_mode *mode = get_ia32_ls_mode(node);
463 assert(mode != NULL);
464 be_emit_char(get_xmm_mode_suffix(mode));
467 void ia32_emit_extend_suffix(const ir_node *node)
469 ir_mode *mode = get_ia32_ls_mode(node);
470 if (get_mode_size_bits(mode) == 32)
472 be_emit_char(mode_is_signed(mode) ? 's' : 'z');
473 ia32_emit_mode_suffix_mode(mode);
476 void ia32_emit_source_register_or_immediate(const ir_node *node, int pos)
478 ir_node *in = get_irn_n(node, pos);
479 if (is_ia32_Immediate(in)) {
480 emit_ia32_Immediate(in);
482 const ir_mode *mode = get_ia32_ls_mode(node);
483 const arch_register_t *reg = get_in_reg(node, pos);
484 emit_register(reg, mode);
489 * Returns the target block for a control flow node.
491 static ir_node *get_cfop_target_block(const ir_node *irn)
493 assert(get_irn_mode(irn) == mode_X);
494 return get_irn_link(irn);
498 * Emits a block label for the given block.
500 static void ia32_emit_block_name(const ir_node *block)
502 if (has_Block_entity(block)) {
503 ir_entity *entity = get_Block_entity(block);
504 be_gas_emit_entity(entity);
506 be_emit_cstring(BLOCK_PREFIX);
507 be_emit_irprintf("%ld", get_irn_node_nr(block));
512 * Emits the target label for a control flow node.
514 static void ia32_emit_cfop_target(const ir_node *node)
516 ir_node *block = get_cfop_target_block(node);
517 ia32_emit_block_name(block);
521 * positive conditions for signed compares
523 static const char *const cmp2condition_s[] = {
524 NULL, /* always false */
531 NULL /* always true */
535 * positive conditions for unsigned compares
537 static const char *const cmp2condition_u[] = {
538 NULL, /* always false */
545 NULL /* always true */
549 * Emit the suffix for a compare instruction.
551 static void ia32_emit_cmp_suffix(int pnc)
555 if (pnc == ia32_pn_Cmp_parity) {
560 if (pnc & ia32_pn_Cmp_float || pnc & ia32_pn_Cmp_unsigned) {
561 str = cmp2condition_u[pnc & 7];
563 str = cmp2condition_s[pnc & 7];
569 typedef enum ia32_emit_mod_t {
570 EMIT_RESPECT_LS = 1U << 0,
571 EMIT_ALTERNATE_AM = 1U << 1,
573 EMIT_HIGH_REG = 1U << 3,
574 EMIT_LOW_REG = 1U << 4
578 * Emits address mode.
580 void ia32_emit_am(const ir_node *node)
582 ir_entity *ent = get_ia32_am_sc(node);
583 int offs = get_ia32_am_offs_int(node);
584 ir_node *base = get_irn_n(node, n_ia32_base);
585 int has_base = !is_ia32_NoReg_GP(base);
586 ir_node *index = get_irn_n(node, n_ia32_index);
587 int has_index = !is_ia32_NoReg_GP(index);
589 /* just to be sure... */
590 assert(!is_ia32_use_frame(node) || get_ia32_frame_ent(node) != NULL);
594 const ia32_attr_t *attr = get_ia32_attr_const(node);
595 if (is_ia32_am_sc_sign(node))
597 ia32_emit_entity(ent, attr->data.am_sc_no_pic_adjust);
600 /* also handle special case if nothing is set */
601 if (offs != 0 || (ent == NULL && !has_base && !has_index)) {
603 be_emit_irprintf("%+d", offs);
605 be_emit_irprintf("%d", offs);
609 if (has_base || has_index) {
614 const arch_register_t *reg = get_in_reg(node, n_ia32_base);
615 emit_register(reg, NULL);
618 /* emit index + scale */
620 const arch_register_t *reg = get_in_reg(node, n_ia32_index);
623 emit_register(reg, NULL);
625 scale = get_ia32_am_scale(node);
627 be_emit_irprintf(",%d", 1 << scale);
635 * fmt parameter output
636 * ---- ---------------------- ---------------------------------------------
638 * %AM <node> address mode of the node
639 * %AR const arch_register_t* address mode of the node or register
640 * %ASx <node> address mode of the node or source register x
641 * %Dx <node> destination register x
642 * %I <node> immediate of the node
643 * %L <node> control flow target of the node
644 * %M <node> mode suffix of the node
645 * %P int condition code
646 * %R const arch_register_t* register
647 * %Sx <node> source register x
648 * %s const char* string
649 * %u unsigned int unsigned int
650 * %d signed int signed int
653 * # modifier for %ASx, %D and %S uses ls mode of node to alter register width
654 * * modifier does not prefix immediates with $, but AM with *
655 * l modifier for %lu and %ld
656 * + modifier to output high 8bit register (ah, bh)
658 static void ia32_emitf(const ir_node *node, const char *fmt, ...)
664 const char *start = fmt;
665 ia32_emit_mod_t mod = 0;
667 while (*fmt != '%' && *fmt != '\n' && *fmt != '\0')
670 be_emit_string_len(start, fmt - start);
674 be_emit_finish_line_gas(node);
687 case '*': mod |= EMIT_ALTERNATE_AM; break;
688 case '#': mod |= EMIT_RESPECT_LS; break;
689 case 'l': mod |= EMIT_LONG; break;
690 case '+': mod |= EMIT_HIGH_REG; break;
691 case '-': mod |= EMIT_LOW_REG; break;
707 if (mod & EMIT_ALTERNATE_AM)
714 const arch_register_t *reg = va_arg(ap, const arch_register_t*);
715 if (mod & EMIT_ALTERNATE_AM)
717 if (get_ia32_op_type(node) == ia32_AddrModeS) {
720 emit_register(reg, NULL);
726 if (get_ia32_op_type(node) == ia32_AddrModeS) {
727 if (mod & EMIT_ALTERNATE_AM)
732 assert(get_ia32_op_type(node) == ia32_Normal);
737 default: goto unknown;
744 const arch_register_t *reg;
746 if (*fmt < '0' || '9' <= *fmt)
750 reg = get_out_reg(node, pos);
751 emit_register(reg, mod & EMIT_RESPECT_LS ? get_ia32_ls_mode(node) : NULL);
756 if (!(mod & EMIT_ALTERNATE_AM))
758 emit_ia32_Immediate_no_prefix(node);
762 ia32_emit_cfop_target(node);
766 ia32_emit_mode_suffix_mode(get_ia32_ls_mode(node));
771 int pnc = va_arg(ap, int);
772 ia32_emit_cmp_suffix(pnc);
777 const arch_register_t *reg = va_arg(ap, const arch_register_t*);
778 if (mod & EMIT_HIGH_REG) {
779 emit_8bit_register_high(reg);
780 } else if (mod & EMIT_LOW_REG) {
781 emit_8bit_register(reg);
783 emit_register(reg, mod & EMIT_RESPECT_LS ? get_ia32_ls_mode(node) : NULL);
793 if (*fmt < '0' || '9' <= *fmt)
797 in = get_irn_n(node, pos);
798 if (is_ia32_Immediate(in)) {
799 if (!(mod & EMIT_ALTERNATE_AM))
801 emit_ia32_Immediate_no_prefix(in);
803 const arch_register_t *reg;
805 if (mod & EMIT_ALTERNATE_AM)
807 reg = get_in_reg(node, pos);
808 emit_register(reg, mod & EMIT_RESPECT_LS ? get_ia32_ls_mode(node) : NULL);
814 const char *str = va_arg(ap, const char*);
820 if (mod & EMIT_LONG) {
821 unsigned long num = va_arg(ap, unsigned long);
822 be_emit_irprintf("%lu", num);
824 unsigned num = va_arg(ap, unsigned);
825 be_emit_irprintf("%u", num);
830 if (mod & EMIT_LONG) {
831 long num = va_arg(ap, long);
832 be_emit_irprintf("%ld", num);
834 int num = va_arg(ap, int);
835 be_emit_irprintf("%d", num);
841 panic("unknown format conversion in ia32_emitf()");
849 * Emits registers and/or address mode of a binary operation.
851 void ia32_emit_binop(const ir_node *node)
853 if (is_ia32_Immediate(get_irn_n(node, n_ia32_binary_right))) {
854 ia32_emitf(node, "%#S4, %#AS3");
856 ia32_emitf(node, "%#AS4, %#S3");
861 * Emits registers and/or address mode of a binary operation.
863 void ia32_emit_x87_binop(const ir_node *node)
865 switch(get_ia32_op_type(node)) {
868 const ia32_x87_attr_t *x87_attr = get_ia32_x87_attr_const(node);
869 const arch_register_t *in1 = x87_attr->x87[0];
870 const arch_register_t *in = x87_attr->x87[1];
871 const arch_register_t *out = x87_attr->x87[2];
875 } else if (out == in) {
880 be_emit_string(arch_register_get_name(in));
881 be_emit_cstring(", %");
882 be_emit_string(arch_register_get_name(out));
890 assert(0 && "unsupported op type");
895 * Emits registers and/or address mode of a unary operation.
897 void ia32_emit_unop(const ir_node *node, int pos)
901 ia32_emitf(node, fmt);
904 static void emit_ia32_IMul(const ir_node *node)
906 ir_node *left = get_irn_n(node, n_ia32_IMul_left);
907 const arch_register_t *out_reg = get_out_reg(node, pn_ia32_IMul_res);
909 /* do we need the 3-address form? */
910 if (is_ia32_NoReg_GP(left) ||
911 get_in_reg(node, n_ia32_IMul_left) != out_reg) {
912 ia32_emitf(node, "\timul%M %#S4, %#AS3, %#D0\n");
914 ia32_emitf(node, "\timul%M %#AS4, %#S3\n");
919 * walks up a tree of copies/perms/spills/reloads to find the original value
920 * that is moved around
922 static ir_node *find_original_value(ir_node *node)
924 if (irn_visited(node))
927 mark_irn_visited(node);
928 if (be_is_Copy(node)) {
929 return find_original_value(be_get_Copy_op(node));
930 } else if (be_is_CopyKeep(node)) {
931 return find_original_value(be_get_CopyKeep_op(node));
932 } else if (is_Proj(node)) {
933 ir_node *pred = get_Proj_pred(node);
934 if (be_is_Perm(pred)) {
935 return find_original_value(get_irn_n(pred, get_Proj_proj(node)));
936 } else if (be_is_MemPerm(pred)) {
937 return find_original_value(get_irn_n(pred, get_Proj_proj(node) + 1));
938 } else if (is_ia32_Load(pred)) {
939 return find_original_value(get_irn_n(pred, n_ia32_Load_mem));
943 } else if (is_ia32_Store(node)) {
944 return find_original_value(get_irn_n(node, n_ia32_Store_val));
945 } else if (is_Phi(node)) {
947 arity = get_irn_arity(node);
948 for (i = 0; i < arity; ++i) {
949 ir_node *in = get_irn_n(node, i);
950 ir_node *res = find_original_value(in);
961 static int determine_final_pnc(const ir_node *node, int flags_pos,
964 ir_node *flags = get_irn_n(node, flags_pos);
965 const ia32_attr_t *flags_attr;
966 flags = skip_Proj(flags);
968 if (is_ia32_Sahf(flags)) {
969 ir_node *cmp = get_irn_n(flags, n_ia32_Sahf_val);
970 if (!(is_ia32_FucomFnstsw(cmp) || is_ia32_FucompFnstsw(cmp)
971 || is_ia32_FucomppFnstsw(cmp) || is_ia32_FtstFnstsw(cmp))) {
972 inc_irg_visited(current_ir_graph);
973 cmp = find_original_value(cmp);
975 assert(is_ia32_FucomFnstsw(cmp) || is_ia32_FucompFnstsw(cmp)
976 || is_ia32_FucomppFnstsw(cmp) || is_ia32_FtstFnstsw(cmp));
979 flags_attr = get_ia32_attr_const(cmp);
980 if (flags_attr->data.ins_permuted)
981 pnc = get_mirrored_pnc(pnc);
982 pnc |= ia32_pn_Cmp_float;
983 } else if (is_ia32_Ucomi(flags) || is_ia32_Fucomi(flags)
984 || is_ia32_Fucompi(flags)) {
985 flags_attr = get_ia32_attr_const(flags);
987 if (flags_attr->data.ins_permuted)
988 pnc = get_mirrored_pnc(pnc);
989 pnc |= ia32_pn_Cmp_float;
991 flags_attr = get_ia32_attr_const(flags);
993 if (flags_attr->data.ins_permuted)
994 pnc = get_mirrored_pnc(pnc);
995 if (flags_attr->data.cmp_unsigned)
996 pnc |= ia32_pn_Cmp_unsigned;
1002 static pn_Cmp ia32_get_negated_pnc(pn_Cmp pnc)
1004 ir_mode *mode = pnc & ia32_pn_Cmp_float ? mode_F : mode_Iu;
1005 return get_negated_pnc(pnc, mode);
1008 void ia32_emit_cmp_suffix_node(const ir_node *node,
1011 const ia32_attr_t *attr = get_ia32_attr_const(node);
1013 pn_Cmp pnc = get_ia32_condcode(node);
1015 pnc = determine_final_pnc(node, flags_pos, pnc);
1016 if (attr->data.ins_permuted)
1017 pnc = ia32_get_negated_pnc(pnc);
1019 ia32_emit_cmp_suffix(pnc);
1023 * Emits an exception label for a given node.
1025 static void ia32_emit_exc_label(const ir_node *node)
1027 be_emit_string(be_gas_insn_label_prefix());
1028 be_emit_irprintf("%lu", get_ia32_exc_label_id(node));
1032 * Returns the Proj with projection number proj and NOT mode_M
1034 static ir_node *get_proj(const ir_node *node, long proj)
1036 const ir_edge_t *edge;
1039 assert(get_irn_mode(node) == mode_T && "expected mode_T node");
1041 foreach_out_edge(node, edge) {
1042 src = get_edge_src_irn(edge);
1044 assert(is_Proj(src) && "Proj expected");
1045 if (get_irn_mode(src) == mode_M)
1048 if (get_Proj_proj(src) == proj)
1054 static int can_be_fallthrough(const ir_node *node)
1056 ir_node *target_block = get_cfop_target_block(node);
1057 ir_node *block = get_nodes_block(node);
1058 return get_prev_block_sched(target_block) == block;
1062 * Emits the jump sequence for a conditional jump (cmp + jmp_true + jmp_false)
1064 static void emit_ia32_Jcc(const ir_node *node)
1066 int need_parity_label = 0;
1067 const ir_node *proj_true;
1068 const ir_node *proj_false;
1069 const ir_node *block;
1070 pn_Cmp pnc = get_ia32_condcode(node);
1072 pnc = determine_final_pnc(node, 0, pnc);
1074 /* get both Projs */
1075 proj_true = get_proj(node, pn_ia32_Jcc_true);
1076 assert(proj_true && "Jcc without true Proj");
1078 proj_false = get_proj(node, pn_ia32_Jcc_false);
1079 assert(proj_false && "Jcc without false Proj");
1081 block = get_nodes_block(node);
1083 if (can_be_fallthrough(proj_true)) {
1084 /* exchange both proj's so the second one can be omitted */
1085 const ir_node *t = proj_true;
1087 proj_true = proj_false;
1089 pnc = ia32_get_negated_pnc(pnc);
1092 if (pnc & ia32_pn_Cmp_float) {
1093 /* Some floating point comparisons require a test of the parity flag,
1094 * which indicates that the result is unordered */
1095 switch (pnc & 0x0f) {
1097 ia32_emitf(proj_true, "\tjp %L\n");
1102 ia32_emitf(proj_true, "\tjnp %L\n");
1108 /* we need a local label if the false proj is a fallthrough
1109 * as the falseblock might have no label emitted then */
1110 if (can_be_fallthrough(proj_false)) {
1111 need_parity_label = 1;
1112 ia32_emitf(proj_false, "\tjp 1f\n");
1114 ia32_emitf(proj_false, "\tjp %L\n");
1121 ia32_emitf(proj_true, "\tjp %L\n");
1129 ia32_emitf(proj_true, "\tj%P %L\n", pnc);
1132 if (need_parity_label) {
1133 ia32_emitf(NULL, "1:\n");
1136 /* the second Proj might be a fallthrough */
1137 if (can_be_fallthrough(proj_false)) {
1138 ia32_emitf(proj_false, "\t/* fallthrough to %L */\n");
1140 ia32_emitf(proj_false, "\tjmp %L\n");
1145 * Emits an ia32 Setcc. This is mostly easy but some floating point compares
1148 static void emit_ia32_Setcc(const ir_node *node)
1150 const arch_register_t *dreg = get_out_reg(node, pn_ia32_Setcc_res);
1152 pn_Cmp pnc = get_ia32_condcode(node);
1153 pnc = determine_final_pnc(node, n_ia32_Setcc_eflags, pnc);
1154 if (pnc & ia32_pn_Cmp_float) {
1155 switch (pnc & 0x0f) {
1157 ia32_emitf(node, "\tsetp %#R\n", dreg);
1161 ia32_emitf(node, "\tsetnp %#R\n", dreg);
1167 ia32_emitf(node, "\tset%P %-R\n", pnc, dreg);
1168 ia32_emitf(node, "\tsetnp %+R\n", dreg);
1169 ia32_emitf(node, "\tandb %+R, %-R\n", dreg, dreg);
1175 ia32_emitf(node, "\tset%P %-R\n", pnc, dreg);
1176 ia32_emitf(node, "\tsetp %+R\n", dreg);
1177 ia32_emitf(node, "\torb %+R, %-R\n", dreg, dreg);
1184 ia32_emitf(node, "\tset%P %#R\n", pnc, dreg);
1187 static void emit_ia32_CMovcc(const ir_node *node)
1189 const ia32_attr_t *attr = get_ia32_attr_const(node);
1190 int ins_permuted = attr->data.ins_permuted;
1191 const arch_register_t *out = arch_irn_get_register(node, pn_ia32_res);
1192 pn_Cmp pnc = get_ia32_condcode(node);
1193 const arch_register_t *in_true;
1194 const arch_register_t *in_false;
1196 pnc = determine_final_pnc(node, n_ia32_CMovcc_eflags, pnc);
1198 in_true = arch_get_irn_register(get_irn_n(node, n_ia32_CMovcc_val_true));
1199 in_false = arch_get_irn_register(get_irn_n(node, n_ia32_CMovcc_val_false));
1201 /* should be same constraint fullfilled? */
1202 if (out == in_false) {
1203 /* yes -> nothing to do */
1204 } else if (out == in_true) {
1205 const arch_register_t *tmp;
1207 assert(get_ia32_op_type(node) == ia32_Normal);
1209 ins_permuted = !ins_permuted;
1216 ia32_emitf(node, "\tmovl %R, %R\n", in_false, out);
1220 pnc = ia32_get_negated_pnc(pnc);
1222 /* TODO: handling of Nans isn't correct yet */
1224 ia32_emitf(node, "\tcmov%P %#AR, %#R\n", pnc, in_true, out);
1227 /*********************************************************
1230 * ___ _ __ ___ _| |_ _ _ _ _ __ ___ _ __ ___
1231 * / _ \ '_ ` _ \| | __| | | | | | '_ ` _ \| '_ \/ __|
1232 * | __/ | | | | | | |_ | | |_| | | | | | | |_) \__ \
1233 * \___|_| |_| |_|_|\__| | |\__,_|_| |_| |_| .__/|___/
1236 *********************************************************/
1238 /* jump table entry (target and corresponding number) */
1239 typedef struct _branch_t {
1244 /* jump table for switch generation */
1245 typedef struct _jmp_tbl_t {
1246 ir_node *defProj; /**< default target */
1247 long min_value; /**< smallest switch case */
1248 long max_value; /**< largest switch case */
1249 long num_branches; /**< number of jumps */
1250 char label[SNPRINTF_BUF_LEN]; /**< label of the jump table */
1251 branch_t *branches; /**< jump array */
1255 * Compare two variables of type branch_t. Used to sort all switch cases
1257 static int ia32_cmp_branch_t(const void *a, const void *b)
1259 branch_t *b1 = (branch_t *)a;
1260 branch_t *b2 = (branch_t *)b;
1262 if (b1->value <= b2->value)
1268 static void generate_jump_table(jmp_tbl_t *tbl, const ir_node *node)
1274 const ir_edge_t *edge;
1276 /* fill the table structure */
1277 get_unique_label(tbl->label, SNPRINTF_BUF_LEN, ".TBL_");
1278 tbl->defProj = NULL;
1279 tbl->num_branches = get_irn_n_edges(node) - 1;
1280 tbl->branches = XMALLOCNZ(branch_t, tbl->num_branches);
1281 tbl->min_value = LONG_MAX;
1282 tbl->max_value = LONG_MIN;
1284 default_pn = get_ia32_condcode(node);
1286 /* go over all proj's and collect them */
1287 foreach_out_edge(node, edge) {
1288 proj = get_edge_src_irn(edge);
1289 assert(is_Proj(proj) && "Only proj allowed at SwitchJmp");
1291 pnc = get_Proj_proj(proj);
1293 /* check for default proj */
1294 if (pnc == default_pn) {
1295 assert(tbl->defProj == NULL && "found two default Projs at SwitchJmp");
1296 tbl->defProj = proj;
1298 tbl->min_value = pnc < tbl->min_value ? pnc : tbl->min_value;
1299 tbl->max_value = pnc > tbl->max_value ? pnc : tbl->max_value;
1301 /* create branch entry */
1302 tbl->branches[i].target = proj;
1303 tbl->branches[i].value = pnc;
1308 assert(i == tbl->num_branches);
1310 /* sort the branches by their number */
1311 qsort(tbl->branches, tbl->num_branches, sizeof(tbl->branches[0]), ia32_cmp_branch_t);
1315 * Emits code for a SwitchJmp (creates a jump table if
1316 * possible otherwise a cmp-jmp cascade). Port from
1319 static void emit_ia32_SwitchJmp(const ir_node *node)
1321 unsigned long interval;
1325 /* fill the table structure */
1326 generate_jump_table(&tbl, node);
1328 /* two-complement's magic make this work without overflow */
1329 interval = tbl.max_value - tbl.min_value;
1331 /* emit the table */
1332 ia32_emitf(node, "\tcmpl $%u, %S0\n", interval);
1333 ia32_emitf(tbl.defProj, "\tja %L\n");
1335 if (tbl.num_branches > 1) {
1337 ia32_emitf(node, "\tjmp *%s(,%S0,4)\n", tbl.label);
1339 be_gas_emit_switch_section(GAS_SECTION_RODATA);
1340 ia32_emitf(NULL, "\t.align 4\n");
1341 ia32_emitf(NULL, "%s:\n", tbl.label);
1343 last_value = tbl.branches[0].value;
1344 for (i = 0; i != tbl.num_branches; ++i) {
1345 while (last_value != tbl.branches[i].value) {
1346 ia32_emitf(tbl.defProj, ".long %L\n");
1349 ia32_emitf(tbl.branches[i].target, ".long %L\n");
1352 be_gas_emit_switch_section(GAS_SECTION_TEXT);
1354 /* one jump is enough */
1355 ia32_emitf(tbl.branches[0].target, "\tjmp %L\n");
1362 * Emits code for a unconditional jump.
1364 static void emit_ia32_Jmp(const ir_node *node)
1368 /* for now, the code works for scheduled and non-schedules blocks */
1369 block = get_nodes_block(node);
1371 /* we have a block schedule */
1372 if (can_be_fallthrough(node)) {
1373 ia32_emitf(node, "\t/* fallthrough to %L */\n");
1375 ia32_emitf(node, "\tjmp %L\n");
1380 * Emit an inline assembler operand.
1382 * @param node the ia32_ASM node
1383 * @param s points to the operand (a %c)
1385 * @return pointer to the first char in s NOT in the current operand
1387 static const char* emit_asm_operand(const ir_node *node, const char *s)
1389 const ia32_attr_t *ia32_attr = get_ia32_attr_const(node);
1390 const ia32_asm_attr_t *attr = CONST_CAST_IA32_ATTR(ia32_asm_attr_t,
1392 const arch_register_t *reg;
1393 const ia32_asm_reg_t *asm_regs = attr->register_map;
1394 const ia32_asm_reg_t *asm_reg;
1395 const char *reg_name;
1404 /* parse modifiers */
1407 ir_fprintf(stderr, "Warning: asm text (%+F) ends with %%\n", node);
1432 "Warning: asm text (%+F) contains unknown modifier '%c' for asm op\n",
1439 sscanf(s, "%d%n", &num, &p);
1441 ir_fprintf(stderr, "Warning: Couldn't parse assembler operand (%+F)\n",
1448 if (num < 0 || ARR_LEN(asm_regs) <= num) {
1450 "Error: Custom assembler references invalid input/output (%+F)\n",
1454 asm_reg = & asm_regs[num];
1455 assert(asm_reg->valid);
1458 if (asm_reg->use_input == 0) {
1459 reg = get_out_reg(node, asm_reg->inout_pos);
1461 ir_node *pred = get_irn_n(node, asm_reg->inout_pos);
1463 /* might be an immediate value */
1464 if (is_ia32_Immediate(pred)) {
1465 emit_ia32_Immediate(pred);
1468 reg = get_in_reg(node, asm_reg->inout_pos);
1472 "Warning: no register assigned for %d asm op (%+F)\n",
1477 if (asm_reg->memory) {
1482 if (modifier != 0) {
1486 reg_name = ia32_get_mapped_reg_name(isa->regs_8bit, reg);
1489 reg_name = ia32_get_mapped_reg_name(isa->regs_8bit_high, reg);
1492 reg_name = ia32_get_mapped_reg_name(isa->regs_16bit, reg);
1495 panic("Invalid asm op modifier");
1497 be_emit_string(reg_name);
1499 emit_register(reg, asm_reg->mode);
1502 if (asm_reg->memory) {
1510 * Emits code for an ASM pseudo op.
1512 static void emit_ia32_Asm(const ir_node *node)
1514 const void *gen_attr = get_irn_generic_attr_const(node);
1515 const ia32_asm_attr_t *attr
1516 = CONST_CAST_IA32_ATTR(ia32_asm_attr_t, gen_attr);
1517 ident *asm_text = attr->asm_text;
1518 const char *s = get_id_str(asm_text);
1520 ia32_emitf(node, "#APP\t\n");
1527 s = emit_asm_operand(node, s);
1533 ia32_emitf(NULL, "\n#NO_APP\n");
1536 /**********************************
1539 * | | ___ _ __ _ _| |_) |
1540 * | | / _ \| '_ \| | | | _ <
1541 * | |___| (_) | |_) | |_| | |_) |
1542 * \_____\___/| .__/ \__, |____/
1545 **********************************/
1548 * Emit movsb/w instructions to make mov count divideable by 4
1550 static void emit_CopyB_prolog(unsigned size)
1553 ia32_emitf(NULL, "\tmovsb\n");
1555 ia32_emitf(NULL, "\tmovsw\n");
1559 * Emit rep movsd instruction for memcopy.
1561 static void emit_ia32_CopyB(const ir_node *node)
1563 unsigned size = get_ia32_copyb_size(node);
1565 emit_CopyB_prolog(size);
1566 ia32_emitf(node, "\trep movsd\n");
1570 * Emits unrolled memcopy.
1572 static void emit_ia32_CopyB_i(const ir_node *node)
1574 unsigned size = get_ia32_copyb_size(node);
1576 emit_CopyB_prolog(size);
1580 ia32_emitf(NULL, "\tmovsd\n");
1586 /***************************
1590 * | | / _ \| '_ \ \ / /
1591 * | |___| (_) | | | \ V /
1592 * \_____\___/|_| |_|\_/
1594 ***************************/
1597 * Emit code for conversions (I, FP), (FP, I) and (FP, FP).
1599 static void emit_ia32_Conv_with_FP(const ir_node *node, const char* conv_f,
1602 ir_mode *ls_mode = get_ia32_ls_mode(node);
1603 int ls_bits = get_mode_size_bits(ls_mode);
1604 const char *conv = ls_bits == 32 ? conv_f : conv_d;
1606 ia32_emitf(node, "\tcvt%s %AS3, %D0\n", conv);
1609 static void emit_ia32_Conv_I2FP(const ir_node *node)
1611 emit_ia32_Conv_with_FP(node, "si2ss", "si2sd");
1614 static void emit_ia32_Conv_FP2I(const ir_node *node)
1616 emit_ia32_Conv_with_FP(node, "ss2si", "sd2si");
1619 static void emit_ia32_Conv_FP2FP(const ir_node *node)
1621 emit_ia32_Conv_with_FP(node, "sd2ss", "ss2sd");
1625 * Emits code for an Int conversion.
1627 static void emit_ia32_Conv_I2I(const ir_node *node)
1629 ir_mode *smaller_mode = get_ia32_ls_mode(node);
1630 int signed_mode = mode_is_signed(smaller_mode);
1631 const char *sign_suffix;
1633 assert(!mode_is_float(smaller_mode));
1635 sign_suffix = signed_mode ? "s" : "z";
1636 ia32_emitf(node, "\tmov%s%Ml %#AS3, %D0\n", sign_suffix);
1642 static void emit_ia32_Call(const ir_node *node)
1644 /* Special case: Call must not have its immediates prefixed by $, instead
1645 * address mode is prefixed by *. */
1646 ia32_emitf(node, "\tcall %*AS3\n");
1650 /*******************************************
1653 * | |__ ___ _ __ ___ __| | ___ ___
1654 * | '_ \ / _ \ '_ \ / _ \ / _` |/ _ \/ __|
1655 * | |_) | __/ | | | (_) | (_| | __/\__ \
1656 * |_.__/ \___|_| |_|\___/ \__,_|\___||___/
1658 *******************************************/
1661 * Emits code to increase stack pointer.
1663 static void emit_be_IncSP(const ir_node *node)
1665 int offs = be_get_IncSP_offset(node);
1671 ia32_emitf(node, "\tsubl $%u, %D0\n", offs);
1673 ia32_emitf(node, "\taddl $%u, %D0\n", -offs);
1677 static inline bool is_unknown_reg(const arch_register_t *reg)
1679 if(reg == &ia32_gp_regs[REG_GP_UKNWN]
1680 || reg == &ia32_xmm_regs[REG_XMM_UKNWN]
1681 || reg == &ia32_vfp_regs[REG_VFP_UKNWN])
1688 * Emits code for Copy/CopyKeep.
1690 static void Copy_emitter(const ir_node *node, const ir_node *op)
1692 const arch_register_t *in = arch_get_irn_register(op);
1693 const arch_register_t *out = arch_get_irn_register(node);
1698 if (is_unknown_reg(in))
1700 /* copies of vf nodes aren't real... */
1701 if (arch_register_get_class(in) == &ia32_reg_classes[CLASS_ia32_vfp])
1704 if (get_irn_mode(node) == mode_E) {
1705 ia32_emitf(node, "\tmovsd %R, %R\n", in, out);
1707 ia32_emitf(node, "\tmovl %R, %R\n", in, out);
1711 static void emit_be_Copy(const ir_node *node)
1713 Copy_emitter(node, be_get_Copy_op(node));
1716 static void emit_be_CopyKeep(const ir_node *node)
1718 Copy_emitter(node, be_get_CopyKeep_op(node));
1722 * Emits code for exchange.
1724 static void emit_be_Perm(const ir_node *node)
1726 const arch_register_t *in0, *in1;
1727 const arch_register_class_t *cls0, *cls1;
1729 in0 = arch_get_irn_register(get_irn_n(node, 0));
1730 in1 = arch_get_irn_register(get_irn_n(node, 1));
1732 cls0 = arch_register_get_class(in0);
1733 cls1 = arch_register_get_class(in1);
1735 assert(cls0 == cls1 && "Register class mismatch at Perm");
1737 if (cls0 == &ia32_reg_classes[CLASS_ia32_gp]) {
1738 ia32_emitf(node, "\txchg %R, %R\n", in1, in0);
1739 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_xmm]) {
1740 ia32_emitf(NULL, "\txorpd %R, %R\n", in1, in0);
1741 ia32_emitf(NULL, "\txorpd %R, %R\n", in0, in1);
1742 ia32_emitf(node, "\txorpd %R, %R\n", in1, in0);
1743 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_vfp]) {
1745 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_st]) {
1748 panic("unexpected register class in be_Perm (%+F)", node);
1753 * Emits code for Constant loading.
1755 static void emit_ia32_Const(const ir_node *node)
1757 ia32_emitf(node, "\tmovl %I, %D0\n");
1761 * Emits code to load the TLS base
1763 static void emit_ia32_LdTls(const ir_node *node)
1765 ia32_emitf(node, "\tmovl %%gs:0, %D0\n");
1768 /* helper function for emit_ia32_Minus64Bit */
1769 static void emit_mov(const ir_node* node, const arch_register_t *src, const arch_register_t *dst)
1771 ia32_emitf(node, "\tmovl %R, %R\n", src, dst);
1774 /* helper function for emit_ia32_Minus64Bit */
1775 static void emit_neg(const ir_node* node, const arch_register_t *reg)
1777 ia32_emitf(node, "\tnegl %R\n", reg);
1780 /* helper function for emit_ia32_Minus64Bit */
1781 static void emit_sbb0(const ir_node* node, const arch_register_t *reg)
1783 ia32_emitf(node, "\tsbbl $0, %R\n", reg);
1786 /* helper function for emit_ia32_Minus64Bit */
1787 static void emit_sbb(const ir_node* node, const arch_register_t *src, const arch_register_t *dst)
1789 ia32_emitf(node, "\tsbbl %R, %R\n", src, dst);
1792 /* helper function for emit_ia32_Minus64Bit */
1793 static void emit_xchg(const ir_node* node, const arch_register_t *src, const arch_register_t *dst)
1795 ia32_emitf(node, "\txchgl %R, %R\n", src, dst);
1798 /* helper function for emit_ia32_Minus64Bit */
1799 static void emit_zero(const ir_node* node, const arch_register_t *reg)
1801 ia32_emitf(node, "\txorl %R, %R\n", reg, reg);
1804 static void emit_ia32_Minus64Bit(const ir_node *node)
1806 const arch_register_t *in_lo = get_in_reg(node, 0);
1807 const arch_register_t *in_hi = get_in_reg(node, 1);
1808 const arch_register_t *out_lo = get_out_reg(node, 0);
1809 const arch_register_t *out_hi = get_out_reg(node, 1);
1811 if (out_lo == in_lo) {
1812 if (out_hi != in_hi) {
1813 /* a -> a, b -> d */
1816 /* a -> a, b -> b */
1819 } else if (out_lo == in_hi) {
1820 if (out_hi == in_lo) {
1821 /* a -> b, b -> a */
1822 emit_xchg(node, in_lo, in_hi);
1825 /* a -> b, b -> d */
1826 emit_mov(node, in_hi, out_hi);
1827 emit_mov(node, in_lo, out_lo);
1831 if (out_hi == in_lo) {
1832 /* a -> c, b -> a */
1833 emit_mov(node, in_lo, out_lo);
1835 } else if (out_hi == in_hi) {
1836 /* a -> c, b -> b */
1837 emit_mov(node, in_lo, out_lo);
1840 /* a -> c, b -> d */
1841 emit_mov(node, in_lo, out_lo);
1847 emit_neg( node, out_hi);
1848 emit_neg( node, out_lo);
1849 emit_sbb0(node, out_hi);
1853 emit_zero(node, out_hi);
1854 emit_neg( node, out_lo);
1855 emit_sbb( node, in_hi, out_hi);
1858 static void emit_ia32_GetEIP(const ir_node *node)
1860 ia32_emitf(node, "\tcall %s\n", pic_base_label);
1861 ia32_emitf(NULL, "%s:\n", pic_base_label);
1862 ia32_emitf(node, "\tpopl %D0\n");
1865 static void emit_ia32_ClimbFrame(const ir_node *node)
1867 const ia32_climbframe_attr_t *attr = get_ia32_climbframe_attr_const(node);
1869 ia32_emitf(node, "\tmovl %S0, %D0\n");
1870 ia32_emitf(node, "\tmovl $%u, %S1\n", attr->count);
1871 ia32_emitf(NULL, BLOCK_PREFIX "%ld:\n", get_irn_node_nr(node));
1872 ia32_emitf(node, "\tmovl (%D0), %D0\n");
1873 ia32_emitf(node, "\tdec %S1\n");
1874 ia32_emitf(node, "\tjnz " BLOCK_PREFIX "%ld\n", get_irn_node_nr(node));
1877 static void emit_be_Return(const ir_node *node)
1879 unsigned pop = be_Return_get_pop(node);
1881 if (pop > 0 || be_Return_get_emit_pop(node)) {
1882 ia32_emitf(node, "\tret $%u\n", pop);
1884 ia32_emitf(node, "\tret\n");
1888 static void emit_Nothing(const ir_node *node)
1894 /***********************************************************************************
1897 * _ __ ___ __ _ _ _ __ | |_ _ __ __ _ _ __ ___ _____ _____ _ __| | __
1898 * | '_ ` _ \ / _` | | '_ \ | _| '__/ _` | '_ ` _ \ / _ \ \ /\ / / _ \| '__| |/ /
1899 * | | | | | | (_| | | | | | | | | | | (_| | | | | | | __/\ V V / (_) | | | <
1900 * |_| |_| |_|\__,_|_|_| |_| |_| |_| \__,_|_| |_| |_|\___| \_/\_/ \___/|_| |_|\_\
1902 ***********************************************************************************/
1905 * Enters the emitter functions for handled nodes into the generic
1906 * pointer of an opcode.
1908 static void ia32_register_emitters(void)
1910 #define IA32_EMIT2(a,b) op_ia32_##a->ops.generic = (op_func)emit_ia32_##b
1911 #define IA32_EMIT(a) IA32_EMIT2(a,a)
1912 #define EMIT(a) op_##a->ops.generic = (op_func)emit_##a
1913 #define IGN(a) op_##a->ops.generic = (op_func)emit_Nothing
1914 #define BE_EMIT(a) op_be_##a->ops.generic = (op_func)emit_be_##a
1915 #define BE_IGN(a) op_be_##a->ops.generic = (op_func)emit_Nothing
1917 /* first clear the generic function pointer for all ops */
1918 clear_irp_opcodes_generic_func();
1920 /* register all emitter functions defined in spec */
1921 ia32_register_spec_emitters();
1923 /* other ia32 emitter functions */
1924 IA32_EMIT2(Conv_I2I8Bit, Conv_I2I);
1929 IA32_EMIT(Conv_FP2FP);
1930 IA32_EMIT(Conv_FP2I);
1931 IA32_EMIT(Conv_I2FP);
1932 IA32_EMIT(Conv_I2I);
1940 IA32_EMIT(Minus64Bit);
1941 IA32_EMIT(SwitchJmp);
1942 IA32_EMIT(ClimbFrame);
1945 /* benode emitter */
1966 typedef void (*emit_func_ptr) (const ir_node *);
1969 * Assign and emit an exception label if the current instruction can fail.
1971 static void ia32_assign_exc_label(ir_node *node)
1973 /* assign a new ID to the instruction */
1974 set_ia32_exc_label_id(node, ++exc_label_id);
1976 ia32_emit_exc_label(node);
1978 be_emit_pad_comment();
1979 be_emit_cstring("/* exception to Block ");
1980 ia32_emit_cfop_target(node);
1981 be_emit_cstring(" */\n");
1982 be_emit_write_line();
1986 * Emits code for a node.
1988 static void ia32_emit_node(ir_node *node)
1990 ir_op *op = get_irn_op(node);
1992 DBG((dbg, LEVEL_1, "emitting code for %+F\n", node));
1994 if (is_ia32_irn(node)) {
1995 if (get_ia32_exc_label(node)) {
1996 /* emit the exception label of this instruction */
1997 ia32_assign_exc_label(node);
1999 if (mark_spill_reload) {
2000 if (is_ia32_is_spill(node)) {
2001 ia32_emitf(NULL, "\txchg %ebx, %ebx /* spill mark */\n");
2003 if (is_ia32_is_reload(node)) {
2004 ia32_emitf(NULL, "\txchg %edx, %edx /* reload mark */\n");
2006 if (is_ia32_is_remat(node)) {
2007 ia32_emitf(NULL, "\txchg %ecx, %ecx /* remat mark */\n");
2011 if (op->ops.generic) {
2012 emit_func_ptr func = (emit_func_ptr) op->ops.generic;
2014 be_dbg_set_dbg_info(get_irn_dbg_info(node));
2019 ir_fprintf(stderr, "Error: No emit handler for node %+F (%+G, graph %+F)\n", node, node, current_ir_graph);
2025 * Emits gas alignment directives
2027 static void ia32_emit_alignment(unsigned align, unsigned skip)
2029 ia32_emitf(NULL, "\t.p2align %u,,%u\n", align, skip);
2033 * Emits gas alignment directives for Labels depended on cpu architecture.
2035 static void ia32_emit_align_label(void)
2037 unsigned align = ia32_cg_config.label_alignment;
2038 unsigned maximum_skip = ia32_cg_config.label_alignment_max_skip;
2039 ia32_emit_alignment(align, maximum_skip);
2043 * Test whether a block should be aligned.
2044 * For cpus in the P4/Athlon class it is useful to align jump labels to
2045 * 16 bytes. However we should only do that if the alignment nops before the
2046 * label aren't executed more often than we have jumps to the label.
2048 static int should_align_block(const ir_node *block)
2050 static const double DELTA = .0001;
2051 ir_exec_freq *exec_freq = cg->birg->exec_freq;
2052 ir_node *prev = get_prev_block_sched(block);
2054 double prev_freq = 0; /**< execfreq of the fallthrough block */
2055 double jmp_freq = 0; /**< execfreq of all non-fallthrough blocks */
2058 if (exec_freq == NULL)
2060 if (ia32_cg_config.label_alignment_factor <= 0)
2063 block_freq = get_block_execfreq(exec_freq, block);
2064 if (block_freq < DELTA)
2067 n_cfgpreds = get_Block_n_cfgpreds(block);
2068 for(i = 0; i < n_cfgpreds; ++i) {
2069 const ir_node *pred = get_Block_cfgpred_block(block, i);
2070 double pred_freq = get_block_execfreq(exec_freq, pred);
2073 prev_freq += pred_freq;
2075 jmp_freq += pred_freq;
2079 if (prev_freq < DELTA && !(jmp_freq < DELTA))
2082 jmp_freq /= prev_freq;
2084 return jmp_freq > ia32_cg_config.label_alignment_factor;
2088 * Emit the block header for a block.
2090 * @param block the block
2091 * @param prev_block the previous block
2093 static void ia32_emit_block_header(ir_node *block)
2095 ir_graph *irg = current_ir_graph;
2096 int need_label = block_needs_label(block);
2098 ir_exec_freq *exec_freq = cg->birg->exec_freq;
2100 if (block == get_irg_end_block(irg))
2103 if (ia32_cg_config.label_alignment > 0) {
2104 /* align the current block if:
2105 * a) if should be aligned due to its execution frequency
2106 * b) there is no fall-through here
2108 if (should_align_block(block)) {
2109 ia32_emit_align_label();
2111 /* if the predecessor block has no fall-through,
2112 we can always align the label. */
2114 int has_fallthrough = 0;
2116 for (i = get_Block_n_cfgpreds(block) - 1; i >= 0; --i) {
2117 ir_node *cfg_pred = get_Block_cfgpred(block, i);
2118 if (can_be_fallthrough(cfg_pred)) {
2119 has_fallthrough = 1;
2124 if (!has_fallthrough)
2125 ia32_emit_align_label();
2130 ia32_emit_block_name(block);
2133 be_emit_pad_comment();
2134 be_emit_cstring(" /* ");
2136 be_emit_cstring("\t/* ");
2137 ia32_emit_block_name(block);
2138 be_emit_cstring(": ");
2141 be_emit_cstring("preds:");
2143 /* emit list of pred blocks in comment */
2144 arity = get_irn_arity(block);
2146 be_emit_cstring(" none");
2148 for (i = 0; i < arity; ++i) {
2149 ir_node *predblock = get_Block_cfgpred_block(block, i);
2150 be_emit_irprintf(" %d", get_irn_node_nr(predblock));
2153 if (exec_freq != NULL) {
2154 be_emit_irprintf(", freq: %f",
2155 get_block_execfreq(exec_freq, block));
2157 be_emit_cstring(" */\n");
2158 be_emit_write_line();
2162 * Walks over the nodes in a block connected by scheduling edges
2163 * and emits code for each node.
2165 static void ia32_gen_block(ir_node *block)
2169 ia32_emit_block_header(block);
2171 /* emit the contents of the block */
2172 be_dbg_set_dbg_info(get_irn_dbg_info(block));
2173 sched_foreach(block, node) {
2174 ia32_emit_node(node);
2178 typedef struct exc_entry {
2179 ir_node *exc_instr; /** The instruction that can issue an exception. */
2180 ir_node *block; /** The block to call then. */
2185 * Sets labels for control flow nodes (jump target).
2186 * Links control predecessors to there destination blocks.
2188 static void ia32_gen_labels(ir_node *block, void *data)
2190 exc_entry **exc_list = data;
2194 for (n = get_Block_n_cfgpreds(block) - 1; n >= 0; --n) {
2195 pred = get_Block_cfgpred(block, n);
2196 set_irn_link(pred, block);
2198 pred = skip_Proj(pred);
2199 if (is_ia32_irn(pred) && get_ia32_exc_label(pred)) {
2204 ARR_APP1(exc_entry, *exc_list, e);
2205 set_irn_link(pred, block);
2211 * Compare two exception_entries.
2213 static int cmp_exc_entry(const void *a, const void *b)
2215 const exc_entry *ea = a;
2216 const exc_entry *eb = b;
2218 if (get_ia32_exc_label_id(ea->exc_instr) < get_ia32_exc_label_id(eb->exc_instr))
2224 * Main driver. Emits the code for one routine.
2226 void ia32_gen_routine(ia32_code_gen_t *ia32_cg, ir_graph *irg)
2228 ir_entity *entity = get_irg_entity(irg);
2229 exc_entry *exc_list = NEW_ARR_F(exc_entry, 0);
2234 do_pic = cg->birg->main_env->options->pic;
2236 ia32_register_emitters();
2238 get_unique_label(pic_base_label, sizeof(pic_base_label), ".PIC_BASE");
2240 be_dbg_method_begin(entity, be_abi_get_stack_layout(cg->birg->abi));
2241 be_gas_emit_function_prolog(entity, ia32_cg_config.function_alignment);
2243 /* we use links to point to target blocks */
2244 ir_reserve_resources(irg, IR_RESOURCE_IRN_LINK);
2245 irg_block_walk_graph(irg, ia32_gen_labels, NULL, &exc_list);
2247 /* initialize next block links */
2248 n = ARR_LEN(cg->blk_sched);
2249 for (i = 0; i < n; ++i) {
2250 ir_node *block = cg->blk_sched[i];
2251 ir_node *prev = i > 0 ? cg->blk_sched[i-1] : NULL;
2253 set_irn_link(block, prev);
2256 for (i = 0; i < n; ++i) {
2257 ir_node *block = cg->blk_sched[i];
2259 ia32_gen_block(block);
2262 be_gas_emit_function_epilog(entity);
2263 be_dbg_method_end();
2265 be_emit_write_line();
2267 ir_free_resources(irg, IR_RESOURCE_IRN_LINK);
2269 /* Sort the exception table using the exception label id's.
2270 Those are ascending with ascending addresses. */
2271 qsort(exc_list, ARR_LEN(exc_list), sizeof(exc_list[0]), cmp_exc_entry);
2275 for (i = 0; i < ARR_LEN(exc_list); ++i) {
2276 be_emit_cstring("\t.long ");
2277 ia32_emit_exc_label(exc_list[i].exc_instr);
2279 be_emit_cstring("\t.long ");
2280 ia32_emit_block_name(exc_list[i].block);
2284 DEL_ARR_F(exc_list);
2287 static const lc_opt_table_entry_t ia32_emitter_options[] = {
2288 LC_OPT_ENT_BOOL("mark_spill_reload", "mark spills and reloads with ud opcodes", &mark_spill_reload),
2292 /* ==== Experimental binary emitter ==== */
2294 static unsigned char reg_gp_map[N_ia32_gp_REGS];
2295 //static unsigned char reg_mmx_map[N_ia32_mmx_REGS];
2296 //static unsigned char reg_sse_map[N_ia32_xmm_REGS];
2297 static unsigned char pnc_map_signed[8];
2298 static unsigned char pnc_map_unsigned[8];
2300 static void build_reg_map(void)
2302 reg_gp_map[REG_EAX] = 0x0;
2303 reg_gp_map[REG_ECX] = 0x1;
2304 reg_gp_map[REG_EDX] = 0x2;
2305 reg_gp_map[REG_EBX] = 0x3;
2306 reg_gp_map[REG_ESP] = 0x4;
2307 reg_gp_map[REG_EBP] = 0x5;
2308 reg_gp_map[REG_ESI] = 0x6;
2309 reg_gp_map[REG_EDI] = 0x7;
2311 pnc_map_signed[pn_Cmp_Eq] = 0x04;
2312 pnc_map_signed[pn_Cmp_Lt] = 0x0C;
2313 pnc_map_signed[pn_Cmp_Le] = 0x0E;
2314 pnc_map_signed[pn_Cmp_Gt] = 0x0F;
2315 pnc_map_signed[pn_Cmp_Ge] = 0x0D;
2316 pnc_map_signed[pn_Cmp_Lg] = 0x05;
2318 pnc_map_unsigned[pn_Cmp_Eq] = 0x04;
2319 pnc_map_unsigned[pn_Cmp_Lt] = 0x02;
2320 pnc_map_unsigned[pn_Cmp_Le] = 0x06;
2321 pnc_map_unsigned[pn_Cmp_Gt] = 0x07;
2322 pnc_map_unsigned[pn_Cmp_Ge] = 0x03;
2323 pnc_map_unsigned[pn_Cmp_Lg] = 0x05;
2326 static unsigned char pnc2cc(int pnc)
2329 if (pnc == ia32_pn_Cmp_parity) {
2331 } else if (pnc & ia32_pn_Cmp_float || pnc & ia32_pn_Cmp_unsigned) {
2332 cc = pnc_map_unsigned[pnc & 0x07];
2334 cc = pnc_map_signed[pnc & 0x07];
2340 /** Sign extension bit values for binops */
2342 UNSIGNED_IMM = 0, /**< unsigned immediate */
2343 SIGNEXT_IMM = 2, /**< sign extended immediate */
2346 /** The mod encoding of the ModR/M */
2348 MOD_IND = 0x00, /**< [reg1] */
2349 MOD_IND_BYTE_OFS = 0x40, /**< [reg1 + byte ofs] */
2350 MOD_IND_WORD_OFS = 0x80, /**< [reg1 + word ofs] */
2351 MOD_REG = 0xC0 /**< reg1 */
2354 /** create R/M encoding for ModR/M */
2355 #define ENC_RM(x) (x)
2356 /** create REG encoding for ModR/M */
2357 #define ENC_REG(x) ((x) << 3)
2359 /** create encoding for a SIB byte */
2360 #define ENC_SIB(scale, index, base) ((scale) << 6 | (index) << 3 | (base))
2362 /* Node: The following routines are supposed to append bytes, words, dwords
2363 to the output stream.
2364 Currently the implementation is stupid in that it still creates output
2365 for an "assembler" in the form of .byte, .long
2366 We will change this when enough infrastructure is there to create complete
2367 machine code in memory/object files */
2369 static void bemit8(const unsigned char byte)
2371 be_emit_irprintf("\t.byte 0x%x\n", byte);
2372 be_emit_write_line();
2375 static void bemit16(const unsigned short u16)
2377 be_emit_irprintf("\t.word 0x%x\n", u16);
2378 be_emit_write_line();
2381 static void bemit32(const unsigned u32)
2383 be_emit_irprintf("\t.long 0x%x\n", u32);
2384 be_emit_write_line();
2388 * Emit address of an entity. If @p is_relative is true then a relative
2389 * offset from behind the address to the entity is created.
2391 static void bemit_entity(ir_entity *entity, bool entity_sign, int offset,
2394 if (entity == NULL) {
2399 /* the final version should remember the position in the bytestream
2400 and patch it with the correct address at linktime... */
2401 be_emit_cstring("\t.long ");
2404 set_entity_backend_marked(entity, 1);
2405 be_gas_emit_entity(entity);
2407 if (get_entity_owner(entity) == get_tls_type()) {
2408 if (get_entity_visibility(entity) == visibility_external_allocated) {
2409 be_emit_cstring("@INDNTPOFF");
2411 be_emit_cstring("@NTPOFF");
2416 be_emit_cstring("-.");
2421 be_emit_irprintf("%+d", offset);
2424 be_emit_write_line();
2427 static void bemit_jmp_destination(const ir_node *dest_block)
2429 be_emit_cstring("\t.long ");
2430 ia32_emit_block_name(dest_block);
2431 be_emit_cstring(" - . - 4\n");
2432 be_emit_write_line();
2435 /* end emit routines, all emitters following here should only use the functions
2438 /** Create a ModR/M byte for src1,src2 registers */
2439 static void bemit_modrr(const arch_register_t *src1,
2440 const arch_register_t *src2)
2442 unsigned char modrm = MOD_REG;
2443 modrm |= ENC_RM(reg_gp_map[src1->index]);
2444 modrm |= ENC_REG(reg_gp_map[src2->index]);
2448 /** Create a ModR/M byte for one register and extension */
2449 static void bemit_modru(const arch_register_t *reg, unsigned ext)
2451 unsigned char modrm = MOD_REG;
2453 modrm |= ENC_RM(reg_gp_map[reg->index]);
2454 modrm |= ENC_REG(ext);
2459 * Calculate the size of an signed immediate in bytes.
2461 * @param offset an offset
2463 static unsigned get_signed_imm_size(int offset)
2465 if (-128 <= offset && offset < 128) {
2467 } else if (-32768 <= offset && offset < 32768) {
2475 * Emit an address mode.
2477 * @param reg content of the reg field: either a register index or an opcode extension
2478 * @param node the node
2480 static void bemit_mod_am(unsigned reg, const ir_node *node)
2482 ir_entity *ent = get_ia32_am_sc(node);
2483 int offs = get_ia32_am_offs_int(node);
2484 ir_node *base = get_irn_n(node, n_ia32_base);
2485 int has_base = !is_ia32_NoReg_GP(base);
2486 ir_node *index = get_irn_n(node, n_ia32_index);
2487 int has_index = !is_ia32_NoReg_GP(index);
2490 unsigned emitoffs = 0;
2491 bool emitsib = false;
2494 /* set the mod part depending on displacement */
2496 modrm |= MOD_IND_WORD_OFS;
2498 } else if (offs == 0) {
2501 } else if (-128 <= offs && offs < 128) {
2502 modrm |= MOD_IND_BYTE_OFS;
2505 modrm |= MOD_IND_WORD_OFS;
2510 const arch_register_t *base_reg = arch_get_irn_register(base);
2511 base_enc = reg_gp_map[base_reg->index];
2513 /* Use the EBP encoding + MOD_IND if NO base register. There is
2514 * always a 32bit offset present in this case. */
2520 /* Determine if we need a SIB byte. */
2522 const arch_register_t *reg_index = arch_get_irn_register(index);
2523 int scale = get_ia32_am_scale(node);
2525 /* R/M set to ESP means SIB in 32bit mode. */
2526 modrm |= ENC_RM(0x04);
2527 sib = ENC_SIB(scale, reg_gp_map[reg_index->index], base_enc);
2529 } else if (base_enc == 0x04) {
2530 /* for the above reason we are forced to emit a SIB when base is ESP.
2531 * Only the base is used, index must be ESP too, which means no index.
2533 modrm |= ENC_RM(0x04);
2534 sib = ENC_SIB(0, 0x04, 0x04);
2537 modrm |= ENC_RM(base_enc);
2540 /* We are forced to emit an 8bit offset as EBP base without offset is a
2541 * special case for SIB without base register. */
2542 if (base_enc == 0x05 && emitoffs == 0) {
2543 modrm |= MOD_IND_BYTE_OFS;
2547 modrm |= ENC_REG(reg);
2553 /* emit displacement */
2554 if (emitoffs == 8) {
2555 bemit8((unsigned) offs);
2556 } else if (emitoffs == 32) {
2557 bemit_entity(ent, is_ia32_am_sc_sign(node), offs, false);
2562 * Emit a binop with a immediate operand.
2564 * @param node the node to emit
2565 * @param opcode_eax the opcode for the op eax, imm variant
2566 * @param opcode the opcode for the reg, imm variant
2567 * @param ruval the opcode extension for opcode
2569 static void bemit_binop_with_imm(
2570 const ir_node *node,
2571 unsigned char opcode_ax,
2572 unsigned char opcode, unsigned char ruval)
2574 /* Use in-reg, because some instructions (cmp, test) have no out-reg. */
2575 const ir_node *op = get_irn_n(node, n_ia32_binary_right);
2576 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(op);
2579 /* Some instructions (test) have no short form with 32bit value + 8bit
2581 if (attr->symconst != NULL || opcode & SIGNEXT_IMM) {
2584 /* check for sign extension */
2585 size = get_signed_imm_size(attr->offset);
2590 bemit8(opcode | SIGNEXT_IMM);
2591 /* cmp has this special mode */
2592 if (get_ia32_op_type(node) == ia32_AddrModeS) {
2593 bemit_mod_am(ruval, node);
2595 const arch_register_t *reg = get_in_reg(node, n_ia32_binary_left);
2596 bemit_modru(reg, ruval);
2598 bemit8((unsigned char)attr->offset);
2602 /* check for eax variant: this variant is shorter for 32bit immediates only */
2603 if (get_ia32_op_type(node) == ia32_AddrModeS) {
2605 bemit_mod_am(ruval, node);
2607 const arch_register_t *reg = get_in_reg(node, n_ia32_binary_left);
2608 if (reg->index == REG_EAX) {
2612 bemit_modru(reg, ruval);
2615 bemit_entity(attr->symconst, attr->sc_sign, attr->offset, false);
2618 panic("invalid imm size?!?");
2624 static void bemit_binop_2(const ir_node *node, unsigned code)
2626 const arch_register_t *out = get_in_reg(node, n_ia32_binary_left);
2628 if (get_ia32_op_type(node) == ia32_Normal) {
2629 const arch_register_t *op2 = get_in_reg(node, n_ia32_binary_right);
2630 bemit_modrr(op2, out);
2632 bemit_mod_am(reg_gp_map[out->index], node);
2639 static void bemit_binop(const ir_node *node, const unsigned char opcodes[4])
2641 ir_node *right = get_irn_n(node, n_ia32_binary_right);
2642 if (is_ia32_Immediate(right)) {
2643 bemit_binop_with_imm(node, opcodes[1], opcodes[2], opcodes[3]);
2645 bemit_binop_2(node, opcodes[0]);
2652 static void bemit_unop(const ir_node *node, unsigned char code, unsigned char ext, int input)
2655 if (get_ia32_op_type(node) == ia32_Normal) {
2656 const arch_register_t *in = get_in_reg(node, input);
2657 bemit_modru(in, ext);
2659 bemit_mod_am(ext, node);
2663 static void bemit_unop_reg(const ir_node *node, unsigned char code, int input)
2665 const arch_register_t *out = get_out_reg(node, 0);
2666 bemit_unop(node, code, reg_gp_map[out->index], input);
2669 static void bemit_unop_mem(const ir_node *node, unsigned char code, unsigned char ext)
2671 unsigned size = get_mode_size_bits(get_ia32_ls_mode(node));
2674 bemit8(size == 8 ? code : code + 1);
2675 bemit_mod_am(ext, node);
2678 static void bemit_immediate(const ir_node *node, bool relative)
2680 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(node);
2681 bemit_entity(attr->symconst, attr->sc_sign, attr->offset, relative);
2684 static void bemit_copy(const ir_node *copy)
2686 const arch_register_t *in = get_in_reg(copy, 0);
2687 const arch_register_t *out = get_out_reg(copy, 0);
2689 if (in == out || is_unknown_reg(in))
2691 /* copies of vf nodes aren't real... */
2692 if (arch_register_get_class(in) == &ia32_reg_classes[CLASS_ia32_vfp])
2695 if (get_irn_mode(copy) == mode_E) {
2698 assert(arch_register_get_class(in) == &ia32_reg_classes[CLASS_ia32_gp]);
2700 bemit_modrr(in, out);
2704 static void bemit_perm(const ir_node *node)
2706 const arch_register_t *in0 = arch_get_irn_register(get_irn_n(node, 0));
2707 const arch_register_t *in1 = arch_get_irn_register(get_irn_n(node, 1));
2708 const arch_register_class_t *cls0 = arch_register_get_class(in0);
2710 assert(cls0 == arch_register_get_class(in1) && "Register class mismatch at Perm");
2712 if (cls0 == &ia32_reg_classes[CLASS_ia32_gp]) {
2713 if (in0->index == REG_EAX) {
2714 bemit8(0x90 + reg_gp_map[in1->index]);
2715 } else if (in1->index == REG_EAX) {
2716 bemit8(0x90 + reg_gp_map[in0->index]);
2719 bemit_modrr(in0, in1);
2721 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_xmm]) {
2722 panic("unimplemented"); // TODO implement
2723 //ia32_emitf(NULL, "\txorpd %R, %R\n", in1, in0);
2724 //ia32_emitf(NULL, "\txorpd %R, %R\n", in0, in1);
2725 //ia32_emitf(node, "\txorpd %R, %R\n", in1, in0);
2726 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_vfp]) {
2728 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_st]) {
2731 panic("unexpected register class in be_Perm (%+F)", node);
2735 static void bemit_xor0(const ir_node *node)
2737 const arch_register_t *out = get_out_reg(node, 0);
2739 bemit_modrr(out, out);
2742 static void bemit_mov_const(const ir_node *node)
2744 const arch_register_t *out = get_out_reg(node, 0);
2745 bemit8(0xB8 + reg_gp_map[out->index]);
2746 bemit_immediate(node, false);
2750 * Creates a function for a Binop with 3 possible encodings.
2752 #define BINOP(op, op0, op1, op2, op2_ext) \
2753 static void bemit_ ## op(const ir_node *node) { \
2754 static const unsigned char op ## _codes[] = {op0, op1, op2, op2_ext}; \
2755 bemit_binop(node, op ## _codes); \
2758 /* insn def eax,imm imm */
2759 BINOP(add, 0x03, 0x05, 0x81, 0)
2760 BINOP(or, 0x0B, 0x0D, 0x81, 1)
2761 BINOP(adc, 0x13, 0x15, 0x81, 2)
2762 BINOP(sbb, 0x1B, 0x1D, 0x81, 3)
2763 BINOP(and, 0x23, 0x25, 0x81, 4)
2764 BINOP(sub, 0x2B, 0x2D, 0x81, 5)
2765 BINOP(xor, 0x33, 0x35, 0x81, 6)
2766 BINOP(test, 0x85, 0xA9, 0xF7, 0)
2768 #define BINOPMEM(op, ext) \
2769 static void bemit_##op(const ir_node *node) \
2772 unsigned size = get_mode_size_bits(get_ia32_ls_mode(node)); \
2775 val = get_irn_n(node, n_ia32_unary_op); \
2776 if (is_ia32_Immediate(val)) { \
2777 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(val); \
2778 int offset = attr->offset; \
2779 if (attr->symconst == NULL && get_signed_imm_size(offset) == 1) { \
2781 bemit_mod_am(ext, node); \
2785 bemit_mod_am(ext, node); \
2789 bemit_entity(attr->symconst, attr->sc_sign, offset, false); \
2793 bemit8(ext << 3 | 1); \
2794 bemit_mod_am(reg_gp_map[get_out_reg(val, 0)->index], node); \
2798 static void bemit_##op##8bit(const ir_node *node) \
2800 ir_node *val = get_irn_n(node, n_ia32_unary_op); \
2801 if (is_ia32_Immediate(val)) { \
2803 bemit_mod_am(ext, node); \
2804 bemit8(get_ia32_immediate_attr_const(val)->offset); \
2807 bemit_mod_am(reg_gp_map[get_out_reg(val, 0)->index], node); \
2819 * Creates a function for an Unop with code /ext encoding.
2821 #define UNOP(op, code, ext, input) \
2822 static void bemit_ ## op(const ir_node *node) { \
2823 bemit_unop(node, code, ext, input); \
2826 UNOP(not, 0xF7, 2, n_ia32_Not_val)
2827 UNOP(neg, 0xF7, 3, n_ia32_Neg_val)
2828 UNOP(mul, 0xF7, 4, n_ia32_Mul_right)
2829 UNOP(imul1op, 0xF7, 5, n_ia32_IMul1OP_right)
2830 UNOP(div, 0xF7, 6, n_ia32_Div_divisor)
2831 UNOP(idiv, 0xF7, 7, n_ia32_IDiv_divisor)
2833 /* TODO: am support for IJmp */
2834 UNOP(ijmp, 0xFF, 4, n_ia32_IJmp_target)
2836 #define SHIFT(op, ext) \
2837 static void bemit_##op(const ir_node *node) \
2839 const arch_register_t *out = get_out_reg(node, 0); \
2840 ir_node *count = get_irn_n(node, 1); \
2841 if (is_ia32_Immediate(count)) { \
2842 int offset = get_ia32_immediate_attr_const(count)->offset; \
2843 if (offset == 1) { \
2845 bemit_modru(out, ext); \
2848 bemit_modru(out, ext); \
2853 bemit_modru(out, ext); \
2857 static void bemit_##op##mem(const ir_node *node) \
2860 unsigned size = get_mode_size_bits(get_ia32_ls_mode(node)); \
2863 count = get_irn_n(node, 1); \
2864 if (is_ia32_Immediate(count)) { \
2865 int offset = get_ia32_immediate_attr_const(count)->offset; \
2866 if (offset == 1) { \
2867 bemit8(size == 8 ? 0xD0 : 0xD1); \
2868 bemit_mod_am(ext, node); \
2870 bemit8(size == 8 ? 0xC0 : 0xC1); \
2871 bemit_mod_am(ext, node); \
2875 bemit8(size == 8 ? 0xD2 : 0xD3); \
2876 bemit_mod_am(ext, node); \
2886 static void bemit_shld(const ir_node *node)
2888 const arch_register_t *in = get_in_reg(node, n_ia32_ShlD_val_low);
2889 const arch_register_t *out = get_out_reg(node, pn_ia32_ShlD_res);
2890 ir_node *count = get_irn_n(node, n_ia32_ShlD_count);
2892 if (is_ia32_Immediate(count)) {
2894 bemit_modrr(out, in);
2895 bemit8(get_ia32_immediate_attr_const(count)->offset);
2898 bemit_modrr(out, in);
2902 static void bemit_shrd(const ir_node *node)
2904 const arch_register_t *in = get_in_reg(node, n_ia32_ShrD_val_low);
2905 const arch_register_t *out = get_out_reg(node, pn_ia32_ShrD_res);
2906 ir_node *count = get_irn_n(node, n_ia32_ShrD_count);
2908 if (is_ia32_Immediate(count)) {
2910 bemit_modrr(out, in);
2911 bemit8(get_ia32_immediate_attr_const(count)->offset);
2914 bemit_modrr(out, in);
2918 static void bemit_cmovcc(const ir_node *node)
2920 const ia32_attr_t *attr = get_ia32_attr_const(node);
2921 int ins_permuted = attr->data.ins_permuted;
2922 const arch_register_t *out = arch_irn_get_register(node, pn_ia32_res);
2923 pn_Cmp pnc = get_ia32_condcode(node);
2924 const arch_register_t *in_true;
2925 const arch_register_t *in_false;
2927 pnc = determine_final_pnc(node, n_ia32_CMovcc_eflags, pnc);
2929 in_true = arch_get_irn_register(get_irn_n(node, n_ia32_CMovcc_val_true));
2930 in_false = arch_get_irn_register(get_irn_n(node, n_ia32_CMovcc_val_false));
2932 /* should be same constraint fullfilled? */
2933 if (out == in_false) {
2934 /* yes -> nothing to do */
2935 } else if (out == in_true) {
2936 assert(get_ia32_op_type(node) == ia32_Normal);
2937 ins_permuted = !ins_permuted;
2941 bemit8(0x8B); // mov %in_false, %out
2942 bemit_modrr(in_false, out);
2946 pnc = ia32_get_negated_pnc(pnc);
2948 /* TODO: handling of Nans isn't correct yet */
2951 bemit8(0x40 + pnc2cc(pnc));
2952 if (get_ia32_op_type(node) == ia32_Normal) {
2953 bemit_modrr(in_true, out);
2955 bemit_mod_am(reg_gp_map[out->index], node);
2959 static void bemit_cmp(const ir_node *node)
2961 unsigned ls_size = get_mode_size_bits(get_ia32_ls_mode(node));
2967 right = get_irn_n(node, n_ia32_binary_right);
2968 if (is_ia32_Immediate(right)) {
2969 /* Use in-reg, because some instructions (cmp, test) have no out-reg. */
2970 const ir_node *op = get_irn_n(node, n_ia32_binary_right);
2971 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(op);
2974 if (attr->symconst != NULL) {
2977 /* check for sign extension */
2978 size = get_signed_imm_size(attr->offset);
2983 bemit8(0x81 | SIGNEXT_IMM);
2984 /* cmp has this special mode */
2985 if (get_ia32_op_type(node) == ia32_AddrModeS) {
2986 bemit_mod_am(7, node);
2988 const arch_register_t *reg = get_in_reg(node, n_ia32_binary_left);
2989 bemit_modru(reg, 7);
2991 bemit8((unsigned char)attr->offset);
2995 /* check for eax variant: this variant is shorter for 32bit immediates only */
2996 if (get_ia32_op_type(node) == ia32_AddrModeS) {
2998 bemit_mod_am(7, node);
3000 const arch_register_t *reg = get_in_reg(node, n_ia32_binary_left);
3001 if (reg->index == REG_EAX) {
3005 bemit_modru(reg, 7);
3008 if (ls_size == 16) {
3009 bemit16(attr->offset);
3011 bemit_entity(attr->symconst, attr->sc_sign, attr->offset, false);
3015 panic("invalid imm size?!?");
3017 const arch_register_t *out = get_in_reg(node, n_ia32_binary_left);
3019 if (get_ia32_op_type(node) == ia32_Normal) {
3020 const arch_register_t *op2 = get_in_reg(node, n_ia32_binary_right);
3021 bemit_modrr(op2, out);
3023 bemit_mod_am(reg_gp_map[out->index], node);
3028 static void bemit_cmp8bit(const ir_node *node)
3030 ir_node *right = get_irn_n(node, n_ia32_binary_right);
3031 if (is_ia32_Immediate(right)) {
3032 if (get_ia32_op_type(node) == ia32_Normal) {
3033 const arch_register_t *out = get_in_reg(node, n_ia32_Cmp_left);
3034 if (out->index == REG_EAX) {
3038 bemit_modru(out, 7);
3042 bemit_mod_am(7, node);
3044 bemit8(get_ia32_immediate_attr_const(right)->offset);
3046 const arch_register_t *out = get_in_reg(node, n_ia32_Cmp_left);
3048 if (get_ia32_op_type(node) == ia32_Normal) {
3049 const arch_register_t *in = get_in_reg(node, n_ia32_Cmp_right);
3050 bemit_modrr(out, in);
3052 bemit_mod_am(reg_gp_map[out->index], node);
3057 static void bemit_test8bit(const ir_node *node)
3059 ir_node *right = get_irn_n(node, n_ia32_Test8Bit_right);
3060 if (is_ia32_Immediate(right)) {
3061 if (get_ia32_op_type(node) == ia32_Normal) {
3062 const arch_register_t *out = get_in_reg(node, n_ia32_Test8Bit_left);
3063 if (out->index == REG_EAX) {
3067 bemit_modru(out, 0);
3071 bemit_mod_am(0, node);
3073 bemit8(get_ia32_immediate_attr_const(right)->offset);
3075 const arch_register_t *out = get_in_reg(node, n_ia32_Test8Bit_left);
3077 if (get_ia32_op_type(node) == ia32_Normal) {
3078 const arch_register_t *in = get_in_reg(node, n_ia32_Test8Bit_right);
3079 bemit_modrr(out, in);
3081 bemit_mod_am(reg_gp_map[out->index], node);
3086 static void bemit_imul(const ir_node *node)
3088 ir_node *right = get_irn_n(node, n_ia32_IMul_right);
3089 /* Do we need the immediate form? */
3090 if (is_ia32_Immediate(right)) {
3091 int imm = get_ia32_immediate_attr_const(right)->offset;
3092 if (get_signed_imm_size(imm) == 1) {
3093 bemit_unop_reg(node, 0x6B, n_ia32_IMul_left);
3096 bemit_unop_reg(node, 0x69, n_ia32_IMul_left);
3101 bemit_unop_reg(node, 0xAF, n_ia32_IMul_right);
3105 static void bemit_dec(const ir_node *node)
3107 const arch_register_t *out = get_out_reg(node, pn_ia32_Dec_res);
3108 bemit8(0x48 + reg_gp_map[out->index]);
3111 static void bemit_inc(const ir_node *node)
3113 const arch_register_t *out = get_out_reg(node, pn_ia32_Inc_res);
3114 bemit8(0x40 + reg_gp_map[out->index]);
3117 #define UNOPMEM(op, code, ext) \
3118 static void bemit_##op(const ir_node *node) \
3120 bemit_unop_mem(node, code, ext); \
3123 UNOPMEM(notmem, 0xF6, 2)
3124 UNOPMEM(negmem, 0xF6, 3)
3125 UNOPMEM(incmem, 0xFE, 0)
3126 UNOPMEM(decmem, 0xFE, 1)
3128 static void bemit_setcc(const ir_node *node)
3134 pnc = get_ia32_condcode(node);
3135 pnc = determine_final_pnc(node, n_ia32_Setcc_eflags, pnc);
3137 /* TODO: all the special casing for float compares is missing */
3138 if (pnc & ia32_pn_Cmp_float)
3139 panic("binary setcc from float compare not implemented yet");
3141 bemit8(0x90 + pnc2cc(pnc));
3142 bemit_modru(get_out_reg(node, pn_ia32_Setcc_res), 2);
3145 static void bemit_ldtls(const ir_node *node)
3147 const arch_register_t *out = get_out_reg(node, 0);
3149 bemit8(0x65); // gs:
3150 if (out->index == REG_EAX) {
3151 bemit8(0xA1); // movl 0, %eax
3153 bemit8(0x8B); // movl 0, %reg
3154 bemit8(MOD_IND | ENC_REG(reg_gp_map[out->index]) | ENC_RM(0x05));
3162 static void bemit_lea(const ir_node *node)
3164 const arch_register_t *out = get_out_reg(node, 0);
3166 bemit_mod_am(reg_gp_map[out->index], node);
3169 /* helper function for bemit_minus64bit */
3170 static void bemit_helper_mov(const arch_register_t *src, const arch_register_t *dst)
3172 bemit8(0x8B); // movl %src, %dst
3173 bemit_modrr(src, dst);
3176 /* helper function for bemit_minus64bit */
3177 static void bemit_helper_neg(const arch_register_t *reg)
3179 bemit8(0xF7); // negl %reg
3180 bemit_modru(reg, 3);
3183 /* helper function for bemit_minus64bit */
3184 static void bemit_helper_sbb0(const arch_register_t *reg)
3186 bemit8(0x83); // sbbl $0, %reg
3187 bemit_modru(reg, 3);
3191 /* helper function for bemit_minus64bit */
3192 static void bemit_helper_sbb(const arch_register_t *src, const arch_register_t *dst)
3194 bemit8(0x1B); // sbbl %src, %dst
3195 bemit_modrr(src, dst);
3198 /* helper function for bemit_minus64bit */
3199 static void bemit_helper_xchg(const arch_register_t *src, const arch_register_t *dst)
3201 if (src->index == REG_EAX) {
3202 bemit8(0x90 + reg_gp_map[dst->index]); // xchgl %eax, %dst
3203 } else if (dst->index == REG_EAX) {
3204 bemit8(0x90 + reg_gp_map[src->index]); // xchgl %src, %eax
3206 bemit8(0x87); // xchgl %src, %dst
3207 bemit_modrr(src, dst);
3211 /* helper function for bemit_minus64bit */
3212 static void bemit_helper_zero(const arch_register_t *reg)
3214 bemit8(0x33); // xorl %reg, %reg
3215 bemit_modrr(reg, reg);
3218 static void bemit_minus64bit(const ir_node *node)
3220 const arch_register_t *in_lo = get_in_reg(node, 0);
3221 const arch_register_t *in_hi = get_in_reg(node, 1);
3222 const arch_register_t *out_lo = get_out_reg(node, 0);
3223 const arch_register_t *out_hi = get_out_reg(node, 1);
3225 if (out_lo == in_lo) {
3226 if (out_hi != in_hi) {
3227 /* a -> a, b -> d */
3230 /* a -> a, b -> b */
3233 } else if (out_lo == in_hi) {
3234 if (out_hi == in_lo) {
3235 /* a -> b, b -> a */
3236 bemit_helper_xchg(in_lo, in_hi);
3239 /* a -> b, b -> d */
3240 bemit_helper_mov(in_hi, out_hi);
3241 bemit_helper_mov(in_lo, out_lo);
3245 if (out_hi == in_lo) {
3246 /* a -> c, b -> a */
3247 bemit_helper_mov(in_lo, out_lo);
3249 } else if (out_hi == in_hi) {
3250 /* a -> c, b -> b */
3251 bemit_helper_mov(in_lo, out_lo);
3254 /* a -> c, b -> d */
3255 bemit_helper_mov(in_lo, out_lo);
3261 bemit_helper_neg( out_hi);
3262 bemit_helper_neg( out_lo);
3263 bemit_helper_sbb0(out_hi);
3267 bemit_helper_zero(out_hi);
3268 bemit_helper_neg( out_lo);
3269 bemit_helper_sbb( in_hi, out_hi);
3273 * Emit a single opcode.
3275 #define EMIT_SINGLEOP(op, code) \
3276 static void bemit_ ## op(const ir_node *node) { \
3281 //EMIT_SINGLEOP(daa, 0x27)
3282 //EMIT_SINGLEOP(das, 0x2F)
3283 //EMIT_SINGLEOP(aaa, 0x37)
3284 //EMIT_SINGLEOP(aas, 0x3F)
3285 //EMIT_SINGLEOP(nop, 0x90)
3286 EMIT_SINGLEOP(cwtl, 0x98)
3287 EMIT_SINGLEOP(cltd, 0x99)
3288 //EMIT_SINGLEOP(fwait, 0x9B)
3289 EMIT_SINGLEOP(sahf, 0x9E)
3290 //EMIT_SINGLEOP(popf, 0x9D)
3291 EMIT_SINGLEOP(leave, 0xC9)
3292 EMIT_SINGLEOP(int3, 0xCC)
3293 //EMIT_SINGLEOP(iret, 0xCF)
3294 //EMIT_SINGLEOP(xlat, 0xD7)
3295 //EMIT_SINGLEOP(lock, 0xF0)
3296 EMIT_SINGLEOP(rep, 0xF3)
3297 //EMIT_SINGLEOP(halt, 0xF4)
3298 EMIT_SINGLEOP(cmc, 0xF5)
3299 EMIT_SINGLEOP(stc, 0xF9)
3300 //EMIT_SINGLEOP(cli, 0xFA)
3301 //EMIT_SINGLEOP(sti, 0xFB)
3302 //EMIT_SINGLEOP(std, 0xFD)
3305 * Emits a MOV out, [MEM].
3307 static void bemit_load(const ir_node *node)
3309 const arch_register_t *out = get_out_reg(node, 0);
3311 if (out->index == REG_EAX) {
3312 ir_node *base = get_irn_n(node, n_ia32_base);
3313 int has_base = !is_ia32_NoReg_GP(base);
3314 ir_node *index = get_irn_n(node, n_ia32_index);
3315 int has_index = !is_ia32_NoReg_GP(index);
3316 if (!has_base && !has_index) {
3317 ir_entity *ent = get_ia32_am_sc(node);
3318 int offs = get_ia32_am_offs_int(node);
3319 /* load from constant address to EAX can be encoded
3322 bemit_entity(ent, 0, offs, false);
3327 bemit_mod_am(reg_gp_map[out->index], node);
3331 * Emits a MOV [mem], in.
3333 static void bemit_store(const ir_node *node)
3335 const ir_node *value = get_irn_n(node, n_ia32_Store_val);
3336 unsigned size = get_mode_size_bits(get_ia32_ls_mode(node));
3338 if (is_ia32_Immediate(value)) {
3341 bemit_mod_am(0, node);
3342 bemit8(get_ia32_immediate_attr_const(value)->offset);
3343 } else if (size == 16) {
3346 bemit_mod_am(0, node);
3347 bemit16(get_ia32_immediate_attr_const(value)->offset);
3350 bemit_mod_am(0, node);
3351 bemit_immediate(value, false);
3354 const arch_register_t *in = get_in_reg(node, n_ia32_Store_val);
3356 if (in->index == REG_EAX) {
3357 ir_node *base = get_irn_n(node, n_ia32_base);
3358 int has_base = !is_ia32_NoReg_GP(base);
3359 ir_node *index = get_irn_n(node, n_ia32_index);
3360 int has_index = !is_ia32_NoReg_GP(index);
3361 if (!has_base && !has_index) {
3362 ir_entity *ent = get_ia32_am_sc(node);
3363 int offs = get_ia32_am_offs_int(node);
3364 /* store to constant address from EAX can be encoded as
3365 * 0xA2/0xA3 [offset]*/
3373 bemit_entity(ent, 0, offs, false);
3385 bemit_mod_am(reg_gp_map[in->index], node);
3389 static void bemit_conv_i2i(const ir_node *node)
3391 ir_mode *smaller_mode = get_ia32_ls_mode(node);
3400 if (mode_is_signed(smaller_mode)) opcode |= 0x08;
3401 if (get_mode_size_bits(smaller_mode) == 16) opcode |= 0x01;
3402 bemit_unop_reg(node, opcode, n_ia32_Conv_I2I_val);
3408 static void bemit_push(const ir_node *node)
3410 const ir_node *value = get_irn_n(node, n_ia32_Push_val);
3412 if (is_ia32_Immediate(value)) {
3413 const ia32_immediate_attr_t *attr
3414 = get_ia32_immediate_attr_const(value);
3415 unsigned size = get_signed_imm_size(attr->offset);
3421 bemit8((unsigned char)attr->offset);
3426 bemit_immediate(value, false);
3429 } else if (is_ia32_NoReg_GP(value)) {
3431 bemit_mod_am(6, node);
3433 const arch_register_t *reg = get_in_reg(node, n_ia32_Push_val);
3434 bemit8(0x50 + reg_gp_map[reg->index]);
3441 static void bemit_pop(const ir_node *node)
3443 const arch_register_t *reg = get_out_reg(node, pn_ia32_Pop_res);
3444 bemit8(0x58 + reg_gp_map[reg->index]);
3447 static void bemit_popmem(const ir_node *node)
3450 bemit_mod_am(0, node);
3453 static void bemit_call(const ir_node *node)
3455 ir_node *proc = get_irn_n(node, n_ia32_Call_addr);
3457 if (is_ia32_Immediate(proc)) {
3459 bemit_immediate(proc, true);
3461 bemit_unop(node, 0xFF, 2, n_ia32_Call_addr);
3465 static void bemit_jmp(const ir_node *dest_block)
3468 bemit_jmp_destination(dest_block);
3471 static void bemit_jump(const ir_node *node)
3473 if (can_be_fallthrough(node))
3476 bemit_jmp(get_cfop_target_block(node));
3479 static void bemit_jcc(int pnc, const ir_node *dest_block)
3481 unsigned char cc = pnc2cc(pnc);
3484 bemit_jmp_destination(dest_block);
3487 static void bemit_jp(bool odd, const ir_node *dest_block)
3491 bemit_jmp_destination(dest_block);
3494 static void bemit_ia32_jcc(const ir_node *node)
3496 int pnc = get_ia32_condcode(node);
3497 const ir_node *proj_true;
3498 const ir_node *proj_false;
3499 const ir_node *dest_true;
3500 const ir_node *dest_false;
3501 const ir_node *block;
3503 pnc = determine_final_pnc(node, 0, pnc);
3505 /* get both Projs */
3506 proj_true = get_proj(node, pn_ia32_Jcc_true);
3507 assert(proj_true && "Jcc without true Proj");
3509 proj_false = get_proj(node, pn_ia32_Jcc_false);
3510 assert(proj_false && "Jcc without false Proj");
3512 block = get_nodes_block(node);
3514 if (can_be_fallthrough(proj_true)) {
3515 /* exchange both proj's so the second one can be omitted */
3516 const ir_node *t = proj_true;
3518 proj_true = proj_false;
3520 pnc = ia32_get_negated_pnc(pnc);
3523 dest_true = get_cfop_target_block(proj_true);
3524 dest_false = get_cfop_target_block(proj_false);
3526 if (pnc & ia32_pn_Cmp_float) {
3527 /* Some floating point comparisons require a test of the parity flag,
3528 * which indicates that the result is unordered */
3531 bemit_jp(false, dest_true);
3536 bemit_jp(true, dest_true);
3542 /* we need a local label if the false proj is a fallthrough
3543 * as the falseblock might have no label emitted then */
3544 if (can_be_fallthrough(proj_false)) {
3546 bemit8(0x06); // jp + 6
3548 bemit_jp(false, dest_false);
3555 bemit_jp(false, dest_true);
3563 bemit_jcc(pnc, dest_true);
3566 /* the second Proj might be a fallthrough */
3567 if (can_be_fallthrough(proj_false)) {
3568 /* it's a fallthrough */
3570 bemit_jmp(dest_false);
3574 static void bemit_switchjmp(const ir_node *node)
3576 unsigned long interval;
3580 const arch_register_t *in;
3582 /* fill the table structure */
3583 generate_jump_table(&tbl, node);
3585 /* two-complement's magic make this work without overflow */
3586 interval = tbl.max_value - tbl.min_value;
3588 in = get_in_reg(node, 0);
3589 /* emit the table */
3590 if (get_signed_imm_size(interval) == 1) {
3591 bemit8(0x83); // cmpl $imm8, %in
3595 bemit8(0x81); // cmpl $imm32, %in
3599 bemit8(0x0F); // ja tbl.defProj
3601 ia32_emitf(tbl.defProj, ".long %L - . - 4\n");
3603 if (tbl.num_branches > 1) {
3605 bemit8(0xFF); // jmp *tbl.label(,%in,4)
3606 bemit8(MOD_IND | ENC_REG(4) | ENC_RM(0x04));
3607 bemit8(ENC_SIB(2, reg_gp_map[in->index], 0x05));
3608 be_emit_irprintf("\t.long %s\n", tbl.label);
3610 be_gas_emit_switch_section(GAS_SECTION_RODATA);
3611 be_emit_cstring(".align 4\n");
3612 be_emit_irprintf("%s:\n", tbl.label);
3614 last_value = tbl.branches[0].value;
3615 for (i = 0; i != tbl.num_branches; ++i) {
3616 while (last_value != tbl.branches[i].value) {
3617 ia32_emitf(tbl.defProj, ".long %L\n");
3620 ia32_emitf(tbl.branches[i].target, ".long %L\n");
3623 be_gas_emit_switch_section(GAS_SECTION_TEXT);
3625 /* one jump is enough */
3626 panic("switch only has one case");
3627 //ia32_emitf(tbl.branches[0].target, "\tjmp %L\n");
3630 be_emit_write_line();
3638 static void bemit_return(const ir_node *node)
3640 unsigned pop = be_Return_get_pop(node);
3641 if (pop > 0 || be_Return_get_emit_pop(node)) {
3643 assert(pop <= 0xffff);
3650 static void bemit_subsp(const ir_node *node)
3652 const arch_register_t *out;
3655 /* mov %esp, %out */
3657 out = get_out_reg(node, 1);
3658 bemit8(MOD_REG | ENC_REG(reg_gp_map[out->index]) | ENC_RM(0x04));
3661 static void bemit_incsp(const ir_node *node)
3664 const arch_register_t *reg;
3668 offs = be_get_IncSP_offset(node);
3679 size = get_signed_imm_size(offs);
3680 bemit8(size == 1 ? 0x83 : 0x81);
3682 reg = get_out_reg(node, 0);
3683 bemit_modru(reg, ext);
3692 static void bemit_copybi(const ir_node *node)
3694 unsigned size = get_ia32_copyb_size(node);
3696 bemit8(0xA4); // movsb
3699 bemit8(0xA5); // movsw
3703 bemit8(0xA5); // movsl
3707 static void bemit_fbinop(const ir_node *node, unsigned code, unsigned code_to)
3709 if (get_ia32_op_type(node) == ia32_Normal) {
3710 const ia32_x87_attr_t *x87_attr = get_ia32_x87_attr_const(node);
3711 const arch_register_t *in1 = x87_attr->x87[0];
3712 const arch_register_t *in = x87_attr->x87[1];
3713 const arch_register_t *out = x87_attr->x87[2];
3717 } else if (out == in) {
3721 if (out->index == 0) {
3723 bemit8(MOD_REG | ENC_REG(code) | ENC_RM(in->index));
3726 bemit8(MOD_REG | ENC_REG(code_to) | ENC_RM(out->index));
3729 if (get_mode_size_bits(get_ia32_ls_mode(node)) == 32) {
3734 bemit_mod_am(code, node);
3738 static void bemit_fbinopp(const ir_node *node, unsigned const code)
3740 const ia32_x87_attr_t *x87_attr = get_ia32_x87_attr_const(node);
3741 const arch_register_t *out = x87_attr->x87[2];
3743 bemit8(code + out->index);
3746 static void bemit_fabs(const ir_node *node)
3754 static void bemit_fadd(const ir_node *node)
3756 bemit_fbinop(node, 0, 0);
3759 static void bemit_faddp(const ir_node *node)
3761 bemit_fbinopp(node, 0xC0);
3764 static void bemit_fchs(const ir_node *node)
3772 static void bemit_fdiv(const ir_node *node)
3774 bemit_fbinop(node, 6, 7);
3777 static void bemit_fdivp(const ir_node *node)
3779 bemit_fbinopp(node, 0xF8);
3782 static void bemit_fdivr(const ir_node *node)
3784 bemit_fbinop(node, 7, 6);
3787 static void bemit_fdivrp(const ir_node *node)
3789 bemit_fbinopp(node, 0xF0);
3792 static void bemit_fild(const ir_node *node)
3794 switch (get_mode_size_bits(get_ia32_ls_mode(node))) {
3796 bemit8(0xDF); // filds
3797 bemit_mod_am(0, node);
3801 bemit8(0xDB); // fildl
3802 bemit_mod_am(0, node);
3806 bemit8(0xDF); // fildll
3807 bemit_mod_am(5, node);
3811 panic("invalid mode size");
3815 static void bemit_fist(const ir_node *node)
3817 switch (get_mode_size_bits(get_ia32_ls_mode(node))) {
3819 bemit8(0xDF); // fists
3823 bemit8(0xDB); // fistl
3827 panic("invalid mode size");
3829 bemit_mod_am(2, node);
3832 static void bemit_fistp(const ir_node *node)
3834 switch (get_mode_size_bits(get_ia32_ls_mode(node))) {
3836 bemit8(0xDF); // fistps
3837 bemit_mod_am(3, node);
3841 bemit8(0xDB); // fistpl
3842 bemit_mod_am(3, node);
3846 bemit8(0xDF); // fistpll
3847 bemit_mod_am(7, node);
3851 panic("invalid mode size");
3855 static void bemit_fld(const ir_node *node)
3857 switch (get_mode_size_bits(get_ia32_ls_mode(node))) {
3859 bemit8(0xD9); // flds
3860 bemit_mod_am(0, node);
3864 bemit8(0xDD); // fldl
3865 bemit_mod_am(0, node);
3870 bemit8(0xDB); // fldt
3871 bemit_mod_am(5, node);
3875 panic("invalid mode size");
3879 static void bemit_fld1(const ir_node *node)
3883 bemit8(0xE8); // fld1
3886 static void bemit_fldcw(const ir_node *node)
3888 bemit8(0xD9); // fldcw
3889 bemit_mod_am(5, node);
3892 static void bemit_fldz(const ir_node *node)
3896 bemit8(0xEE); // fldz
3899 static void bemit_fmul(const ir_node *node)
3901 bemit_fbinop(node, 1, 1);
3904 static void bemit_fmulp(const ir_node *node)
3906 bemit_fbinopp(node, 0xC8);
3909 static void bemit_fpop(const ir_node *node)
3911 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
3913 bemit8(0xD8 + attr->x87[0]->index);
3916 static void bemit_fpush(const ir_node *node)
3918 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
3920 bemit8(0xC0 + attr->x87[0]->index);
3923 static void bemit_fpushcopy(const ir_node *node)
3925 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
3927 bemit8(0xC0 + attr->x87[0]->index);
3930 static void bemit_fst(const ir_node *node)
3932 switch (get_mode_size_bits(get_ia32_ls_mode(node))) {
3934 bemit8(0xD9); // fsts
3938 bemit8(0xDD); // fstl
3942 panic("invalid mode size");
3944 bemit_mod_am(2, node);
3947 static void bemit_fstp(const ir_node *node)
3949 switch (get_mode_size_bits(get_ia32_ls_mode(node))) {
3951 bemit8(0xD9); // fstps
3952 bemit_mod_am(3, node);
3956 bemit8(0xDD); // fstpl
3957 bemit_mod_am(3, node);
3962 bemit8(0xDB); // fstpt
3963 bemit_mod_am(7, node);
3967 panic("invalid mode size");
3971 static void bemit_fsub(const ir_node *node)
3973 bemit_fbinop(node, 4, 5);
3976 static void bemit_fsubp(const ir_node *node)
3978 bemit_fbinopp(node, 0xE8);
3981 static void bemit_fsubr(const ir_node *node)
3983 bemit_fbinop(node, 5, 4);
3986 static void bemit_fsubrp(const ir_node *node)
3988 bemit_fbinopp(node, 0xE0);
3991 static void bemit_fnstcw(const ir_node *node)
3993 bemit8(0xD9); // fnstcw
3994 bemit_mod_am(7, node);
3997 static void bemit_fnstsw(void)
3999 bemit8(0xDF); // fnstsw %ax
4003 static void bemit_ftstfnstsw(const ir_node *node)
4007 bemit8(0xD9); // ftst
4012 static void bemit_fucomi(const ir_node *node)
4014 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
4015 bemit8(0xDB); // fucomi
4016 bemit8(0xE8 + attr->x87[1]->index);
4019 static void bemit_fucomip(const ir_node *node)
4021 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
4022 bemit8(0xDF); // fucomip
4023 bemit8(0xE8 + attr->x87[1]->index);
4026 static void bemit_fucomfnstsw(const ir_node *node)
4028 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
4029 bemit8(0xDD); // fucom
4030 bemit8(0xE0 + attr->x87[1]->index);
4034 static void bemit_fucompfnstsw(const ir_node *node)
4036 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
4037 bemit8(0xDD); // fucomp
4038 bemit8(0xE8 + attr->x87[1]->index);
4042 static void bemit_fucomppfnstsw(const ir_node *node)
4046 bemit8(0xDA); // fucompp
4051 static void bemit_fxch(const ir_node *node)
4053 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
4055 bemit8(0xC8 + attr->x87[0]->index);
4059 * The type of a emitter function.
4061 typedef void (*emit_func) (const ir_node *);
4064 * Set a node emitter. Make it a bit more type safe.
4066 static void register_emitter(ir_op *op, emit_func func)
4068 op->ops.generic = (op_func) func;
4071 static void ia32_register_binary_emitters(void)
4073 /* first clear the generic function pointer for all ops */
4074 clear_irp_opcodes_generic_func();
4076 /* benode emitter */
4077 register_emitter(op_be_Copy, bemit_copy);
4078 register_emitter(op_be_CopyKeep, bemit_copy);
4079 register_emitter(op_be_IncSP, bemit_incsp);
4080 register_emitter(op_be_Perm, bemit_perm);
4081 register_emitter(op_be_Return, bemit_return);
4082 register_emitter(op_ia32_Adc, bemit_adc);
4083 register_emitter(op_ia32_Add, bemit_add);
4084 register_emitter(op_ia32_AddMem, bemit_addmem);
4085 register_emitter(op_ia32_AddMem8Bit, bemit_addmem8bit);
4086 register_emitter(op_ia32_And, bemit_and);
4087 register_emitter(op_ia32_AndMem, bemit_andmem);
4088 register_emitter(op_ia32_AndMem8Bit, bemit_andmem8bit);
4089 register_emitter(op_ia32_Breakpoint, bemit_int3);
4090 register_emitter(op_ia32_CMovcc, bemit_cmovcc);
4091 register_emitter(op_ia32_Call, bemit_call);
4092 register_emitter(op_ia32_Cltd, bemit_cltd);
4093 register_emitter(op_ia32_Cmc, bemit_cmc);
4094 register_emitter(op_ia32_Cmp, bemit_cmp);
4095 register_emitter(op_ia32_Cmp8Bit, bemit_cmp8bit);
4096 register_emitter(op_ia32_Const, bemit_mov_const);
4097 register_emitter(op_ia32_Conv_I2I, bemit_conv_i2i);
4098 register_emitter(op_ia32_Conv_I2I8Bit, bemit_conv_i2i);
4099 register_emitter(op_ia32_CopyB_i, bemit_copybi);
4100 register_emitter(op_ia32_Cwtl, bemit_cwtl);
4101 register_emitter(op_ia32_Dec, bemit_dec);
4102 register_emitter(op_ia32_DecMem, bemit_decmem);
4103 register_emitter(op_ia32_Div, bemit_div);
4104 register_emitter(op_ia32_FldCW, bemit_fldcw);
4105 register_emitter(op_ia32_FnstCW, bemit_fnstcw);
4106 register_emitter(op_ia32_FtstFnstsw, bemit_ftstfnstsw);
4107 register_emitter(op_ia32_FucomFnstsw, bemit_fucomfnstsw);
4108 register_emitter(op_ia32_Fucomi, bemit_fucomi);
4109 register_emitter(op_ia32_FucompFnstsw, bemit_fucompfnstsw);
4110 register_emitter(op_ia32_Fucompi, bemit_fucomip);
4111 register_emitter(op_ia32_FucomppFnstsw, bemit_fucomppfnstsw);
4112 register_emitter(op_ia32_IDiv, bemit_idiv);
4113 register_emitter(op_ia32_IJmp, bemit_ijmp);
4114 register_emitter(op_ia32_IMul, bemit_imul);
4115 register_emitter(op_ia32_IMul1OP, bemit_imul1op);
4116 register_emitter(op_ia32_Inc, bemit_inc);
4117 register_emitter(op_ia32_IncMem, bemit_incmem);
4118 register_emitter(op_ia32_Jcc, bemit_ia32_jcc);
4119 register_emitter(op_ia32_Jmp, bemit_jump);
4120 register_emitter(op_ia32_LdTls, bemit_ldtls);
4121 register_emitter(op_ia32_Lea, bemit_lea);
4122 register_emitter(op_ia32_Leave, bemit_leave);
4123 register_emitter(op_ia32_Load, bemit_load);
4124 register_emitter(op_ia32_Minus64Bit, bemit_minus64bit);
4125 register_emitter(op_ia32_Mul, bemit_mul);
4126 register_emitter(op_ia32_Neg, bemit_neg);
4127 register_emitter(op_ia32_NegMem, bemit_negmem);
4128 register_emitter(op_ia32_Not, bemit_not);
4129 register_emitter(op_ia32_NotMem, bemit_notmem);
4130 register_emitter(op_ia32_Or, bemit_or);
4131 register_emitter(op_ia32_OrMem, bemit_ormem);
4132 register_emitter(op_ia32_OrMem8Bit, bemit_ormem8bit);
4133 register_emitter(op_ia32_Pop, bemit_pop);
4134 register_emitter(op_ia32_PopEbp, bemit_pop);
4135 register_emitter(op_ia32_PopMem, bemit_popmem);
4136 register_emitter(op_ia32_Push, bemit_push);
4137 register_emitter(op_ia32_RepPrefix, bemit_rep);
4138 register_emitter(op_ia32_Rol, bemit_rol);
4139 register_emitter(op_ia32_RolMem, bemit_rolmem);
4140 register_emitter(op_ia32_Ror, bemit_ror);
4141 register_emitter(op_ia32_RorMem, bemit_rormem);
4142 register_emitter(op_ia32_Sahf, bemit_sahf);
4143 register_emitter(op_ia32_Sar, bemit_sar);
4144 register_emitter(op_ia32_SarMem, bemit_sarmem);
4145 register_emitter(op_ia32_Sbb, bemit_sbb);
4146 register_emitter(op_ia32_Setcc, bemit_setcc);
4147 register_emitter(op_ia32_Shl, bemit_shl);
4148 register_emitter(op_ia32_ShlD, bemit_shld);
4149 register_emitter(op_ia32_ShlMem, bemit_shlmem);
4150 register_emitter(op_ia32_Shr, bemit_shr);
4151 register_emitter(op_ia32_ShrD, bemit_shrd);
4152 register_emitter(op_ia32_ShrMem, bemit_shrmem);
4153 register_emitter(op_ia32_Stc, bemit_stc);
4154 register_emitter(op_ia32_Store, bemit_store);
4155 register_emitter(op_ia32_Store8Bit, bemit_store);
4156 register_emitter(op_ia32_Sub, bemit_sub);
4157 register_emitter(op_ia32_SubMem, bemit_submem);
4158 register_emitter(op_ia32_SubMem8Bit, bemit_submem8bit);
4159 register_emitter(op_ia32_SubSP, bemit_subsp);
4160 register_emitter(op_ia32_SwitchJmp, bemit_switchjmp);
4161 register_emitter(op_ia32_Test, bemit_test);
4162 register_emitter(op_ia32_Test8Bit, bemit_test8bit);
4163 register_emitter(op_ia32_Xor, bemit_xor);
4164 register_emitter(op_ia32_Xor0, bemit_xor0);
4165 register_emitter(op_ia32_XorMem, bemit_xormem);
4166 register_emitter(op_ia32_XorMem8Bit, bemit_xormem8bit);
4167 register_emitter(op_ia32_fabs, bemit_fabs);
4168 register_emitter(op_ia32_fadd, bemit_fadd);
4169 register_emitter(op_ia32_faddp, bemit_faddp);
4170 register_emitter(op_ia32_fchs, bemit_fchs);
4171 register_emitter(op_ia32_fdiv, bemit_fdiv);
4172 register_emitter(op_ia32_fdivp, bemit_fdivp);
4173 register_emitter(op_ia32_fdivr, bemit_fdivr);
4174 register_emitter(op_ia32_fdivrp, bemit_fdivrp);
4175 register_emitter(op_ia32_fild, bemit_fild);
4176 register_emitter(op_ia32_fist, bemit_fist);
4177 register_emitter(op_ia32_fistp, bemit_fistp);
4178 register_emitter(op_ia32_fld, bemit_fld);
4179 register_emitter(op_ia32_fld1, bemit_fld1);
4180 register_emitter(op_ia32_fldz, bemit_fldz);
4181 register_emitter(op_ia32_fmul, bemit_fmul);
4182 register_emitter(op_ia32_fmulp, bemit_fmulp);
4183 register_emitter(op_ia32_fpop, bemit_fpop);
4184 register_emitter(op_ia32_fpush, bemit_fpush);
4185 register_emitter(op_ia32_fpushCopy, bemit_fpushcopy);
4186 register_emitter(op_ia32_fst, bemit_fst);
4187 register_emitter(op_ia32_fstp, bemit_fstp);
4188 register_emitter(op_ia32_fsub, bemit_fsub);
4189 register_emitter(op_ia32_fsubp, bemit_fsubp);
4190 register_emitter(op_ia32_fsubr, bemit_fsubr);
4191 register_emitter(op_ia32_fsubrp, bemit_fsubrp);
4192 register_emitter(op_ia32_fxch, bemit_fxch);
4194 /* ignore the following nodes */
4195 register_emitter(op_ia32_ProduceVal, emit_Nothing);
4196 register_emitter(op_be_Barrier, emit_Nothing);
4197 register_emitter(op_be_Keep, emit_Nothing);
4198 register_emitter(op_be_Start, emit_Nothing);
4199 register_emitter(op_Phi, emit_Nothing);
4200 register_emitter(op_Start, emit_Nothing);
4203 static void gen_binary_block(ir_node *block)
4207 ia32_emit_block_header(block);
4209 /* emit the contents of the block */
4210 sched_foreach(block, node) {
4211 ia32_emit_node(node);
4215 void ia32_gen_binary_routine(ia32_code_gen_t *ia32_cg, ir_graph *irg)
4217 ir_entity *entity = get_irg_entity(irg);
4223 ia32_register_binary_emitters();
4225 be_gas_emit_function_prolog(entity, ia32_cg_config.function_alignment);
4227 /* we use links to point to target blocks */
4228 ir_reserve_resources(irg, IR_RESOURCE_IRN_LINK);
4229 irg_block_walk_graph(irg, ia32_gen_labels, NULL, NULL);
4231 /* initialize next block links */
4232 n = ARR_LEN(cg->blk_sched);
4233 for (i = 0; i < n; ++i) {
4234 ir_node *block = cg->blk_sched[i];
4235 ir_node *prev = i > 0 ? cg->blk_sched[i-1] : NULL;
4237 set_irn_link(block, prev);
4240 for (i = 0; i < n; ++i) {
4241 ir_node *block = cg->blk_sched[i];
4242 gen_binary_block(block);
4245 be_gas_emit_function_epilog(entity);
4246 be_dbg_method_end();
4248 be_emit_write_line();
4250 ir_free_resources(irg, IR_RESOURCE_IRN_LINK);
4256 void ia32_init_emitter(void)
4258 lc_opt_entry_t *be_grp;
4259 lc_opt_entry_t *ia32_grp;
4261 be_grp = lc_opt_get_grp(firm_opt_get_root(), "be");
4262 ia32_grp = lc_opt_get_grp(be_grp, "ia32");
4264 lc_opt_add_table(ia32_grp, ia32_emitter_options);
4268 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.emitter");