2 * Copyright (C) 1995-2011 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This file implements the ia32 node emitter.
23 * @author Christian Wuerdig, Matthias Braun
26 * Summary table for x86 floatingpoint compares:
27 * (remember effect of unordered on x86: ZF=1, PF=1, CF=1)
35 * pnc_Leg => NP (ordered)
57 #include "iredges_t.h"
61 #include "raw_bitset.h"
65 #include "../besched.h"
66 #include "../benode.h"
68 #include "../be_dbgout.h"
69 #include "../beemitter.h"
70 #include "../begnuas.h"
72 #include "../be_dbgout.h"
74 #include "ia32_emitter.h"
75 #include "ia32_common_transform.h"
76 #include "gen_ia32_emitter.h"
77 #include "gen_ia32_regalloc_if.h"
78 #include "ia32_nodes_attr.h"
79 #include "ia32_new_nodes.h"
80 #include "ia32_architecture.h"
81 #include "bearch_ia32_t.h"
83 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
85 #define SNPRINTF_BUF_LEN 128
87 static const ia32_isa_t *isa;
88 static char pic_base_label[128];
89 static ir_label_t exc_label_id;
90 static int mark_spill_reload = 0;
93 /** Return the next block in Block schedule */
94 static ir_node *get_prev_block_sched(const ir_node *block)
96 return (ir_node*)get_irn_link(block);
99 /** Checks if the current block is a fall-through target. */
100 static int is_fallthrough(const ir_node *cfgpred)
104 if (!is_Proj(cfgpred))
106 pred = get_Proj_pred(cfgpred);
107 if (is_ia32_SwitchJmp(pred))
114 * returns non-zero if the given block needs a label
115 * because of being a jump-target (and not a fall-through)
117 static int block_needs_label(const ir_node *block)
120 int n_cfgpreds = get_Block_n_cfgpreds(block);
122 if (has_Block_entity(block))
125 if (n_cfgpreds == 0) {
127 } else if (n_cfgpreds == 1) {
128 ir_node *cfgpred = get_Block_cfgpred(block, 0);
129 ir_node *cfgpred_block = get_nodes_block(cfgpred);
131 if (get_prev_block_sched(block) == cfgpred_block
132 && is_fallthrough(cfgpred)) {
141 * Returns the register at in position pos.
143 static const arch_register_t *get_in_reg(const ir_node *irn, int pos)
146 const arch_register_t *reg = NULL;
148 assert(get_irn_arity(irn) > pos && "Invalid IN position");
150 /* The out register of the operator at position pos is the
151 in register we need. */
152 op = get_irn_n(irn, pos);
154 reg = arch_get_irn_register(op);
156 assert(reg && "no in register found");
158 if (reg == &ia32_registers[REG_GP_NOREG])
159 panic("trying to emit noreg for %+F input %d", irn, pos);
165 * Returns the register at out position pos.
167 static const arch_register_t *get_out_reg(const ir_node *irn, int pos)
170 const arch_register_t *reg = NULL;
172 /* 1st case: irn is not of mode_T, so it has only */
173 /* one OUT register -> good */
174 /* 2nd case: irn is of mode_T -> collect all Projs and ask the */
175 /* Proj with the corresponding projnum for the register */
177 if (get_irn_mode(irn) != mode_T) {
179 reg = arch_get_irn_register(irn);
180 } else if (is_ia32_irn(irn)) {
181 reg = arch_irn_get_register(irn, pos);
183 const ir_edge_t *edge;
185 foreach_out_edge(irn, edge) {
186 proj = get_edge_src_irn(edge);
187 assert(is_Proj(proj) && "non-Proj from mode_T node");
188 if (get_Proj_proj(proj) == pos) {
189 reg = arch_get_irn_register(proj);
195 assert(reg && "no out register found");
200 * Add a number to a prefix. This number will not be used a second time.
202 static char *get_unique_label(char *buf, size_t buflen, const char *prefix)
204 static unsigned long id = 0;
205 snprintf(buf, buflen, "%s%s%lu", be_gas_get_private_prefix(), prefix, ++id);
210 * Emit the name of the 8bit low register
212 static void emit_8bit_register(const arch_register_t *reg)
214 const char *reg_name = arch_register_get_name(reg);
215 assert(reg->index == REG_GP_EAX || reg->index == REG_GP_EBX
216 || reg->index == REG_GP_ECX || reg->index == REG_GP_EDX);
219 be_emit_char(reg_name[1]); /* get the basic name of the register */
224 * Emit the name of the 8bit high register
226 static void emit_8bit_register_high(const arch_register_t *reg)
228 const char *reg_name = arch_register_get_name(reg);
229 assert(reg->index == REG_GP_EAX || reg->index == REG_GP_EBX
230 || reg->index == REG_GP_ECX || reg->index == REG_GP_EDX);
233 be_emit_char(reg_name[1]); /* get the basic name of the register */
237 static void emit_16bit_register(const arch_register_t *reg)
239 const char *reg_name = arch_register_get_name(reg);
242 be_emit_string(reg_name+1); /* skip the 'e' prefix of the 32bit names */
246 * emit a register, possible shortened by a mode
248 * @param reg the register
249 * @param mode the mode of the register or NULL for full register
251 static void emit_register(const arch_register_t *reg, const ir_mode *mode)
253 const char *reg_name;
256 int size = get_mode_size_bits(mode);
258 case 8: emit_8bit_register(reg); return;
259 case 16: emit_16bit_register(reg); return;
261 assert(mode_is_float(mode) || size == 32);
264 reg_name = arch_register_get_name(reg);
267 be_emit_string(reg_name);
270 void ia32_emit_source_register(const ir_node *node, int pos)
272 const arch_register_t *reg = get_in_reg(node, pos);
274 emit_register(reg, NULL);
277 static void ia32_emit_entity(ir_entity *entity, int no_pic_adjust)
279 be_gas_emit_entity(entity);
281 if (get_entity_owner(entity) == get_tls_type()) {
282 if (get_entity_visibility(entity) == ir_visibility_external) {
283 be_emit_cstring("@INDNTPOFF");
285 be_emit_cstring("@NTPOFF");
289 if (do_pic && !no_pic_adjust) {
291 be_emit_string(pic_base_label);
295 static void emit_ia32_Immediate_no_prefix(const ir_node *node)
297 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(node);
299 if (attr->symconst != NULL) {
302 ia32_emit_entity(attr->symconst, attr->no_pic_adjust);
304 if (attr->symconst == NULL || attr->offset != 0) {
305 if (attr->symconst != NULL) {
306 be_emit_irprintf("%+d", attr->offset);
308 be_emit_irprintf("0x%X", attr->offset);
313 static void emit_ia32_Immediate(const ir_node *node)
316 emit_ia32_Immediate_no_prefix(node);
319 void ia32_emit_8bit_source_register_or_immediate(const ir_node *node, int pos)
321 const arch_register_t *reg;
322 const ir_node *in = get_irn_n(node, pos);
323 if (is_ia32_Immediate(in)) {
324 emit_ia32_Immediate(in);
328 reg = get_in_reg(node, pos);
329 emit_8bit_register(reg);
332 void ia32_emit_8bit_high_source_register(const ir_node *node, int pos)
334 const arch_register_t *reg = get_in_reg(node, pos);
335 emit_8bit_register_high(reg);
338 void ia32_emit_16bit_source_register_or_immediate(const ir_node *node, int pos)
340 const arch_register_t *reg;
341 const ir_node *in = get_irn_n(node, pos);
342 if (is_ia32_Immediate(in)) {
343 emit_ia32_Immediate(in);
347 reg = get_in_reg(node, pos);
348 emit_16bit_register(reg);
351 void ia32_emit_dest_register(const ir_node *node, int pos)
353 const arch_register_t *reg = get_out_reg(node, pos);
355 emit_register(reg, NULL);
358 void ia32_emit_dest_register_size(const ir_node *node, int pos)
360 const arch_register_t *reg = get_out_reg(node, pos);
362 emit_register(reg, get_ia32_ls_mode(node));
365 void ia32_emit_8bit_dest_register(const ir_node *node, int pos)
367 const arch_register_t *reg = get_out_reg(node, pos);
369 emit_register(reg, mode_Bu);
372 void ia32_emit_x87_register(const ir_node *node, int pos)
374 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
378 be_emit_string(attr->x87[pos]->name);
381 static void ia32_emit_mode_suffix_mode(const ir_mode *mode)
383 assert(mode_is_int(mode) || mode_is_reference(mode));
384 switch (get_mode_size_bits(mode)) {
385 case 8: be_emit_char('b'); return;
386 case 16: be_emit_char('w'); return;
387 case 32: be_emit_char('l'); return;
388 /* gas docu says q is the suffix but gcc, objdump and icc use ll
390 case 64: be_emit_cstring("ll"); return;
392 panic("Can't output mode_suffix for %+F", mode);
395 void ia32_emit_mode_suffix(const ir_node *node)
397 ir_mode *mode = get_ia32_ls_mode(node);
401 ia32_emit_mode_suffix_mode(mode);
404 void ia32_emit_x87_mode_suffix(const ir_node *node)
408 /* we only need to emit the mode on address mode */
409 if (get_ia32_op_type(node) == ia32_Normal)
412 mode = get_ia32_ls_mode(node);
413 assert(mode != NULL);
415 if (mode_is_float(mode)) {
416 switch (get_mode_size_bits(mode)) {
417 case 32: be_emit_char('s'); return;
418 case 64: be_emit_char('l'); return;
419 /* long doubles have different sizes due to alignment on different
423 case 128: be_emit_char('t'); return;
426 assert(mode_is_int(mode) || mode_is_reference(mode));
427 switch (get_mode_size_bits(mode)) {
428 case 16: be_emit_char('s'); return;
429 case 32: be_emit_char('l'); return;
430 /* gas docu says q is the suffix but gcc, objdump and icc use ll
432 case 64: be_emit_cstring("ll"); return;
435 panic("Can't output mode_suffix for %+F", mode);
438 static char get_xmm_mode_suffix(ir_mode *mode)
440 assert(mode_is_float(mode));
441 switch (get_mode_size_bits(mode)) {
444 default: panic("Invalid XMM mode");
448 void ia32_emit_xmm_mode_suffix(const ir_node *node)
450 ir_mode *mode = get_ia32_ls_mode(node);
451 assert(mode != NULL);
453 be_emit_char(get_xmm_mode_suffix(mode));
456 void ia32_emit_xmm_mode_suffix_s(const ir_node *node)
458 ir_mode *mode = get_ia32_ls_mode(node);
459 assert(mode != NULL);
460 be_emit_char(get_xmm_mode_suffix(mode));
463 void ia32_emit_extend_suffix(const ir_node *node)
465 ir_mode *mode = get_ia32_ls_mode(node);
466 if (get_mode_size_bits(mode) == 32)
468 be_emit_char(mode_is_signed(mode) ? 's' : 'z');
469 ia32_emit_mode_suffix_mode(mode);
472 void ia32_emit_source_register_or_immediate(const ir_node *node, int pos)
474 ir_node *in = get_irn_n(node, pos);
475 if (is_ia32_Immediate(in)) {
476 emit_ia32_Immediate(in);
478 const ir_mode *mode = get_ia32_ls_mode(node);
479 const arch_register_t *reg = get_in_reg(node, pos);
480 emit_register(reg, mode);
485 * Returns the target block for a control flow node.
487 static ir_node *get_cfop_target_block(const ir_node *irn)
489 assert(get_irn_mode(irn) == mode_X);
490 return (ir_node*)get_irn_link(irn);
494 * Emits the target label for a control flow node.
496 static void ia32_emit_cfop_target(const ir_node *node)
498 ir_node *block = get_cfop_target_block(node);
499 be_gas_emit_block_name(block);
503 * Emit the suffix for a compare instruction.
505 static void ia32_emit_condition_code(ia32_condition_code_t cc)
508 case ia32_cc_overflow: be_emit_cstring("o"); return;
509 case ia32_cc_not_overflow: be_emit_cstring("no"); return;
510 case ia32_cc_float_below:
511 case ia32_cc_float_unordered_below:
512 case ia32_cc_below: be_emit_cstring("b"); return;
513 case ia32_cc_float_above_equal:
514 case ia32_cc_float_unordered_above_equal:
515 case ia32_cc_above_equal: be_emit_cstring("ae"); return;
516 case ia32_cc_float_equal:
517 case ia32_cc_equal: be_emit_cstring("e"); return;
518 case ia32_cc_float_not_equal:
519 case ia32_cc_not_equal: be_emit_cstring("ne"); return;
520 case ia32_cc_float_below_equal:
521 case ia32_cc_float_unordered_below_equal:
522 case ia32_cc_below_equal: be_emit_cstring("be"); return;
523 case ia32_cc_float_above:
524 case ia32_cc_float_unordered_above:
525 case ia32_cc_above: be_emit_cstring("a"); return;
526 case ia32_cc_sign: be_emit_cstring("s"); return;
527 case ia32_cc_not_sign: be_emit_cstring("ns"); return;
528 case ia32_cc_parity: be_emit_cstring("p"); return;
529 case ia32_cc_not_parity: be_emit_cstring("np"); return;
530 case ia32_cc_less: be_emit_cstring("l"); return;
531 case ia32_cc_greater_equal: be_emit_cstring("ge"); return;
532 case ia32_cc_less_equal: be_emit_cstring("le"); return;
533 case ia32_cc_greater: be_emit_cstring("g"); return;
534 case ia32_cc_float_parity_cases:
535 case ia32_cc_additional_float_cases:
538 panic("Invalid ia32 condition code");
541 typedef enum ia32_emit_mod_t {
543 EMIT_RESPECT_LS = 1U << 0,
544 EMIT_ALTERNATE_AM = 1U << 1,
546 EMIT_HIGH_REG = 1U << 3,
547 EMIT_LOW_REG = 1U << 4
549 ENUM_BITSET(ia32_emit_mod_t)
552 * Emits address mode.
554 void ia32_emit_am(const ir_node *node)
556 ir_entity *ent = get_ia32_am_sc(node);
557 int offs = get_ia32_am_offs_int(node);
558 ir_node *base = get_irn_n(node, n_ia32_base);
559 int has_base = !is_ia32_NoReg_GP(base);
560 ir_node *index = get_irn_n(node, n_ia32_index);
561 int has_index = !is_ia32_NoReg_GP(index);
563 /* just to be sure... */
564 assert(!is_ia32_use_frame(node) || get_ia32_frame_ent(node) != NULL);
566 if (get_ia32_am_tls_segment(node))
567 be_emit_cstring("%gs:");
571 const ia32_attr_t *attr = get_ia32_attr_const(node);
572 if (is_ia32_am_sc_sign(node))
574 ia32_emit_entity(ent, attr->data.am_sc_no_pic_adjust);
577 /* also handle special case if nothing is set */
578 if (offs != 0 || (ent == NULL && !has_base && !has_index)) {
580 be_emit_irprintf("%+d", offs);
582 be_emit_irprintf("%d", offs);
586 if (has_base || has_index) {
591 const arch_register_t *reg = get_in_reg(node, n_ia32_base);
592 emit_register(reg, NULL);
595 /* emit index + scale */
597 const arch_register_t *reg = get_in_reg(node, n_ia32_index);
600 emit_register(reg, NULL);
602 scale = get_ia32_am_scale(node);
604 be_emit_irprintf(",%d", 1 << scale);
612 * fmt parameter output
613 * ---- ---------------------- ---------------------------------------------
615 * %AM <node> address mode of the node
616 * %AR const arch_register_t* address mode of the node or register
617 * %ASx <node> address mode of the node or source register x
618 * %Dx <node> destination register x
619 * %I <node> immediate of the node
620 * %L <node> control flow target of the node
621 * %M <node> mode suffix of the node
622 * %P int condition code
623 * %R const arch_register_t* register
624 * %Sx <node> source register x
625 * %s const char* string
626 * %u unsigned int unsigned int
627 * %d signed int signed int
630 * # modifier for %ASx, %D, %R, and %S uses ls mode of node to alter register width
631 * * modifier does not prefix immediates with $, but AM with *
632 * l modifier for %lu and %ld
633 * > modifier to output high 8bit register (ah, bh)
634 * < modifier to output low 8bit register (al, bl)
636 static void ia32_emitf(const ir_node *node, const char *fmt, ...)
642 const char *start = fmt;
643 ia32_emit_mod_t mod = EMIT_NONE;
645 while (*fmt != '%' && *fmt != '\n' && *fmt != '\0')
648 be_emit_string_len(start, fmt - start);
652 be_emit_finish_line_gas(node);
665 case '*': mod |= EMIT_ALTERNATE_AM; break;
666 case '#': mod |= EMIT_RESPECT_LS; break;
667 case 'l': mod |= EMIT_LONG; break;
668 case '>': mod |= EMIT_HIGH_REG; break;
669 case '<': mod |= EMIT_LOW_REG; break;
686 if (mod & EMIT_ALTERNATE_AM)
692 const arch_register_t *reg = va_arg(ap, const arch_register_t*);
693 if (get_ia32_op_type(node) == ia32_AddrModeS) {
696 if (mod & EMIT_ALTERNATE_AM)
698 emit_register(reg, NULL);
704 if (get_ia32_op_type(node) == ia32_AddrModeS) {
708 assert(get_ia32_op_type(node) == ia32_Normal);
713 default: goto unknown;
720 const arch_register_t *reg;
722 if (*fmt < '0' || '9' <= *fmt)
726 reg = get_out_reg(node, pos);
727 emit_register(reg, mod & EMIT_RESPECT_LS ? get_ia32_ls_mode(node) : NULL);
732 if (!(mod & EMIT_ALTERNATE_AM))
734 emit_ia32_Immediate_no_prefix(node);
738 ia32_emit_cfop_target(node);
742 ia32_emit_mode_suffix_mode(get_ia32_ls_mode(node));
747 ia32_condition_code_t cc = va_arg(ap, ia32_condition_code_t);
748 ia32_emit_condition_code(cc);
753 const arch_register_t *reg = va_arg(ap, const arch_register_t*);
754 if (mod & EMIT_HIGH_REG) {
755 emit_8bit_register_high(reg);
756 } else if (mod & EMIT_LOW_REG) {
757 emit_8bit_register(reg);
759 emit_register(reg, mod & EMIT_RESPECT_LS ? get_ia32_ls_mode(node) : NULL);
769 if (*fmt < '0' || '9' <= *fmt)
773 in = get_irn_n(node, pos);
774 if (is_ia32_Immediate(in)) {
775 if (!(mod & EMIT_ALTERNATE_AM))
777 emit_ia32_Immediate_no_prefix(in);
779 const arch_register_t *reg;
781 if (mod & EMIT_ALTERNATE_AM)
783 reg = get_in_reg(node, pos);
784 emit_register(reg, mod & EMIT_RESPECT_LS ? get_ia32_ls_mode(node) : NULL);
790 const char *str = va_arg(ap, const char*);
796 if (mod & EMIT_LONG) {
797 unsigned long num = va_arg(ap, unsigned long);
798 be_emit_irprintf("%lu", num);
800 unsigned num = va_arg(ap, unsigned);
801 be_emit_irprintf("%u", num);
806 if (mod & EMIT_LONG) {
807 long num = va_arg(ap, long);
808 be_emit_irprintf("%ld", num);
810 int num = va_arg(ap, int);
811 be_emit_irprintf("%d", num);
817 panic("unknown format conversion in ia32_emitf()");
825 * Emits registers and/or address mode of a binary operation.
827 void ia32_emit_binop(const ir_node *node)
829 if (is_ia32_Immediate(get_irn_n(node, n_ia32_binary_right))) {
830 ia32_emitf(node, "%#S4, %#AS3");
832 ia32_emitf(node, "%#AS4, %#S3");
837 * Emits registers and/or address mode of a binary operation.
839 void ia32_emit_x87_binop(const ir_node *node)
841 switch (get_ia32_op_type(node)) {
844 const ia32_x87_attr_t *x87_attr = get_ia32_x87_attr_const(node);
845 const arch_register_t *in1 = x87_attr->x87[0];
846 const arch_register_t *in = x87_attr->x87[1];
847 const arch_register_t *out = x87_attr->x87[2];
851 } else if (out == in) {
856 be_emit_string(arch_register_get_name(in));
857 be_emit_cstring(", %");
858 be_emit_string(arch_register_get_name(out));
866 assert(0 && "unsupported op type");
871 * Emits registers and/or address mode of a unary operation.
873 void ia32_emit_unop(const ir_node *node, int pos)
877 ia32_emitf(node, fmt);
880 static void emit_ia32_IMul(const ir_node *node)
882 ir_node *left = get_irn_n(node, n_ia32_IMul_left);
883 const arch_register_t *out_reg = get_out_reg(node, pn_ia32_IMul_res);
885 /* do we need the 3-address form? */
886 if (is_ia32_NoReg_GP(left) ||
887 get_in_reg(node, n_ia32_IMul_left) != out_reg) {
888 ia32_emitf(node, "\timul%M %#S4, %#AS3, %#D0\n");
890 ia32_emitf(node, "\timul%M %#AS4, %#S3\n");
895 * walks up a tree of copies/perms/spills/reloads to find the original value
896 * that is moved around
898 static ir_node *find_original_value(ir_node *node)
900 if (irn_visited(node))
903 mark_irn_visited(node);
904 if (be_is_Copy(node)) {
905 return find_original_value(be_get_Copy_op(node));
906 } else if (be_is_CopyKeep(node)) {
907 return find_original_value(be_get_CopyKeep_op(node));
908 } else if (is_Proj(node)) {
909 ir_node *pred = get_Proj_pred(node);
910 if (be_is_Perm(pred)) {
911 return find_original_value(get_irn_n(pred, get_Proj_proj(node)));
912 } else if (be_is_MemPerm(pred)) {
913 return find_original_value(get_irn_n(pred, get_Proj_proj(node) + 1));
914 } else if (is_ia32_Load(pred)) {
915 return find_original_value(get_irn_n(pred, n_ia32_Load_mem));
919 } else if (is_ia32_Store(node)) {
920 return find_original_value(get_irn_n(node, n_ia32_Store_val));
921 } else if (is_Phi(node)) {
923 arity = get_irn_arity(node);
924 for (i = 0; i < arity; ++i) {
925 ir_node *in = get_irn_n(node, i);
926 ir_node *res = find_original_value(in);
937 static int determine_final_cc(const ir_node *node, int flags_pos, int cc)
939 ir_node *flags = get_irn_n(node, flags_pos);
940 const ia32_attr_t *flags_attr;
941 flags = skip_Proj(flags);
943 if (is_ia32_Sahf(flags)) {
944 ir_node *cmp = get_irn_n(flags, n_ia32_Sahf_val);
945 if (!(is_ia32_FucomFnstsw(cmp) || is_ia32_FucompFnstsw(cmp)
946 || is_ia32_FucomppFnstsw(cmp) || is_ia32_FtstFnstsw(cmp))) {
947 inc_irg_visited(current_ir_graph);
948 cmp = find_original_value(cmp);
950 assert(is_ia32_FucomFnstsw(cmp) || is_ia32_FucompFnstsw(cmp)
951 || is_ia32_FucomppFnstsw(cmp) || is_ia32_FtstFnstsw(cmp));
954 flags_attr = get_ia32_attr_const(cmp);
956 flags_attr = get_ia32_attr_const(flags);
959 if (flags_attr->data.ins_permuted)
960 cc = ia32_invert_condition_code(cc);
964 void ia32_emit_cmp_suffix_node(const ir_node *node, int flags_pos)
966 ia32_condition_code_t cc = get_ia32_condcode(node);
967 cc = determine_final_cc(node, flags_pos, cc);
969 ia32_emit_condition_code(cc);
973 * Emits an exception label for a given node.
975 static void ia32_emit_exc_label(const ir_node *node)
977 be_emit_string(be_gas_insn_label_prefix());
978 be_emit_irprintf("%lu", get_ia32_exc_label_id(node));
982 * Returns the Proj with projection number proj and NOT mode_M
984 static ir_node *get_proj(const ir_node *node, long proj)
986 const ir_edge_t *edge;
989 assert(get_irn_mode(node) == mode_T && "expected mode_T node");
991 foreach_out_edge(node, edge) {
992 src = get_edge_src_irn(edge);
994 assert(is_Proj(src) && "Proj expected");
995 if (get_irn_mode(src) == mode_M)
998 if (get_Proj_proj(src) == proj)
1004 static int can_be_fallthrough(const ir_node *node)
1006 ir_node *target_block = get_cfop_target_block(node);
1007 ir_node *block = get_nodes_block(node);
1008 return get_prev_block_sched(target_block) == block;
1012 * Emits the jump sequence for a conditional jump (cmp + jmp_true + jmp_false)
1014 static void emit_ia32_Jcc(const ir_node *node)
1016 int need_parity_label = 0;
1017 ia32_condition_code_t cc = get_ia32_condcode(node);
1018 const ir_node *proj_true;
1019 const ir_node *proj_false;
1021 cc = determine_final_cc(node, 0, cc);
1023 /* get both Projs */
1024 proj_true = get_proj(node, pn_ia32_Jcc_true);
1025 assert(proj_true && "Jcc without true Proj");
1027 proj_false = get_proj(node, pn_ia32_Jcc_false);
1028 assert(proj_false && "Jcc without false Proj");
1030 if (can_be_fallthrough(proj_true)) {
1031 /* exchange both proj's so the second one can be omitted */
1032 const ir_node *t = proj_true;
1034 proj_true = proj_false;
1036 cc = ia32_negate_condition_code(cc);
1039 if (cc & ia32_cc_float_parity_cases) {
1040 /* Some floating point comparisons require a test of the parity flag,
1041 * which indicates that the result is unordered */
1042 if (cc & ia32_cc_negated) {
1043 ia32_emitf(proj_true, "\tjp %L\n");
1045 /* we need a local label if the false proj is a fallthrough
1046 * as the falseblock might have no label emitted then */
1047 if (can_be_fallthrough(proj_false)) {
1048 need_parity_label = 1;
1049 ia32_emitf(proj_false, "\tjp 1f\n");
1051 ia32_emitf(proj_false, "\tjp %L\n");
1055 ia32_emitf(proj_true, "\tj%P %L\n", cc);
1056 if (need_parity_label) {
1057 ia32_emitf(NULL, "1:\n");
1060 /* the second Proj might be a fallthrough */
1061 if (can_be_fallthrough(proj_false)) {
1062 ia32_emitf(proj_false, "\t/* fallthrough to %L */\n");
1064 ia32_emitf(proj_false, "\tjmp %L\n");
1069 * Emits an ia32 Setcc. This is mostly easy but some floating point compares
1072 static void emit_ia32_Setcc(const ir_node *node)
1074 const arch_register_t *dreg = get_out_reg(node, pn_ia32_Setcc_res);
1076 ia32_condition_code_t cc = get_ia32_condcode(node);
1077 cc = determine_final_cc(node, n_ia32_Setcc_eflags, cc);
1078 if (cc & ia32_cc_float_parity_cases) {
1079 if (cc & ia32_cc_negated) {
1080 ia32_emitf(node, "\tset%P %<R\n", cc, dreg);
1081 ia32_emitf(node, "\tsetp %>R\n", dreg);
1082 ia32_emitf(node, "\torb %>R, %<R\n", dreg, dreg);
1084 ia32_emitf(node, "\tset%P %<R\n", cc, dreg);
1085 ia32_emitf(node, "\tsetnp %>R\n", dreg);
1086 ia32_emitf(node, "\tandb %>R, %<R\n", dreg, dreg);
1089 ia32_emitf(node, "\tset%P %#R\n", cc, dreg);
1093 static void emit_ia32_CMovcc(const ir_node *node)
1095 const ia32_attr_t *attr = get_ia32_attr_const(node);
1096 const arch_register_t *out = arch_irn_get_register(node, pn_ia32_res);
1097 ia32_condition_code_t cc = get_ia32_condcode(node);
1098 const arch_register_t *in_true;
1099 const arch_register_t *in_false;
1101 cc = determine_final_cc(node, n_ia32_CMovcc_eflags, cc);
1102 /* although you can't set ins_permuted in the constructor it might still
1103 * be set by memory operand folding
1104 * Permuting inputs of a cmov means the condition is negated!
1106 if (attr->data.ins_permuted)
1107 cc = ia32_negate_condition_code(cc);
1109 in_true = arch_get_irn_register(get_irn_n(node, n_ia32_CMovcc_val_true));
1110 in_false = arch_get_irn_register(get_irn_n(node, n_ia32_CMovcc_val_false));
1112 /* should be same constraint fullfilled? */
1113 if (out == in_false) {
1114 /* yes -> nothing to do */
1115 } else if (out == in_true) {
1116 const arch_register_t *tmp;
1118 assert(get_ia32_op_type(node) == ia32_Normal);
1120 cc = ia32_negate_condition_code(cc);
1127 ia32_emitf(node, "\tmovl %R, %R\n", in_false, out);
1130 if (cc & ia32_cc_float_parity_cases) {
1131 panic("CMov with floatingpoint compare/parity not supported yet");
1134 ia32_emitf(node, "\tcmov%P %#AR, %#R\n", cc, in_true, out);
1138 * Emits code for a SwitchJmp
1140 static void emit_ia32_SwitchJmp(const ir_node *node)
1142 ir_entity *jump_table = get_ia32_am_sc(node);
1143 long default_pn = get_ia32_default_pn(node);
1145 ia32_emitf(node, "\tjmp *%AM\n", node);
1147 emit_jump_table(node, default_pn, jump_table, get_cfop_target_block);
1151 * Emits code for a unconditional jump.
1153 static void emit_ia32_Jmp(const ir_node *node)
1155 /* we have a block schedule */
1156 if (can_be_fallthrough(node)) {
1157 ia32_emitf(node, "\t/* fallthrough to %L */\n");
1159 ia32_emitf(node, "\tjmp %L\n");
1164 * Emit an inline assembler operand.
1166 * @param node the ia32_ASM node
1167 * @param s points to the operand (a %c)
1169 * @return pointer to the first char in s NOT in the current operand
1171 static const char* emit_asm_operand(const ir_node *node, const char *s)
1173 const ia32_attr_t *ia32_attr = get_ia32_attr_const(node);
1174 const ia32_asm_attr_t *attr = CONST_CAST_IA32_ATTR(ia32_asm_attr_t,
1176 const arch_register_t *reg;
1177 const ia32_asm_reg_t *asm_regs = attr->register_map;
1178 const ia32_asm_reg_t *asm_reg;
1187 /* parse modifiers */
1190 ir_fprintf(stderr, "Warning: asm text (%+F) ends with %%\n", node);
1215 "Warning: asm text (%+F) contains unknown modifier '%c' for asm op\n",
1222 if (sscanf(s, "%d%n", &num, &p) != 1) {
1223 ir_fprintf(stderr, "Warning: Couldn't parse assembler operand (%+F)\n",
1230 if (num < 0 || ARR_LEN(asm_regs) <= (size_t)num) {
1232 "Error: Custom assembler references invalid input/output (%+F)\n",
1236 asm_reg = & asm_regs[num];
1237 assert(asm_reg->valid);
1240 if (asm_reg->use_input == 0) {
1241 reg = get_out_reg(node, asm_reg->inout_pos);
1243 ir_node *pred = get_irn_n(node, asm_reg->inout_pos);
1245 /* might be an immediate value */
1246 if (is_ia32_Immediate(pred)) {
1247 emit_ia32_Immediate(pred);
1250 reg = get_in_reg(node, asm_reg->inout_pos);
1254 "Warning: no register assigned for %d asm op (%+F)\n",
1259 if (asm_reg->memory) {
1264 if (modifier != 0) {
1267 emit_8bit_register(reg);
1270 emit_8bit_register_high(reg);
1273 emit_16bit_register(reg);
1276 panic("Invalid asm op modifier");
1279 emit_register(reg, asm_reg->mode);
1282 if (asm_reg->memory) {
1290 * Emits code for an ASM pseudo op.
1292 static void emit_ia32_Asm(const ir_node *node)
1294 const void *gen_attr = get_irn_generic_attr_const(node);
1295 const ia32_asm_attr_t *attr
1296 = CONST_CAST_IA32_ATTR(ia32_asm_attr_t, gen_attr);
1297 ident *asm_text = attr->asm_text;
1298 const char *s = get_id_str(asm_text);
1300 ia32_emitf(node, "#APP\t\n");
1307 s = emit_asm_operand(node, s);
1313 ia32_emitf(NULL, "\n#NO_APP\n");
1318 * Emit movsb/w instructions to make mov count divideable by 4
1320 static void emit_CopyB_prolog(unsigned size)
1323 ia32_emitf(NULL, "\tmovsb\n");
1325 ia32_emitf(NULL, "\tmovsw\n");
1329 * Emit rep movsd instruction for memcopy.
1331 static void emit_ia32_CopyB(const ir_node *node)
1333 unsigned size = get_ia32_copyb_size(node);
1335 emit_CopyB_prolog(size);
1336 ia32_emitf(node, "\trep movsd\n");
1340 * Emits unrolled memcopy.
1342 static void emit_ia32_CopyB_i(const ir_node *node)
1344 unsigned size = get_ia32_copyb_size(node);
1346 emit_CopyB_prolog(size);
1350 ia32_emitf(NULL, "\tmovsd\n");
1356 * Emit code for conversions (I, FP), (FP, I) and (FP, FP).
1358 static void emit_ia32_Conv_with_FP(const ir_node *node, const char* conv_f,
1361 ir_mode *ls_mode = get_ia32_ls_mode(node);
1362 int ls_bits = get_mode_size_bits(ls_mode);
1363 const char *conv = ls_bits == 32 ? conv_f : conv_d;
1365 ia32_emitf(node, "\tcvt%s %AS3, %D0\n", conv);
1368 static void emit_ia32_Conv_I2FP(const ir_node *node)
1370 emit_ia32_Conv_with_FP(node, "si2ss", "si2sd");
1373 static void emit_ia32_Conv_FP2I(const ir_node *node)
1375 emit_ia32_Conv_with_FP(node, "ss2si", "sd2si");
1378 static void emit_ia32_Conv_FP2FP(const ir_node *node)
1380 emit_ia32_Conv_with_FP(node, "sd2ss", "ss2sd");
1384 * Emits code for an Int conversion.
1386 static void emit_ia32_Conv_I2I(const ir_node *node)
1388 ir_mode *smaller_mode = get_ia32_ls_mode(node);
1389 int signed_mode = mode_is_signed(smaller_mode);
1390 const char *sign_suffix;
1392 assert(!mode_is_float(smaller_mode));
1394 sign_suffix = signed_mode ? "s" : "z";
1395 ia32_emitf(node, "\tmov%s%Ml %#AS3, %D0\n", sign_suffix);
1401 static void emit_ia32_Call(const ir_node *node)
1403 /* Special case: Call must not have its immediates prefixed by $, instead
1404 * address mode is prefixed by *. */
1405 ia32_emitf(node, "\tcall %*AS3\n");
1410 * Emits code to increase stack pointer.
1412 static void emit_be_IncSP(const ir_node *node)
1414 int offs = be_get_IncSP_offset(node);
1420 ia32_emitf(node, "\tsubl $%u, %D0\n", offs);
1422 ia32_emitf(node, "\taddl $%u, %D0\n", -offs);
1427 * Emits code for Copy/CopyKeep.
1429 static void Copy_emitter(const ir_node *node, const ir_node *op)
1431 const arch_register_t *in = arch_get_irn_register(op);
1432 const arch_register_t *out = arch_get_irn_register(node);
1437 /* copies of vf nodes aren't real... */
1438 if (arch_register_get_class(in) == &ia32_reg_classes[CLASS_ia32_vfp])
1441 if (get_irn_mode(node) == mode_E) {
1442 ia32_emitf(node, "\tmovsd %R, %R\n", in, out);
1444 ia32_emitf(node, "\tmovl %R, %R\n", in, out);
1448 static void emit_be_Copy(const ir_node *node)
1450 Copy_emitter(node, be_get_Copy_op(node));
1453 static void emit_be_CopyKeep(const ir_node *node)
1455 Copy_emitter(node, be_get_CopyKeep_op(node));
1459 * Emits code for exchange.
1461 static void emit_be_Perm(const ir_node *node)
1463 const arch_register_t *in0, *in1;
1464 const arch_register_class_t *cls0, *cls1;
1466 in0 = arch_get_irn_register(get_irn_n(node, 0));
1467 in1 = arch_get_irn_register(get_irn_n(node, 1));
1469 cls0 = arch_register_get_class(in0);
1470 cls1 = arch_register_get_class(in1);
1472 assert(cls0 == cls1 && "Register class mismatch at Perm");
1474 if (cls0 == &ia32_reg_classes[CLASS_ia32_gp]) {
1475 ia32_emitf(node, "\txchg %R, %R\n", in1, in0);
1476 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_xmm]) {
1477 ia32_emitf(NULL, "\txorpd %R, %R\n", in1, in0);
1478 ia32_emitf(NULL, "\txorpd %R, %R\n", in0, in1);
1479 ia32_emitf(node, "\txorpd %R, %R\n", in1, in0);
1480 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_vfp]) {
1482 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_st]) {
1485 panic("unexpected register class in be_Perm (%+F)", node);
1490 * Emits code for Constant loading.
1492 static void emit_ia32_Const(const ir_node *node)
1494 ia32_emitf(node, "\tmovl %I, %D0\n");
1497 /* helper function for emit_ia32_Minus64Bit */
1498 static void emit_mov(const ir_node* node, const arch_register_t *src, const arch_register_t *dst)
1500 ia32_emitf(node, "\tmovl %R, %R\n", src, dst);
1503 /* helper function for emit_ia32_Minus64Bit */
1504 static void emit_neg(const ir_node* node, const arch_register_t *reg)
1506 ia32_emitf(node, "\tnegl %R\n", reg);
1509 /* helper function for emit_ia32_Minus64Bit */
1510 static void emit_sbb0(const ir_node* node, const arch_register_t *reg)
1512 ia32_emitf(node, "\tsbbl $0, %R\n", reg);
1515 /* helper function for emit_ia32_Minus64Bit */
1516 static void emit_sbb(const ir_node* node, const arch_register_t *src, const arch_register_t *dst)
1518 ia32_emitf(node, "\tsbbl %R, %R\n", src, dst);
1521 /* helper function for emit_ia32_Minus64Bit */
1522 static void emit_xchg(const ir_node* node, const arch_register_t *src, const arch_register_t *dst)
1524 ia32_emitf(node, "\txchgl %R, %R\n", src, dst);
1527 /* helper function for emit_ia32_Minus64Bit */
1528 static void emit_zero(const ir_node* node, const arch_register_t *reg)
1530 ia32_emitf(node, "\txorl %R, %R\n", reg, reg);
1533 static void emit_ia32_Minus64Bit(const ir_node *node)
1535 const arch_register_t *in_lo = get_in_reg(node, 0);
1536 const arch_register_t *in_hi = get_in_reg(node, 1);
1537 const arch_register_t *out_lo = get_out_reg(node, 0);
1538 const arch_register_t *out_hi = get_out_reg(node, 1);
1540 if (out_lo == in_lo) {
1541 if (out_hi != in_hi) {
1542 /* a -> a, b -> d */
1545 /* a -> a, b -> b */
1548 } else if (out_lo == in_hi) {
1549 if (out_hi == in_lo) {
1550 /* a -> b, b -> a */
1551 emit_xchg(node, in_lo, in_hi);
1554 /* a -> b, b -> d */
1555 emit_mov(node, in_hi, out_hi);
1556 emit_mov(node, in_lo, out_lo);
1560 if (out_hi == in_lo) {
1561 /* a -> c, b -> a */
1562 emit_mov(node, in_lo, out_lo);
1564 } else if (out_hi == in_hi) {
1565 /* a -> c, b -> b */
1566 emit_mov(node, in_lo, out_lo);
1569 /* a -> c, b -> d */
1570 emit_mov(node, in_lo, out_lo);
1576 emit_neg( node, out_hi);
1577 emit_neg( node, out_lo);
1578 emit_sbb0(node, out_hi);
1582 emit_zero(node, out_hi);
1583 emit_neg( node, out_lo);
1584 emit_sbb( node, in_hi, out_hi);
1587 static void emit_ia32_GetEIP(const ir_node *node)
1589 ia32_emitf(node, "\tcall %s\n", pic_base_label);
1590 ia32_emitf(NULL, "%s:\n", pic_base_label);
1591 ia32_emitf(node, "\tpopl %D0\n");
1594 static void emit_ia32_ClimbFrame(const ir_node *node)
1596 const ia32_climbframe_attr_t *attr = get_ia32_climbframe_attr_const(node);
1598 ia32_emitf(node, "\tmovl %S0, %D0\n");
1599 ia32_emitf(node, "\tmovl $%u, %S1\n", attr->count);
1600 be_gas_emit_block_name(node);
1601 be_emit_cstring(":\n");
1602 be_emit_write_line();
1603 ia32_emitf(node, "\tmovl (%D0), %D0\n");
1604 ia32_emitf(node, "\tdec %S1\n");
1605 be_emit_cstring("\tjnz ");
1606 be_gas_emit_block_name(node);
1607 be_emit_finish_line_gas(node);
1610 static void emit_be_Return(const ir_node *node)
1612 unsigned pop = be_Return_get_pop(node);
1614 if (pop > 0 || be_Return_get_emit_pop(node)) {
1615 ia32_emitf(node, "\tret $%u\n", pop);
1617 ia32_emitf(node, "\tret\n");
1621 static void emit_Nothing(const ir_node *node)
1628 * Enters the emitter functions for handled nodes into the generic
1629 * pointer of an opcode.
1631 static void ia32_register_emitters(void)
1633 #define IA32_EMIT2(a,b) op_ia32_##a->ops.generic = (op_func)emit_ia32_##b
1634 #define IA32_EMIT(a) IA32_EMIT2(a,a)
1635 #define EMIT(a) op_##a->ops.generic = (op_func)emit_##a
1636 #define IGN(a) op_##a->ops.generic = (op_func)emit_Nothing
1637 #define BE_EMIT(a) op_be_##a->ops.generic = (op_func)emit_be_##a
1638 #define BE_IGN(a) op_be_##a->ops.generic = (op_func)emit_Nothing
1640 /* first clear the generic function pointer for all ops */
1641 clear_irp_opcodes_generic_func();
1643 /* register all emitter functions defined in spec */
1644 ia32_register_spec_emitters();
1646 /* other ia32 emitter functions */
1647 IA32_EMIT2(Conv_I2I8Bit, Conv_I2I);
1652 IA32_EMIT(Conv_FP2FP);
1653 IA32_EMIT(Conv_FP2I);
1654 IA32_EMIT(Conv_I2FP);
1655 IA32_EMIT(Conv_I2I);
1662 IA32_EMIT(Minus64Bit);
1663 IA32_EMIT(SwitchJmp);
1664 IA32_EMIT(ClimbFrame);
1667 /* benode emitter */
1687 typedef void (*emit_func_ptr) (const ir_node *);
1690 * Assign and emit an exception label if the current instruction can fail.
1692 static void ia32_assign_exc_label(ir_node *node)
1694 /* assign a new ID to the instruction */
1695 set_ia32_exc_label_id(node, ++exc_label_id);
1697 ia32_emit_exc_label(node);
1699 be_emit_pad_comment();
1700 be_emit_cstring("/* exception to Block ");
1701 ia32_emit_cfop_target(node);
1702 be_emit_cstring(" */\n");
1703 be_emit_write_line();
1707 * Emits code for a node.
1709 static void ia32_emit_node(ir_node *node)
1711 ir_op *op = get_irn_op(node);
1713 DBG((dbg, LEVEL_1, "emitting code for %+F\n", node));
1715 if (is_ia32_irn(node)) {
1716 if (get_ia32_exc_label(node)) {
1717 /* emit the exception label of this instruction */
1718 ia32_assign_exc_label(node);
1720 if (mark_spill_reload) {
1721 if (is_ia32_is_spill(node)) {
1722 ia32_emitf(NULL, "\txchg %ebx, %ebx /* spill mark */\n");
1724 if (is_ia32_is_reload(node)) {
1725 ia32_emitf(NULL, "\txchg %edx, %edx /* reload mark */\n");
1727 if (is_ia32_is_remat(node)) {
1728 ia32_emitf(NULL, "\txchg %ecx, %ecx /* remat mark */\n");
1732 if (op->ops.generic) {
1733 emit_func_ptr func = (emit_func_ptr) op->ops.generic;
1735 be_dbg_set_dbg_info(get_irn_dbg_info(node));
1740 ir_fprintf(stderr, "Error: No emit handler for node %+F (%+G, graph %+F)\n", node, node, current_ir_graph);
1746 * Emits gas alignment directives
1748 static void ia32_emit_alignment(unsigned align, unsigned skip)
1750 ia32_emitf(NULL, "\t.p2align %u,,%u\n", align, skip);
1754 * Emits gas alignment directives for Labels depended on cpu architecture.
1756 static void ia32_emit_align_label(void)
1758 unsigned align = ia32_cg_config.label_alignment;
1759 unsigned maximum_skip = ia32_cg_config.label_alignment_max_skip;
1760 ia32_emit_alignment(align, maximum_skip);
1764 * Test whether a block should be aligned.
1765 * For cpus in the P4/Athlon class it is useful to align jump labels to
1766 * 16 bytes. However we should only do that if the alignment nops before the
1767 * label aren't executed more often than we have jumps to the label.
1769 static int should_align_block(const ir_node *block)
1771 static const double DELTA = .0001;
1772 ir_graph *irg = get_irn_irg(block);
1773 ir_exec_freq *exec_freq = be_get_irg_exec_freq(irg);
1774 ir_node *prev = get_prev_block_sched(block);
1776 double prev_freq = 0; /**< execfreq of the fallthrough block */
1777 double jmp_freq = 0; /**< execfreq of all non-fallthrough blocks */
1780 if (exec_freq == NULL)
1782 if (ia32_cg_config.label_alignment_factor <= 0)
1785 block_freq = get_block_execfreq(exec_freq, block);
1786 if (block_freq < DELTA)
1789 n_cfgpreds = get_Block_n_cfgpreds(block);
1790 for (i = 0; i < n_cfgpreds; ++i) {
1791 const ir_node *pred = get_Block_cfgpred_block(block, i);
1792 double pred_freq = get_block_execfreq(exec_freq, pred);
1795 prev_freq += pred_freq;
1797 jmp_freq += pred_freq;
1801 if (prev_freq < DELTA && !(jmp_freq < DELTA))
1804 jmp_freq /= prev_freq;
1806 return jmp_freq > ia32_cg_config.label_alignment_factor;
1810 * Emit the block header for a block.
1812 * @param block the block
1813 * @param prev_block the previous block
1815 static void ia32_emit_block_header(ir_node *block)
1817 ir_graph *irg = current_ir_graph;
1818 int need_label = block_needs_label(block);
1820 ir_exec_freq *exec_freq = be_get_irg_exec_freq(irg);
1822 if (block == get_irg_end_block(irg))
1825 if (ia32_cg_config.label_alignment > 0) {
1826 /* align the current block if:
1827 * a) if should be aligned due to its execution frequency
1828 * b) there is no fall-through here
1830 if (should_align_block(block)) {
1831 ia32_emit_align_label();
1833 /* if the predecessor block has no fall-through,
1834 we can always align the label. */
1836 int has_fallthrough = 0;
1838 for (i = get_Block_n_cfgpreds(block) - 1; i >= 0; --i) {
1839 ir_node *cfg_pred = get_Block_cfgpred(block, i);
1840 if (can_be_fallthrough(cfg_pred)) {
1841 has_fallthrough = 1;
1846 if (!has_fallthrough)
1847 ia32_emit_align_label();
1852 be_gas_emit_block_name(block);
1855 be_emit_pad_comment();
1856 be_emit_cstring(" /* ");
1858 be_emit_cstring("\t/* ");
1859 be_gas_emit_block_name(block);
1860 be_emit_cstring(": ");
1863 be_emit_cstring("preds:");
1865 /* emit list of pred blocks in comment */
1866 arity = get_irn_arity(block);
1868 be_emit_cstring(" none");
1870 for (i = 0; i < arity; ++i) {
1871 ir_node *predblock = get_Block_cfgpred_block(block, i);
1872 be_emit_irprintf(" %d", get_irn_node_nr(predblock));
1875 if (exec_freq != NULL) {
1876 be_emit_irprintf(", freq: %f",
1877 get_block_execfreq(exec_freq, block));
1879 be_emit_cstring(" */\n");
1880 be_emit_write_line();
1884 * Walks over the nodes in a block connected by scheduling edges
1885 * and emits code for each node.
1887 static void ia32_gen_block(ir_node *block)
1891 ia32_emit_block_header(block);
1893 /* emit the contents of the block */
1894 be_dbg_set_dbg_info(get_irn_dbg_info(block));
1895 sched_foreach(block, node) {
1896 ia32_emit_node(node);
1900 typedef struct exc_entry {
1901 ir_node *exc_instr; /** The instruction that can issue an exception. */
1902 ir_node *block; /** The block to call then. */
1907 * Sets labels for control flow nodes (jump target).
1908 * Links control predecessors to there destination blocks.
1910 static void ia32_gen_labels(ir_node *block, void *data)
1912 exc_entry **exc_list = (exc_entry**)data;
1916 for (n = get_Block_n_cfgpreds(block) - 1; n >= 0; --n) {
1917 pred = get_Block_cfgpred(block, n);
1918 set_irn_link(pred, block);
1920 pred = skip_Proj(pred);
1921 if (is_ia32_irn(pred) && get_ia32_exc_label(pred)) {
1926 ARR_APP1(exc_entry, *exc_list, e);
1927 set_irn_link(pred, block);
1933 * Compare two exception_entries.
1935 static int cmp_exc_entry(const void *a, const void *b)
1937 const exc_entry *ea = (const exc_entry*)a;
1938 const exc_entry *eb = (const exc_entry*)b;
1940 if (get_ia32_exc_label_id(ea->exc_instr) < get_ia32_exc_label_id(eb->exc_instr))
1946 * Main driver. Emits the code for one routine.
1948 void ia32_gen_routine(ir_graph *irg)
1950 ir_entity *entity = get_irg_entity(irg);
1951 exc_entry *exc_list = NEW_ARR_F(exc_entry, 0);
1952 const arch_env_t *arch_env = be_get_irg_arch_env(irg);
1953 ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
1954 ir_node **blk_sched = irg_data->blk_sched;
1957 isa = (ia32_isa_t*) arch_env;
1958 do_pic = be_get_irg_options(irg)->pic;
1960 be_gas_elf_type_char = '@';
1962 ia32_register_emitters();
1964 get_unique_label(pic_base_label, sizeof(pic_base_label), "PIC_BASE");
1966 be_dbg_method_begin(entity);
1967 be_gas_emit_function_prolog(entity, ia32_cg_config.function_alignment);
1969 /* we use links to point to target blocks */
1970 ir_reserve_resources(irg, IR_RESOURCE_IRN_LINK);
1971 irg_block_walk_graph(irg, ia32_gen_labels, NULL, &exc_list);
1973 /* initialize next block links */
1974 n = ARR_LEN(blk_sched);
1975 for (i = 0; i < n; ++i) {
1976 ir_node *block = blk_sched[i];
1977 ir_node *prev = i > 0 ? blk_sched[i-1] : NULL;
1979 set_irn_link(block, prev);
1982 for (i = 0; i < n; ++i) {
1983 ir_node *block = blk_sched[i];
1985 ia32_gen_block(block);
1988 be_gas_emit_function_epilog(entity);
1989 be_dbg_method_end();
1991 be_emit_write_line();
1993 ir_free_resources(irg, IR_RESOURCE_IRN_LINK);
1995 /* Sort the exception table using the exception label id's.
1996 Those are ascending with ascending addresses. */
1997 qsort(exc_list, ARR_LEN(exc_list), sizeof(exc_list[0]), cmp_exc_entry);
2001 for (i = 0; i < ARR_LEN(exc_list); ++i) {
2002 be_emit_cstring("\t.long ");
2003 ia32_emit_exc_label(exc_list[i].exc_instr);
2005 be_emit_cstring("\t.long ");
2006 be_gas_emit_block_name(exc_list[i].block);
2010 DEL_ARR_F(exc_list);
2013 static const lc_opt_table_entry_t ia32_emitter_options[] = {
2014 LC_OPT_ENT_BOOL("mark_spill_reload", "mark spills and reloads with ud opcodes", &mark_spill_reload),
2018 /* ==== Experimental binary emitter ==== */
2020 static unsigned char reg_gp_map[N_ia32_gp_REGS];
2021 //static unsigned char reg_mmx_map[N_ia32_mmx_REGS];
2022 //static unsigned char reg_sse_map[N_ia32_xmm_REGS];
2024 static void build_reg_map(void)
2026 reg_gp_map[REG_GP_EAX] = 0x0;
2027 reg_gp_map[REG_GP_ECX] = 0x1;
2028 reg_gp_map[REG_GP_EDX] = 0x2;
2029 reg_gp_map[REG_GP_EBX] = 0x3;
2030 reg_gp_map[REG_GP_ESP] = 0x4;
2031 reg_gp_map[REG_GP_EBP] = 0x5;
2032 reg_gp_map[REG_GP_ESI] = 0x6;
2033 reg_gp_map[REG_GP_EDI] = 0x7;
2036 /** Returns the encoding for a pnc field. */
2037 static unsigned char pnc2cc(ia32_condition_code_t cc)
2042 /** Sign extension bit values for binops */
2044 UNSIGNED_IMM = 0, /**< unsigned immediate */
2045 SIGNEXT_IMM = 2, /**< sign extended immediate */
2048 /** The mod encoding of the ModR/M */
2050 MOD_IND = 0x00, /**< [reg1] */
2051 MOD_IND_BYTE_OFS = 0x40, /**< [reg1 + byte ofs] */
2052 MOD_IND_WORD_OFS = 0x80, /**< [reg1 + word ofs] */
2053 MOD_REG = 0xC0 /**< reg1 */
2056 /** create R/M encoding for ModR/M */
2057 #define ENC_RM(x) (x)
2058 /** create REG encoding for ModR/M */
2059 #define ENC_REG(x) ((x) << 3)
2061 /** create encoding for a SIB byte */
2062 #define ENC_SIB(scale, index, base) ((scale) << 6 | (index) << 3 | (base))
2064 /* Node: The following routines are supposed to append bytes, words, dwords
2065 to the output stream.
2066 Currently the implementation is stupid in that it still creates output
2067 for an "assembler" in the form of .byte, .long
2068 We will change this when enough infrastructure is there to create complete
2069 machine code in memory/object files */
2071 static void bemit8(const unsigned char byte)
2073 be_emit_irprintf("\t.byte 0x%x\n", byte);
2074 be_emit_write_line();
2077 static void bemit16(const unsigned short u16)
2079 be_emit_irprintf("\t.word 0x%x\n", u16);
2080 be_emit_write_line();
2083 static void bemit32(const unsigned u32)
2085 be_emit_irprintf("\t.long 0x%x\n", u32);
2086 be_emit_write_line();
2090 * Emit address of an entity. If @p is_relative is true then a relative
2091 * offset from behind the address to the entity is created.
2093 static void bemit_entity(ir_entity *entity, bool entity_sign, int offset,
2096 if (entity == NULL) {
2101 /* the final version should remember the position in the bytestream
2102 and patch it with the correct address at linktime... */
2103 be_emit_cstring("\t.long ");
2106 be_gas_emit_entity(entity);
2108 if (get_entity_owner(entity) == get_tls_type()) {
2109 if (get_entity_visibility(entity) == ir_visibility_external) {
2110 be_emit_cstring("@INDNTPOFF");
2112 be_emit_cstring("@NTPOFF");
2117 be_emit_cstring("-.");
2122 be_emit_irprintf("%+d", offset);
2125 be_emit_write_line();
2128 static void bemit_jmp_destination(const ir_node *dest_block)
2130 be_emit_cstring("\t.long ");
2131 be_gas_emit_block_name(dest_block);
2132 be_emit_cstring(" - . - 4\n");
2133 be_emit_write_line();
2136 /* end emit routines, all emitters following here should only use the functions
2139 typedef enum reg_modifier {
2144 /** Create a ModR/M byte for src1,src2 registers */
2145 static void bemit_modrr(const arch_register_t *src1,
2146 const arch_register_t *src2)
2148 unsigned char modrm = MOD_REG;
2149 modrm |= ENC_RM(reg_gp_map[src1->index]);
2150 modrm |= ENC_REG(reg_gp_map[src2->index]);
2154 /** Create a ModR/M8 byte for src1,src2 registers */
2155 static void bemit_modrr8(reg_modifier_t high_part1, const arch_register_t *src1,
2156 reg_modifier_t high_part2, const arch_register_t *src2)
2158 unsigned char modrm = MOD_REG;
2159 modrm |= ENC_RM(reg_gp_map[src1->index] + (high_part1 == REG_HIGH ? 4 : 0));
2160 modrm |= ENC_REG(reg_gp_map[src2->index] + (high_part2 == REG_HIGH ? 4 : 0));
2164 /** Create a ModR/M byte for one register and extension */
2165 static void bemit_modru(const arch_register_t *reg, unsigned ext)
2167 unsigned char modrm = MOD_REG;
2169 modrm |= ENC_RM(reg_gp_map[reg->index]);
2170 modrm |= ENC_REG(ext);
2174 /** Create a ModR/M8 byte for one register */
2175 static void bemit_modrm8(reg_modifier_t high_part, const arch_register_t *reg)
2177 unsigned char modrm = MOD_REG;
2178 assert(reg_gp_map[reg->index] < 4);
2179 modrm |= ENC_RM(reg_gp_map[reg->index] + (high_part == REG_HIGH ? 4 : 0));
2185 * Calculate the size of an signed immediate in bytes.
2187 * @param offset an offset
2189 static unsigned get_signed_imm_size(int offset)
2191 if (-128 <= offset && offset < 128) {
2193 } else if (-32768 <= offset && offset < 32768) {
2201 * Emit an address mode.
2203 * @param reg content of the reg field: either a register index or an opcode extension
2204 * @param node the node
2206 static void bemit_mod_am(unsigned reg, const ir_node *node)
2208 ir_entity *ent = get_ia32_am_sc(node);
2209 int offs = get_ia32_am_offs_int(node);
2210 ir_node *base = get_irn_n(node, n_ia32_base);
2211 int has_base = !is_ia32_NoReg_GP(base);
2212 ir_node *index = get_irn_n(node, n_ia32_index);
2213 int has_index = !is_ia32_NoReg_GP(index);
2216 unsigned emitoffs = 0;
2217 bool emitsib = false;
2220 /* set the mod part depending on displacement */
2222 modrm |= MOD_IND_WORD_OFS;
2224 } else if (offs == 0) {
2227 } else if (-128 <= offs && offs < 128) {
2228 modrm |= MOD_IND_BYTE_OFS;
2231 modrm |= MOD_IND_WORD_OFS;
2236 const arch_register_t *base_reg = arch_get_irn_register(base);
2237 base_enc = reg_gp_map[base_reg->index];
2239 /* Use the EBP encoding + MOD_IND if NO base register. There is
2240 * always a 32bit offset present in this case. */
2246 /* Determine if we need a SIB byte. */
2248 const arch_register_t *reg_index = arch_get_irn_register(index);
2249 int scale = get_ia32_am_scale(node);
2251 /* R/M set to ESP means SIB in 32bit mode. */
2252 modrm |= ENC_RM(0x04);
2253 sib = ENC_SIB(scale, reg_gp_map[reg_index->index], base_enc);
2255 } else if (base_enc == 0x04) {
2256 /* for the above reason we are forced to emit a SIB when base is ESP.
2257 * Only the base is used, index must be ESP too, which means no index.
2259 modrm |= ENC_RM(0x04);
2260 sib = ENC_SIB(0, 0x04, 0x04);
2263 modrm |= ENC_RM(base_enc);
2266 /* We are forced to emit an 8bit offset as EBP base without offset is a
2267 * special case for SIB without base register. */
2268 if (base_enc == 0x05 && emitoffs == 0) {
2269 modrm |= MOD_IND_BYTE_OFS;
2273 modrm |= ENC_REG(reg);
2279 /* emit displacement */
2280 if (emitoffs == 8) {
2281 bemit8((unsigned) offs);
2282 } else if (emitoffs == 32) {
2283 bemit_entity(ent, is_ia32_am_sc_sign(node), offs, false);
2288 * Emit a binop with a immediate operand.
2290 * @param node the node to emit
2291 * @param opcode_eax the opcode for the op eax, imm variant
2292 * @param opcode the opcode for the reg, imm variant
2293 * @param ruval the opcode extension for opcode
2295 static void bemit_binop_with_imm(
2296 const ir_node *node,
2297 unsigned char opcode_ax,
2298 unsigned char opcode, unsigned char ruval)
2300 /* Use in-reg, because some instructions (cmp, test) have no out-reg. */
2301 const ir_node *op = get_irn_n(node, n_ia32_binary_right);
2302 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(op);
2305 /* Some instructions (test) have no short form with 32bit value + 8bit
2307 if (attr->symconst != NULL || opcode & SIGNEXT_IMM) {
2310 /* check for sign extension */
2311 size = get_signed_imm_size(attr->offset);
2316 bemit8(opcode | SIGNEXT_IMM);
2317 /* cmp has this special mode */
2318 if (get_ia32_op_type(node) == ia32_AddrModeS) {
2319 bemit_mod_am(ruval, node);
2321 const arch_register_t *reg = get_in_reg(node, n_ia32_binary_left);
2322 bemit_modru(reg, ruval);
2324 bemit8((unsigned char)attr->offset);
2328 /* check for eax variant: this variant is shorter for 32bit immediates only */
2329 if (get_ia32_op_type(node) == ia32_AddrModeS) {
2331 bemit_mod_am(ruval, node);
2333 const arch_register_t *reg = get_in_reg(node, n_ia32_binary_left);
2334 if (reg->index == REG_GP_EAX) {
2338 bemit_modru(reg, ruval);
2341 bemit_entity(attr->symconst, attr->sc_sign, attr->offset, false);
2344 panic("invalid imm size?!?");
2350 static void bemit_binop_2(const ir_node *node, unsigned code)
2352 const arch_register_t *out = get_in_reg(node, n_ia32_binary_left);
2354 if (get_ia32_op_type(node) == ia32_Normal) {
2355 const arch_register_t *op2 = get_in_reg(node, n_ia32_binary_right);
2356 bemit_modrr(op2, out);
2358 bemit_mod_am(reg_gp_map[out->index], node);
2365 static void bemit_binop(const ir_node *node, const unsigned char opcodes[4])
2367 ir_node *right = get_irn_n(node, n_ia32_binary_right);
2368 if (is_ia32_Immediate(right)) {
2369 bemit_binop_with_imm(node, opcodes[1], opcodes[2], opcodes[3]);
2371 bemit_binop_2(node, opcodes[0]);
2378 static void bemit_unop(const ir_node *node, unsigned char code, unsigned char ext, int input)
2381 if (get_ia32_op_type(node) == ia32_Normal) {
2382 const arch_register_t *in = get_in_reg(node, input);
2383 bemit_modru(in, ext);
2385 bemit_mod_am(ext, node);
2389 static void bemit_unop_reg(const ir_node *node, unsigned char code, int input)
2391 const arch_register_t *out = get_out_reg(node, 0);
2392 bemit_unop(node, code, reg_gp_map[out->index], input);
2395 static void bemit_unop_mem(const ir_node *node, unsigned char code, unsigned char ext)
2397 unsigned size = get_mode_size_bits(get_ia32_ls_mode(node));
2400 bemit8(size == 8 ? code : code + 1);
2401 bemit_mod_am(ext, node);
2404 static void bemit_immediate(const ir_node *node, bool relative)
2406 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(node);
2407 bemit_entity(attr->symconst, attr->sc_sign, attr->offset, relative);
2410 static void bemit_copy(const ir_node *copy)
2412 const arch_register_t *in = get_in_reg(copy, 0);
2413 const arch_register_t *out = get_out_reg(copy, 0);
2417 /* copies of vf nodes aren't real... */
2418 if (arch_register_get_class(in) == &ia32_reg_classes[CLASS_ia32_vfp])
2421 if (get_irn_mode(copy) == mode_E) {
2424 assert(arch_register_get_class(in) == &ia32_reg_classes[CLASS_ia32_gp]);
2426 bemit_modrr(in, out);
2430 static void bemit_perm(const ir_node *node)
2432 const arch_register_t *in0 = arch_get_irn_register(get_irn_n(node, 0));
2433 const arch_register_t *in1 = arch_get_irn_register(get_irn_n(node, 1));
2434 const arch_register_class_t *cls0 = arch_register_get_class(in0);
2436 assert(cls0 == arch_register_get_class(in1) && "Register class mismatch at Perm");
2438 if (cls0 == &ia32_reg_classes[CLASS_ia32_gp]) {
2439 if (in0->index == REG_GP_EAX) {
2440 bemit8(0x90 + reg_gp_map[in1->index]);
2441 } else if (in1->index == REG_GP_EAX) {
2442 bemit8(0x90 + reg_gp_map[in0->index]);
2445 bemit_modrr(in0, in1);
2447 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_xmm]) {
2448 panic("unimplemented"); // TODO implement
2449 //ia32_emitf(NULL, "\txorpd %R, %R\n", in1, in0);
2450 //ia32_emitf(NULL, "\txorpd %R, %R\n", in0, in1);
2451 //ia32_emitf(node, "\txorpd %R, %R\n", in1, in0);
2452 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_vfp]) {
2454 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_st]) {
2457 panic("unexpected register class in be_Perm (%+F)", node);
2461 static void bemit_xor0(const ir_node *node)
2463 const arch_register_t *out = get_out_reg(node, 0);
2465 bemit_modrr(out, out);
2468 static void bemit_mov_const(const ir_node *node)
2470 const arch_register_t *out = get_out_reg(node, 0);
2471 bemit8(0xB8 + reg_gp_map[out->index]);
2472 bemit_immediate(node, false);
2476 * Creates a function for a Binop with 3 possible encodings.
2478 #define BINOP(op, op0, op1, op2, op2_ext) \
2479 static void bemit_ ## op(const ir_node *node) { \
2480 static const unsigned char op ## _codes[] = {op0, op1, op2, op2_ext}; \
2481 bemit_binop(node, op ## _codes); \
2484 /* insn def eax,imm imm */
2485 BINOP(add, 0x03, 0x05, 0x81, 0)
2486 BINOP(or, 0x0B, 0x0D, 0x81, 1)
2487 BINOP(adc, 0x13, 0x15, 0x81, 2)
2488 BINOP(sbb, 0x1B, 0x1D, 0x81, 3)
2489 BINOP(and, 0x23, 0x25, 0x81, 4)
2490 BINOP(sub, 0x2B, 0x2D, 0x81, 5)
2491 BINOP(xor, 0x33, 0x35, 0x81, 6)
2492 BINOP(test, 0x85, 0xA9, 0xF7, 0)
2494 #define BINOPMEM(op, ext) \
2495 static void bemit_##op(const ir_node *node) \
2498 unsigned size = get_mode_size_bits(get_ia32_ls_mode(node)); \
2501 val = get_irn_n(node, n_ia32_unary_op); \
2502 if (is_ia32_Immediate(val)) { \
2503 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(val); \
2504 int offset = attr->offset; \
2505 if (attr->symconst == NULL && get_signed_imm_size(offset) == 1) { \
2507 bemit_mod_am(ext, node); \
2511 bemit_mod_am(ext, node); \
2515 bemit_entity(attr->symconst, attr->sc_sign, offset, false); \
2519 bemit8(ext << 3 | 1); \
2520 bemit_mod_am(reg_gp_map[get_out_reg(val, 0)->index], node); \
2524 static void bemit_##op##8bit(const ir_node *node) \
2526 ir_node *val = get_irn_n(node, n_ia32_unary_op); \
2527 if (is_ia32_Immediate(val)) { \
2529 bemit_mod_am(ext, node); \
2530 bemit8(get_ia32_immediate_attr_const(val)->offset); \
2533 bemit_mod_am(reg_gp_map[get_out_reg(val, 0)->index], node); \
2545 * Creates a function for an Unop with code /ext encoding.
2547 #define UNOP(op, code, ext, input) \
2548 static void bemit_ ## op(const ir_node *node) { \
2549 bemit_unop(node, code, ext, input); \
2552 UNOP(not, 0xF7, 2, n_ia32_Not_val)
2553 UNOP(neg, 0xF7, 3, n_ia32_Neg_val)
2554 UNOP(mul, 0xF7, 4, n_ia32_Mul_right)
2555 UNOP(imul1op, 0xF7, 5, n_ia32_IMul1OP_right)
2556 UNOP(div, 0xF7, 6, n_ia32_Div_divisor)
2557 UNOP(idiv, 0xF7, 7, n_ia32_IDiv_divisor)
2559 /* TODO: am support for IJmp */
2560 UNOP(ijmp, 0xFF, 4, n_ia32_IJmp_target)
2562 #define SHIFT(op, ext) \
2563 static void bemit_##op(const ir_node *node) \
2565 const arch_register_t *out = get_out_reg(node, 0); \
2566 ir_node *count = get_irn_n(node, 1); \
2567 if (is_ia32_Immediate(count)) { \
2568 int offset = get_ia32_immediate_attr_const(count)->offset; \
2569 if (offset == 1) { \
2571 bemit_modru(out, ext); \
2574 bemit_modru(out, ext); \
2579 bemit_modru(out, ext); \
2583 static void bemit_##op##mem(const ir_node *node) \
2586 unsigned size = get_mode_size_bits(get_ia32_ls_mode(node)); \
2589 count = get_irn_n(node, 1); \
2590 if (is_ia32_Immediate(count)) { \
2591 int offset = get_ia32_immediate_attr_const(count)->offset; \
2592 if (offset == 1) { \
2593 bemit8(size == 8 ? 0xD0 : 0xD1); \
2594 bemit_mod_am(ext, node); \
2596 bemit8(size == 8 ? 0xC0 : 0xC1); \
2597 bemit_mod_am(ext, node); \
2601 bemit8(size == 8 ? 0xD2 : 0xD3); \
2602 bemit_mod_am(ext, node); \
2612 static void bemit_shld(const ir_node *node)
2614 const arch_register_t *in = get_in_reg(node, n_ia32_ShlD_val_low);
2615 const arch_register_t *out = get_out_reg(node, pn_ia32_ShlD_res);
2616 ir_node *count = get_irn_n(node, n_ia32_ShlD_count);
2618 if (is_ia32_Immediate(count)) {
2620 bemit_modrr(out, in);
2621 bemit8(get_ia32_immediate_attr_const(count)->offset);
2624 bemit_modrr(out, in);
2628 static void bemit_shrd(const ir_node *node)
2630 const arch_register_t *in = get_in_reg(node, n_ia32_ShrD_val_low);
2631 const arch_register_t *out = get_out_reg(node, pn_ia32_ShrD_res);
2632 ir_node *count = get_irn_n(node, n_ia32_ShrD_count);
2634 if (is_ia32_Immediate(count)) {
2636 bemit_modrr(out, in);
2637 bemit8(get_ia32_immediate_attr_const(count)->offset);
2640 bemit_modrr(out, in);
2645 * binary emitter for setcc.
2647 static void bemit_setcc(const ir_node *node)
2649 const arch_register_t *dreg = get_out_reg(node, pn_ia32_Setcc_res);
2651 ia32_condition_code_t cc = get_ia32_condcode(node);
2652 cc = determine_final_cc(node, n_ia32_Setcc_eflags, cc);
2653 if (cc & ia32_cc_float_parity_cases) {
2654 if (cc & ia32_cc_negated) {
2657 bemit8(0x90 | pnc2cc(cc));
2658 bemit_modrm8(REG_LOW, dreg);
2663 bemit_modrm8(REG_HIGH, dreg);
2665 /* orb %>dreg, %<dreg */
2667 bemit_modrr8(REG_LOW, dreg, REG_HIGH, dreg);
2671 bemit8(0x90 | pnc2cc(cc));
2672 bemit_modrm8(REG_LOW, dreg);
2677 bemit_modrm8(REG_HIGH, dreg);
2679 /* andb %>dreg, %<dreg */
2681 bemit_modrr8(REG_LOW, dreg, REG_HIGH, dreg);
2686 bemit8(0x90 | pnc2cc(cc));
2687 bemit_modrm8(REG_LOW, dreg);
2691 static void bemit_cmovcc(const ir_node *node)
2693 const ia32_attr_t *attr = get_ia32_attr_const(node);
2694 int ins_permuted = attr->data.ins_permuted;
2695 const arch_register_t *out = arch_irn_get_register(node, pn_ia32_res);
2696 ia32_condition_code_t cc = get_ia32_condcode(node);
2697 const arch_register_t *in_true;
2698 const arch_register_t *in_false;
2700 cc = determine_final_cc(node, n_ia32_CMovcc_eflags, cc);
2702 in_true = arch_get_irn_register(get_irn_n(node, n_ia32_CMovcc_val_true));
2703 in_false = arch_get_irn_register(get_irn_n(node, n_ia32_CMovcc_val_false));
2705 /* should be same constraint fullfilled? */
2706 if (out == in_false) {
2707 /* yes -> nothing to do */
2708 } else if (out == in_true) {
2709 assert(get_ia32_op_type(node) == ia32_Normal);
2710 ins_permuted = !ins_permuted;
2714 bemit8(0x8B); // mov %in_false, %out
2715 bemit_modrr(in_false, out);
2719 cc = ia32_negate_condition_code(cc);
2721 if (cc & ia32_cc_float_parity_cases)
2722 panic("cmov can't handle parity float cases");
2725 bemit8(0x40 | pnc2cc(cc));
2726 if (get_ia32_op_type(node) == ia32_Normal) {
2727 bemit_modrr(in_true, out);
2729 bemit_mod_am(reg_gp_map[out->index], node);
2733 static void bemit_cmp(const ir_node *node)
2735 unsigned ls_size = get_mode_size_bits(get_ia32_ls_mode(node));
2741 right = get_irn_n(node, n_ia32_binary_right);
2742 if (is_ia32_Immediate(right)) {
2743 /* Use in-reg, because some instructions (cmp, test) have no out-reg. */
2744 const ir_node *op = get_irn_n(node, n_ia32_binary_right);
2745 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(op);
2748 if (attr->symconst != NULL) {
2751 /* check for sign extension */
2752 size = get_signed_imm_size(attr->offset);
2757 bemit8(0x81 | SIGNEXT_IMM);
2758 /* cmp has this special mode */
2759 if (get_ia32_op_type(node) == ia32_AddrModeS) {
2760 bemit_mod_am(7, node);
2762 const arch_register_t *reg = get_in_reg(node, n_ia32_binary_left);
2763 bemit_modru(reg, 7);
2765 bemit8((unsigned char)attr->offset);
2769 /* check for eax variant: this variant is shorter for 32bit immediates only */
2770 if (get_ia32_op_type(node) == ia32_AddrModeS) {
2772 bemit_mod_am(7, node);
2774 const arch_register_t *reg = get_in_reg(node, n_ia32_binary_left);
2775 if (reg->index == REG_GP_EAX) {
2779 bemit_modru(reg, 7);
2782 if (ls_size == 16) {
2783 bemit16(attr->offset);
2785 bemit_entity(attr->symconst, attr->sc_sign, attr->offset, false);
2789 panic("invalid imm size?!?");
2791 const arch_register_t *out = get_in_reg(node, n_ia32_binary_left);
2793 if (get_ia32_op_type(node) == ia32_Normal) {
2794 const arch_register_t *op2 = get_in_reg(node, n_ia32_binary_right);
2795 bemit_modrr(op2, out);
2797 bemit_mod_am(reg_gp_map[out->index], node);
2802 static void bemit_cmp8bit(const ir_node *node)
2804 ir_node *right = get_irn_n(node, n_ia32_binary_right);
2805 if (is_ia32_Immediate(right)) {
2806 if (get_ia32_op_type(node) == ia32_Normal) {
2807 const arch_register_t *out = get_in_reg(node, n_ia32_Cmp_left);
2808 if (out->index == REG_GP_EAX) {
2812 bemit_modru(out, 7);
2816 bemit_mod_am(7, node);
2818 bemit8(get_ia32_immediate_attr_const(right)->offset);
2820 const arch_register_t *out = get_in_reg(node, n_ia32_Cmp_left);
2822 if (get_ia32_op_type(node) == ia32_Normal) {
2823 const arch_register_t *in = get_in_reg(node, n_ia32_Cmp_right);
2824 bemit_modrr(out, in);
2826 bemit_mod_am(reg_gp_map[out->index], node);
2831 static void bemit_test8bit(const ir_node *node)
2833 ir_node *right = get_irn_n(node, n_ia32_Test8Bit_right);
2834 if (is_ia32_Immediate(right)) {
2835 if (get_ia32_op_type(node) == ia32_Normal) {
2836 const arch_register_t *out = get_in_reg(node, n_ia32_Test8Bit_left);
2837 if (out->index == REG_GP_EAX) {
2841 bemit_modru(out, 0);
2845 bemit_mod_am(0, node);
2847 bemit8(get_ia32_immediate_attr_const(right)->offset);
2849 const arch_register_t *out = get_in_reg(node, n_ia32_Test8Bit_left);
2851 if (get_ia32_op_type(node) == ia32_Normal) {
2852 const arch_register_t *in = get_in_reg(node, n_ia32_Test8Bit_right);
2853 bemit_modrr(out, in);
2855 bemit_mod_am(reg_gp_map[out->index], node);
2860 static void bemit_imul(const ir_node *node)
2862 ir_node *right = get_irn_n(node, n_ia32_IMul_right);
2863 /* Do we need the immediate form? */
2864 if (is_ia32_Immediate(right)) {
2865 int imm = get_ia32_immediate_attr_const(right)->offset;
2866 if (get_signed_imm_size(imm) == 1) {
2867 bemit_unop_reg(node, 0x6B, n_ia32_IMul_left);
2870 bemit_unop_reg(node, 0x69, n_ia32_IMul_left);
2875 bemit_unop_reg(node, 0xAF, n_ia32_IMul_right);
2879 static void bemit_dec(const ir_node *node)
2881 const arch_register_t *out = get_out_reg(node, pn_ia32_Dec_res);
2882 bemit8(0x48 + reg_gp_map[out->index]);
2885 static void bemit_inc(const ir_node *node)
2887 const arch_register_t *out = get_out_reg(node, pn_ia32_Inc_res);
2888 bemit8(0x40 + reg_gp_map[out->index]);
2891 #define UNOPMEM(op, code, ext) \
2892 static void bemit_##op(const ir_node *node) \
2894 bemit_unop_mem(node, code, ext); \
2897 UNOPMEM(notmem, 0xF6, 2)
2898 UNOPMEM(negmem, 0xF6, 3)
2899 UNOPMEM(incmem, 0xFE, 0)
2900 UNOPMEM(decmem, 0xFE, 1)
2902 static void bemit_ldtls(const ir_node *node)
2904 const arch_register_t *out = get_out_reg(node, 0);
2906 bemit8(0x65); // gs:
2907 if (out->index == REG_GP_EAX) {
2908 bemit8(0xA1); // movl 0, %eax
2910 bemit8(0x8B); // movl 0, %reg
2911 bemit8(MOD_IND | ENC_REG(reg_gp_map[out->index]) | ENC_RM(0x05));
2919 static void bemit_lea(const ir_node *node)
2921 const arch_register_t *out = get_out_reg(node, 0);
2923 bemit_mod_am(reg_gp_map[out->index], node);
2926 /* helper function for bemit_minus64bit */
2927 static void bemit_helper_mov(const arch_register_t *src, const arch_register_t *dst)
2929 bemit8(0x8B); // movl %src, %dst
2930 bemit_modrr(src, dst);
2933 /* helper function for bemit_minus64bit */
2934 static void bemit_helper_neg(const arch_register_t *reg)
2936 bemit8(0xF7); // negl %reg
2937 bemit_modru(reg, 3);
2940 /* helper function for bemit_minus64bit */
2941 static void bemit_helper_sbb0(const arch_register_t *reg)
2943 bemit8(0x83); // sbbl $0, %reg
2944 bemit_modru(reg, 3);
2948 /* helper function for bemit_minus64bit */
2949 static void bemit_helper_sbb(const arch_register_t *src, const arch_register_t *dst)
2951 bemit8(0x1B); // sbbl %src, %dst
2952 bemit_modrr(src, dst);
2955 /* helper function for bemit_minus64bit */
2956 static void bemit_helper_xchg(const arch_register_t *src, const arch_register_t *dst)
2958 if (src->index == REG_GP_EAX) {
2959 bemit8(0x90 + reg_gp_map[dst->index]); // xchgl %eax, %dst
2960 } else if (dst->index == REG_GP_EAX) {
2961 bemit8(0x90 + reg_gp_map[src->index]); // xchgl %src, %eax
2963 bemit8(0x87); // xchgl %src, %dst
2964 bemit_modrr(src, dst);
2968 /* helper function for bemit_minus64bit */
2969 static void bemit_helper_zero(const arch_register_t *reg)
2971 bemit8(0x33); // xorl %reg, %reg
2972 bemit_modrr(reg, reg);
2975 static void bemit_minus64bit(const ir_node *node)
2977 const arch_register_t *in_lo = get_in_reg(node, 0);
2978 const arch_register_t *in_hi = get_in_reg(node, 1);
2979 const arch_register_t *out_lo = get_out_reg(node, 0);
2980 const arch_register_t *out_hi = get_out_reg(node, 1);
2982 if (out_lo == in_lo) {
2983 if (out_hi != in_hi) {
2984 /* a -> a, b -> d */
2987 /* a -> a, b -> b */
2990 } else if (out_lo == in_hi) {
2991 if (out_hi == in_lo) {
2992 /* a -> b, b -> a */
2993 bemit_helper_xchg(in_lo, in_hi);
2996 /* a -> b, b -> d */
2997 bemit_helper_mov(in_hi, out_hi);
2998 bemit_helper_mov(in_lo, out_lo);
3002 if (out_hi == in_lo) {
3003 /* a -> c, b -> a */
3004 bemit_helper_mov(in_lo, out_lo);
3006 } else if (out_hi == in_hi) {
3007 /* a -> c, b -> b */
3008 bemit_helper_mov(in_lo, out_lo);
3011 /* a -> c, b -> d */
3012 bemit_helper_mov(in_lo, out_lo);
3018 bemit_helper_neg( out_hi);
3019 bemit_helper_neg( out_lo);
3020 bemit_helper_sbb0(out_hi);
3024 bemit_helper_zero(out_hi);
3025 bemit_helper_neg( out_lo);
3026 bemit_helper_sbb( in_hi, out_hi);
3030 * Emit a single opcode.
3032 #define EMIT_SINGLEOP(op, code) \
3033 static void bemit_ ## op(const ir_node *node) { \
3038 //EMIT_SINGLEOP(daa, 0x27)
3039 //EMIT_SINGLEOP(das, 0x2F)
3040 //EMIT_SINGLEOP(aaa, 0x37)
3041 //EMIT_SINGLEOP(aas, 0x3F)
3042 //EMIT_SINGLEOP(nop, 0x90)
3043 EMIT_SINGLEOP(cwtl, 0x98)
3044 EMIT_SINGLEOP(cltd, 0x99)
3045 //EMIT_SINGLEOP(fwait, 0x9B)
3046 EMIT_SINGLEOP(sahf, 0x9E)
3047 //EMIT_SINGLEOP(popf, 0x9D)
3048 EMIT_SINGLEOP(leave, 0xC9)
3049 EMIT_SINGLEOP(int3, 0xCC)
3050 //EMIT_SINGLEOP(iret, 0xCF)
3051 //EMIT_SINGLEOP(xlat, 0xD7)
3052 //EMIT_SINGLEOP(lock, 0xF0)
3053 EMIT_SINGLEOP(rep, 0xF3)
3054 //EMIT_SINGLEOP(halt, 0xF4)
3055 EMIT_SINGLEOP(cmc, 0xF5)
3056 EMIT_SINGLEOP(stc, 0xF9)
3057 //EMIT_SINGLEOP(cli, 0xFA)
3058 //EMIT_SINGLEOP(sti, 0xFB)
3059 //EMIT_SINGLEOP(std, 0xFD)
3062 * Emits a MOV out, [MEM].
3064 static void bemit_load(const ir_node *node)
3066 const arch_register_t *out = get_out_reg(node, 0);
3068 if (out->index == REG_GP_EAX) {
3069 ir_node *base = get_irn_n(node, n_ia32_base);
3070 int has_base = !is_ia32_NoReg_GP(base);
3071 ir_node *index = get_irn_n(node, n_ia32_index);
3072 int has_index = !is_ia32_NoReg_GP(index);
3073 if (!has_base && !has_index) {
3074 ir_entity *ent = get_ia32_am_sc(node);
3075 int offs = get_ia32_am_offs_int(node);
3076 /* load from constant address to EAX can be encoded
3079 bemit_entity(ent, 0, offs, false);
3084 bemit_mod_am(reg_gp_map[out->index], node);
3088 * Emits a MOV [mem], in.
3090 static void bemit_store(const ir_node *node)
3092 const ir_node *value = get_irn_n(node, n_ia32_Store_val);
3093 unsigned size = get_mode_size_bits(get_ia32_ls_mode(node));
3095 if (is_ia32_Immediate(value)) {
3098 bemit_mod_am(0, node);
3099 bemit8(get_ia32_immediate_attr_const(value)->offset);
3100 } else if (size == 16) {
3103 bemit_mod_am(0, node);
3104 bemit16(get_ia32_immediate_attr_const(value)->offset);
3107 bemit_mod_am(0, node);
3108 bemit_immediate(value, false);
3111 const arch_register_t *in = get_in_reg(node, n_ia32_Store_val);
3113 if (in->index == REG_GP_EAX) {
3114 ir_node *base = get_irn_n(node, n_ia32_base);
3115 int has_base = !is_ia32_NoReg_GP(base);
3116 ir_node *index = get_irn_n(node, n_ia32_index);
3117 int has_index = !is_ia32_NoReg_GP(index);
3118 if (!has_base && !has_index) {
3119 ir_entity *ent = get_ia32_am_sc(node);
3120 int offs = get_ia32_am_offs_int(node);
3121 /* store to constant address from EAX can be encoded as
3122 * 0xA2/0xA3 [offset]*/
3130 bemit_entity(ent, 0, offs, false);
3142 bemit_mod_am(reg_gp_map[in->index], node);
3146 static void bemit_conv_i2i(const ir_node *node)
3148 ir_mode *smaller_mode = get_ia32_ls_mode(node);
3157 if (mode_is_signed(smaller_mode)) opcode |= 0x08;
3158 if (get_mode_size_bits(smaller_mode) == 16) opcode |= 0x01;
3159 bemit_unop_reg(node, opcode, n_ia32_Conv_I2I_val);
3165 static void bemit_push(const ir_node *node)
3167 const ir_node *value = get_irn_n(node, n_ia32_Push_val);
3169 if (is_ia32_Immediate(value)) {
3170 const ia32_immediate_attr_t *attr
3171 = get_ia32_immediate_attr_const(value);
3172 unsigned size = get_signed_imm_size(attr->offset);
3178 bemit8((unsigned char)attr->offset);
3183 bemit_immediate(value, false);
3186 } else if (is_ia32_NoReg_GP(value)) {
3188 bemit_mod_am(6, node);
3190 const arch_register_t *reg = get_in_reg(node, n_ia32_Push_val);
3191 bemit8(0x50 + reg_gp_map[reg->index]);
3198 static void bemit_pop(const ir_node *node)
3200 const arch_register_t *reg = get_out_reg(node, pn_ia32_Pop_res);
3201 bemit8(0x58 + reg_gp_map[reg->index]);
3204 static void bemit_popmem(const ir_node *node)
3207 bemit_mod_am(0, node);
3210 static void bemit_call(const ir_node *node)
3212 ir_node *proc = get_irn_n(node, n_ia32_Call_addr);
3214 if (is_ia32_Immediate(proc)) {
3216 bemit_immediate(proc, true);
3218 bemit_unop(node, 0xFF, 2, n_ia32_Call_addr);
3222 static void bemit_jmp(const ir_node *dest_block)
3225 bemit_jmp_destination(dest_block);
3228 static void bemit_jump(const ir_node *node)
3230 if (can_be_fallthrough(node))
3233 bemit_jmp(get_cfop_target_block(node));
3236 static void bemit_jcc(int pnc, const ir_node *dest_block)
3238 unsigned char cc = pnc2cc(pnc);
3241 bemit_jmp_destination(dest_block);
3244 static void bemit_jp(bool odd, const ir_node *dest_block)
3248 bemit_jmp_destination(dest_block);
3251 static void bemit_ia32_jcc(const ir_node *node)
3253 ia32_condition_code_t cc = get_ia32_condcode(node);
3254 const ir_node *proj_true;
3255 const ir_node *proj_false;
3256 const ir_node *dest_true;
3257 const ir_node *dest_false;
3259 cc = determine_final_cc(node, 0, cc);
3261 /* get both Projs */
3262 proj_true = get_proj(node, pn_ia32_Jcc_true);
3263 assert(proj_true && "Jcc without true Proj");
3265 proj_false = get_proj(node, pn_ia32_Jcc_false);
3266 assert(proj_false && "Jcc without false Proj");
3268 if (can_be_fallthrough(proj_true)) {
3269 /* exchange both proj's so the second one can be omitted */
3270 const ir_node *t = proj_true;
3272 proj_true = proj_false;
3274 cc = ia32_negate_condition_code(cc);
3277 dest_true = get_cfop_target_block(proj_true);
3278 dest_false = get_cfop_target_block(proj_false);
3280 if (cc & ia32_cc_float_parity_cases) {
3281 /* Some floating point comparisons require a test of the parity flag,
3282 * which indicates that the result is unordered */
3283 if (cc & ia32_cc_negated) {
3284 bemit_jp(false, dest_true);
3286 /* we need a local label if the false proj is a fallthrough
3287 * as the falseblock might have no label emitted then */
3288 if (can_be_fallthrough(proj_false)) {
3290 bemit8(0x06); // jp + 6
3292 bemit_jp(false, dest_false);
3296 bemit_jcc(cc, dest_true);
3298 /* the second Proj might be a fallthrough */
3299 if (can_be_fallthrough(proj_false)) {
3300 /* it's a fallthrough */
3302 bemit_jmp(dest_false);
3306 static void bemit_switchjmp(const ir_node *node)
3308 ir_entity *jump_table = get_ia32_am_sc(node);
3309 long default_pn = get_ia32_default_pn(node);
3311 bemit8(0xFF); // jmp *tbl.label(,%in,4)
3312 bemit_mod_am(0x05, node);
3314 emit_jump_table(node, default_pn, jump_table, get_cfop_target_block);
3320 static void bemit_return(const ir_node *node)
3322 unsigned pop = be_Return_get_pop(node);
3323 if (pop > 0 || be_Return_get_emit_pop(node)) {
3325 assert(pop <= 0xffff);
3332 static void bemit_subsp(const ir_node *node)
3334 const arch_register_t *out;
3337 /* mov %esp, %out */
3339 out = get_out_reg(node, 1);
3340 bemit8(MOD_REG | ENC_REG(reg_gp_map[out->index]) | ENC_RM(0x04));
3343 static void bemit_incsp(const ir_node *node)
3346 const arch_register_t *reg;
3350 offs = be_get_IncSP_offset(node);
3361 size = get_signed_imm_size(offs);
3362 bemit8(size == 1 ? 0x83 : 0x81);
3364 reg = get_out_reg(node, 0);
3365 bemit_modru(reg, ext);
3374 static void bemit_copybi(const ir_node *node)
3376 unsigned size = get_ia32_copyb_size(node);
3378 bemit8(0xA4); // movsb
3381 bemit8(0xA5); // movsw
3385 bemit8(0xA5); // movsl
3389 static void bemit_fbinop(const ir_node *node, unsigned code, unsigned code_to)
3391 if (get_ia32_op_type(node) == ia32_Normal) {
3392 const ia32_x87_attr_t *x87_attr = get_ia32_x87_attr_const(node);
3393 const arch_register_t *in1 = x87_attr->x87[0];
3394 const arch_register_t *in = x87_attr->x87[1];
3395 const arch_register_t *out = x87_attr->x87[2];
3399 } else if (out == in) {
3403 if (out->index == 0) {
3405 bemit8(MOD_REG | ENC_REG(code) | ENC_RM(in->index));
3408 bemit8(MOD_REG | ENC_REG(code_to) | ENC_RM(out->index));
3411 if (get_mode_size_bits(get_ia32_ls_mode(node)) == 32) {
3416 bemit_mod_am(code, node);
3420 static void bemit_fbinopp(const ir_node *node, unsigned const code)
3422 const ia32_x87_attr_t *x87_attr = get_ia32_x87_attr_const(node);
3423 const arch_register_t *out = x87_attr->x87[2];
3425 bemit8(code + out->index);
3428 static void bemit_fabs(const ir_node *node)
3436 static void bemit_fadd(const ir_node *node)
3438 bemit_fbinop(node, 0, 0);
3441 static void bemit_faddp(const ir_node *node)
3443 bemit_fbinopp(node, 0xC0);
3446 static void bemit_fchs(const ir_node *node)
3454 static void bemit_fdiv(const ir_node *node)
3456 bemit_fbinop(node, 6, 7);
3459 static void bemit_fdivp(const ir_node *node)
3461 bemit_fbinopp(node, 0xF8);
3464 static void bemit_fdivr(const ir_node *node)
3466 bemit_fbinop(node, 7, 6);
3469 static void bemit_fdivrp(const ir_node *node)
3471 bemit_fbinopp(node, 0xF0);
3474 static void bemit_fild(const ir_node *node)
3476 switch (get_mode_size_bits(get_ia32_ls_mode(node))) {
3478 bemit8(0xDF); // filds
3479 bemit_mod_am(0, node);
3483 bemit8(0xDB); // fildl
3484 bemit_mod_am(0, node);
3488 bemit8(0xDF); // fildll
3489 bemit_mod_am(5, node);
3493 panic("invalid mode size");
3497 static void bemit_fist(const ir_node *node)
3499 switch (get_mode_size_bits(get_ia32_ls_mode(node))) {
3501 bemit8(0xDF); // fists
3505 bemit8(0xDB); // fistl
3509 panic("invalid mode size");
3511 bemit_mod_am(2, node);
3514 static void bemit_fistp(const ir_node *node)
3516 switch (get_mode_size_bits(get_ia32_ls_mode(node))) {
3518 bemit8(0xDF); // fistps
3519 bemit_mod_am(3, node);
3523 bemit8(0xDB); // fistpl
3524 bemit_mod_am(3, node);
3528 bemit8(0xDF); // fistpll
3529 bemit_mod_am(7, node);
3533 panic("invalid mode size");
3537 static void bemit_fld(const ir_node *node)
3539 switch (get_mode_size_bits(get_ia32_ls_mode(node))) {
3541 bemit8(0xD9); // flds
3542 bemit_mod_am(0, node);
3546 bemit8(0xDD); // fldl
3547 bemit_mod_am(0, node);
3552 bemit8(0xDB); // fldt
3553 bemit_mod_am(5, node);
3557 panic("invalid mode size");
3561 static void bemit_fld1(const ir_node *node)
3565 bemit8(0xE8); // fld1
3568 static void bemit_fldcw(const ir_node *node)
3570 bemit8(0xD9); // fldcw
3571 bemit_mod_am(5, node);
3574 static void bemit_fldz(const ir_node *node)
3578 bemit8(0xEE); // fldz
3581 static void bemit_fmul(const ir_node *node)
3583 bemit_fbinop(node, 1, 1);
3586 static void bemit_fmulp(const ir_node *node)
3588 bemit_fbinopp(node, 0xC8);
3591 static void bemit_fpop(const ir_node *node)
3593 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
3595 bemit8(0xD8 + attr->x87[0]->index);
3598 static void bemit_fpush(const ir_node *node)
3600 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
3602 bemit8(0xC0 + attr->x87[0]->index);
3605 static void bemit_fpushcopy(const ir_node *node)
3607 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
3609 bemit8(0xC0 + attr->x87[0]->index);
3612 static void bemit_fst(const ir_node *node)
3614 switch (get_mode_size_bits(get_ia32_ls_mode(node))) {
3616 bemit8(0xD9); // fsts
3620 bemit8(0xDD); // fstl
3624 panic("invalid mode size");
3626 bemit_mod_am(2, node);
3629 static void bemit_fstp(const ir_node *node)
3631 switch (get_mode_size_bits(get_ia32_ls_mode(node))) {
3633 bemit8(0xD9); // fstps
3634 bemit_mod_am(3, node);
3638 bemit8(0xDD); // fstpl
3639 bemit_mod_am(3, node);
3644 bemit8(0xDB); // fstpt
3645 bemit_mod_am(7, node);
3649 panic("invalid mode size");
3653 static void bemit_fsub(const ir_node *node)
3655 bemit_fbinop(node, 4, 5);
3658 static void bemit_fsubp(const ir_node *node)
3660 bemit_fbinopp(node, 0xE8);
3663 static void bemit_fsubr(const ir_node *node)
3665 bemit_fbinop(node, 5, 4);
3668 static void bemit_fsubrp(const ir_node *node)
3670 bemit_fbinopp(node, 0xE0);
3673 static void bemit_fnstcw(const ir_node *node)
3675 bemit8(0xD9); // fnstcw
3676 bemit_mod_am(7, node);
3679 static void bemit_fnstsw(void)
3681 bemit8(0xDF); // fnstsw %ax
3685 static void bemit_ftstfnstsw(const ir_node *node)
3689 bemit8(0xD9); // ftst
3694 static void bemit_fucomi(const ir_node *node)
3696 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
3697 bemit8(0xDB); // fucomi
3698 bemit8(0xE8 + attr->x87[1]->index);
3701 static void bemit_fucomip(const ir_node *node)
3703 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
3704 bemit8(0xDF); // fucomip
3705 bemit8(0xE8 + attr->x87[1]->index);
3708 static void bemit_fucomfnstsw(const ir_node *node)
3710 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
3711 bemit8(0xDD); // fucom
3712 bemit8(0xE0 + attr->x87[1]->index);
3716 static void bemit_fucompfnstsw(const ir_node *node)
3718 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
3719 bemit8(0xDD); // fucomp
3720 bemit8(0xE8 + attr->x87[1]->index);
3724 static void bemit_fucomppfnstsw(const ir_node *node)
3728 bemit8(0xDA); // fucompp
3733 static void bemit_fxch(const ir_node *node)
3735 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
3737 bemit8(0xC8 + attr->x87[0]->index);
3741 * The type of a emitter function.
3743 typedef void (*emit_func) (const ir_node *);
3746 * Set a node emitter. Make it a bit more type safe.
3748 static void register_emitter(ir_op *op, emit_func func)
3750 op->ops.generic = (op_func) func;
3753 static void ia32_register_binary_emitters(void)
3755 /* first clear the generic function pointer for all ops */
3756 clear_irp_opcodes_generic_func();
3758 /* benode emitter */
3759 register_emitter(op_be_Copy, bemit_copy);
3760 register_emitter(op_be_CopyKeep, bemit_copy);
3761 register_emitter(op_be_IncSP, bemit_incsp);
3762 register_emitter(op_be_Perm, bemit_perm);
3763 register_emitter(op_be_Return, bemit_return);
3764 register_emitter(op_ia32_Adc, bemit_adc);
3765 register_emitter(op_ia32_Add, bemit_add);
3766 register_emitter(op_ia32_AddMem, bemit_addmem);
3767 register_emitter(op_ia32_AddMem8Bit, bemit_addmem8bit);
3768 register_emitter(op_ia32_And, bemit_and);
3769 register_emitter(op_ia32_AndMem, bemit_andmem);
3770 register_emitter(op_ia32_AndMem8Bit, bemit_andmem8bit);
3771 register_emitter(op_ia32_Breakpoint, bemit_int3);
3772 register_emitter(op_ia32_CMovcc, bemit_cmovcc);
3773 register_emitter(op_ia32_Call, bemit_call);
3774 register_emitter(op_ia32_Cltd, bemit_cltd);
3775 register_emitter(op_ia32_Cmc, bemit_cmc);
3776 register_emitter(op_ia32_Cmp, bemit_cmp);
3777 register_emitter(op_ia32_Cmp8Bit, bemit_cmp8bit);
3778 register_emitter(op_ia32_Const, bemit_mov_const);
3779 register_emitter(op_ia32_Conv_I2I, bemit_conv_i2i);
3780 register_emitter(op_ia32_Conv_I2I8Bit, bemit_conv_i2i);
3781 register_emitter(op_ia32_CopyB_i, bemit_copybi);
3782 register_emitter(op_ia32_Cwtl, bemit_cwtl);
3783 register_emitter(op_ia32_Dec, bemit_dec);
3784 register_emitter(op_ia32_DecMem, bemit_decmem);
3785 register_emitter(op_ia32_Div, bemit_div);
3786 register_emitter(op_ia32_FldCW, bemit_fldcw);
3787 register_emitter(op_ia32_FnstCW, bemit_fnstcw);
3788 register_emitter(op_ia32_FtstFnstsw, bemit_ftstfnstsw);
3789 register_emitter(op_ia32_FucomFnstsw, bemit_fucomfnstsw);
3790 register_emitter(op_ia32_Fucomi, bemit_fucomi);
3791 register_emitter(op_ia32_FucompFnstsw, bemit_fucompfnstsw);
3792 register_emitter(op_ia32_Fucompi, bemit_fucomip);
3793 register_emitter(op_ia32_FucomppFnstsw, bemit_fucomppfnstsw);
3794 register_emitter(op_ia32_IDiv, bemit_idiv);
3795 register_emitter(op_ia32_IJmp, bemit_ijmp);
3796 register_emitter(op_ia32_IMul, bemit_imul);
3797 register_emitter(op_ia32_IMul1OP, bemit_imul1op);
3798 register_emitter(op_ia32_Inc, bemit_inc);
3799 register_emitter(op_ia32_IncMem, bemit_incmem);
3800 register_emitter(op_ia32_Jcc, bemit_ia32_jcc);
3801 register_emitter(op_ia32_Jmp, bemit_jump);
3802 register_emitter(op_ia32_LdTls, bemit_ldtls);
3803 register_emitter(op_ia32_Lea, bemit_lea);
3804 register_emitter(op_ia32_Leave, bemit_leave);
3805 register_emitter(op_ia32_Load, bemit_load);
3806 register_emitter(op_ia32_Minus64Bit, bemit_minus64bit);
3807 register_emitter(op_ia32_Mul, bemit_mul);
3808 register_emitter(op_ia32_Neg, bemit_neg);
3809 register_emitter(op_ia32_NegMem, bemit_negmem);
3810 register_emitter(op_ia32_Not, bemit_not);
3811 register_emitter(op_ia32_NotMem, bemit_notmem);
3812 register_emitter(op_ia32_Or, bemit_or);
3813 register_emitter(op_ia32_OrMem, bemit_ormem);
3814 register_emitter(op_ia32_OrMem8Bit, bemit_ormem8bit);
3815 register_emitter(op_ia32_Pop, bemit_pop);
3816 register_emitter(op_ia32_PopEbp, bemit_pop);
3817 register_emitter(op_ia32_PopMem, bemit_popmem);
3818 register_emitter(op_ia32_Push, bemit_push);
3819 register_emitter(op_ia32_RepPrefix, bemit_rep);
3820 register_emitter(op_ia32_Rol, bemit_rol);
3821 register_emitter(op_ia32_RolMem, bemit_rolmem);
3822 register_emitter(op_ia32_Ror, bemit_ror);
3823 register_emitter(op_ia32_RorMem, bemit_rormem);
3824 register_emitter(op_ia32_Sahf, bemit_sahf);
3825 register_emitter(op_ia32_Sar, bemit_sar);
3826 register_emitter(op_ia32_SarMem, bemit_sarmem);
3827 register_emitter(op_ia32_Sbb, bemit_sbb);
3828 register_emitter(op_ia32_Setcc, bemit_setcc);
3829 register_emitter(op_ia32_Shl, bemit_shl);
3830 register_emitter(op_ia32_ShlD, bemit_shld);
3831 register_emitter(op_ia32_ShlMem, bemit_shlmem);
3832 register_emitter(op_ia32_Shr, bemit_shr);
3833 register_emitter(op_ia32_ShrD, bemit_shrd);
3834 register_emitter(op_ia32_ShrMem, bemit_shrmem);
3835 register_emitter(op_ia32_Stc, bemit_stc);
3836 register_emitter(op_ia32_Store, bemit_store);
3837 register_emitter(op_ia32_Store8Bit, bemit_store);
3838 register_emitter(op_ia32_Sub, bemit_sub);
3839 register_emitter(op_ia32_SubMem, bemit_submem);
3840 register_emitter(op_ia32_SubMem8Bit, bemit_submem8bit);
3841 register_emitter(op_ia32_SubSP, bemit_subsp);
3842 register_emitter(op_ia32_SwitchJmp, bemit_switchjmp);
3843 register_emitter(op_ia32_Test, bemit_test);
3844 register_emitter(op_ia32_Test8Bit, bemit_test8bit);
3845 register_emitter(op_ia32_Xor, bemit_xor);
3846 register_emitter(op_ia32_Xor0, bemit_xor0);
3847 register_emitter(op_ia32_XorMem, bemit_xormem);
3848 register_emitter(op_ia32_XorMem8Bit, bemit_xormem8bit);
3849 register_emitter(op_ia32_fabs, bemit_fabs);
3850 register_emitter(op_ia32_fadd, bemit_fadd);
3851 register_emitter(op_ia32_faddp, bemit_faddp);
3852 register_emitter(op_ia32_fchs, bemit_fchs);
3853 register_emitter(op_ia32_fdiv, bemit_fdiv);
3854 register_emitter(op_ia32_fdivp, bemit_fdivp);
3855 register_emitter(op_ia32_fdivr, bemit_fdivr);
3856 register_emitter(op_ia32_fdivrp, bemit_fdivrp);
3857 register_emitter(op_ia32_fild, bemit_fild);
3858 register_emitter(op_ia32_fist, bemit_fist);
3859 register_emitter(op_ia32_fistp, bemit_fistp);
3860 register_emitter(op_ia32_fld, bemit_fld);
3861 register_emitter(op_ia32_fld1, bemit_fld1);
3862 register_emitter(op_ia32_fldz, bemit_fldz);
3863 register_emitter(op_ia32_fmul, bemit_fmul);
3864 register_emitter(op_ia32_fmulp, bemit_fmulp);
3865 register_emitter(op_ia32_fpop, bemit_fpop);
3866 register_emitter(op_ia32_fpush, bemit_fpush);
3867 register_emitter(op_ia32_fpushCopy, bemit_fpushcopy);
3868 register_emitter(op_ia32_fst, bemit_fst);
3869 register_emitter(op_ia32_fstp, bemit_fstp);
3870 register_emitter(op_ia32_fsub, bemit_fsub);
3871 register_emitter(op_ia32_fsubp, bemit_fsubp);
3872 register_emitter(op_ia32_fsubr, bemit_fsubr);
3873 register_emitter(op_ia32_fsubrp, bemit_fsubrp);
3874 register_emitter(op_ia32_fxch, bemit_fxch);
3876 /* ignore the following nodes */
3877 register_emitter(op_ia32_ProduceVal, emit_Nothing);
3878 register_emitter(op_be_Keep, emit_Nothing);
3879 register_emitter(op_be_Start, emit_Nothing);
3880 register_emitter(op_Phi, emit_Nothing);
3881 register_emitter(op_Start, emit_Nothing);
3884 static void gen_binary_block(ir_node *block)
3888 ia32_emit_block_header(block);
3890 /* emit the contents of the block */
3891 sched_foreach(block, node) {
3892 ia32_emit_node(node);
3896 void ia32_gen_binary_routine(ir_graph *irg)
3898 ir_entity *entity = get_irg_entity(irg);
3899 const arch_env_t *arch_env = be_get_irg_arch_env(irg);
3900 ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
3901 ir_node **blk_sched = irg_data->blk_sched;
3904 isa = (ia32_isa_t*) arch_env;
3906 ia32_register_binary_emitters();
3908 be_gas_emit_function_prolog(entity, ia32_cg_config.function_alignment);
3910 /* we use links to point to target blocks */
3911 ir_reserve_resources(irg, IR_RESOURCE_IRN_LINK);
3912 irg_block_walk_graph(irg, ia32_gen_labels, NULL, NULL);
3914 /* initialize next block links */
3915 n = ARR_LEN(blk_sched);
3916 for (i = 0; i < n; ++i) {
3917 ir_node *block = blk_sched[i];
3918 ir_node *prev = i > 0 ? blk_sched[i-1] : NULL;
3920 set_irn_link(block, prev);
3923 for (i = 0; i < n; ++i) {
3924 ir_node *block = blk_sched[i];
3925 gen_binary_block(block);
3928 be_gas_emit_function_epilog(entity);
3929 be_dbg_method_end();
3931 be_emit_write_line();
3933 ir_free_resources(irg, IR_RESOURCE_IRN_LINK);
3937 void ia32_init_emitter(void)
3939 lc_opt_entry_t *be_grp;
3940 lc_opt_entry_t *ia32_grp;
3942 be_grp = lc_opt_get_grp(firm_opt_get_root(), "be");
3943 ia32_grp = lc_opt_get_grp(be_grp, "ia32");
3945 lc_opt_add_table(ia32_grp, ia32_emitter_options);
3949 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.emitter");