2 * This file implements the node emitter.
3 * @author Christian Wuerdig
22 #include "iredges_t.h"
25 #include "../besched_t.h"
26 #include "../benode_t.h"
28 #include "../be_dbgout.h"
30 #include "ia32_emitter.h"
31 #include "gen_ia32_emitter.h"
32 #include "gen_ia32_regalloc_if.h"
33 #include "ia32_nodes_attr.h"
34 #include "ia32_new_nodes.h"
35 #include "ia32_map_regs.h"
36 #include "bearch_ia32_t.h"
38 #define BLOCK_PREFIX(x) ".L" x
40 #define SNPRINTF_BUF_LEN 128
42 /* global arch_env for lc_printf functions */
43 static const arch_env_t *arch_env = NULL;
45 /** by default, we generate assembler code for the Linux gas */
46 asm_flavour_t asm_flavour = ASM_LINUX_GAS;
49 * Switch to a new section
51 void ia32_switch_section(FILE *F, section_t sec) {
52 static section_t curr_sec = NO_SECTION;
53 static const char *text[ASM_MAX][SECTION_MAX] = {
59 ".section\t.tbss,\"awT\",@nobits",
60 ".section\t.ctors,\"aw\",@progbits"
65 ".section .rdata,\"dr\"",
67 ".section\t.tbss,\"awT\",@nobits",
68 ".section\t.ctors,\"aw\",@progbits"
87 fprintf(F, "\t%s\n", text[asm_flavour][sec]);
95 static void ia32_dump_function_object(FILE *F, const char *name)
97 switch (asm_flavour) {
99 fprintf(F, "\t.type\t%s, @function\n", name);
102 fprintf(F, "\t.def\t%s;\t.scl\t2;\t.type\t32;\t.endef\n", name);
109 static void ia32_dump_function_size(FILE *F, const char *name)
111 switch (asm_flavour) {
113 fprintf(F, "\t.size\t%s, .-%s\n", name, name);
120 /*************************************************************
122 * (_) | | / _| | | | |
123 * _ __ _ __ _ _ __ | |_| |_ | |__ ___| |_ __ ___ _ __
124 * | '_ \| '__| | '_ \| __| _| | '_ \ / _ \ | '_ \ / _ \ '__|
125 * | |_) | | | | | | | |_| | | | | | __/ | |_) | __/ |
126 * | .__/|_| |_|_| |_|\__|_| |_| |_|\___|_| .__/ \___|_|
129 *************************************************************/
131 /* We always pass the ir_node which is a pointer. */
132 static int ia32_get_arg_type(const lc_arg_occ_t *occ) {
133 return lc_arg_type_ptr;
138 * Returns the register at in position pos.
140 static const arch_register_t *get_in_reg(const ir_node *irn, int pos) {
142 const arch_register_t *reg = NULL;
144 assert(get_irn_arity(irn) > pos && "Invalid IN position");
146 /* The out register of the operator at position pos is the
147 in register we need. */
148 op = get_irn_n(irn, pos);
150 reg = arch_get_irn_register(arch_env, op);
152 assert(reg && "no in register found");
154 /* in case of a joker register: just return a valid register */
155 if (arch_register_type_is(reg, joker)) {
156 arch_register_req_t req;
157 const arch_register_req_t *p_req;
159 /* ask for the requirements */
160 p_req = arch_get_register_req(arch_env, &req, irn, pos);
162 if (arch_register_req_is(p_req, limited)) {
163 /* in case of limited requirements: get the first allowed register */
165 bitset_t *bs = bitset_alloca(arch_register_class_n_regs(p_req->cls));
168 p_req->limited(p_req->limited_env, bs);
169 idx = bitset_next_set(bs, 0);
170 reg = arch_register_for_index(p_req->cls, idx);
173 /* otherwise get first register in class */
174 reg = arch_register_for_index(p_req->cls, 0);
182 * Returns the register at out position pos.
184 static const arch_register_t *get_out_reg(const ir_node *irn, int pos) {
186 const arch_register_t *reg = NULL;
188 /* 1st case: irn is not of mode_T, so it has only */
189 /* one OUT register -> good */
190 /* 2nd case: irn is of mode_T -> collect all Projs and ask the */
191 /* Proj with the corresponding projnum for the register */
193 if (get_irn_mode(irn) != mode_T) {
194 reg = arch_get_irn_register(arch_env, irn);
196 else if (is_ia32_irn(irn)) {
197 reg = get_ia32_out_reg(irn, pos);
200 const ir_edge_t *edge;
202 foreach_out_edge(irn, edge) {
203 proj = get_edge_src_irn(edge);
204 assert(is_Proj(proj) && "non-Proj from mode_T node");
205 if (get_Proj_proj(proj) == pos) {
206 reg = arch_get_irn_register(arch_env, proj);
212 assert(reg && "no out register found");
222 * Returns the name of the in register at position pos.
224 static const char *get_ia32_reg_name(ir_node *irn, int pos, enum io_direction in_out) {
225 const arch_register_t *reg;
227 if (in_out == IN_REG) {
228 reg = get_in_reg(irn, pos);
230 if (reg->reg_class == &ia32_reg_classes[CLASS_ia32_vfp]) {
231 /* FIXME: works for binop only */
232 assert(2 <= pos && pos <= 3);
233 reg = get_ia32_attr(irn)->x87[pos - 2];
237 /* destination address mode nodes don't have outputs */
238 if (is_ia32_irn(irn) && get_ia32_op_type(irn) == ia32_AddrModeD) {
242 reg = get_out_reg(irn, pos);
243 if (reg->reg_class == &ia32_reg_classes[CLASS_ia32_vfp])
244 reg = get_ia32_attr(irn)->x87[pos + 2];
246 return arch_register_get_name(reg);
250 * Get the register name for a node.
252 static int ia32_get_reg_name(lc_appendable_t *app,
253 const lc_arg_occ_t *occ, const lc_arg_value_t *arg)
256 ir_node *irn = arg->v_ptr;
257 int nr = occ->width - 1;
260 return lc_appendable_snadd(app, "(null)", 6);
262 buf = get_ia32_reg_name(irn, nr, occ->conversion == 'S' ? IN_REG : OUT_REG);
264 /* append the stupid % to register names */
265 lc_appendable_chadd(app, '%');
266 return lc_appendable_snadd(app, buf, strlen(buf));
270 * Get the x87 register name for a node.
272 static int ia32_get_x87_name(lc_appendable_t *app,
273 const lc_arg_occ_t *occ, const lc_arg_value_t *arg)
276 ir_node *irn = arg->v_ptr;
277 int nr = occ->width - 1;
282 return lc_appendable_snadd(app, "(null)", 6);
284 attr = get_ia32_attr(irn);
285 buf = attr->x87[nr]->name;
287 res += lc_appendable_chadd(app, '%');
288 res += lc_appendable_snadd(app, buf, strlen(buf));
294 * Returns the tarval, offset or scale of an ia32 as a string.
296 static int ia32_const_to_str(lc_appendable_t *app,
297 const lc_arg_occ_t *occ, const lc_arg_value_t *arg)
300 ir_node *irn = arg->v_ptr;
303 return lc_arg_append(app, occ, "(null)", 6);
305 if (occ->conversion == 'C') {
306 buf = get_ia32_cnst(irn);
309 buf = get_ia32_am_offs(irn);
312 return buf ? lc_appendable_snadd(app, buf, strlen(buf)) : 0;
316 * Determines the SSE suffix depending on the mode.
318 static int ia32_get_mode_suffix(lc_appendable_t *app,
319 const lc_arg_occ_t *occ, const lc_arg_value_t *arg)
321 ir_node *irn = arg->v_ptr;
322 ir_mode *mode = get_irn_mode(irn);
324 if (mode == mode_T) {
325 mode = get_ia32_res_mode(irn);
327 mode = get_ia32_ls_mode(irn);
331 return lc_arg_append(app, occ, "(null)", 6);
333 if (mode_is_float(mode)) {
334 return lc_appendable_chadd(app, get_mode_size_bits(mode) == 32 ? 's' : 'd');
337 return lc_appendable_chadd(app, mode_is_signed(mode) ? 's' : 'z');
342 * Return the ia32 printf arg environment.
343 * We use the firm environment with some additional handlers.
345 const lc_arg_env_t *ia32_get_arg_env(void) {
346 static lc_arg_env_t *env = NULL;
348 static const lc_arg_handler_t ia32_reg_handler = { ia32_get_arg_type, ia32_get_reg_name };
349 static const lc_arg_handler_t ia32_const_handler = { ia32_get_arg_type, ia32_const_to_str };
350 static const lc_arg_handler_t ia32_mode_handler = { ia32_get_arg_type, ia32_get_mode_suffix };
351 static const lc_arg_handler_t ia32_x87_handler = { ia32_get_arg_type, ia32_get_x87_name };
354 /* extend the firm printer */
355 env = firm_get_arg_env();
357 lc_arg_register(env, "ia32:sreg", 'S', &ia32_reg_handler);
358 lc_arg_register(env, "ia32:dreg", 'D', &ia32_reg_handler);
359 lc_arg_register(env, "ia32:cnst", 'C', &ia32_const_handler);
360 lc_arg_register(env, "ia32:offs", 'O', &ia32_const_handler);
361 lc_arg_register(env, "ia32:mode", 'M', &ia32_mode_handler);
362 lc_arg_register(env, "ia32:x87", 'X', &ia32_x87_handler);
368 static const char *ia32_get_reg_name_for_mode(ia32_emit_env_t *env, ir_mode *mode, const arch_register_t *reg) {
369 switch(get_mode_size_bits(mode)) {
371 return ia32_get_mapped_reg_name(env->isa->regs_8bit, reg);
373 return ia32_get_mapped_reg_name(env->isa->regs_16bit, reg);
375 return (char *)arch_register_get_name(reg);
380 * Emits registers and/or address mode of a binary operation.
382 const char *ia32_emit_binop(const ir_node *n, ia32_emit_env_t *env) {
383 static char *buf = NULL;
385 /* verify that this function is never called on non-AM supporting operations */
386 //assert(get_ia32_am_support(n) != ia32_am_None && "emit binop expects addressmode support");
388 #define PRODUCES_RESULT(n) \
389 (!(is_ia32_St(n) || \
390 is_ia32_Store8Bit(n) || \
391 is_ia32_CondJmp(n) || \
392 is_ia32_xCondJmp(n) || \
393 is_ia32_CmpSet(n) || \
394 is_ia32_xCmpSet(n) || \
395 is_ia32_SwitchJmp(n)))
398 buf = xcalloc(1, SNPRINTF_BUF_LEN);
401 memset(buf, 0, SNPRINTF_BUF_LEN);
404 switch(get_ia32_op_type(n)) {
406 if (is_ia32_ImmConst(n)) {
407 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%3S, %s", n, get_ia32_cnst(n));
409 else if (is_ia32_ImmSymConst(n)) {
410 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%3S, OFFSET FLAT:%s", n, get_ia32_cnst(n));
413 const arch_register_t *in1 = get_in_reg(n, 2);
414 const arch_register_t *in2 = get_in_reg(n, 3);
415 const arch_register_t *out = PRODUCES_RESULT(n) ? get_out_reg(n, 0) : NULL;
416 const arch_register_t *in;
419 in = out ? (REGS_ARE_EQUAL(out, in2) ? in1 : in2) : in2;
420 out = out ? out : in1;
421 in_name = arch_register_get_name(in);
423 if (is_ia32_emit_cl(n)) {
424 assert(REGS_ARE_EQUAL(&ia32_gp_regs[REG_ECX], in) && "shift operation needs ecx");
428 snprintf(buf, SNPRINTF_BUF_LEN, "%%%s, %%%s", arch_register_get_name(out), in_name);
432 if (is_ia32_ImmConst(n) || is_ia32_ImmSymConst(n)) {
433 assert(! PRODUCES_RESULT(n) && "Source AM with Const must not produce result");
434 snprintf(buf, SNPRINTF_BUF_LEN, "%s, %s", get_ia32_cnst(n), ia32_emit_am(n, env));
437 if (PRODUCES_RESULT(n)) {
438 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%1D, %s", n, ia32_emit_am(n, env));
441 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%3S, %s", n, ia32_emit_am(n, env));
446 if (is_ia32_ImmConst(n) || is_ia32_ImmSymConst(n)) {
447 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%s,%s%s",
448 ia32_emit_am(n, env),
449 is_ia32_ImmSymConst(n) ? " OFFSET FLAT:" : " ", /* In case of a symconst we must add OFFSET to */
450 get_ia32_cnst(n)); /* tell the assembler to store it's address. */
453 const arch_register_t *in1 = get_in_reg(n, get_irn_arity(n) == 5 ? 3 : 2);
454 ir_mode *mode = get_ia32_res_mode(n);
457 mode = mode ? mode : get_ia32_ls_mode(n);
458 in_name = ia32_get_reg_name_for_mode(env, mode, in1);
460 if (is_ia32_emit_cl(n)) {
461 assert(REGS_ARE_EQUAL(&ia32_gp_regs[REG_ECX], in1) && "shift operation needs ecx");
465 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%s, %%%s", ia32_emit_am(n, env), in_name);
469 assert(0 && "unsupported op type");
472 #undef PRODUCES_RESULT
478 * Returns the xxx PTR string for a given mode
480 * @param mode the mode
481 * @param x87_insn if non-zero returns the string for a x87 instruction
482 * else for a SSE instruction
484 static const char *pointer_size(ir_mode *mode, int x87_insn)
487 switch (get_mode_size_bits(mode)) {
488 case 8: return "BYTE PTR";
489 case 16: return "WORD PTR";
490 case 32: return "DWORD PTR";
496 case 96: return "XWORD PTR";
497 default: return NULL;
504 * Emits registers and/or address mode of a binary operation.
506 const char *ia32_emit_x87_binop(const ir_node *n, ia32_emit_env_t *env) {
507 static char *buf = NULL;
509 /* verify that this function is never called on non-AM supporting operations */
510 //assert(get_ia32_am_support(n) != ia32_am_None && "emit binop expects addressmode support");
513 buf = xcalloc(1, SNPRINTF_BUF_LEN);
516 memset(buf, 0, SNPRINTF_BUF_LEN);
519 switch(get_ia32_op_type(n)) {
521 if (is_ia32_ImmConst(n) || is_ia32_ImmSymConst(n)) {
522 ir_mode *mode = get_ia32_ls_mode(n);
523 const char *p = pointer_size(mode, 1);
524 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%s %s", p, get_ia32_cnst(n));
527 ia32_attr_t *attr = get_ia32_attr(n);
528 const arch_register_t *in1 = attr->x87[0];
529 const arch_register_t *in2 = attr->x87[1];
530 const arch_register_t *out = attr->x87[2];
531 const arch_register_t *in;
533 in = out ? (REGS_ARE_EQUAL(out, in2) ? in1 : in2) : in2;
534 out = out ? out : in1;
536 snprintf(buf, SNPRINTF_BUF_LEN, "%%%s, %%%s",
537 arch_register_get_name(out), arch_register_get_name(in));
542 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%s", ia32_emit_am(n, env));
545 assert(0 && "unsupported op type");
552 * Emits registers and/or address mode of a unary operation.
554 const char *ia32_emit_unop(const ir_node *n, ia32_emit_env_t *env) {
555 static char *buf = NULL;
558 buf = xcalloc(1, SNPRINTF_BUF_LEN);
561 memset(buf, 0, SNPRINTF_BUF_LEN);
564 switch(get_ia32_op_type(n)) {
566 if (is_ia32_ImmConst(n)) {
567 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%C", n);
569 else if (is_ia32_ImmSymConst(n)) {
570 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "OFFSET FLAT:%C", n);
573 if (is_ia32_MulS(n) || is_ia32_Mulh(n)) {
574 /* MulS and Mulh implicitly multiply by EAX */
575 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%4S", n);
576 } else if(is_ia32_Push(n)) {
577 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%3S", n);
579 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%1D", n);
584 assert(!is_ia32_Push(n));
585 snprintf(buf, SNPRINTF_BUF_LEN, "%s", ia32_emit_am(n, env));
589 Mulh is emitted via emit_unop
590 imul [MEM] means EDX:EAX <- EAX * [MEM]
592 assert((is_ia32_Mulh(n) || is_ia32_MulS(n) || is_ia32_Push(n)) && "Only MulS and Mulh can have AM source as unop");
593 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%s", ia32_emit_am(n, env));
596 assert(0 && "unsupported op type");
603 * Emits address mode.
605 const char *ia32_emit_am(const ir_node *n, ia32_emit_env_t *env) {
606 ia32_am_flavour_t am_flav = get_ia32_am_flavour(n);
610 static struct obstack *obst = NULL;
611 ir_mode *mode = get_ia32_ls_mode(n);
613 if (! is_ia32_Lea(n))
614 assert(mode && "AM node must have ls_mode attribute set.");
617 obst = xcalloc(1, sizeof(*obst));
620 obstack_free(obst, NULL);
623 /* obstack_free with NULL results in an uninitialized obstack */
626 p = pointer_size(mode, ia32_has_x87_register(n) || is_ia32_GetST0(n) || is_ia32_SetST0(n));
628 obstack_printf(obst, "%s ", p);
630 /* emit address mode symconst */
631 if (get_ia32_am_sc(n)) {
632 if (is_ia32_am_sc_sign(n))
633 obstack_printf(obst, "-");
634 obstack_printf(obst, "%s", get_id_str(get_ia32_am_sc(n)));
637 if (am_flav & ia32_B) {
638 obstack_printf(obst, "[");
639 lc_eoprintf(ia32_get_arg_env(), obst, "%1S", n);
643 if (am_flav & ia32_I) {
645 obstack_printf(obst, "+");
648 obstack_printf(obst, "[");
651 lc_eoprintf(ia32_get_arg_env(), obst, "%2S", n);
653 if (am_flav & ia32_S) {
654 obstack_printf(obst, "*%d", 1 << get_ia32_am_scale(n));
660 if (am_flav & ia32_O) {
661 int offs = get_ia32_am_offs_int(n);
664 /* omit explicit + if there was no base or index */
666 obstack_printf(obst, "[%d", offs);
668 obstack_printf(obst, "%+d", offs);
676 obstack_printf(obst, "] ");
678 obstack_1grow(obst, '\0');
679 s = obstack_finish(obst);
687 const char *ia32_emit_adr(const ir_node *irn, ia32_emit_env_t *env)
689 static char buf[SNPRINTF_BUF_LEN];
690 ir_mode *mode = get_ia32_ls_mode(irn);
691 const char *adr = get_ia32_cnst(irn);
692 const char *pref = pointer_size(mode, ia32_has_x87_register(irn));
694 snprintf(buf, SNPRINTF_BUF_LEN, "%s %s", pref ? pref : "", adr);
699 * Formated print of commands and comments.
701 static void ia32_fprintf_format(FILE *F, const ir_node *irn, char *cmd_buf, char *cmnt_buf) {
703 const char *name = irn ? be_retrieve_dbg_info(get_irn_dbg_info((ir_node *)irn), &lineno) : NULL;
706 fprintf(F, "\t%-35s %-60s /* %s:%u */\n", cmd_buf, cmnt_buf, name, lineno);
708 fprintf(F, "\t%-35s %-60s\n", cmd_buf, cmnt_buf);
714 * Add a number to a prefix. This number will not be used a second time.
716 static char *get_unique_label(char *buf, size_t buflen, const char *prefix) {
717 static unsigned long id = 0;
718 snprintf(buf, buflen, "%s%lu", prefix, ++id);
724 /*************************************************
727 * ___ _ __ ___ _| |_ ___ ___ _ __ __| |
728 * / _ \ '_ ` _ \| | __| / __/ _ \| '_ \ / _` |
729 * | __/ | | | | | | |_ | (_| (_) | | | | (_| |
730 * \___|_| |_| |_|_|\__| \___\___/|_| |_|\__,_|
732 *************************************************/
735 #define IA32_DO_EMIT(irn) ia32_fprintf_format(F, irn, cmd_buf, cmnt_buf)
738 * coding of conditions
740 struct cmp2conditon_t {
746 * positive conditions for signed compares
748 static const struct cmp2conditon_t cmp2condition_s[] = {
749 { NULL, pn_Cmp_False }, /* always false */
750 { "e", pn_Cmp_Eq }, /* == */
751 { "l", pn_Cmp_Lt }, /* < */
752 { "le", pn_Cmp_Le }, /* <= */
753 { "g", pn_Cmp_Gt }, /* > */
754 { "ge", pn_Cmp_Ge }, /* >= */
755 { "ne", pn_Cmp_Lg }, /* != */
756 { "ordered", pn_Cmp_Leg }, /* Floating point: ordered */
757 { "unordered", pn_Cmp_Uo }, /* FLoting point: unordered */
758 { "e", pn_Cmp_Ue }, /* Floating point: unordered or == */
759 { "b", pn_Cmp_Ul }, /* Floating point: unordered or < */
760 { "be", pn_Cmp_Ule }, /* Floating point: unordered or <= */
761 { "a", pn_Cmp_Ug }, /* Floating point: unordered or > */
762 { "ae", pn_Cmp_Uge }, /* Floating point: unordered or >= */
763 { "ne", pn_Cmp_Ne }, /* Floating point: unordered or != */
764 { NULL, pn_Cmp_True }, /* always true */
768 * positive conditions for unsigned compares
770 static const struct cmp2conditon_t cmp2condition_u[] = {
771 { NULL, pn_Cmp_False }, /* always false */
772 { "e", pn_Cmp_Eq }, /* == */
773 { "b", pn_Cmp_Lt }, /* < */
774 { "be", pn_Cmp_Le }, /* <= */
775 { "a", pn_Cmp_Gt }, /* > */
776 { "ae", pn_Cmp_Ge }, /* >= */
777 { "ne", pn_Cmp_Lg }, /* != */
778 { "ordered", pn_Cmp_Leg }, /* Floating point: ordered */
779 { "unordered", pn_Cmp_Uo }, /* FLoting point: unordered */
780 { "e", pn_Cmp_Ue }, /* Floating point: unordered or == */
781 { "b", pn_Cmp_Ul }, /* Floating point: unordered or < */
782 { "be", pn_Cmp_Ule }, /* Floating point: unordered or <= */
783 { "a", pn_Cmp_Ug }, /* Floating point: unordered or > */
784 { "ae", pn_Cmp_Uge }, /* Floating point: unordered or >= */
785 { "ne", pn_Cmp_Ne }, /* Floating point: unordered or != */
786 { NULL, pn_Cmp_True }, /* always true */
790 * returns the condition code
792 static const char *get_cmp_suffix(int cmp_code, int unsigned_cmp)
794 assert(cmp2condition_s[cmp_code].num == cmp_code);
795 assert(cmp2condition_u[cmp_code].num == cmp_code);
797 return unsigned_cmp ? cmp2condition_u[cmp_code & 7].name : cmp2condition_s[cmp_code & 7].name;
801 * Returns the target block for a control flow node.
803 static ir_node *get_cfop_target_block(const ir_node *irn) {
804 return get_irn_link(irn);
808 * Returns the target label for a control flow node.
810 static char *get_cfop_target(const ir_node *irn, char *buf) {
811 ir_node *bl = get_cfop_target_block(irn);
813 snprintf(buf, SNPRINTF_BUF_LEN, BLOCK_PREFIX("%ld"), get_irn_node_nr(bl));
817 /** Return the next block in Block schedule */
818 static ir_node *next_blk_sched(const ir_node *block) {
819 return get_irn_link(block);
823 * Returns the Proj with projection number proj and NOT mode_M
825 static ir_node *get_proj(const ir_node *irn, long proj) {
826 const ir_edge_t *edge;
829 assert(get_irn_mode(irn) == mode_T && "expected mode_T node");
831 foreach_out_edge(irn, edge) {
832 src = get_edge_src_irn(edge);
834 assert(is_Proj(src) && "Proj expected");
835 if (get_irn_mode(src) == mode_M)
838 if (get_Proj_proj(src) == proj)
845 * Emits the jump sequence for a conditional jump (cmp + jmp_true + jmp_false)
847 static void finish_CondJmp(FILE *F, const ir_node *irn, ir_mode *mode) {
848 const ir_node *proj_true;
849 const ir_node *proj_false;
850 const ir_node *block;
851 const ir_node *next_block;
852 char buf[SNPRINTF_BUF_LEN];
853 char cmd_buf[SNPRINTF_BUF_LEN];
854 char cmnt_buf[SNPRINTF_BUF_LEN];
859 /* get both Proj's */
860 proj_true = get_proj(irn, pn_Cond_true);
861 assert(proj_true && "CondJmp without true Proj");
863 proj_false = get_proj(irn, pn_Cond_false);
864 assert(proj_false && "CondJmp without false Proj");
866 pnc = get_ia32_pncode(irn);
868 /* for now, the code works for scheduled and non-schedules blocks */
869 block = get_nodes_block(irn);
871 /* we have a block schedule */
872 next_block = next_blk_sched(block);
874 if (get_cfop_target_block(proj_true) == next_block) {
875 /* exchange both proj's so the second one can be omitted */
876 const ir_node *t = proj_true;
878 proj_true = proj_false;
881 pnc = get_negated_pnc(pnc, mode);
884 /* the first Proj must always be created */
885 is_unsigned = mode_is_float(mode) || ! mode_is_signed(mode);
887 /* in case of unordered compare, check for parity */
888 if (pnc & pn_Cmp_Uo) {
889 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "jp %s", get_cfop_target(proj_true, buf));
890 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* jump to false if result is unordered */");
894 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "j%s %s",
895 get_cmp_suffix(pnc, is_unsigned),
896 get_cfop_target(proj_true, buf));
897 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* %s(a, b) %s*/",
898 get_pnc_string(pnc), flipped ? "(was flipped)" : "");
901 /* the second Proj might be a fallthrough */
902 if (get_cfop_target_block(proj_false) != next_block) {
903 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "jmp %s", get_cfop_target(proj_false, buf));
904 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* otherwise */");
908 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* fallthrough %s */", get_cfop_target(proj_false, buf));
914 * Emits code for conditional jump.
916 static void CondJmp_emitter(const ir_node *irn, ia32_emit_env_t *env) {
918 char cmd_buf[SNPRINTF_BUF_LEN];
919 char cmnt_buf[SNPRINTF_BUF_LEN];
921 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "cmp %s", ia32_emit_binop(irn, env));
922 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F */", irn);
924 finish_CondJmp(F, irn, get_ia32_res_mode(irn));
928 * Emits code for conditional jump with two variables.
930 static void emit_ia32_CondJmp(const ir_node *irn, ia32_emit_env_t *env) {
931 CondJmp_emitter(irn, env);
935 * Emits code for conditional test and jump.
937 static void TestJmp_emitter(const ir_node *irn, ia32_emit_env_t *env) {
939 #define IA32_IS_IMMOP (is_ia32_ImmConst(irn) || is_ia32_ImmSymConst(irn))
942 const char *op1 = arch_register_get_name(get_in_reg(irn, 0));
943 const char *op2 = IA32_IS_IMMOP ? get_ia32_cnst(irn) : NULL;
944 char cmd_buf[SNPRINTF_BUF_LEN];
945 char cmnt_buf[SNPRINTF_BUF_LEN];
948 op2 = arch_register_get_name(get_in_reg(irn, 1));
950 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "test %%%s,%s%s ", op1, IA32_IS_IMMOP ? " " : " %", op2);
951 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F */", irn);
954 finish_CondJmp(F, irn, get_ia32_res_mode(irn));
960 * Emits code for conditional test and jump with two variables.
962 static void emit_ia32_TestJmp(const ir_node *irn, ia32_emit_env_t *env) {
963 TestJmp_emitter(irn, env);
966 static void emit_ia32_CJmp(const ir_node *irn, ia32_emit_env_t *env) {
968 char cmd_buf[SNPRINTF_BUF_LEN];
969 char cmnt_buf[SNPRINTF_BUF_LEN];
971 snprintf(cmd_buf, SNPRINTF_BUF_LEN, " ");
972 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F omitted redundant test */", irn);
974 finish_CondJmp(F, irn, get_ia32_res_mode(irn));
977 static void emit_ia32_CJmpAM(const ir_node *irn, ia32_emit_env_t *env) {
979 char cmd_buf[SNPRINTF_BUF_LEN];
980 char cmnt_buf[SNPRINTF_BUF_LEN];
982 snprintf(cmd_buf, SNPRINTF_BUF_LEN, " ");
983 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F omitted redundant test/cmp */", irn);
985 finish_CondJmp(F, irn, get_ia32_res_mode(irn));
989 * Emits code for conditional SSE floating point jump with two variables.
991 static void emit_ia32_xCondJmp(ir_node *irn, ia32_emit_env_t *env) {
993 char cmd_buf[SNPRINTF_BUF_LEN];
994 char cmnt_buf[SNPRINTF_BUF_LEN];
995 const lc_arg_env_t *arg_env = ia32_get_arg_env();
997 lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "ucomis%M %s", irn, ia32_emit_binop(irn, env));
998 lc_esnprintf(arg_env, cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F */", irn);
1001 finish_CondJmp(F, irn, mode_F);
1005 * Emits code for conditional x87 floating point jump with two variables.
1007 static void emit_ia32_x87CondJmp(ir_node *irn, ia32_emit_env_t *env) {
1009 char cmd_buf[SNPRINTF_BUF_LEN];
1010 char cmnt_buf[SNPRINTF_BUF_LEN];
1011 ia32_attr_t *attr = get_ia32_attr(irn);
1012 const char *reg = attr->x87[1]->name;
1013 const char *instr = "fcom";
1016 switch (get_ia32_irn_opcode(irn)) {
1017 case iro_ia32_fcomrJmp:
1019 case iro_ia32_fcomJmp:
1023 case iro_ia32_fcomrpJmp:
1025 case iro_ia32_fcompJmp:
1028 case iro_ia32_fcomrppJmp:
1030 case iro_ia32_fcomppJmp:
1037 set_ia32_pncode(irn, (long)get_inversed_pnc(get_ia32_pncode(irn)));
1039 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "%s %s%s", instr, reg[0] == '\0' ? "" : "%", reg);
1040 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F */", irn);
1042 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "fnstsw %%ax", irn);
1043 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* Store x87 FPU Control Word */");
1045 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "sahf");
1046 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* Store ah into flags */");
1049 /* the compare flags must be evaluated using carry , ie unsigned */
1050 finish_CondJmp(F, irn, mode_Iu);
1053 static void CMov_emitter(ir_node *irn, ia32_emit_env_t *env) {
1055 const lc_arg_env_t *arg_env = ia32_get_arg_env();
1056 ir_mode *mode = get_irn_mode(get_irn_n(irn, 0));
1057 int is_unsigned = mode_is_float(mode) || ! mode_is_signed(mode);
1058 const char *cmp_suffix = get_cmp_suffix(get_ia32_pncode(irn), is_unsigned);
1059 int is_PsiCondCMov = is_ia32_PsiCondCMov(irn);
1060 int idx_left = 2 - is_PsiCondCMov;
1061 int idx_right = 3 - is_PsiCondCMov;
1063 char cmd_buf[SNPRINTF_BUF_LEN];
1064 char cmnt_buf[SNPRINTF_BUF_LEN];
1065 const arch_register_t *in1, *in2, *out;
1067 out = arch_get_irn_register(env->arch_env, irn);
1068 in1 = arch_get_irn_register(env->arch_env, get_irn_n(irn, idx_left));
1069 in2 = arch_get_irn_register(env->arch_env, get_irn_n(irn, idx_right));
1071 /* we have to emit the cmp first, because the destination register */
1072 /* could be one of the compare registers */
1073 if (is_ia32_CmpCMov(irn)) {
1074 lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "cmp %1S, %2S", irn, irn);
1076 else if (is_ia32_xCmpCMov(irn)) {
1077 lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "ucomis%M %1S, %2S", get_irn_n(irn, 0), irn, irn);
1079 else if (is_PsiCondCMov) {
1080 /* omit compare because flags are already set by And/Or */
1081 lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "test %1S, %1S", irn, irn);
1084 assert(0 && "unsupported CMov");
1086 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* Psi condition */" );
1089 if (REGS_ARE_EQUAL(out, in2)) {
1090 /* best case: default in == out -> do nothing */
1092 else if (REGS_ARE_EQUAL(out, in1)) {
1093 /* true in == out -> need complement compare and exchange true and default in */
1094 ir_node *t = get_irn_n(irn, idx_left);
1095 set_irn_n(irn, idx_left, get_irn_n(irn, idx_right));
1096 set_irn_n(irn, idx_right, t);
1098 cmp_suffix = get_cmp_suffix(get_negated_pnc(get_ia32_pncode(irn), get_irn_mode(irn)), is_unsigned);
1102 /* out is different from in: need copy default -> out */
1104 lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "mov %1D, %3S", irn, irn);
1106 lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "mov %1D, %4S", irn, irn);
1108 lc_esnprintf(arg_env, cmnt_buf, SNPRINTF_BUF_LEN, "/* copy default -> out */" );
1113 lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "cmov%s %1D, %2S", cmp_suffix, irn, irn);
1115 lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "cmov%s %1D, %3S", cmp_suffix, irn, irn);
1117 lc_esnprintf(arg_env, cmnt_buf, SNPRINTF_BUF_LEN, "/* condition is true case */" );
1121 static void emit_ia32_CmpCMov(ir_node *irn, ia32_emit_env_t *env) {
1122 CMov_emitter(irn, env);
1125 static void emit_ia32_PsiCondCMov(ir_node *irn, ia32_emit_env_t *env) {
1126 CMov_emitter(irn, env);
1129 static void emit_ia32_xCmpCMov(ir_node *irn, ia32_emit_env_t *env) {
1130 CMov_emitter(irn, env);
1133 static void Set_emitter(ir_node *irn, ir_mode *mode, ia32_emit_env_t *env) {
1135 const lc_arg_env_t *arg_env = ia32_get_arg_env();
1136 int is_unsigned = mode_is_float(mode) || ! mode_is_signed(mode);
1137 const char *cmp_suffix = get_cmp_suffix(get_ia32_pncode(irn), is_unsigned);
1138 const char *reg8bit;
1140 char cmd_buf[SNPRINTF_BUF_LEN];
1141 char cmnt_buf[SNPRINTF_BUF_LEN];
1142 const arch_register_t *out;
1144 out = arch_get_irn_register(env->arch_env, irn);
1145 reg8bit = ia32_get_mapped_reg_name(env->isa->regs_8bit, out);
1147 if (is_ia32_CmpSet(irn)) {
1148 lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "cmp %s", ia32_emit_binop(irn, env));
1150 else if (is_ia32_xCmpSet(irn)) {
1151 lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "ucomis%M %s", get_irn_n(irn, 2), ia32_emit_binop(irn, env));
1153 else if (is_ia32_PsiCondSet(irn)) {
1154 lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "cmp %1S, 0", irn);
1157 assert(0 && "unsupported Set");
1159 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* calculate Psi condition */" );
1162 /* use mov to clear target because it doesn't affect the eflags */
1163 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "mov %%%s, 0", arch_register_get_name(out));
1164 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* clear target as set modifies only lower 8 bit */");
1167 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "set%s %%%s", cmp_suffix, reg8bit);
1168 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* set 1 iff true, 0 otherweise */" );
1172 static void emit_ia32_CmpSet(ir_node *irn, ia32_emit_env_t *env) {
1173 Set_emitter(irn, get_irn_mode(get_irn_n(irn, 2)), env);
1176 static void emit_ia32_PsiCondSet(ir_node *irn, ia32_emit_env_t *env) {
1177 Set_emitter(irn, get_irn_mode(get_irn_n(irn, 0)), env);
1180 static void emit_ia32_xCmpSet(ir_node *irn, ia32_emit_env_t *env) {
1181 Set_emitter(irn, get_irn_mode(get_irn_n(irn, 2)), env);
1184 static void emit_ia32_xCmp(ir_node *irn, ia32_emit_env_t *env) {
1186 const lc_arg_env_t *arg_env = ia32_get_arg_env();
1188 long pnc = get_ia32_pncode(irn);
1189 long unord = pnc & pn_Cmp_Uo;
1190 char cmd_buf[SNPRINTF_BUF_LEN];
1191 char cmnt_buf[SNPRINTF_BUF_LEN];
1194 case pn_Cmp_Leg: /* odered */
1197 case pn_Cmp_Uo: /* unordered */
1201 case pn_Cmp_Eq: /* == */
1205 case pn_Cmp_Lt: /* < */
1209 case pn_Cmp_Le: /* <= */
1213 case pn_Cmp_Gt: /* > */
1217 case pn_Cmp_Ge: /* >= */
1221 case pn_Cmp_Lg: /* != */
1226 assert(sse_pnc >= 0 && "unsupported compare");
1228 if (unord && sse_pnc != 3) {
1230 We need a separate compare against unordered.
1231 Quick and Dirty solution:
1232 - get some memory on stack
1236 - and result and stored result
1239 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "sub %%esp, 8");
1240 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* reserve some space for unordered compare result */");
1242 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "cmpsd %s, 3", ia32_emit_binop(irn, env));
1243 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* SSE compare: unordered */");
1245 lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "movsd [%%esp], %1D", irn);
1246 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* store compare result */");
1250 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "cmpsd %s, %d", ia32_emit_binop(irn, env), sse_pnc);
1251 lc_esnprintf(arg_env, cmnt_buf, SNPRINTF_BUF_LEN, "/* SSE compare (%+F) with result in %1D */", irn, irn);
1254 if (unord && sse_pnc != 3) {
1255 lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "andpd %1D, [%%esp]", irn);
1256 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* build the final result */");
1258 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "add %%esp, 8");
1259 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* free allocated space */");
1264 /*********************************************************
1267 * ___ _ __ ___ _| |_ _ _ _ _ __ ___ _ __ ___
1268 * / _ \ '_ ` _ \| | __| | | | | | '_ ` _ \| '_ \/ __|
1269 * | __/ | | | | | | |_ | | |_| | | | | | | |_) \__ \
1270 * \___|_| |_| |_|_|\__| | |\__,_|_| |_| |_| .__/|___/
1273 *********************************************************/
1275 /* jump table entry (target and corresponding number) */
1276 typedef struct _branch_t {
1281 /* jump table for switch generation */
1282 typedef struct _jmp_tbl_t {
1283 ir_node *defProj; /**< default target */
1284 int min_value; /**< smallest switch case */
1285 int max_value; /**< largest switch case */
1286 int num_branches; /**< number of jumps */
1287 char *label; /**< label of the jump table */
1288 branch_t *branches; /**< jump array */
1292 * Compare two variables of type branch_t. Used to sort all switch cases
1294 static int ia32_cmp_branch_t(const void *a, const void *b) {
1295 branch_t *b1 = (branch_t *)a;
1296 branch_t *b2 = (branch_t *)b;
1298 if (b1->value <= b2->value)
1305 * Emits code for a SwitchJmp (creates a jump table if
1306 * possible otherwise a cmp-jmp cascade). Port from
1309 static void emit_ia32_SwitchJmp(const ir_node *irn, ia32_emit_env_t *emit_env) {
1310 unsigned long interval;
1311 char buf[SNPRINTF_BUF_LEN];
1312 int last_value, i, pn;
1315 const ir_edge_t *edge;
1316 const lc_arg_env_t *env = ia32_get_arg_env();
1317 FILE *F = emit_env->out;
1318 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1320 /* fill the table structure */
1321 tbl.label = xmalloc(SNPRINTF_BUF_LEN);
1322 tbl.label = get_unique_label(tbl.label, SNPRINTF_BUF_LEN, ".TBL_");
1324 tbl.num_branches = get_irn_n_edges(irn);
1325 tbl.branches = xcalloc(tbl.num_branches, sizeof(tbl.branches[0]));
1326 tbl.min_value = INT_MAX;
1327 tbl.max_value = INT_MIN;
1330 /* go over all proj's and collect them */
1331 foreach_out_edge(irn, edge) {
1332 proj = get_edge_src_irn(edge);
1333 assert(is_Proj(proj) && "Only proj allowed at SwitchJmp");
1335 pn = get_Proj_proj(proj);
1337 /* create branch entry */
1338 tbl.branches[i].target = proj;
1339 tbl.branches[i].value = pn;
1341 tbl.min_value = pn < tbl.min_value ? pn : tbl.min_value;
1342 tbl.max_value = pn > tbl.max_value ? pn : tbl.max_value;
1344 /* check for default proj */
1345 if (pn == get_ia32_pncode(irn)) {
1346 assert(tbl.defProj == NULL && "found two defProjs at SwitchJmp");
1353 /* sort the branches by their number */
1354 qsort(tbl.branches, tbl.num_branches, sizeof(tbl.branches[0]), ia32_cmp_branch_t);
1356 /* two-complement's magic make this work without overflow */
1357 interval = tbl.max_value - tbl.min_value;
1359 /* emit the table */
1360 lc_esnprintf(env, cmd_buf, SNPRINTF_BUF_LEN, "cmp %1S, %u", irn, interval);
1361 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* compare for switch */");
1364 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "ja %s", get_cfop_target(tbl.defProj, buf));
1365 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* default jump if out of range */");
1368 if (tbl.num_branches > 1) {
1371 lc_esnprintf(env, cmd_buf, SNPRINTF_BUF_LEN, "jmp %s[%1S*4]", tbl.label, irn);
1372 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* get jump table entry as target */");
1375 ia32_switch_section(F, SECTION_RODATA);
1376 fprintf(F, "\t.align 4\n");
1378 fprintf(F, "%s:\n", tbl.label);
1380 snprintf(cmd_buf, SNPRINTF_BUF_LEN, ".long %s", get_cfop_target(tbl.branches[0].target, buf));
1381 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* case %d */", tbl.branches[0].value);
1384 last_value = tbl.branches[0].value;
1385 for (i = 1; i < tbl.num_branches; ++i) {
1386 while (++last_value < tbl.branches[i].value) {
1387 snprintf(cmd_buf, SNPRINTF_BUF_LEN, ".long %s", get_cfop_target(tbl.defProj, buf));
1388 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* default case */");
1391 snprintf(cmd_buf, SNPRINTF_BUF_LEN, ".long %s", get_cfop_target(tbl.branches[i].target, buf));
1392 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* case %d */", last_value);
1395 ia32_switch_section(F, SECTION_TEXT);
1398 /* one jump is enough */
1399 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "jmp %s", get_cfop_target(tbl.branches[0].target, buf));
1400 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* only one case given */");
1411 * Emits code for a unconditional jump.
1413 static void emit_Jmp(const ir_node *irn, ia32_emit_env_t *env) {
1414 ir_node *block, *next_bl;
1416 char buf[SNPRINTF_BUF_LEN], cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1418 /* for now, the code works for scheduled and non-schedules blocks */
1419 block = get_nodes_block(irn);
1421 /* we have a block schedule */
1422 next_bl = next_blk_sched(block);
1423 if (get_cfop_target_block(irn) != next_bl) {
1424 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "jmp %s", get_cfop_target(irn, buf));
1425 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F(%+F) */", irn, get_cfop_target_block(irn));
1429 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* fallthrough %s */", get_cfop_target(irn, buf));
1434 /****************************
1437 * _ __ _ __ ___ _ ___
1438 * | '_ \| '__/ _ \| |/ __|
1439 * | |_) | | | (_) | |\__ \
1440 * | .__/|_| \___/| ||___/
1443 ****************************/
1446 * Emits code for a proj -> node
1448 static void emit_Proj(const ir_node *irn, ia32_emit_env_t *env) {
1449 ir_node *pred = get_Proj_pred(irn);
1451 if (get_irn_op(pred) == op_Start) {
1452 switch(get_Proj_proj(irn)) {
1453 case pn_Start_X_initial_exec:
1462 /**********************************
1465 * | | ___ _ __ _ _| |_) |
1466 * | | / _ \| '_ \| | | | _ <
1467 * | |___| (_) | |_) | |_| | |_) |
1468 * \_____\___/| .__/ \__, |____/
1471 **********************************/
1474 * Emit movsb/w instructions to make mov count divideable by 4
1476 static void emit_CopyB_prolog(FILE *F, const ir_node *irn, int rem) {
1477 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1479 ir_fprintf(F, "\t/* memcopy prolog %+F */\n", irn);
1481 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "cld");
1482 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* copy direction forward */");
1487 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "movsb");
1488 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* memcopy remainder 1 */");
1492 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "movsw");
1493 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* memcopy remainder 2 */");
1497 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "movsb");
1498 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* memcopy remainder 3 */");
1500 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "movsw");
1501 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* memcopy remainder 3 */");
1509 * Emit rep movsd instruction for memcopy.
1511 static void emit_ia32_CopyB(const ir_node *irn, ia32_emit_env_t *emit_env) {
1512 FILE *F = emit_env->out;
1513 tarval *tv = get_ia32_Immop_tarval(irn);
1514 int rem = get_tarval_long(tv);
1515 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1517 emit_CopyB_prolog(F, irn, rem);
1519 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "rep movsd");
1520 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* memcopy */");
1525 * Emits unrolled memcopy.
1527 static void emit_ia32_CopyB_i(const ir_node *irn, ia32_emit_env_t *emit_env) {
1528 tarval *tv = get_ia32_Immop_tarval(irn);
1529 int size = get_tarval_long(tv);
1530 FILE *F = emit_env->out;
1531 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1533 emit_CopyB_prolog(F, irn, size & 0x3);
1537 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "movsd");
1538 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* memcopy unrolled */");
1545 /***************************
1549 * | | / _ \| '_ \ \ / /
1550 * | |___| (_) | | | \ V /
1551 * \_____\___/|_| |_|\_/
1553 ***************************/
1556 * Emit code for conversions (I, FP), (FP, I) and (FP, FP).
1558 static void emit_ia32_Conv_with_FP(const ir_node *irn, ia32_emit_env_t *emit_env) {
1559 FILE *F = emit_env->out;
1560 const lc_arg_env_t *env = ia32_get_arg_env();
1561 ir_mode *src_mode = get_ia32_Conv_src_mode(irn);
1562 ir_mode *tgt_mode = get_ia32_Conv_tgt_mode(irn);
1563 char *from, *to, buf[64];
1564 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1566 from = mode_is_float(src_mode) ? (get_mode_size_bits(src_mode) == 32 ? "ss" : "sd") : "si";
1567 to = mode_is_float(tgt_mode) ? (get_mode_size_bits(tgt_mode) == 32 ? "ss" : "sd") : "si";
1569 switch(get_ia32_op_type(irn)) {
1571 lc_esnprintf(env, buf, sizeof(buf), "%1D, %3S", irn, irn);
1573 case ia32_AddrModeS:
1574 lc_esnprintf(env, buf, sizeof(buf), "%1D, %s", irn, ia32_emit_am(irn, emit_env));
1577 assert(0 && "unsupported op type for Conv");
1580 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "cvt%s2%s %s", from, to, buf);
1581 lc_esnprintf(env, cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F(%+F, %+F) */", irn, src_mode, tgt_mode);
1585 static void emit_ia32_Conv_I2FP(const ir_node *irn, ia32_emit_env_t *emit_env) {
1586 emit_ia32_Conv_with_FP(irn, emit_env);
1589 static void emit_ia32_Conv_FP2I(const ir_node *irn, ia32_emit_env_t *emit_env) {
1590 emit_ia32_Conv_with_FP(irn, emit_env);
1593 static void emit_ia32_Conv_FP2FP(const ir_node *irn, ia32_emit_env_t *emit_env) {
1594 emit_ia32_Conv_with_FP(irn, emit_env);
1598 * Emits code for an Int conversion.
1600 static void emit_ia32_Conv_I2I(const ir_node *irn, ia32_emit_env_t *emit_env) {
1601 FILE *F = emit_env->out;
1602 const lc_arg_env_t *env = ia32_get_arg_env();
1603 char *move_cmd = "movzx";
1604 char *conv_cmd = NULL;
1605 ir_mode *src_mode = get_ia32_Conv_src_mode(irn);
1606 ir_mode *tgt_mode = get_ia32_Conv_tgt_mode(irn);
1608 int src_bits = get_mode_size_bits(src_mode);
1609 int tgt_bits = get_mode_size_bits(tgt_mode);
1610 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1611 const arch_register_t *in_reg, *out_reg;
1613 assert(mode_is_int(src_mode) && mode_is_int(tgt_mode));
1614 assert(src_bits == 8 || src_bits == 16 || src_bits == 32);
1615 assert(tgt_bits == 8 || tgt_bits == 16 || tgt_bits == 32);
1616 assert(src_bits != tgt_bits);
1618 signed_mode = mode_is_signed(src_bits < tgt_bits ? src_mode : tgt_mode);
1623 switch(get_ia32_op_type(irn)) {
1625 in_reg = get_in_reg(irn, 2);
1626 out_reg = get_out_reg(irn, 0);
1628 if (REGS_ARE_EQUAL(in_reg, &ia32_gp_regs[REG_EAX]) &&
1629 REGS_ARE_EQUAL(out_reg, in_reg) &&
1632 if (src_bits == 8 || tgt_bits == 8)
1634 else if (src_bits == 16 || tgt_bits == 16)
1637 /* argument and result are both in EAX and */
1638 /* signedness is ok: -> use converts */
1639 lc_esnprintf(env, cmd_buf, SNPRINTF_BUF_LEN, "%s", conv_cmd);
1641 else if (REGS_ARE_EQUAL(out_reg, in_reg) && ! signed_mode)
1643 /* argument and result are in the same register */
1644 /* and signedness is ok: -> use and with mask */
1645 int mask = (1 << (src_bits < tgt_bits ? src_bits : tgt_bits)) - 1;
1646 lc_esnprintf(env, cmd_buf, SNPRINTF_BUF_LEN, "and %1D, 0x%x", irn, mask);
1649 /* use move w/o sign extension */
1650 ir_mode *smaller_mode = src_bits < tgt_bits ? src_mode : tgt_mode;
1651 lc_esnprintf(env, cmd_buf, SNPRINTF_BUF_LEN, "%s %1D, %%%s",
1653 ia32_get_reg_name_for_mode(emit_env, smaller_mode, in_reg));
1657 case ia32_AddrModeS:
1658 lc_esnprintf(env, cmd_buf, SNPRINTF_BUF_LEN, "%s %1D, %s",
1659 move_cmd, irn, ia32_emit_am(irn, emit_env));
1662 assert(0 && "unsupported op type for Conv");
1665 lc_esnprintf(env, cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F(%d Bit mode_%F -> %d Bit mode_%F) */",
1666 irn, src_bits, src_mode, tgt_bits, tgt_mode);
1672 * Emits code for an 8Bit Int conversion.
1674 void emit_ia32_Conv_I2I8Bit(const ir_node *irn, ia32_emit_env_t *emit_env) {
1675 emit_ia32_Conv_I2I(irn, emit_env);
1679 /*******************************************
1682 * | |__ ___ _ __ ___ __| | ___ ___
1683 * | '_ \ / _ \ '_ \ / _ \ / _` |/ _ \/ __|
1684 * | |_) | __/ | | | (_) | (_| | __/\__ \
1685 * |_.__/ \___|_| |_|\___/ \__,_|\___||___/
1687 *******************************************/
1690 * Emits a backend call
1692 static void emit_be_Call(const ir_node *irn, ia32_emit_env_t *emit_env) {
1693 FILE *F = emit_env->out;
1694 ir_entity *ent = be_Call_get_entity(irn);
1695 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1698 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "call %s", get_entity_ld_name(ent));
1701 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "call %1D", get_irn_n(irn, be_pos_Call_ptr));
1704 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F (be_Call) */", irn);
1710 * Emits code to increase stack pointer.
1712 static void emit_be_IncSP(const ir_node *irn, ia32_emit_env_t *emit_env) {
1713 FILE *F = emit_env->out;
1714 int offs = be_get_IncSP_offset(irn);
1715 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1719 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "sub %1S, %u", irn, offs);
1721 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "add %1S, %u", irn, -offs);
1722 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F (IncSP) */", irn);
1725 snprintf(cmd_buf, SNPRINTF_BUF_LEN, " ");
1726 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* omitted %+F (IncSP) with 0 */", irn);
1733 * Emits code to set stack pointer.
1735 static void emit_be_SetSP(const ir_node *irn, ia32_emit_env_t *emit_env) {
1736 FILE *F = emit_env->out;
1737 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1739 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "mov %1D, %3S", irn, irn);
1740 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F (restore SP) */", irn);
1745 * Emits code for Copy/CopyKeep.
1747 static void Copy_emitter(const ir_node *irn, ir_node *op, ia32_emit_env_t *emit_env) {
1748 FILE *F = emit_env->out;
1749 const arch_env_t *aenv = emit_env->arch_env;
1750 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1752 if (REGS_ARE_EQUAL(arch_get_irn_register(aenv, irn), arch_get_irn_register(aenv, op)) ||
1753 arch_register_type_is(arch_get_irn_register(aenv, op), virtual))
1756 if (mode_is_float(get_irn_mode(irn)))
1757 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "movs%M %1D, %1S", irn, irn, irn);
1759 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "mov %1D, %1S", irn, irn);
1760 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F */", irn);
1764 static void emit_be_Copy(const ir_node *irn, ia32_emit_env_t *emit_env) {
1765 Copy_emitter(irn, be_get_Copy_op(irn), emit_env);
1768 static void emit_be_CopyKeep(const ir_node *irn, ia32_emit_env_t *emit_env) {
1769 Copy_emitter(irn, be_get_CopyKeep_op(irn), emit_env);
1773 * Emits code for exchange.
1775 static void emit_be_Perm(const ir_node *irn, ia32_emit_env_t *emit_env) {
1776 FILE *F = emit_env->out;
1777 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1778 const arch_register_t *in1, *in2;
1779 const arch_register_class_t *cls1, *cls2;
1781 in1 = arch_get_irn_register(emit_env->arch_env, get_irn_n(irn, 0));
1782 in2 = arch_get_irn_register(emit_env->arch_env, get_irn_n(irn, 1));
1784 cls1 = arch_register_get_class(in1);
1785 cls2 = arch_register_get_class(in2);
1787 assert(cls1 == cls2 && "Register class mismatch at Perm");
1789 if (cls1 == &ia32_reg_classes[CLASS_ia32_gp]) {
1791 if(emit_env->isa->opt_arch == arch_athlon) {
1792 // xchg commands are Vector path on athlons and therefore stall the DirectPath pipeline
1793 // it is often beneficial to use the 3 xor trick instead of an xchg
1795 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "xor %1S, %2S", irn, irn);
1797 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "xor %2S, %1S", irn, irn);
1799 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "xor %1S, %2S", irn, irn);
1802 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "xchg %1S, %2S", irn, irn);
1807 else if (cls1 == &ia32_reg_classes[CLASS_ia32_xmm]) {
1808 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN,
1809 "pxor %1S, %2S\n\tpxor %2S, %1S\n\tpxor %1S, %2S", irn, irn, irn, irn, irn, irn);
1811 else if (cls1 == &ia32_reg_classes[CLASS_ia32_vfp]) {
1815 else if (cls1 == &ia32_reg_classes[CLASS_ia32_st]) {
1820 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F(%1A, %2A) */", irn, irn, irn);
1825 * Emits code for Constant loading.
1827 static void emit_ia32_Const(const ir_node *n, ia32_emit_env_t *env) {
1829 char cmd_buf[256], cmnt_buf[256];
1830 const lc_arg_env_t *arg_env = ia32_get_arg_env();
1831 ir_mode *mode = get_irn_mode(n);
1832 tarval *tv = get_ia32_Immop_tarval(n);
1834 if (get_ia32_op_type(n) == ia32_SymConst) {
1835 lc_esnprintf(arg_env, cmd_buf, 256, "mov %1D, OFFSET FLAT:%C ", n, n);
1836 lc_esnprintf(arg_env, cmnt_buf, 256, "/* Move address of SymConst into register */");
1838 assert(mode == get_tarval_mode(tv) || (mode_is_reference(get_tarval_mode(tv)) && mode == mode_Iu));
1839 /* beware: in some rare cases mode is mode_b which has no tarval_null() */
1840 if (tv == get_tarval_b_false() || tv == get_tarval_null(mode)) {
1841 const char *instr = "xor";
1842 if (env->isa->opt_arch == arch_pentium_4) {
1843 /* P4 prefers sub r, r, others xor r, r */
1846 lc_esnprintf(arg_env, cmd_buf, 256, "%s %1D, %1D ", instr, n, n);
1847 lc_esnprintf(arg_env, cmnt_buf, 256, "/* optimized mov 0 to register */");
1849 lc_esnprintf(arg_env, cmd_buf, 256, "mov %1D, %C ", n, n);
1850 lc_esnprintf(arg_env, cmnt_buf, 256, "/* Mov Const into register */");
1853 lc_efprintf(arg_env, F, "\t%-35s %-60s /* %+F (%+G) */\n", cmd_buf, cmnt_buf, n, n);
1857 * Emits code to increase stack pointer.
1859 static void emit_ia32_AddSP(const ir_node *irn, ia32_emit_env_t *emit_env) {
1860 FILE *F = emit_env->out;
1861 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1863 if (is_ia32_ImmConst(irn)) {
1864 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "sub %1D, %C", irn, irn);
1866 else if (is_ia32_ImmSymConst(irn)) {
1867 if (get_ia32_op_type(irn) == ia32_Normal)
1868 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "sub %1D, OFFSET_FLAT:%C", irn, irn);
1869 else /* source address mode */
1870 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "sub %1D, [%s%s]", irn, get_id_str(get_ia32_am_sc(irn)), get_ia32_am_offs(irn));
1873 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "sub %1D, %2S", irn, irn);
1875 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* reserve space on stack */");
1881 * Emits code to increase stack pointer.
1883 static void emit_ia32_SubSP(const ir_node *irn, ia32_emit_env_t *emit_env) {
1884 FILE *F = emit_env->out;
1885 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1887 if (is_ia32_ImmConst(irn)) {
1888 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "add %1D, %C", irn, irn);
1890 else if (is_ia32_ImmSymConst(irn)) {
1891 if (get_ia32_op_type(irn) == ia32_Normal)
1892 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "add %1D, OFFSET_FLAT:%C", irn, irn);
1893 else /* source address mode */
1894 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "add %1D, [%s%s]", irn, get_id_str(get_ia32_am_sc(irn)), get_ia32_am_offs(irn));
1897 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "add %1D, %2S", irn, irn);
1899 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* free space on stack */");
1905 * Emits code to load the TLS base
1907 static void emit_ia32_LdTls(const ir_node *irn, ia32_emit_env_t *emit_env) {
1908 FILE *F = emit_env->out;
1909 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1911 switch (asm_flavour) {
1913 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "mov %1D, DWORD PTR %%gs:0", irn);
1916 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "mov %1D, DWORD PTR %%gs:0", irn);
1919 assert(0 && "unsupported TLS");
1922 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* get thread local storage base */");
1927 static void emit_be_Return(const ir_node *n, ia32_emit_env_t *env) {
1929 const lc_arg_env_t *arg_env = ia32_get_arg_env();
1931 lc_efprintf(arg_env, F, "\t%-35s %-60s /* %+F (%+G) */\n", "ret", "/* be_Return */", n, n);
1934 static void emit_Nothing(const ir_node *n, ia32_emit_env_t *env) {
1937 ir_fprintf(F, "\t%35s /* %+F (%+G) */\n", " ", n, n);
1941 /***********************************************************************************
1944 * _ __ ___ __ _ _ _ __ | |_ _ __ __ _ _ __ ___ _____ _____ _ __| | __
1945 * | '_ ` _ \ / _` | | '_ \ | _| '__/ _` | '_ ` _ \ / _ \ \ /\ / / _ \| '__| |/ /
1946 * | | | | | | (_| | | | | | | | | | | (_| | | | | | | __/\ V V / (_) | | | <
1947 * |_| |_| |_|\__,_|_|_| |_| |_| |_| \__,_|_| |_| |_|\___| \_/\_/ \___/|_| |_|\_\
1949 ***********************************************************************************/
1952 * Enters the emitter functions for handled nodes into the generic
1953 * pointer of an opcode.
1955 static void ia32_register_emitters(void) {
1957 #define IA32_EMIT2(a,b) op_ia32_##a->ops.generic = (op_func)emit_ia32_##b
1958 #define IA32_EMIT(a) IA32_EMIT2(a,a)
1959 #define EMIT(a) op_##a->ops.generic = (op_func)emit_##a
1960 #define IGN(a) op_##a->ops.generic = (op_func)emit_Nothing
1961 #define BE_EMIT(a) op_be_##a->ops.generic = (op_func)emit_be_##a
1962 #define BE_IGN(a) op_be_##a->ops.generic = (op_func)emit_Nothing
1964 /* first clear the generic function pointer for all ops */
1965 clear_irp_opcodes_generic_func();
1967 /* register all emitter functions defined in spec */
1968 ia32_register_spec_emitters();
1970 /* other ia32 emitter functions */
1976 IA32_EMIT(PsiCondCMov);
1978 IA32_EMIT(PsiCondSet);
1979 IA32_EMIT(SwitchJmp);
1982 IA32_EMIT(Conv_I2FP);
1983 IA32_EMIT(Conv_FP2I);
1984 IA32_EMIT(Conv_FP2FP);
1985 IA32_EMIT(Conv_I2I);
1986 IA32_EMIT(Conv_I2I8Bit);
1993 IA32_EMIT(xCmpCMov);
1994 IA32_EMIT(xCondJmp);
1995 IA32_EMIT2(fcomJmp, x87CondJmp);
1996 IA32_EMIT2(fcompJmp, x87CondJmp);
1997 IA32_EMIT2(fcomppJmp, x87CondJmp);
1998 IA32_EMIT2(fcomrJmp, x87CondJmp);
1999 IA32_EMIT2(fcomrpJmp, x87CondJmp);
2000 IA32_EMIT2(fcomrppJmp, x87CondJmp);
2002 /* benode emitter */
2028 static const char *last_name = NULL;
2029 static unsigned last_line = -1;
2030 static unsigned num = -1;
2033 * Emit the debug support for node irn.
2035 static void ia32_emit_dbg(const ir_node *irn, ia32_emit_env_t *env) {
2036 dbg_info *db = get_irn_dbg_info(irn);
2038 const char *fname = be_retrieve_dbg_info(db, &lineno);
2040 if (! env->cg->birg->main_env->options->stabs_debug_support)
2044 if (last_name != fname) {
2046 be_dbg_include_begin(env->cg->birg->main_env->db_handle, fname);
2049 if (last_line != lineno) {
2053 snprintf(name, sizeof(name), ".LM%u", ++num);
2055 be_dbg_line(env->cg->birg->main_env->db_handle, lineno, name);
2056 fprintf(F, "%s:\n", name);
2062 * Emits code for a node.
2064 static void ia32_emit_node(const ir_node *irn, void *env) {
2065 ia32_emit_env_t *emit_env = env;
2066 ir_op *op = get_irn_op(irn);
2067 DEBUG_ONLY(firm_dbg_module_t *mod = emit_env->mod;)
2069 DBG((mod, LEVEL_1, "emitting code for %+F\n", irn));
2071 if (op->ops.generic) {
2072 void (*emit)(const ir_node *, void *) = (void (*)(const ir_node *, void *))op->ops.generic;
2073 ia32_emit_dbg(irn, emit_env);
2077 emit_Nothing(irn, env);
2078 ir_fprintf(stderr, "Warning: No emit handler for node %+F (%+G)\n", irn, irn);
2083 * Emits gas alignment directives
2085 static void ia32_emit_alignment(FILE *F, unsigned align, unsigned skip) {
2086 fprintf(F, "\t.p2align %u,,%u\n", align, skip);
2090 * Emits gas alignment directives for Functions depended on cpu architecture.
2092 static void ia32_emit_align_func(FILE *F, cpu_support cpu) {
2094 unsigned maximum_skip;
2109 maximum_skip = (1 << align) - 1;
2110 ia32_emit_alignment(F, align, maximum_skip);
2114 * Emits gas alignment directives for Labels depended on cpu architecture.
2116 static void ia32_emit_align_label(FILE *F, cpu_support cpu) {
2117 unsigned align; unsigned maximum_skip;
2132 maximum_skip = (1 << align) - 1;
2133 ia32_emit_alignment(F, align, maximum_skip);
2136 static int is_first_loop_block(ir_node *block, ir_node *prev_block, ia32_emit_env_t *env) {
2137 ir_exec_freq *exec_freq = env->cg->birg->exec_freq;
2138 double block_freq, prev_freq;
2139 static const double DELTA = .0001;
2140 cpu_support cpu = env->isa->opt_arch;
2142 if(exec_freq == NULL)
2144 if(cpu == arch_i386 || cpu == arch_i486)
2147 block_freq = get_block_execfreq(exec_freq, block);
2148 prev_freq = get_block_execfreq(exec_freq, prev_block);
2150 if(block_freq < DELTA || prev_freq < DELTA)
2153 block_freq /= prev_freq;
2157 case arch_athlon_64:
2159 return block_freq > 3;
2164 return block_freq > 2;
2168 * Walks over the nodes in a block connected by scheduling edges
2169 * and emits code for each node.
2171 static void ia32_gen_block(ir_node *block, ir_node *last_block, ia32_emit_env_t *env) {
2172 ir_graph *irg = get_irn_irg(block);
2173 ir_node *start_block = get_irg_start_block(irg);
2179 assert(is_Block(block));
2181 if (block == start_block)
2184 if (need_label && get_irn_arity(block) == 1) {
2185 ir_node *pred_block = get_Block_cfgpred_block(block, 0);
2187 if (pred_block == last_block && get_irn_n_edges_kind(pred_block, EDGE_KIND_BLOCK) <= 2)
2191 /* special case: if one of our cfg preds is a switch-jmp we need a label, */
2192 /* otherwise there might be jump table entries jumping to */
2193 /* non-existent (omitted) labels */
2194 for (i = get_Block_n_cfgpreds(block) - 1; i >= 0; --i) {
2195 ir_node *pred = get_Block_cfgpred(block, i);
2197 if (is_Proj(pred)) {
2198 assert(get_irn_mode(pred) == mode_X);
2199 if (is_ia32_SwitchJmp(get_Proj_pred(pred))) {
2206 /* special case because the start block contains no jump instruction */
2207 if (last_block == start_block) {
2208 const ir_edge_t *edge;
2209 ir_node *startsucc = NULL;
2211 foreach_block_succ(start_block, edge) {
2212 startsucc = get_edge_src_irn(edge);
2213 if (startsucc != start_block)
2216 assert(startsucc != NULL);
2218 /* if the last block was the start block and we are not inside the */
2219 /* start successor, emit a jump to the start successor */
2220 if (startsucc != block) {
2221 char buf[SNPRINTF_BUF_LEN];
2222 ir_snprintf(buf, sizeof(buf), BLOCK_PREFIX("%d"),
2223 get_irn_node_nr(startsucc));
2224 ir_fprintf(F, "\tjmp %s\n", buf);
2229 char cmd_buf[SNPRINTF_BUF_LEN];
2232 ir_exec_freq *exec_freq = env->cg->birg->exec_freq;
2234 /* align the loop headers */
2235 if (! is_first_loop_block(block, last_block, env)) {
2236 /* align blocks where the previous block has no fallthrough */
2237 arity = get_irn_arity(block);
2239 for (i = 0; i < arity; ++i) {
2240 ir_node *predblock = get_Block_cfgpred_block(block, i);
2242 if (predblock == last_block) {
2250 ia32_emit_align_label(env->out, env->isa->opt_arch);
2252 ir_snprintf(cmd_buf, sizeof(cmd_buf), BLOCK_PREFIX("%d:"),
2253 get_irn_node_nr(block));
2254 fprintf(F, "%-43s ", cmd_buf);
2256 /* emit list of pred blocks in comment */
2257 fprintf(F, "/* preds:");
2259 arity = get_irn_arity(block);
2260 for (i = 0; i < arity; ++i) {
2261 ir_node *predblock = get_Block_cfgpred_block(block, i);
2262 fprintf(F, " %ld", get_irn_node_nr(predblock));
2265 if (exec_freq != NULL) {
2266 fprintf(F, " freq: %f", get_block_execfreq(exec_freq, block));
2269 fprintf(F, " */\n");
2272 /* emit the contents of the block */
2273 ia32_emit_dbg(block, env);
2274 sched_foreach(block, irn) {
2275 ia32_emit_node(irn, env);
2280 * Emits code for function start.
2282 static void ia32_emit_func_prolog(FILE *F, ir_graph *irg, ia32_emit_env_t *emit_env) {
2283 ir_entity *irg_ent = get_irg_entity(irg);
2284 const char *irg_name = get_entity_ld_name(irg_ent);
2285 cpu_support cpu = emit_env->isa->opt_arch;
2286 const be_irg_t *birg = emit_env->cg->birg;
2289 ia32_switch_section(F, SECTION_TEXT);
2290 be_dbg_method_begin(birg->main_env->db_handle, irg_ent, be_abi_get_stack_layout(birg->abi));
2291 ia32_emit_align_func(F, cpu);
2292 if (get_entity_visibility(irg_ent) == visibility_external_visible) {
2293 fprintf(F, ".globl %s\n", irg_name);
2295 ia32_dump_function_object(F, irg_name);
2296 fprintf(F, "%s:\n", irg_name);
2300 * Emits code for function end
2302 static void ia32_emit_func_epilog(FILE *F, ir_graph *irg, ia32_emit_env_t *emit_env) {
2303 const char *irg_name = get_entity_ld_name(get_irg_entity(irg));
2304 const be_irg_t *birg = emit_env->cg->birg;
2306 ia32_dump_function_size(F, irg_name);
2307 be_dbg_method_end(birg->main_env->db_handle);
2313 * Sets labels for control flow nodes (jump target)
2314 * TODO: Jump optimization
2316 static void ia32_gen_labels(ir_node *block, void *env) {
2318 int n = get_Block_n_cfgpreds(block);
2320 for (n--; n >= 0; n--) {
2321 pred = get_Block_cfgpred(block, n);
2322 set_irn_link(pred, block);
2327 * Main driver. Emits the code for one routine.
2329 void ia32_gen_routine(FILE *F, ir_graph *irg, const ia32_code_gen_t *cg) {
2330 ia32_emit_env_t emit_env;
2332 ir_node *last_block = NULL;
2335 emit_env.arch_env = cg->arch_env;
2337 emit_env.isa = (ia32_isa_t *)cg->arch_env->isa;
2338 FIRM_DBG_REGISTER(emit_env.mod, "firm.be.ia32.emitter");
2340 /* set the global arch_env (needed by print hooks) */
2341 arch_env = cg->arch_env;
2343 ia32_register_emitters();
2345 ia32_emit_func_prolog(F, irg, &emit_env);
2346 irg_block_walk_graph(irg, ia32_gen_labels, NULL, &emit_env);
2348 if ((cg->opt & IA32_OPT_EXTBB) && cg->blk_sched) {
2349 int i, n = ARR_LEN(cg->blk_sched);
2351 for (i = 0; i < n;) {
2354 block = cg->blk_sched[i];
2356 next_bl = i < n ? cg->blk_sched[i] : NULL;
2358 /* set here the link. the emitter expects to find the next block here */
2359 set_irn_link(block, next_bl);
2360 ia32_gen_block(block, last_block, &emit_env);
2365 /* "normal" block schedule: Note the get_next_block() returns the NUMBER of the block
2366 in the block schedule. As this number should NEVER be equal the next block,
2367 we does not need a clear block link here. */
2369 //irg_walk_blkwise_graph(irg, NULL, ia32_gen_block, &emit_env);
2373 ia32_emit_func_epilog(F, irg, &emit_env);