2 * Copyright (C) 1995-2007 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This file implements the ia32 node emitter.
23 * @author Christian Wuerdig, Matthias Braun
41 #include "iredges_t.h"
44 #include "raw_bitset.h"
46 #include "../besched_t.h"
47 #include "../benode_t.h"
49 #include "../be_dbgout.h"
50 #include "../beemitter.h"
51 #include "../begnuas.h"
52 #include "../beirg_t.h"
54 #include "ia32_emitter.h"
55 #include "gen_ia32_emitter.h"
56 #include "gen_ia32_regalloc_if.h"
57 #include "ia32_nodes_attr.h"
58 #include "ia32_new_nodes.h"
59 #include "ia32_map_regs.h"
60 #include "bearch_ia32_t.h"
62 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
64 #define BLOCK_PREFIX ".L"
66 #define SNPRINTF_BUF_LEN 128
69 * Returns the register at in position pos.
72 const arch_register_t *get_in_reg(ia32_emit_env_t *env, const ir_node *irn,
75 const arch_env_t *arch_env = env->arch_env;
77 const arch_register_t *reg = NULL;
79 assert(get_irn_arity(irn) > pos && "Invalid IN position");
81 /* The out register of the operator at position pos is the
82 in register we need. */
83 op = get_irn_n(irn, pos);
85 reg = arch_get_irn_register(arch_env, op);
87 assert(reg && "no in register found");
89 /* in case of a joker register: just return a valid register */
90 if (arch_register_type_is(reg, joker)) {
91 const arch_register_req_t *req;
93 /* ask for the requirements */
94 req = arch_get_register_req(arch_env, irn, pos);
96 if (arch_register_req_is(req, limited)) {
97 /* in case of limited requirements: get the first allowed register */
98 unsigned idx = rbitset_next(req->limited, 0, 1);
99 reg = arch_register_for_index(req->cls, idx);
101 /* otherwise get first register in class */
102 reg = arch_register_for_index(req->cls, 0);
110 * Returns the register at out position pos.
113 const arch_register_t *get_out_reg(ia32_emit_env_t *env, const ir_node *irn,
116 const arch_env_t *arch_env = env->arch_env;
118 const arch_register_t *reg = NULL;
120 /* 1st case: irn is not of mode_T, so it has only */
121 /* one OUT register -> good */
122 /* 2nd case: irn is of mode_T -> collect all Projs and ask the */
123 /* Proj with the corresponding projnum for the register */
125 if (get_irn_mode(irn) != mode_T) {
126 reg = arch_get_irn_register(arch_env, irn);
127 } else if (is_ia32_irn(irn)) {
128 reg = get_ia32_out_reg(irn, pos);
130 const ir_edge_t *edge;
132 foreach_out_edge(irn, edge) {
133 proj = get_edge_src_irn(edge);
134 assert(is_Proj(proj) && "non-Proj from mode_T node");
135 if (get_Proj_proj(proj) == pos) {
136 reg = arch_get_irn_register(arch_env, proj);
142 assert(reg && "no out register found");
147 * Determine the gnu assembler suffix that indicates a mode
150 char get_mode_suffix(const ir_mode *mode) {
151 if(mode_is_float(mode)) {
152 switch(get_mode_size_bits(mode)) {
161 assert(mode_is_int(mode) || mode_is_reference(mode) || mode_is_character(mode));
162 switch(get_mode_size_bits(mode)) {
173 panic("Can't output mode_suffix for %+F\n", mode);
177 int produces_result(const ir_node *node) {
178 return !(is_ia32_St(node) ||
179 is_ia32_CondJmp(node) ||
180 is_ia32_xCondJmp(node) ||
181 is_ia32_CmpSet(node) ||
182 is_ia32_xCmpSet(node) ||
183 is_ia32_SwitchJmp(node));
187 const char *ia32_get_reg_name_for_mode(ia32_emit_env_t *env, ir_mode *mode,
188 const arch_register_t *reg) {
189 switch(get_mode_size_bits(mode)) {
191 return ia32_get_mapped_reg_name(env->isa->regs_8bit, reg);
193 return ia32_get_mapped_reg_name(env->isa->regs_16bit, reg);
195 return (char *)arch_register_get_name(reg);
200 * Add a number to a prefix. This number will not be used a second time.
203 char *get_unique_label(char *buf, size_t buflen, const char *prefix) {
204 static unsigned long id = 0;
205 snprintf(buf, buflen, "%s%lu", prefix, ++id);
209 /*************************************************************
211 * (_) | | / _| | | | |
212 * _ __ _ __ _ _ __ | |_| |_ | |__ ___| |_ __ ___ _ __
213 * | '_ \| '__| | '_ \| __| _| | '_ \ / _ \ | '_ \ / _ \ '__|
214 * | |_) | | | | | | | |_| | | | | | __/ | |_) | __/ |
215 * | .__/|_| |_|_| |_|\__|_| |_| |_|\___|_| .__/ \___|_|
218 *************************************************************/
220 // we have no C++ and can't define an implicit ia32_emit_env_t* cast to
221 // be_emit_env_t* so we cheat a bit...
222 #define be_emit_char(env,c) be_emit_char(env->emit,c)
223 #define be_emit_string(env,s) be_emit_string(env->emit,s)
224 #undef be_emit_cstring
225 #define be_emit_cstring(env,x) { be_emit_string_len(env->emit, x, sizeof(x)-1); }
226 #define be_emit_ident(env,i) be_emit_ident(env->emit,i)
227 #define be_emit_tarval(env,tv) be_emit_tarval(env->emit,tv)
228 #define be_emit_write_line(env) be_emit_write_line(env->emit)
229 #define be_emit_finish_line_gas(env,n) be_emit_finish_line_gas(env->emit,n)
230 #define be_emit_pad_comment(env) be_emit_pad_comment(env->emit)
232 void ia32_emit_source_register(ia32_emit_env_t *env, const ir_node *node, int pos)
234 const arch_register_t *reg = get_in_reg(env, node, pos);
235 const char *reg_name = arch_register_get_name(reg);
237 assert(pos < get_irn_arity(node));
239 be_emit_char(env, '%');
240 be_emit_string(env, reg_name);
243 void ia32_emit_dest_register(ia32_emit_env_t *env, const ir_node *node, int pos) {
244 const arch_register_t *reg = get_out_reg(env, node, pos);
245 const char *reg_name = arch_register_get_name(reg);
247 be_emit_char(env, '%');
248 be_emit_string(env, reg_name);
251 void ia32_emit_x87_name(ia32_emit_env_t *env, const ir_node *node, int pos)
253 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
256 be_emit_char(env, '%');
257 be_emit_string(env, attr->x87[pos]->name);
260 void ia32_emit_immediate(ia32_emit_env_t *env, const ir_node *node)
266 be_emit_char(env, '$');
268 switch(get_ia32_immop_type(node)) {
270 tv = get_ia32_Immop_tarval(node);
271 be_emit_tarval(env, tv);
273 case ia32_ImmSymConst:
274 ent = get_ia32_Immop_symconst(node);
275 mark_entity_visited(ent);
276 id = get_entity_ld_ident(ent);
277 be_emit_ident(env, id);
284 be_emit_string(env, "BAD");
289 void ia32_emit_mode_suffix_mode(ia32_emit_env_t *env, const ir_mode *mode)
291 be_emit_char(env, get_mode_suffix(mode));
294 void ia32_emit_mode_suffix(ia32_emit_env_t *env, const ir_node *node)
296 ir_mode *mode = get_ia32_ls_mode(node);
300 ia32_emit_mode_suffix_mode(env, mode);
303 void ia32_emit_x87_mode_suffix(ia32_emit_env_t *env, const ir_node *node)
305 ir_mode *mode = get_ia32_ls_mode(node);
307 ia32_emit_mode_suffix_mode(env, mode);
311 char get_xmm_mode_suffix(ir_mode *mode)
313 assert(mode_is_float(mode));
314 switch(get_mode_size_bits(mode)) {
325 void ia32_emit_xmm_mode_suffix(ia32_emit_env_t *env, const ir_node *node)
327 ir_mode *mode = get_ia32_ls_mode(node);
328 assert(mode != NULL);
329 be_emit_char(env, 's');
330 be_emit_char(env, get_xmm_mode_suffix(mode));
333 void ia32_emit_xmm_mode_suffix_s(ia32_emit_env_t *env, const ir_node *node)
335 ir_mode *mode = get_ia32_ls_mode(node);
336 assert(mode != NULL);
337 be_emit_char(env, get_xmm_mode_suffix(mode));
340 void ia32_emit_extend_suffix(ia32_emit_env_t *env, const ir_mode *mode)
342 if(get_mode_size_bits(mode) == 32)
344 if(mode_is_signed(mode)) {
345 be_emit_char(env, 's');
347 be_emit_char(env, 'z');
352 void ia32_emit_function_object(ia32_emit_env_t *env, const char *name)
354 switch (be_gas_flavour) {
355 case GAS_FLAVOUR_NORMAL:
356 be_emit_cstring(env, "\t.type\t");
357 be_emit_string(env, name);
358 be_emit_cstring(env, ", @function\n");
359 be_emit_write_line(env);
361 case GAS_FLAVOUR_MINGW:
362 be_emit_cstring(env, "\t.def\t");
363 be_emit_string(env, name);
364 be_emit_cstring(env, ";\t.scl\t2;\t.type\t32;\t.endef\n");
365 be_emit_write_line(env);
373 void ia32_emit_function_size(ia32_emit_env_t *env, const char *name)
375 switch (be_gas_flavour) {
376 case GAS_FLAVOUR_NORMAL:
377 be_emit_cstring(env, "\t.size\t");
378 be_emit_string(env, name);
379 be_emit_cstring(env, ", .-");
380 be_emit_string(env, name);
381 be_emit_char(env, '\n');
382 be_emit_write_line(env);
392 * Emits registers and/or address mode of a binary operation.
394 void ia32_emit_binop(ia32_emit_env_t *env, const ir_node *node) {
395 switch(get_ia32_op_type(node)) {
397 if (is_ia32_ImmConst(node) || is_ia32_ImmSymConst(node)) {
398 ia32_emit_immediate(env, node);
399 be_emit_cstring(env, ", ");
400 ia32_emit_source_register(env, node, 2);
402 const arch_register_t *in1 = get_in_reg(env, node, 2);
403 const arch_register_t *in2 = get_in_reg(env, node, 3);
404 const arch_register_t *out = produces_result(node) ? get_out_reg(env, node, 0) : NULL;
405 const arch_register_t *in;
408 in = out ? (REGS_ARE_EQUAL(out, in2) ? in1 : in2) : in2;
409 out = out ? out : in1;
410 in_name = arch_register_get_name(in);
412 if (is_ia32_emit_cl(node)) {
413 assert(REGS_ARE_EQUAL(&ia32_gp_regs[REG_ECX], in) && "shift operation needs ecx");
417 be_emit_char(env, '%');
418 be_emit_string(env, in_name);
419 be_emit_cstring(env, ", %");
420 be_emit_string(env, arch_register_get_name(out));
424 ia32_emit_am(env, node);
425 be_emit_cstring(env, ", ");
426 if (is_ia32_ImmConst(node) || is_ia32_ImmSymConst(node)) {
427 assert(!produces_result(node) && "Source AM with Const must not produce result");
428 ia32_emit_immediate(env, node);
429 } else if (produces_result(node)) {
430 ia32_emit_dest_register(env, node, 0);
432 ia32_emit_source_register(env, node, 2);
436 if (is_ia32_ImmConst(node) || is_ia32_ImmSymConst(node)) {
437 ia32_emit_immediate(env, node);
438 be_emit_cstring(env, ", ");
439 ia32_emit_am(env, node);
441 const arch_register_t *in1 = get_in_reg(env, node,
442 get_irn_arity(node) == 5 ? 3 : 2);
443 ir_mode *mode = get_ia32_ls_mode(node);
446 in_name = ia32_get_reg_name_for_mode(env, mode, in1);
448 if (is_ia32_emit_cl(node)) {
449 assert(REGS_ARE_EQUAL(&ia32_gp_regs[REG_ECX], in1) && "shift operation needs ecx");
453 be_emit_char(env, '%');
454 be_emit_string(env, in_name);
455 be_emit_cstring(env, ", ");
456 ia32_emit_am(env, node);
460 assert(0 && "unsupported op type");
465 * Emits registers and/or address mode of a binary operation.
467 void ia32_emit_x87_binop(ia32_emit_env_t *env, const ir_node *node) {
468 switch(get_ia32_op_type(node)) {
470 if (is_ia32_ImmConst(node) || is_ia32_ImmSymConst(node)) {
471 // should not happen...
474 const ia32_x87_attr_t *x87_attr = get_ia32_x87_attr_const(node);
475 const arch_register_t *in1 = x87_attr->x87[0];
476 const arch_register_t *in2 = x87_attr->x87[1];
477 const arch_register_t *out = x87_attr->x87[2];
478 const arch_register_t *in;
480 in = out ? (REGS_ARE_EQUAL(out, in2) ? in1 : in2) : in2;
481 out = out ? out : in1;
483 be_emit_char(env, '%');
484 be_emit_string(env, arch_register_get_name(in));
485 be_emit_cstring(env, ", %");
486 be_emit_string(env, arch_register_get_name(out));
491 ia32_emit_am(env, node);
494 assert(0 && "unsupported op type");
499 * Emits registers and/or address mode of a unary operation.
501 void ia32_emit_unop(ia32_emit_env_t *env, const ir_node *node) {
502 switch(get_ia32_op_type(node)) {
504 if (is_ia32_ImmConst(node) || is_ia32_ImmSymConst(node)) {
505 ia32_emit_immediate(env, node);
507 if (is_ia32_Mul(node) || is_ia32_IMul1OP(node)) {
508 ia32_emit_source_register(env, node, 3);
509 } else if(is_ia32_IDiv(node) || is_ia32_Div(node)) {
510 ia32_emit_source_register(env, node, 4);
511 } else if(is_ia32_Push(node)) {
512 ia32_emit_source_register(env, node, 2);
513 } else if(is_ia32_Pop(node)) {
514 ia32_emit_dest_register(env, node, 1);
516 ia32_emit_dest_register(env, node, 0);
522 ia32_emit_am(env, node);
525 assert(0 && "unsupported op type");
530 * Emits address mode.
532 void ia32_emit_am(ia32_emit_env_t *env, const ir_node *node) {
533 ir_entity *ent = get_ia32_am_sc(node);
534 int offs = get_ia32_am_offs_int(node);
535 ir_node *base = get_irn_n(node, 0);
536 int has_base = !is_ia32_NoReg_GP(base);
537 ir_node *index = get_irn_n(node, 1);
538 int has_index = !is_ia32_NoReg_GP(index);
540 /* just to be sure... */
541 assert(!is_ia32_use_frame(node) || get_ia32_frame_ent(node) != NULL);
547 mark_entity_visited(ent);
548 id = get_entity_ld_ident(ent);
549 if (is_ia32_am_sc_sign(node))
550 be_emit_char(env, '-');
551 be_emit_ident(env, id);
553 if(get_entity_owner(ent) == get_tls_type()) {
554 if (get_entity_visibility(ent) == visibility_external_allocated) {
555 be_emit_cstring(env, "@INDNTPOFF");
557 be_emit_cstring(env, "@NTPOFF");
564 be_emit_irprintf(env->emit, "%+d", offs);
566 be_emit_irprintf(env->emit, "%d", offs);
570 if (has_base || has_index) {
571 be_emit_char(env, '(');
575 ia32_emit_source_register(env, node, 0);
578 /* emit index + scale */
581 be_emit_char(env, ',');
582 ia32_emit_source_register(env, node, 1);
584 scale = get_ia32_am_scale(node);
586 be_emit_irprintf(env->emit, ",%d", 1 << get_ia32_am_scale(node));
589 be_emit_char(env, ')');
593 /*************************************************
596 * ___ _ __ ___ _| |_ ___ ___ _ __ __| |
597 * / _ \ '_ ` _ \| | __| / __/ _ \| '_ \ / _` |
598 * | __/ | | | | | | |_ | (_| (_) | | | | (_| |
599 * \___|_| |_| |_|_|\__| \___\___/|_| |_|\__,_|
601 *************************************************/
604 #define IA32_DO_EMIT(irn) ia32_fprintf_format(F, irn, cmd_buf, cmnt_buf)
607 * coding of conditions
609 struct cmp2conditon_t {
615 * positive conditions for signed compares
618 const struct cmp2conditon_t cmp2condition_s[] = {
619 { NULL, pn_Cmp_False }, /* always false */
620 { "e", pn_Cmp_Eq }, /* == */
621 { "l", pn_Cmp_Lt }, /* < */
622 { "le", pn_Cmp_Le }, /* <= */
623 { "g", pn_Cmp_Gt }, /* > */
624 { "ge", pn_Cmp_Ge }, /* >= */
625 { "ne", pn_Cmp_Lg }, /* != */
626 { NULL, pn_Cmp_Leg}, /* Floating point: ordered */
627 { NULL, pn_Cmp_Uo }, /* Floating point: unordered */
628 { "e", pn_Cmp_Ue }, /* Floating point: unordered or == */
629 { "b", pn_Cmp_Ul }, /* Floating point: unordered or < */
630 { "be", pn_Cmp_Ule }, /* Floating point: unordered or <= */
631 { "a", pn_Cmp_Ug }, /* Floating point: unordered or > */
632 { "ae", pn_Cmp_Uge }, /* Floating point: unordered or >= */
633 { "ne", pn_Cmp_Ne }, /* Floating point: unordered or != */
634 { NULL, pn_Cmp_True }, /* always true */
638 * positive conditions for unsigned compares
641 const struct cmp2conditon_t cmp2condition_u[] = {
642 { NULL, pn_Cmp_False }, /* always false */
643 { "e", pn_Cmp_Eq }, /* == */
644 { "b", pn_Cmp_Lt }, /* < */
645 { "be", pn_Cmp_Le }, /* <= */
646 { "a", pn_Cmp_Gt }, /* > */
647 { "ae", pn_Cmp_Ge }, /* >= */
648 { "ne", pn_Cmp_Lg }, /* != */
649 { NULL, pn_Cmp_True }, /* always true */
653 * returns the condition code
656 const char *get_cmp_suffix(int cmp_code)
658 assert( (cmp2condition_s[cmp_code & 15].num) == (cmp_code & 15));
659 assert( (cmp2condition_u[cmp_code & 7].num) == (cmp_code & 7));
661 if((cmp_code & ia32_pn_Cmp_Unsigned)) {
662 return cmp2condition_u[cmp_code & 7].name;
664 return cmp2condition_s[cmp_code & 15].name;
668 void ia32_emit_cmp_suffix(ia32_emit_env_t *env, long pnc)
670 be_emit_string(env, get_cmp_suffix(pnc));
675 * Returns the target block for a control flow node.
678 ir_node *get_cfop_target_block(const ir_node *irn) {
679 return get_irn_link(irn);
683 void ia32_emit_block_name(ia32_emit_env_t *env, const ir_node *block)
685 be_emit_cstring(env, BLOCK_PREFIX);
686 be_emit_irprintf(env->emit, "%d", get_irn_node_nr(block));
690 * Returns the target label for a control flow node.
693 void ia32_emit_cfop_target(ia32_emit_env_t * env, const ir_node *node) {
694 ir_node *block = get_cfop_target_block(node);
696 ia32_emit_block_name(env, block);
699 /** Return the next block in Block schedule */
700 static ir_node *next_blk_sched(const ir_node *block) {
701 return get_irn_link(block);
705 * Returns the Proj with projection number proj and NOT mode_M
708 ir_node *get_proj(const ir_node *node, long proj) {
709 const ir_edge_t *edge;
712 assert(get_irn_mode(node) == mode_T && "expected mode_T node");
714 foreach_out_edge(node, edge) {
715 src = get_edge_src_irn(edge);
717 assert(is_Proj(src) && "Proj expected");
718 if (get_irn_mode(src) == mode_M)
721 if (get_Proj_proj(src) == proj)
728 * Emits the jump sequence for a conditional jump (cmp + jmp_true + jmp_false)
731 void finish_CondJmp(ia32_emit_env_t *env, const ir_node *node, ir_mode *mode,
733 const ir_node *proj_true;
734 const ir_node *proj_false;
735 const ir_node *block;
736 const ir_node *next_block;
739 /* get both Proj's */
740 proj_true = get_proj(node, pn_Cond_true);
741 assert(proj_true && "CondJmp without true Proj");
743 proj_false = get_proj(node, pn_Cond_false);
744 assert(proj_false && "CondJmp without false Proj");
746 /* for now, the code works for scheduled and non-schedules blocks */
747 block = get_nodes_block(node);
749 /* we have a block schedule */
750 next_block = next_blk_sched(block);
752 if (get_cfop_target_block(proj_true) == next_block) {
753 /* exchange both proj's so the second one can be omitted */
754 const ir_node *t = proj_true;
756 proj_true = proj_false;
759 pnc = get_negated_pnc(pnc, mode);
762 /* in case of unordered compare, check for parity */
763 if (pnc & pn_Cmp_Uo) {
764 be_emit_cstring(env, "\tjp ");
765 ia32_emit_cfop_target(env, proj_true);
766 be_emit_finish_line_gas(env, proj_true);
769 be_emit_cstring(env, "\tj");
770 ia32_emit_cmp_suffix(env, pnc);
771 be_emit_char(env, ' ');
772 ia32_emit_cfop_target(env, proj_true);
773 be_emit_finish_line_gas(env, proj_true);
775 /* the second Proj might be a fallthrough */
776 if (get_cfop_target_block(proj_false) != next_block) {
777 be_emit_cstring(env, "\tjmp ");
778 ia32_emit_cfop_target(env, proj_false);
779 be_emit_finish_line_gas(env, proj_false);
781 be_emit_cstring(env, "\t/* fallthrough to ");
782 ia32_emit_cfop_target(env, proj_false);
783 be_emit_cstring(env, " */");
784 be_emit_finish_line_gas(env, proj_false);
789 * Emits code for conditional jump.
792 void CondJmp_emitter(ia32_emit_env_t *env, const ir_node *node) {
793 be_emit_cstring(env, "\tcmp ");
794 ia32_emit_binop(env, node);
795 be_emit_finish_line_gas(env, node);
797 finish_CondJmp(env, node, mode_Iu, get_ia32_pncode(node));
801 * Emits code for conditional jump with two variables.
804 void emit_ia32_CondJmp(ia32_emit_env_t *env, const ir_node *node) {
805 CondJmp_emitter(env, node);
809 * Emits code for conditional test and jump.
812 void TestJmp_emitter(ia32_emit_env_t *env, const ir_node *node) {
813 if(is_ia32_ImmSymConst(node) || is_ia32_ImmConst(node)) {
814 be_emit_cstring(env, "\ttest ");
815 ia32_emit_immediate(env, node);
816 be_emit_cstring(env, ", ");
817 ia32_emit_source_register(env, node, 0);
818 be_emit_finish_line_gas(env, node);
820 be_emit_cstring(env, "\ttest ");
821 ia32_emit_source_register(env, node, 1);
822 be_emit_cstring(env, ", ");
823 ia32_emit_source_register(env, node, 0);
824 be_emit_finish_line_gas(env, node);
826 finish_CondJmp(env, node, mode_Iu, get_ia32_pncode(node));
830 * Emits code for conditional test and jump with two variables.
833 void emit_ia32_TestJmp(ia32_emit_env_t *env, const ir_node *node) {
834 TestJmp_emitter(env, node);
838 void emit_ia32_CJmp(ia32_emit_env_t *env, const ir_node *node) {
839 be_emit_cstring(env, "/* omitted redundant test */");
840 be_emit_finish_line_gas(env, node);
842 finish_CondJmp(env, node, mode_Is, get_ia32_pncode(node));
846 void emit_ia32_CJmpAM(ia32_emit_env_t *env, const ir_node *node) {
847 be_emit_cstring(env, "/* omitted redundant test/cmp */");
848 be_emit_finish_line_gas(env, node);
850 finish_CondJmp(env, node, mode_Is, get_ia32_pncode(node));
854 * Emits code for conditional SSE floating point jump with two variables.
857 void emit_ia32_xCondJmp(ia32_emit_env_t *env, const ir_node *node) {
858 be_emit_cstring(env, "\tucomi");
859 ia32_emit_xmm_mode_suffix(env, node);
860 be_emit_char(env, ' ');
861 ia32_emit_binop(env, node);
862 be_emit_finish_line_gas(env, node);
864 finish_CondJmp(env, node, mode_F, get_ia32_pncode(node));
868 * Emits code for conditional x87 floating point jump with two variables.
871 void emit_ia32_x87CondJmp(ia32_emit_env_t *env, const ir_node *node) {
872 const ia32_x87_attr_t *x87_attr = get_ia32_x87_attr_const(node);
873 const char *reg = x87_attr->x87[1]->name;
874 long pnc = get_ia32_pncode(node);
876 switch (get_ia32_irn_opcode(node)) {
877 case iro_ia32_fcomrJmp:
878 pnc = get_inversed_pnc(pnc);
879 reg = x87_attr->x87[0]->name;
880 case iro_ia32_fcomJmp:
882 be_emit_cstring(env, "\tfucom ");
884 case iro_ia32_fcomrpJmp:
885 pnc = get_inversed_pnc(pnc);
886 reg = x87_attr->x87[0]->name;
887 case iro_ia32_fcompJmp:
888 be_emit_cstring(env, "\tfucomp ");
890 case iro_ia32_fcomrppJmp:
891 pnc = get_inversed_pnc(pnc);
892 case iro_ia32_fcomppJmp:
893 be_emit_cstring(env, "\tfucompp ");
899 be_emit_char(env, '%');
900 be_emit_string(env, reg);
902 be_emit_finish_line_gas(env, node);
904 be_emit_cstring(env, "\tfnstsw %ax");
905 be_emit_finish_line_gas(env, node);
906 be_emit_cstring(env, "\tsahf");
907 be_emit_finish_line_gas(env, node);
909 finish_CondJmp(env, node, mode_E, pnc);
913 void CMov_emitter(ia32_emit_env_t *env, const ir_node *node) {
914 long pnc = get_ia32_pncode(node);
915 int is_PsiCondCMov = is_ia32_PsiCondCMov(node);
916 int idx_left = 2 - is_PsiCondCMov;
917 int idx_right = 3 - is_PsiCondCMov;
918 const arch_register_t *in1, *in2, *out;
920 out = arch_get_irn_register(env->arch_env, node);
921 in1 = arch_get_irn_register(env->arch_env, get_irn_n(node, idx_left));
922 in2 = arch_get_irn_register(env->arch_env, get_irn_n(node, idx_right));
924 /* we have to emit the cmp first, because the destination register */
925 /* could be one of the compare registers */
926 if (is_ia32_CmpCMov(node)) {
927 be_emit_cstring(env, "\tcmp ");
928 ia32_emit_source_register(env, node, 1);
929 be_emit_cstring(env, ", ");
930 ia32_emit_source_register(env, node, 0);
931 } else if (is_ia32_xCmpCMov(node)) {
932 be_emit_cstring(env, "\tucomis");
933 ia32_emit_mode_suffix_mode(env, get_irn_mode(node));
934 be_emit_char(env, ' ');
935 ia32_emit_source_register(env, node, 1);
936 be_emit_cstring(env, ", ");
937 ia32_emit_source_register(env, node, 0);
938 } else if (is_PsiCondCMov) {
939 /* omit compare because flags are already set by And/Or */
940 be_emit_cstring(env, "\ttest ");
941 ia32_emit_source_register(env, node, 0);
942 be_emit_cstring(env, ", ");
943 ia32_emit_source_register(env, node, 0);
945 assert(0 && "unsupported CMov");
947 be_emit_finish_line_gas(env, node);
949 if (REGS_ARE_EQUAL(out, in2)) {
950 /* best case: default in == out -> do nothing */
951 } else if (REGS_ARE_EQUAL(out, in1)) {
952 ir_node *n = (ir_node*) node;
953 /* true in == out -> need complement compare and exchange true and default in */
954 ir_node *t = get_irn_n(n, idx_left);
955 set_irn_n(n, idx_left, get_irn_n(n, idx_right));
956 set_irn_n(n, idx_right, t);
958 pnc = get_negated_pnc(pnc, get_irn_mode(node));
960 /* out is different from in: need copy default -> out */
961 if (is_PsiCondCMov) {
962 be_emit_cstring(env, "\tmovl ");
963 ia32_emit_dest_register(env, node, 2);
964 be_emit_cstring(env, ", ");
965 ia32_emit_dest_register(env, node, 0);
967 be_emit_cstring(env, "\tmovl ");
968 ia32_emit_source_register(env, node, 3);
969 be_emit_cstring(env, ", ");
970 ia32_emit_dest_register(env, node, 0);
972 be_emit_finish_line_gas(env, node);
975 if (is_PsiCondCMov) {
976 be_emit_cstring(env, "\tcmov");
977 ia32_emit_cmp_suffix(env, pnc);
978 be_emit_cstring(env, "l ");
979 ia32_emit_source_register(env, node, 1);
980 be_emit_cstring(env, ", ");
981 ia32_emit_dest_register(env, node, 0);
983 be_emit_cstring(env, "\tcmov");
984 ia32_emit_cmp_suffix(env, pnc);
985 be_emit_cstring(env, "l ");
986 ia32_emit_source_register(env, node, 2);
987 be_emit_cstring(env, ", ");
988 ia32_emit_dest_register(env, node, 0);
990 be_emit_finish_line_gas(env, node);
994 void emit_ia32_CmpCMov(ia32_emit_env_t *env, const ir_node *node) {
995 CMov_emitter(env, node);
999 void emit_ia32_PsiCondCMov(ia32_emit_env_t *env, const ir_node *node) {
1000 CMov_emitter(env, node);
1004 void emit_ia32_xCmpCMov(ia32_emit_env_t *env, const ir_node *node) {
1005 CMov_emitter(env, node);
1009 void Set_emitter(ia32_emit_env_t *env, const ir_node *node, ir_mode *mode) {
1010 int pnc = get_ia32_pncode(node);
1011 const char *reg8bit;
1012 const arch_register_t *out;
1014 out = arch_get_irn_register(env->arch_env, node);
1015 reg8bit = ia32_get_mapped_reg_name(env->isa->regs_8bit, out);
1017 if (is_ia32_CmpSet(node)) {
1018 be_emit_cstring(env, "\tcmp ");
1019 ia32_emit_binop(env, node);
1020 } else if (is_ia32_xCmpSet(node)) {
1021 be_emit_cstring(env, "\tucomis");
1022 ia32_emit_mode_suffix_mode(env, get_irn_mode(get_irn_n(node, 2)));
1023 be_emit_char(env, ' ');
1024 ia32_emit_binop(env, node);
1025 } else if (is_ia32_PsiCondSet(node)) {
1026 be_emit_cstring(env, "\tcmp $0, ");
1027 ia32_emit_source_register(env, node, 0);
1029 assert(0 && "unsupported Set");
1031 be_emit_finish_line_gas(env, node);
1033 /* use mov to clear target because it doesn't affect the eflags */
1034 be_emit_cstring(env, "\tmovl $0, %");
1035 be_emit_string(env, arch_register_get_name(out));
1036 be_emit_finish_line_gas(env, node);
1038 be_emit_cstring(env, "\tset");
1039 ia32_emit_cmp_suffix(env, pnc);
1040 be_emit_cstring(env, " %");
1041 be_emit_string(env, reg8bit);
1042 be_emit_finish_line_gas(env, node);
1046 void emit_ia32_CmpSet(ia32_emit_env_t *env, const ir_node *node) {
1047 Set_emitter(env, node, get_irn_mode(get_irn_n(node, 2)));
1051 void emit_ia32_PsiCondSet(ia32_emit_env_t *env, const ir_node *node) {
1052 Set_emitter(env, node, get_irn_mode(get_irn_n(node, 0)));
1056 void emit_ia32_xCmpSet(ia32_emit_env_t *env, const ir_node *node) {
1057 Set_emitter(env, node, get_irn_mode(get_irn_n(node, 2)));
1061 void emit_ia32_xCmp(ia32_emit_env_t *env, const ir_node *node) {
1063 long pnc = get_ia32_pncode(node);
1064 long unord = pnc & pn_Cmp_Uo;
1066 assert( (pnc & ia32_pn_Cmp_Unsigned) == 0);
1069 case pn_Cmp_Leg: /* odered */
1072 case pn_Cmp_Uo: /* unordered */
1076 case pn_Cmp_Eq: /* == */
1080 case pn_Cmp_Lt: /* < */
1084 case pn_Cmp_Le: /* <= */
1088 case pn_Cmp_Gt: /* > */
1092 case pn_Cmp_Ge: /* >= */
1096 case pn_Cmp_Lg: /* != */
1101 assert(sse_pnc >= 0 && "unsupported compare");
1103 if (unord && sse_pnc != 3) {
1105 We need a separate compare against unordered.
1106 Quick and Dirty solution:
1107 - get some memory on stack
1111 - and result and stored result
1114 be_emit_cstring(env, "\tsubl $8, %esp");
1115 be_emit_finish_line_gas(env, node);
1117 be_emit_cstring(env, "\tcmpsd $3, ");
1118 ia32_emit_binop(env, node);
1119 be_emit_finish_line_gas(env, node);
1121 be_emit_cstring(env, "\tmovsd ");
1122 ia32_emit_dest_register(env, node, 0);
1123 be_emit_cstring(env, ", (%esp)");
1124 be_emit_finish_line_gas(env, node);
1127 be_emit_cstring(env, "\tcmpsd ");
1128 be_emit_irprintf(env->emit, "%d, ", sse_pnc);
1129 ia32_emit_binop(env, node);
1130 be_emit_finish_line_gas(env, node);
1132 if (unord && sse_pnc != 3) {
1133 be_emit_cstring(env, "\tandpd (%esp), ");
1134 ia32_emit_dest_register(env, node, 0);
1135 be_emit_finish_line_gas(env, node);
1137 be_emit_cstring(env, "\taddl $8, %esp");
1138 be_emit_finish_line_gas(env, node);
1142 /*********************************************************
1145 * ___ _ __ ___ _| |_ _ _ _ _ __ ___ _ __ ___
1146 * / _ \ '_ ` _ \| | __| | | | | | '_ ` _ \| '_ \/ __|
1147 * | __/ | | | | | | |_ | | |_| | | | | | | |_) \__ \
1148 * \___|_| |_| |_|_|\__| | |\__,_|_| |_| |_| .__/|___/
1151 *********************************************************/
1153 /* jump table entry (target and corresponding number) */
1154 typedef struct _branch_t {
1159 /* jump table for switch generation */
1160 typedef struct _jmp_tbl_t {
1161 ir_node *defProj; /**< default target */
1162 int min_value; /**< smallest switch case */
1163 int max_value; /**< largest switch case */
1164 int num_branches; /**< number of jumps */
1165 char *label; /**< label of the jump table */
1166 branch_t *branches; /**< jump array */
1170 * Compare two variables of type branch_t. Used to sort all switch cases
1173 int ia32_cmp_branch_t(const void *a, const void *b) {
1174 branch_t *b1 = (branch_t *)a;
1175 branch_t *b2 = (branch_t *)b;
1177 if (b1->value <= b2->value)
1184 * Emits code for a SwitchJmp (creates a jump table if
1185 * possible otherwise a cmp-jmp cascade). Port from
1189 void emit_ia32_SwitchJmp(ia32_emit_env_t *env, const ir_node *node) {
1190 unsigned long interval;
1195 const ir_edge_t *edge;
1197 /* fill the table structure */
1198 tbl.label = xmalloc(SNPRINTF_BUF_LEN);
1199 tbl.label = get_unique_label(tbl.label, SNPRINTF_BUF_LEN, ".TBL_");
1201 tbl.num_branches = get_irn_n_edges(node);
1202 tbl.branches = xcalloc(tbl.num_branches, sizeof(tbl.branches[0]));
1203 tbl.min_value = INT_MAX;
1204 tbl.max_value = INT_MIN;
1207 /* go over all proj's and collect them */
1208 foreach_out_edge(node, edge) {
1209 proj = get_edge_src_irn(edge);
1210 assert(is_Proj(proj) && "Only proj allowed at SwitchJmp");
1212 pnc = get_Proj_proj(proj);
1214 /* create branch entry */
1215 tbl.branches[i].target = proj;
1216 tbl.branches[i].value = pnc;
1218 tbl.min_value = pnc < tbl.min_value ? pnc : tbl.min_value;
1219 tbl.max_value = pnc > tbl.max_value ? pnc : tbl.max_value;
1221 /* check for default proj */
1222 if (pnc == get_ia32_pncode(node)) {
1223 assert(tbl.defProj == NULL && "found two defProjs at SwitchJmp");
1230 /* sort the branches by their number */
1231 qsort(tbl.branches, tbl.num_branches, sizeof(tbl.branches[0]), ia32_cmp_branch_t);
1233 /* two-complement's magic make this work without overflow */
1234 interval = tbl.max_value - tbl.min_value;
1236 /* emit the table */
1237 be_emit_cstring(env, "\tcmpl $");
1238 be_emit_irprintf(env->emit, "%u, ", interval);
1239 ia32_emit_source_register(env, node, 0);
1240 be_emit_finish_line_gas(env, node);
1242 be_emit_cstring(env, "\tja ");
1243 ia32_emit_cfop_target(env, tbl.defProj);
1244 be_emit_finish_line_gas(env, node);
1246 if (tbl.num_branches > 1) {
1248 be_emit_cstring(env, "\tjmp *");
1249 be_emit_string(env, tbl.label);
1250 be_emit_cstring(env, "(,");
1251 ia32_emit_source_register(env, node, 0);
1252 be_emit_cstring(env, ",4)");
1253 be_emit_finish_line_gas(env, node);
1255 be_gas_emit_switch_section(env->emit, GAS_SECTION_RODATA);
1256 be_emit_cstring(env, "\t.align 4\n");
1257 be_emit_write_line(env);
1259 be_emit_string(env, tbl.label);
1260 be_emit_cstring(env, ":\n");
1261 be_emit_write_line(env);
1263 be_emit_cstring(env, ".long ");
1264 ia32_emit_cfop_target(env, tbl.branches[0].target);
1265 be_emit_finish_line_gas(env, NULL);
1267 last_value = tbl.branches[0].value;
1268 for (i = 1; i < tbl.num_branches; ++i) {
1269 while (++last_value < tbl.branches[i].value) {
1270 be_emit_cstring(env, ".long ");
1271 ia32_emit_cfop_target(env, tbl.defProj);
1272 be_emit_finish_line_gas(env, NULL);
1274 be_emit_cstring(env, ".long ");
1275 ia32_emit_cfop_target(env, tbl.branches[i].target);
1276 be_emit_finish_line_gas(env, NULL);
1278 be_gas_emit_switch_section(env->emit, GAS_SECTION_TEXT);
1280 /* one jump is enough */
1281 be_emit_cstring(env, "\tjmp ");
1282 ia32_emit_cfop_target(env, tbl.branches[0].target);
1283 be_emit_finish_line_gas(env, node);
1293 * Emits code for a unconditional jump.
1296 void emit_Jmp(ia32_emit_env_t *env, const ir_node *node) {
1297 ir_node *block, *next_block;
1299 /* for now, the code works for scheduled and non-schedules blocks */
1300 block = get_nodes_block(node);
1302 /* we have a block schedule */
1303 next_block = next_blk_sched(block);
1304 if (get_cfop_target_block(node) != next_block) {
1305 be_emit_cstring(env, "\tjmp ");
1306 ia32_emit_cfop_target(env, node);
1308 be_emit_cstring(env, "\t/* fallthrough to ");
1309 ia32_emit_cfop_target(env, node);
1310 be_emit_cstring(env, " */");
1312 be_emit_finish_line_gas(env, node);
1316 void emit_ia32_Immediate(ia32_emit_env_t *env, const ir_node *node)
1318 const ia32_attr_t *attr = get_ia32_attr_const(node);
1320 if(attr->am_sc != NULL) {
1321 ident *id = get_entity_ld_ident(attr->am_sc);
1323 if(attr->data.am_sc_sign)
1324 be_emit_char(env, '-');
1325 be_emit_ident(env, id);
1327 if(attr->cnst_val.tv != NULL) {
1328 if(attr->am_sc != NULL)
1329 be_emit_char(env, '+');
1331 be_emit_char(env, '$');
1332 be_emit_tarval(env, attr->cnst_val.tv);
1337 const char* emit_asm_operand(ia32_emit_env_t *env, const ir_node *node,
1340 const arch_register_t *reg;
1341 const char *reg_name;
1345 const ia32_attr_t *attr;
1352 /* parse modifiers */
1355 ir_fprintf(stderr, "Warning: asm text (%+F) ends with %\n", node);
1356 be_emit_char(env, '%');
1359 be_emit_char(env, '%');
1379 ir_fprintf(stderr, "Warning: asm text (%+F) contains unknown modifier "
1380 "'%c' for asm op\n", node, c);
1386 sscanf(s, "%d%n", &num, &p);
1388 ir_fprintf(stderr, "Warning: Couldn't parse assembler operand (%+F)\n",
1396 attr = get_ia32_attr_const(node);
1397 n_outs = ARR_LEN(attr->slots);
1399 reg = get_out_reg(env, node, num);
1402 int in = num - n_outs;
1403 if(in >= get_irn_arity(node)) {
1404 ir_fprintf(stderr, "Warning: Invalid input %d specified in asm "
1405 "op (%+F)\n", num, node);
1408 pred = get_irn_n(node, in);
1409 /* might be an immediate value */
1410 if(is_ia32_Immediate(pred)) {
1411 emit_ia32_Immediate(env, pred);
1414 reg = get_in_reg(env, node, in);
1417 ir_fprintf(stderr, "Warning: no register assigned for %d asm op "
1418 "(%+F)\n", num, node);
1423 be_emit_char(env, '%');
1426 reg_name = arch_register_get_name(reg);
1429 reg_name = ia32_get_mapped_reg_name(env->isa->regs_8bit, reg);
1432 reg_name = ia32_get_mapped_reg_name(env->isa->regs_8bit_high, reg);
1435 reg_name = ia32_get_mapped_reg_name(env->isa->regs_16bit, reg);
1438 panic("Invalid asm op modifier");
1440 be_emit_string(env, reg_name);
1446 * Emits code for an ASM pseudo op.
1449 void emit_ia32_Asm(ia32_emit_env_t *env, const ir_node *node)
1451 const void *gen_attr = get_irn_generic_attr_const(node);
1452 const ia32_asm_attr_t *attr
1453 = CONST_CAST_IA32_ATTR(ia32_asm_attr_t, gen_attr);
1454 ident *asm_text = attr->asm_text;
1455 const char *s = get_id_str(asm_text);
1457 be_emit_cstring(env, "# Begin ASM \t");
1458 be_emit_finish_line_gas(env, node);
1461 be_emit_char(env, '\t');
1465 s = emit_asm_operand(env, node, s);
1468 be_emit_char(env, *s);
1473 be_emit_char(env, '\n');
1474 be_emit_write_line(env);
1476 be_emit_cstring(env, "# End ASM\n");
1477 be_emit_write_line(env);
1480 /**********************************
1483 * | | ___ _ __ _ _| |_) |
1484 * | | / _ \| '_ \| | | | _ <
1485 * | |___| (_) | |_) | |_| | |_) |
1486 * \_____\___/| .__/ \__, |____/
1489 **********************************/
1492 * Emit movsb/w instructions to make mov count divideable by 4
1495 void emit_CopyB_prolog(ia32_emit_env_t *env, int rem) {
1496 be_emit_cstring(env, "\tcld");
1497 be_emit_finish_line_gas(env, NULL);
1501 be_emit_cstring(env, "\tmovsb");
1502 be_emit_finish_line_gas(env, NULL);
1505 be_emit_cstring(env, "\tmovsw");
1506 be_emit_finish_line_gas(env, NULL);
1509 be_emit_cstring(env, "\tmovsb");
1510 be_emit_finish_line_gas(env, NULL);
1511 be_emit_cstring(env, "\tmovsw");
1512 be_emit_finish_line_gas(env, NULL);
1518 * Emit rep movsd instruction for memcopy.
1521 void emit_ia32_CopyB(ia32_emit_env_t *env, const ir_node *node) {
1522 tarval *tv = get_ia32_Immop_tarval(node);
1523 int rem = get_tarval_long(tv);
1525 emit_CopyB_prolog(env, rem);
1527 be_emit_cstring(env, "\trep movsd");
1528 be_emit_finish_line_gas(env, node);
1532 * Emits unrolled memcopy.
1535 void emit_ia32_CopyB_i(ia32_emit_env_t *env, const ir_node *node) {
1536 tarval *tv = get_ia32_Immop_tarval(node);
1537 int size = get_tarval_long(tv);
1539 emit_CopyB_prolog(env, size & 0x3);
1543 be_emit_cstring(env, "\tmovsd");
1544 be_emit_finish_line_gas(env, NULL);
1550 /***************************
1554 * | | / _ \| '_ \ \ / /
1555 * | |___| (_) | | | \ V /
1556 * \_____\___/|_| |_|\_/
1558 ***************************/
1561 * Emit code for conversions (I, FP), (FP, I) and (FP, FP).
1564 void emit_ia32_Conv_with_FP(ia32_emit_env_t *env, const ir_node *node) {
1565 ir_mode *ls_mode = get_ia32_ls_mode(node);
1566 int ls_bits = get_mode_size_bits(ls_mode);
1568 be_emit_cstring(env, "\tcvt");
1570 if(is_ia32_Conv_I2FP(node)) {
1572 be_emit_cstring(env, "si2ss");
1574 be_emit_cstring(env, "si2sd");
1576 } else if(is_ia32_Conv_FP2I(node)) {
1578 be_emit_cstring(env, "ss2si");
1580 be_emit_cstring(env, "sd2si");
1583 assert(is_ia32_Conv_FP2FP(node));
1585 be_emit_cstring(env, "sd2ss");
1587 be_emit_cstring(env, "ss2sd");
1590 be_emit_char(env, ' ');
1592 switch(get_ia32_op_type(node)) {
1594 ia32_emit_source_register(env, node, 2);
1595 be_emit_cstring(env, ", ");
1596 ia32_emit_dest_register(env, node, 0);
1598 case ia32_AddrModeS:
1599 ia32_emit_dest_register(env, node, 0);
1600 be_emit_cstring(env, ", ");
1601 ia32_emit_am(env, node);
1604 assert(0 && "unsupported op type for Conv");
1606 be_emit_finish_line_gas(env, node);
1610 void emit_ia32_Conv_I2FP(ia32_emit_env_t *env, const ir_node *node) {
1611 emit_ia32_Conv_with_FP(env, node);
1615 void emit_ia32_Conv_FP2I(ia32_emit_env_t *env, const ir_node *node) {
1616 emit_ia32_Conv_with_FP(env, node);
1620 void emit_ia32_Conv_FP2FP(ia32_emit_env_t *env, const ir_node *node) {
1621 emit_ia32_Conv_with_FP(env, node);
1625 * Emits code for an Int conversion.
1628 void emit_ia32_Conv_I2I(ia32_emit_env_t *env, const ir_node *node) {
1629 const char *sign_suffix;
1630 ir_mode *smaller_mode = get_ia32_ls_mode(node);
1631 int smaller_bits = get_mode_size_bits(smaller_mode);
1633 const arch_register_t *in_reg, *out_reg;
1635 assert(!mode_is_float(smaller_mode));
1636 assert(smaller_bits == 8 || smaller_bits == 16 || smaller_bits == 32);
1638 signed_mode = mode_is_signed(smaller_mode);
1639 if(smaller_bits == 32) {
1640 // this should not happen as it's no convert
1644 sign_suffix = signed_mode ? "s" : "z";
1647 switch(get_ia32_op_type(node)) {
1649 in_reg = get_in_reg(env, node, 2);
1650 out_reg = get_out_reg(env, node, 0);
1652 if (REGS_ARE_EQUAL(in_reg, &ia32_gp_regs[REG_EAX]) &&
1653 REGS_ARE_EQUAL(out_reg, in_reg) &&
1656 /* argument and result are both in EAX and */
1657 /* signedness is ok: -> use converts */
1658 if (smaller_bits == 8) {
1659 be_emit_cstring(env, "\tcbtw");
1660 } else if (smaller_bits == 16) {
1661 be_emit_cstring(env, "\tcwtl");
1666 const char *sreg = ia32_get_reg_name_for_mode(env, smaller_mode, in_reg);
1668 be_emit_cstring(env, "\tmov");
1669 be_emit_string(env, sign_suffix);
1670 ia32_emit_mode_suffix_mode(env, smaller_mode);
1671 be_emit_cstring(env, "l %");
1672 be_emit_string(env, sreg);
1673 be_emit_cstring(env, ", ");
1674 ia32_emit_dest_register(env, node, 0);
1677 case ia32_AddrModeS: {
1678 be_emit_cstring(env, "\tmov");
1679 be_emit_string(env, sign_suffix);
1680 ia32_emit_mode_suffix_mode(env, smaller_mode);
1681 be_emit_cstring(env, "l %");
1682 ia32_emit_am(env, node);
1683 be_emit_cstring(env, ", ");
1684 ia32_emit_dest_register(env, node, 0);
1688 assert(0 && "unsupported op type for Conv");
1690 be_emit_finish_line_gas(env, node);
1694 * Emits code for an 8Bit Int conversion.
1696 void emit_ia32_Conv_I2I8Bit(ia32_emit_env_t *env, const ir_node *node) {
1697 emit_ia32_Conv_I2I(env, node);
1701 /*******************************************
1704 * | |__ ___ _ __ ___ __| | ___ ___
1705 * | '_ \ / _ \ '_ \ / _ \ / _` |/ _ \/ __|
1706 * | |_) | __/ | | | (_) | (_| | __/\__ \
1707 * |_.__/ \___|_| |_|\___/ \__,_|\___||___/
1709 *******************************************/
1712 * Emits a backend call
1715 void emit_be_Call(ia32_emit_env_t *env, const ir_node *node) {
1716 ir_entity *ent = be_Call_get_entity(node);
1718 be_emit_cstring(env, "\tcall ");
1720 mark_entity_visited(ent);
1721 be_emit_string(env, get_entity_ld_name(ent));
1723 be_emit_char(env, '*');
1724 ia32_emit_dest_register(env, get_irn_n(node, be_pos_Call_ptr), 0);
1726 be_emit_finish_line_gas(env, node);
1730 * Emits code to increase stack pointer.
1733 void emit_be_IncSP(ia32_emit_env_t *env, const ir_node *node) {
1734 int offs = be_get_IncSP_offset(node);
1740 be_emit_cstring(env, "\tsubl $");
1741 be_emit_irprintf(env->emit, "%u, ", offs);
1742 ia32_emit_source_register(env, node, 0);
1744 be_emit_cstring(env, "\taddl $");
1745 be_emit_irprintf(env->emit, "%u, ", -offs);
1746 ia32_emit_source_register(env, node, 0);
1748 be_emit_finish_line_gas(env, node);
1752 * Emits code to set stack pointer.
1755 void emit_be_SetSP(ia32_emit_env_t *env, const ir_node *node) {
1756 be_emit_cstring(env, "\tmovl ");
1757 ia32_emit_source_register(env, node, 2);
1758 be_emit_cstring(env, ", ");
1759 ia32_emit_dest_register(env, node, 0);
1760 be_emit_finish_line_gas(env, node);
1764 * Emits code for Copy/CopyKeep.
1767 void Copy_emitter(ia32_emit_env_t *env, const ir_node *node, const ir_node *op)
1769 const arch_env_t *aenv = env->arch_env;
1772 if (REGS_ARE_EQUAL(arch_get_irn_register(aenv, node), arch_get_irn_register(aenv, op)) ||
1773 arch_register_type_is(arch_get_irn_register(aenv, op), virtual))
1776 mode = get_irn_mode(node);
1777 if (mode == mode_E) {
1778 be_emit_cstring(env, "\tmovsd ");
1779 ia32_emit_source_register(env, node, 0);
1780 be_emit_cstring(env, ", ");
1781 ia32_emit_dest_register(env, node, 0);
1783 be_emit_cstring(env, "\tmovl ");
1784 ia32_emit_source_register(env, node, 0);
1785 be_emit_cstring(env, ", ");
1786 ia32_emit_dest_register(env, node, 0);
1788 be_emit_finish_line_gas(env, node);
1792 void emit_be_Copy(ia32_emit_env_t *env, const ir_node *node) {
1793 Copy_emitter(env, node, be_get_Copy_op(node));
1797 void emit_be_CopyKeep(ia32_emit_env_t *env, const ir_node *node) {
1798 Copy_emitter(env, node, be_get_CopyKeep_op(node));
1802 * Emits code for exchange.
1805 void emit_be_Perm(ia32_emit_env_t *env, const ir_node *node) {
1806 const arch_register_t *in1, *in2;
1807 const arch_register_class_t *cls1, *cls2;
1809 in1 = arch_get_irn_register(env->arch_env, get_irn_n(node, 0));
1810 in2 = arch_get_irn_register(env->arch_env, get_irn_n(node, 1));
1812 cls1 = arch_register_get_class(in1);
1813 cls2 = arch_register_get_class(in2);
1815 assert(cls1 == cls2 && "Register class mismatch at Perm");
1817 if (cls1 == &ia32_reg_classes[CLASS_ia32_gp]) {
1818 be_emit_cstring(env, "\txchg ");
1819 ia32_emit_source_register(env, node, 1);
1820 be_emit_cstring(env, ", ");
1821 ia32_emit_source_register(env, node, 0);
1822 be_emit_finish_line_gas(env, node);
1823 } else if (cls1 == &ia32_reg_classes[CLASS_ia32_xmm]) {
1824 be_emit_cstring(env, "\txorpd ");
1825 ia32_emit_source_register(env, node, 1);
1826 be_emit_cstring(env, ", ");
1827 ia32_emit_source_register(env, node, 0);
1828 be_emit_finish_line_gas(env, NULL);
1830 be_emit_cstring(env, "\txorpd ");
1831 ia32_emit_source_register(env, node, 0);
1832 be_emit_cstring(env, ", ");
1833 ia32_emit_source_register(env, node, 1);
1834 be_emit_finish_line_gas(env, NULL);
1836 be_emit_cstring(env, "\txorpd ");
1837 ia32_emit_source_register(env, node, 1);
1838 be_emit_cstring(env, ", ");
1839 ia32_emit_source_register(env, node, 0);
1840 be_emit_finish_line_gas(env, node);
1841 } else if (cls1 == &ia32_reg_classes[CLASS_ia32_vfp]) {
1843 } else if (cls1 == &ia32_reg_classes[CLASS_ia32_st]) {
1849 * Emits code for Constant loading.
1852 void emit_ia32_Const(ia32_emit_env_t *env, const ir_node *node) {
1853 ia32_immop_type_t imm_tp = get_ia32_immop_type(node);
1855 if (imm_tp == ia32_ImmSymConst) {
1856 be_emit_cstring(env, "\tmovl ");
1857 ia32_emit_immediate(env, node);
1858 be_emit_cstring(env, ", ");
1859 ia32_emit_dest_register(env, node, 0);
1861 tarval *tv = get_ia32_Immop_tarval(node);
1862 assert(get_irn_mode(node) == mode_Iu);
1863 /* beware: in some rare cases mode is mode_b which has no tarval_null() */
1864 if (tarval_is_null(tv)) {
1865 if (env->isa->opt_arch == arch_pentium_4) {
1866 /* P4 prefers sub r, r, others xor r, r */
1867 be_emit_cstring(env, "\tsubl ");
1869 be_emit_cstring(env, "\txorl ");
1871 ia32_emit_dest_register(env, node, 0);
1872 be_emit_cstring(env, ", ");
1873 ia32_emit_dest_register(env, node, 0);
1875 be_emit_cstring(env, "\tmovl ");
1876 ia32_emit_immediate(env, node);
1877 be_emit_cstring(env, ", ");
1878 ia32_emit_dest_register(env, node, 0);
1881 be_emit_finish_line_gas(env, node);
1885 * Emits code to load the TLS base
1888 void emit_ia32_LdTls(ia32_emit_env_t *env, const ir_node *node) {
1889 be_emit_cstring(env, "\tmovl %gs:0, ");
1890 ia32_emit_dest_register(env, node, 0);
1891 be_emit_finish_line_gas(env, node);
1895 void emit_be_Return(ia32_emit_env_t *env, const ir_node *node) {
1896 be_emit_cstring(env, "\tret");
1897 be_emit_finish_line_gas(env, node);
1901 void emit_Nothing(ia32_emit_env_t *env, const ir_node *node) {
1905 /***********************************************************************************
1908 * _ __ ___ __ _ _ _ __ | |_ _ __ __ _ _ __ ___ _____ _____ _ __| | __
1909 * | '_ ` _ \ / _` | | '_ \ | _| '__/ _` | '_ ` _ \ / _ \ \ /\ / / _ \| '__| |/ /
1910 * | | | | | | (_| | | | | | | | | | | (_| | | | | | | __/\ V V / (_) | | | <
1911 * |_| |_| |_|\__,_|_|_| |_| |_| |_| \__,_|_| |_| |_|\___| \_/\_/ \___/|_| |_|\_\
1913 ***********************************************************************************/
1916 * Enters the emitter functions for handled nodes into the generic
1917 * pointer of an opcode.
1920 void ia32_register_emitters(void) {
1922 #define IA32_EMIT2(a,b) op_ia32_##a->ops.generic = (op_func)emit_ia32_##b
1923 #define IA32_EMIT(a) IA32_EMIT2(a,a)
1924 #define EMIT(a) op_##a->ops.generic = (op_func)emit_##a
1925 #define IGN(a) op_##a->ops.generic = (op_func)emit_Nothing
1926 #define BE_EMIT(a) op_be_##a->ops.generic = (op_func)emit_be_##a
1927 #define BE_IGN(a) op_be_##a->ops.generic = (op_func)emit_Nothing
1929 /* first clear the generic function pointer for all ops */
1930 clear_irp_opcodes_generic_func();
1932 /* register all emitter functions defined in spec */
1933 ia32_register_spec_emitters();
1935 /* other ia32 emitter functions */
1942 IA32_EMIT(PsiCondCMov);
1944 IA32_EMIT(PsiCondSet);
1945 IA32_EMIT(SwitchJmp);
1948 IA32_EMIT(Conv_I2FP);
1949 IA32_EMIT(Conv_FP2I);
1950 IA32_EMIT(Conv_FP2FP);
1951 IA32_EMIT(Conv_I2I);
1952 IA32_EMIT(Conv_I2I8Bit);
1957 IA32_EMIT(xCmpCMov);
1958 IA32_EMIT(xCondJmp);
1959 IA32_EMIT2(fcomJmp, x87CondJmp);
1960 IA32_EMIT2(fcompJmp, x87CondJmp);
1961 IA32_EMIT2(fcomppJmp, x87CondJmp);
1962 IA32_EMIT2(fcomrJmp, x87CondJmp);
1963 IA32_EMIT2(fcomrpJmp, x87CondJmp);
1964 IA32_EMIT2(fcomrppJmp, x87CondJmp);
1966 /* benode emitter */
1992 static const char *last_name = NULL;
1993 static unsigned last_line = -1;
1994 static unsigned num = -1;
1997 * Emit the debug support for node node.
2000 void ia32_emit_dbg(ia32_emit_env_t *env, const ir_node *node) {
2001 dbg_info *db = get_irn_dbg_info(node);
2003 const char *fname = be_retrieve_dbg_info(db, &lineno);
2005 if (! env->cg->birg->main_env->options->stabs_debug_support)
2009 if (last_name != fname) {
2011 be_dbg_include_begin(env->cg->birg->main_env->db_handle, fname);
2014 if (last_line != lineno) {
2017 snprintf(name, sizeof(name), ".LM%u", ++num);
2019 be_dbg_line(env->cg->birg->main_env->db_handle, lineno, name);
2020 be_emit_string(env, name);
2021 be_emit_cstring(env, ":\n");
2022 be_emit_write_line(env);
2027 typedef void (*emit_func_ptr) (ia32_emit_env_t *, const ir_node *);
2030 * Emits code for a node.
2033 void ia32_emit_node(ia32_emit_env_t *env, const ir_node *node) {
2034 ir_op *op = get_irn_op(node);
2036 DBG((dbg, LEVEL_1, "emitting code for %+F\n", node));
2038 if (op->ops.generic) {
2039 emit_func_ptr func = (emit_func_ptr) op->ops.generic;
2040 ia32_emit_dbg(env, node);
2041 (*func) (env, node);
2043 emit_Nothing(env, node);
2044 ir_fprintf(stderr, "Warning: No emit handler for node %+F (%+G)\n", node, node);
2049 * Emits gas alignment directives
2052 void ia32_emit_alignment(ia32_emit_env_t *env, unsigned align, unsigned skip) {
2053 be_emit_cstring(env, "\t.p2align ");
2054 be_emit_irprintf(env->emit, "%u,,%u\n", align, skip);
2055 be_emit_write_line(env);
2059 * Emits gas alignment directives for Functions depended on cpu architecture.
2062 void ia32_emit_align_func(ia32_emit_env_t *env, cpu_support cpu) {
2064 unsigned maximum_skip;
2079 maximum_skip = (1 << align) - 1;
2080 ia32_emit_alignment(env, align, maximum_skip);
2084 * Emits gas alignment directives for Labels depended on cpu architecture.
2087 void ia32_emit_align_label(ia32_emit_env_t *env, cpu_support cpu) {
2088 unsigned align; unsigned maximum_skip;
2103 maximum_skip = (1 << align) - 1;
2104 ia32_emit_alignment(env, align, maximum_skip);
2108 * Test wether a block should be aligned.
2109 * For cpus in the P4/Athlon class it is usefull to align jump labels to
2110 * 16 bytes. However we should only do that if the alignment nops before the
2111 * label aren't executed more often than we have jumps to the label.
2114 int should_align_block(ia32_emit_env_t *env, ir_node *block, ir_node *prev) {
2115 static const double DELTA = .0001;
2116 ir_exec_freq *exec_freq = env->cg->birg->exec_freq;
2118 double prev_freq = 0; /**< execfreq of the fallthrough block */
2119 double jmp_freq = 0; /**< execfreq of all non-fallthrough blocks */
2120 cpu_support cpu = env->isa->opt_arch;
2123 if(exec_freq == NULL)
2125 if(cpu == arch_i386 || cpu == arch_i486)
2128 block_freq = get_block_execfreq(exec_freq, block);
2129 if(block_freq < DELTA)
2132 n_cfgpreds = get_Block_n_cfgpreds(block);
2133 for(i = 0; i < n_cfgpreds; ++i) {
2134 ir_node *pred = get_Block_cfgpred_block(block, i);
2135 double pred_freq = get_block_execfreq(exec_freq, pred);
2138 prev_freq += pred_freq;
2140 jmp_freq += pred_freq;
2144 if(prev_freq < DELTA && !(jmp_freq < DELTA))
2147 jmp_freq /= prev_freq;
2151 case arch_athlon_64:
2153 return jmp_freq > 3;
2155 return jmp_freq > 2;
2160 void ia32_emit_block_header(ia32_emit_env_t *env, ir_node *block, ir_node *prev)
2165 ir_exec_freq *exec_freq = env->cg->birg->exec_freq;
2168 n_cfgpreds = get_Block_n_cfgpreds(block);
2169 if (n_cfgpreds == 0) {
2171 } else if (n_cfgpreds == 1) {
2172 ir_node *pred = get_Block_cfgpred(block, 0);
2173 ir_node *pred_block = get_nodes_block(pred);
2175 /* we don't need labels for fallthrough blocks, however switch-jmps
2176 * are no fallthoughs */
2177 if(pred_block == prev &&
2178 !(is_Proj(pred) && is_ia32_SwitchJmp(get_Proj_pred(pred)))) {
2187 if (should_align_block(env, block, prev)) {
2189 ia32_emit_align_label(env, env->isa->opt_arch);
2193 ia32_emit_block_name(env, block);
2194 be_emit_char(env, ':');
2196 be_emit_pad_comment(env);
2197 be_emit_cstring(env, " /* preds:");
2199 /* emit list of pred blocks in comment */
2200 arity = get_irn_arity(block);
2201 for (i = 0; i < arity; ++i) {
2202 ir_node *predblock = get_Block_cfgpred_block(block, i);
2203 be_emit_irprintf(env->emit, " %d", get_irn_node_nr(predblock));
2206 be_emit_cstring(env, "\t/* ");
2207 ia32_emit_block_name(env, block);
2208 be_emit_cstring(env, ": ");
2210 if (exec_freq != NULL) {
2211 be_emit_irprintf(env->emit, " freq: %f",
2212 get_block_execfreq(exec_freq, block));
2214 be_emit_cstring(env, " */\n");
2215 be_emit_write_line(env);
2219 * Walks over the nodes in a block connected by scheduling edges
2220 * and emits code for each node.
2223 void ia32_gen_block(ia32_emit_env_t *env, ir_node *block, ir_node *last_block)
2225 const ir_node *node;
2227 ia32_emit_block_header(env, block, last_block);
2229 /* emit the contents of the block */
2230 ia32_emit_dbg(env, block);
2231 sched_foreach(block, node) {
2232 ia32_emit_node(env, node);
2237 * Emits code for function start.
2240 void ia32_emit_func_prolog(ia32_emit_env_t *env, ir_graph *irg) {
2241 ir_entity *irg_ent = get_irg_entity(irg);
2242 const char *irg_name = get_entity_ld_name(irg_ent);
2243 cpu_support cpu = env->isa->opt_arch;
2244 const be_irg_t *birg = env->cg->birg;
2246 be_emit_write_line(env);
2247 be_gas_emit_switch_section(env->emit, GAS_SECTION_TEXT);
2248 be_dbg_method_begin(birg->main_env->db_handle, irg_ent, be_abi_get_stack_layout(birg->abi));
2249 ia32_emit_align_func(env, cpu);
2250 if (get_entity_visibility(irg_ent) == visibility_external_visible) {
2251 be_emit_cstring(env, ".global ");
2252 be_emit_string(env, irg_name);
2253 be_emit_char(env, '\n');
2254 be_emit_write_line(env);
2256 ia32_emit_function_object(env, irg_name);
2257 be_emit_string(env, irg_name);
2258 be_emit_cstring(env, ":\n");
2259 be_emit_write_line(env);
2263 * Emits code for function end
2266 void ia32_emit_func_epilog(ia32_emit_env_t *env, ir_graph *irg) {
2267 const char *irg_name = get_entity_ld_name(get_irg_entity(irg));
2268 const be_irg_t *birg = env->cg->birg;
2270 ia32_emit_function_size(env, irg_name);
2271 be_dbg_method_end(birg->main_env->db_handle);
2272 be_emit_char(env, '\n');
2273 be_emit_write_line(env);
2278 * Sets labels for control flow nodes (jump target)
2281 void ia32_gen_labels(ir_node *block, void *data) {
2283 int n = get_Block_n_cfgpreds(block);
2285 for (n--; n >= 0; n--) {
2286 pred = get_Block_cfgpred(block, n);
2287 set_irn_link(pred, block);
2292 * Emit an exception label if the current instruction can fail.
2294 void ia32_emit_exc_label(ia32_emit_env_t *env, const ir_node *node) {
2295 if (get_ia32_exc_label(node)) {
2296 be_emit_irprintf(env->emit, ".EXL%u\n", 0);
2297 be_emit_write_line(env);
2302 * Main driver. Emits the code for one routine.
2304 void ia32_gen_routine(ia32_code_gen_t *cg, ir_graph *irg) {
2305 ia32_emit_env_t env;
2307 ir_node *last_block = NULL;
2310 env.isa = (ia32_isa_t *)cg->arch_env->isa;
2311 env.emit = &env.isa->emit;
2312 env.arch_env = cg->arch_env;
2315 ia32_register_emitters();
2317 ia32_emit_func_prolog(&env, irg);
2318 irg_block_walk_graph(irg, ia32_gen_labels, NULL, &env);
2320 n = ARR_LEN(cg->blk_sched);
2321 for (i = 0; i < n;) {
2324 block = cg->blk_sched[i];
2326 next_bl = i < n ? cg->blk_sched[i] : NULL;
2328 /* set here the link. the emitter expects to find the next block here */
2329 set_irn_link(block, next_bl);
2330 ia32_gen_block(&env, block, last_block);
2334 ia32_emit_func_epilog(&env, irg);
2337 void ia32_init_emitter(void)
2339 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.emitter");