2 * This file implements the node emitter.
3 * @author Christian Wuerdig
22 #include "iredges_t.h"
24 #include "../besched_t.h"
25 #include "../benode_t.h"
27 #include "ia32_emitter.h"
28 #include "gen_ia32_emitter.h"
29 #include "gen_ia32_regalloc_if.h"
30 #include "ia32_nodes_attr.h"
31 #include "ia32_new_nodes.h"
32 #include "ia32_map_regs.h"
33 #include "bearch_ia32_t.h"
35 #define BLOCK_PREFIX(x) ".L" x
37 #define SNPRINTF_BUF_LEN 128
39 /* global arch_env for lc_printf functions */
40 static const arch_env_t *arch_env = NULL;
42 /** by default, we generate assembler code for the Linux gas */
43 asm_flavour_t asm_flavour = ASM_LINUX_GAS;
46 * Switch to a new section
48 void ia32_switch_section(FILE *F, section_t sec) {
49 static section_t curr_sec = NO_SECTION;
50 static const char *text[ASM_MAX][SECTION_MAX] = {
52 ".section\t.text", ".section\t.data", ".section\t.rodata", ".section\t.text"
55 ".section\t.text", ".section\t.data", ".section .rdata,\"dr\"", ".section\t.text"
72 fprintf(F, "\t%s\n", text[asm_flavour][sec]);
76 static void ia32_dump_function_object(FILE *F, const char *name)
78 switch (asm_flavour) {
80 fprintf(F, "\t.type\t%s, @function\n", name);
83 fprintf(F, "\t.def\t%s;\t.scl\t2;\t.type\t32;\t.endef\n", name);
88 static void ia32_dump_function_size(FILE *F, const char *name)
90 switch (asm_flavour) {
92 fprintf(F, "\t.size\t%s, .-%s\n", name, name);
97 /*************************************************************
99 * (_) | | / _| | | | |
100 * _ __ _ __ _ _ __ | |_| |_ | |__ ___| |_ __ ___ _ __
101 * | '_ \| '__| | '_ \| __| _| | '_ \ / _ \ | '_ \ / _ \ '__|
102 * | |_) | | | | | | | |_| | | | | | __/ | |_) | __/ |
103 * | .__/|_| |_|_| |_|\__|_| |_| |_|\___|_| .__/ \___|_|
106 *************************************************************/
108 static INLINE int be_is_unknown_reg(const arch_register_t *reg) {
110 REGS_ARE_EQUAL(reg, &ia32_gp_regs[REG_GP_UKNWN]) || \
111 REGS_ARE_EQUAL(reg, &ia32_xmm_regs[REG_XMM_UKNWN]) || \
112 REGS_ARE_EQUAL(reg, &ia32_vfp_regs[REG_VFP_UKNWN]);
116 * returns true if a node has x87 registers
118 static INLINE int has_x87_register(const ir_node *n) {
119 return is_irn_machine_user(n, 0);
122 /* We always pass the ir_node which is a pointer. */
123 static int ia32_get_arg_type(const lc_arg_occ_t *occ) {
124 return lc_arg_type_ptr;
129 * Returns the register at in position pos.
131 static const arch_register_t *get_in_reg(const ir_node *irn, int pos) {
133 const arch_register_t *reg = NULL;
135 assert(get_irn_arity(irn) > pos && "Invalid IN position");
137 /* The out register of the operator at position pos is the
138 in register we need. */
139 op = get_irn_n(irn, pos);
141 reg = arch_get_irn_register(arch_env, op);
143 assert(reg && "no in register found");
145 /* in case of unknown: just return a register */
146 if (REGS_ARE_EQUAL(reg, &ia32_gp_regs[REG_GP_UKNWN]))
147 reg = &ia32_gp_regs[REG_EAX];
148 else if (REGS_ARE_EQUAL(reg, &ia32_xmm_regs[REG_XMM_UKNWN]))
149 reg = &ia32_xmm_regs[REG_XMM0];
150 else if (REGS_ARE_EQUAL(reg, &ia32_vfp_regs[REG_VFP_UKNWN]))
151 reg = &ia32_vfp_regs[REG_VF0];
157 * Returns the register at out position pos.
159 static const arch_register_t *get_out_reg(const ir_node *irn, int pos) {
161 const arch_register_t *reg = NULL;
163 /* 1st case: irn is not of mode_T, so it has only */
164 /* one OUT register -> good */
165 /* 2nd case: irn is of mode_T -> collect all Projs and ask the */
166 /* Proj with the corresponding projnum for the register */
168 if (get_irn_mode(irn) != mode_T) {
169 reg = arch_get_irn_register(arch_env, irn);
171 else if (is_ia32_irn(irn)) {
172 reg = get_ia32_out_reg(irn, pos);
175 const ir_edge_t *edge;
177 foreach_out_edge(irn, edge) {
178 proj = get_edge_src_irn(edge);
179 assert(is_Proj(proj) && "non-Proj from mode_T node");
180 if (get_Proj_proj(proj) == pos) {
181 reg = arch_get_irn_register(arch_env, proj);
187 assert(reg && "no out register found");
197 * Returns the name of the in register at position pos.
199 static const char *get_ia32_reg_name(ir_node *irn, int pos, enum io_direction in_out) {
200 const arch_register_t *reg;
202 if (in_out == IN_REG) {
203 reg = get_in_reg(irn, pos);
205 if (reg->reg_class == &ia32_reg_classes[CLASS_ia32_vfp]) {
206 /* FIXME: works for binop only */
207 assert(2 <= pos && pos <= 3);
208 reg = get_ia32_attr(irn)->x87[pos - 2];
212 /* destination address mode nodes don't have outputs */
213 if (is_ia32_irn(irn) && get_ia32_op_type(irn) == ia32_AddrModeD) {
217 reg = get_out_reg(irn, pos);
218 if (reg->reg_class == &ia32_reg_classes[CLASS_ia32_vfp])
219 reg = get_ia32_attr(irn)->x87[pos + 2];
221 return arch_register_get_name(reg);
225 * Get the register name for a node.
227 static int ia32_get_reg_name(lc_appendable_t *app,
228 const lc_arg_occ_t *occ, const lc_arg_value_t *arg)
231 ir_node *irn = arg->v_ptr;
232 int nr = occ->width - 1;
235 return lc_appendable_snadd(app, "(null)", 6);
237 buf = get_ia32_reg_name(irn, nr, occ->conversion == 'S' ? IN_REG : OUT_REG);
239 /* append the stupid % to register names */
240 lc_appendable_chadd(app, '%');
241 return lc_appendable_snadd(app, buf, strlen(buf));
245 * Get the x87 register name for a node.
247 static int ia32_get_x87_name(lc_appendable_t *app,
248 const lc_arg_occ_t *occ, const lc_arg_value_t *arg)
251 ir_node *irn = arg->v_ptr;
252 int nr = occ->width - 1;
256 return lc_appendable_snadd(app, "(null)", 6);
258 attr = get_ia32_attr(irn);
259 buf = attr->x87[nr]->name;
260 lc_appendable_chadd(app, '%');
261 return lc_appendable_snadd(app, buf, strlen(buf));
265 * Returns the tarval, offset or scale of an ia32 as a string.
267 static int ia32_const_to_str(lc_appendable_t *app,
268 const lc_arg_occ_t *occ, const lc_arg_value_t *arg)
271 ir_node *irn = arg->v_ptr;
274 return lc_arg_append(app, occ, "(null)", 6);
276 if (occ->conversion == 'C') {
277 buf = get_ia32_cnst(irn);
280 buf = get_ia32_am_offs(irn);
283 return buf ? lc_appendable_snadd(app, buf, strlen(buf)) : 0;
287 * Determines the SSE suffix depending on the mode.
289 static int ia32_get_mode_suffix(lc_appendable_t *app,
290 const lc_arg_occ_t *occ, const lc_arg_value_t *arg)
292 ir_node *irn = arg->v_ptr;
293 ir_mode *mode = get_irn_mode(irn);
295 if (mode == mode_T) {
296 mode = (is_ia32_Ld(irn) || is_ia32_St(irn)) ? get_ia32_ls_mode(irn) : get_ia32_res_mode(irn);
300 return lc_arg_append(app, occ, "(null)", 6);
302 if (mode_is_float(mode)) {
303 return lc_appendable_chadd(app, get_mode_size_bits(mode) == 32 ? 's' : 'd');
306 return lc_appendable_chadd(app, mode_is_signed(mode) ? 's' : 'z');
311 * Return the ia32 printf arg environment.
312 * We use the firm environment with some additional handlers.
314 const lc_arg_env_t *ia32_get_arg_env(void) {
315 static lc_arg_env_t *env = NULL;
317 static const lc_arg_handler_t ia32_reg_handler = { ia32_get_arg_type, ia32_get_reg_name };
318 static const lc_arg_handler_t ia32_const_handler = { ia32_get_arg_type, ia32_const_to_str };
319 static const lc_arg_handler_t ia32_mode_handler = { ia32_get_arg_type, ia32_get_mode_suffix };
320 static const lc_arg_handler_t ia32_x87_handler = { ia32_get_arg_type, ia32_get_x87_name };
323 /* extend the firm printer */
324 env = firm_get_arg_env();
326 lc_arg_register(env, "ia32:sreg", 'S', &ia32_reg_handler);
327 lc_arg_register(env, "ia32:dreg", 'D', &ia32_reg_handler);
328 lc_arg_register(env, "ia32:cnst", 'C', &ia32_const_handler);
329 lc_arg_register(env, "ia32:offs", 'O', &ia32_const_handler);
330 lc_arg_register(env, "ia32:mode", 'M', &ia32_mode_handler);
331 lc_arg_register(env, "ia32:x87", 'X', &ia32_x87_handler);
337 static const char *ia32_get_reg_name_for_mode(ia32_emit_env_t *env, ir_mode *mode, const arch_register_t *reg) {
338 switch(get_mode_size_bits(mode)) {
340 return ia32_get_mapped_reg_name(env->isa->regs_8bit, reg);
342 return ia32_get_mapped_reg_name(env->isa->regs_16bit, reg);
344 return (char *)arch_register_get_name(reg);
349 * Emits registers and/or address mode of a binary operation.
351 const char *ia32_emit_binop(const ir_node *n, ia32_emit_env_t *env) {
352 static char *buf = NULL;
354 /* verify that this function is never called on non-AM supporting operations */
355 //assert(get_ia32_am_support(n) != ia32_am_None && "emit binop expects addressmode support");
357 #define PRODUCES_RESULT(n) \
358 (!(is_ia32_St(n) || \
359 is_ia32_Store8Bit(n) || \
360 is_ia32_CondJmp(n) || \
361 is_ia32_xCondJmp(n) || \
362 is_ia32_CmpSet(n) || \
363 is_ia32_xCmpSet(n) || \
364 is_ia32_SwitchJmp(n)))
367 buf = xcalloc(1, SNPRINTF_BUF_LEN);
370 memset(buf, 0, SNPRINTF_BUF_LEN);
373 switch(get_ia32_op_type(n)) {
375 if (is_ia32_ImmConst(n)) {
376 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%3S, %s", n, get_ia32_cnst(n));
378 else if (is_ia32_ImmSymConst(n)) {
379 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%3S, OFFSET FLAT:%s", n, get_ia32_cnst(n));
382 const arch_register_t *in1 = get_in_reg(n, 2);
383 const arch_register_t *in2 = get_in_reg(n, 3);
384 const arch_register_t *out = PRODUCES_RESULT(n) ? get_out_reg(n, 0) : NULL;
385 const arch_register_t *in;
388 in = out ? (REGS_ARE_EQUAL(out, in2) ? in1 : in2) : in2;
389 out = out ? out : in1;
390 in_name = arch_register_get_name(in);
392 if (is_ia32_emit_cl(n)) {
393 assert(REGS_ARE_EQUAL(&ia32_gp_regs[REG_ECX], in) && "shift operation needs ecx");
397 snprintf(buf, SNPRINTF_BUF_LEN, "%%%s, %%%s", arch_register_get_name(out), in_name);
401 if (is_ia32_ImmConst(n) || is_ia32_ImmSymConst(n)) {
402 assert(! PRODUCES_RESULT(n) && "Source AM with Const must not produce result");
403 snprintf(buf, SNPRINTF_BUF_LEN, "%s, %s", get_ia32_cnst(n), ia32_emit_am(n, env));
406 if (PRODUCES_RESULT(n)) {
407 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%1D, %s", n, ia32_emit_am(n, env));
410 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%3S, %s", n, ia32_emit_am(n, env));
415 if (is_ia32_ImmConst(n) || is_ia32_ImmSymConst(n)) {
416 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%s,%s%s",
417 ia32_emit_am(n, env),
418 is_ia32_ImmSymConst(n) ? " OFFSET FLAT:" : " ", /* In case of a symconst we must add OFFSET to */
419 get_ia32_cnst(n)); /* tell the assembler to store it's address. */
422 const arch_register_t *in1 = get_in_reg(n, get_irn_arity(n) == 5 ? 3 : 2);
423 ir_mode *mode = get_ia32_res_mode(n);
426 mode = mode ? mode : get_ia32_ls_mode(n);
427 in_name = ia32_get_reg_name_for_mode(env, mode, in1);
429 if (is_ia32_emit_cl(n)) {
430 assert(REGS_ARE_EQUAL(&ia32_gp_regs[REG_ECX], in1) && "shift operation needs ecx");
434 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%s, %%%s", ia32_emit_am(n, env), in_name);
438 assert(0 && "unsupported op type");
441 #undef PRODUCES_RESULT
447 * Returns the xxx PTR string for a given mode
449 * @param mode the mode
450 * @param x87_insn if non-zero returns the string for a x87 instruction
451 * else for a SSE instruction
453 static const char *pointer_size(ir_mode *mode, int x87_insn)
456 switch (get_mode_size_bits(mode)) {
457 case 8: return "BYTE PTR";
458 case 16: return "WORD PTR";
459 case 32: return "DWORD PTR";
465 case 96: return "XWORD PTR";
466 default: return NULL;
473 * Emits registers and/or address mode of a binary operation.
475 const char *ia32_emit_x87_binop(const ir_node *n, ia32_emit_env_t *env) {
476 static char *buf = NULL;
478 /* verify that this function is never called on non-AM supporting operations */
479 //assert(get_ia32_am_support(n) != ia32_am_None && "emit binop expects addressmode support");
482 buf = xcalloc(1, SNPRINTF_BUF_LEN);
485 memset(buf, 0, SNPRINTF_BUF_LEN);
488 switch(get_ia32_op_type(n)) {
490 if (is_ia32_ImmConst(n) || is_ia32_ImmSymConst(n)) {
491 ir_mode *mode = get_ia32_ls_mode(n);
492 const char *p = pointer_size(mode, 1);
493 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%s %s", p, get_ia32_cnst(n));
496 ia32_attr_t *attr = get_ia32_attr(n);
497 const arch_register_t *in1 = attr->x87[0];
498 const arch_register_t *in2 = attr->x87[1];
499 const arch_register_t *out = attr->x87[2];
500 const arch_register_t *in;
503 in = out ? (REGS_ARE_EQUAL(out, in2) ? in1 : in2) : in2;
504 out = out ? out : in1;
505 in_name = arch_register_get_name(in);
507 snprintf(buf, SNPRINTF_BUF_LEN, "%%%s, %%%s", arch_register_get_name(out), in_name);
512 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%s", ia32_emit_am(n, env));
515 assert(0 && "unsupported op type");
522 * Emits registers and/or address mode of a unary operation.
524 const char *ia32_emit_unop(const ir_node *n, ia32_emit_env_t *env) {
525 static char *buf = NULL;
528 buf = xcalloc(1, SNPRINTF_BUF_LEN);
531 memset(buf, 0, SNPRINTF_BUF_LEN);
534 switch(get_ia32_op_type(n)) {
536 if (is_ia32_ImmConst(n) || is_ia32_ImmSymConst(n)) {
537 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%C", n);
540 if (is_ia32_MulS(n) || is_ia32_Mulh(n)) {
541 /* MulS and Mulh implicitly multiply by EAX */
542 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%4S", n);
545 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%1D", n);
549 snprintf(buf, SNPRINTF_BUF_LEN, "%s", ia32_emit_am(n, env));
553 Mulh is emitted via emit_unop
554 imul [MEM] means EDX:EAX <- EAX * [MEM]
556 assert((is_ia32_Mulh(n) || is_ia32_MulS(n)) && "Only MulS and Mulh can have AM source as unop");
557 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%s", ia32_emit_am(n, env));
560 assert(0 && "unsupported op type");
567 * Emits address mode.
569 const char *ia32_emit_am(const ir_node *n, ia32_emit_env_t *env) {
570 ia32_am_flavour_t am_flav = get_ia32_am_flavour(n);
574 static struct obstack *obst = NULL;
575 ir_mode *mode = get_ia32_ls_mode(n);
577 if (! is_ia32_Lea(n))
578 assert(mode && "AM node must have ls_mode attribute set.");
581 obst = xcalloc(1, sizeof(*obst));
584 obstack_free(obst, NULL);
587 /* obstack_free with NULL results in an uninitialized obstack */
590 p = pointer_size(mode, has_x87_register(n));
592 obstack_printf(obst, "%s ", p);
594 /* emit address mode symconst */
595 if (get_ia32_am_sc(n)) {
596 if (is_ia32_am_sc_sign(n))
597 obstack_printf(obst, "-");
598 obstack_printf(obst, "%s", get_id_str(get_ia32_am_sc(n)));
601 if (am_flav & ia32_B) {
602 obstack_printf(obst, "[");
603 lc_eoprintf(ia32_get_arg_env(), obst, "%1S", n);
607 if (am_flav & ia32_I) {
609 obstack_printf(obst, "+");
612 obstack_printf(obst, "[");
615 lc_eoprintf(ia32_get_arg_env(), obst, "%2S", n);
617 if (am_flav & ia32_S) {
618 obstack_printf(obst, "*%d", 1 << get_ia32_am_scale(n));
624 if (am_flav & ia32_O) {
625 s = get_ia32_am_offs(n);
628 /* omit explicit + if there was no base or index */
630 obstack_printf(obst, "[");
635 obstack_printf(obst, s);
641 obstack_printf(obst, "] ");
643 obstack_1grow(obst, '\0');
644 s = obstack_finish(obst);
652 const char *ia32_emit_adr(const ir_node *irn, ia32_emit_env_t *env)
654 static char buf[SNPRINTF_BUF_LEN];
655 ir_mode *mode = get_ia32_ls_mode(irn);
656 const char *adr = get_ia32_cnst(irn);
657 const char *pref = pointer_size(mode, has_x87_register(irn));
659 snprintf(buf, SNPRINTF_BUF_LEN, "%s %s", pref ? pref : "", adr);
664 * Formated print of commands and comments.
666 static void ia32_fprintf_format(FILE *F, const ir_node *irn, char *cmd_buf, char *cmnt_buf) {
668 const char *name = irn ? be_retrieve_dbg_info(get_irn_dbg_info((ir_node *)irn), &lineno) : NULL;
671 fprintf(F, "\t%-35s %-60s /* %s:%u */\n", cmd_buf, cmnt_buf, name, lineno);
673 fprintf(F, "\t%-35s %-60s\n", cmd_buf, cmnt_buf);
679 * Add a number to a prefix. This number will not be used a second time.
681 static char *get_unique_label(char *buf, size_t buflen, const char *prefix) {
682 static unsigned long id = 0;
683 snprintf(buf, buflen, "%s%lu", prefix, ++id);
689 /*************************************************
692 * ___ _ __ ___ _| |_ ___ ___ _ __ __| |
693 * / _ \ '_ ` _ \| | __| / __/ _ \| '_ \ / _` |
694 * | __/ | | | | | | |_ | (_| (_) | | | | (_| |
695 * \___|_| |_| |_|_|\__| \___\___/|_| |_|\__,_|
697 *************************************************/
700 #define IA32_DO_EMIT(irn) ia32_fprintf_format(F, irn, cmd_buf, cmnt_buf)
703 * coding of conditions
705 struct cmp2conditon_t {
711 * positive conditions for signed compares
713 static const struct cmp2conditon_t cmp2condition_s[] = {
714 { NULL, pn_Cmp_False }, /* always false */
715 { "e", pn_Cmp_Eq }, /* == */
716 { "l", pn_Cmp_Lt }, /* < */
717 { "le", pn_Cmp_Le }, /* <= */
718 { "g", pn_Cmp_Gt }, /* > */
719 { "ge", pn_Cmp_Ge }, /* >= */
720 { "ne", pn_Cmp_Lg }, /* != */
721 { "ordered", pn_Cmp_Leg }, /* Floating point: ordered */
722 { "unordered", pn_Cmp_Uo }, /* FLoting point: unordered */
723 { "e", pn_Cmp_Ue }, /* Floating point: unordered or == */
724 { "b", pn_Cmp_Ul }, /* Floating point: unordered or < */
725 { "be", pn_Cmp_Ule }, /* Floating point: unordered or <= */
726 { "a", pn_Cmp_Ug }, /* Floating point: unordered or > */
727 { "ae", pn_Cmp_Uge }, /* Floating point: unordered or >= */
728 { "ne", pn_Cmp_Ne }, /* Floating point: unordered or != */
729 { NULL, pn_Cmp_True }, /* always true */
733 * positive conditions for unsigned compares
735 static const struct cmp2conditon_t cmp2condition_u[] = {
736 { NULL, pn_Cmp_False }, /* always false */
737 { "e", pn_Cmp_Eq }, /* == */
738 { "b", pn_Cmp_Lt }, /* < */
739 { "be", pn_Cmp_Le }, /* <= */
740 { "a", pn_Cmp_Gt }, /* > */
741 { "ae", pn_Cmp_Ge }, /* >= */
742 { "ne", pn_Cmp_Lg }, /* != */
743 { "ordered", pn_Cmp_Leg }, /* Floating point: ordered */
744 { "unordered", pn_Cmp_Uo }, /* FLoting point: unordered */
745 { "e", pn_Cmp_Ue }, /* Floating point: unordered or == */
746 { "b", pn_Cmp_Ul }, /* Floating point: unordered or < */
747 { "be", pn_Cmp_Ule }, /* Floating point: unordered or <= */
748 { "a", pn_Cmp_Ug }, /* Floating point: unordered or > */
749 { "ae", pn_Cmp_Uge }, /* Floating point: unordered or >= */
750 { "ne", pn_Cmp_Ne }, /* Floating point: unordered or != */
751 { NULL, pn_Cmp_True }, /* always true */
755 * returns the condition code
757 static const char *get_cmp_suffix(int cmp_code, int unsigned_cmp)
759 assert(cmp2condition_s[cmp_code].num == cmp_code);
760 assert(cmp2condition_u[cmp_code].num == cmp_code);
762 return unsigned_cmp ? cmp2condition_u[cmp_code & 7].name : cmp2condition_s[cmp_code & 7].name;
766 * Returns the target block for a control flow node.
768 static ir_node *get_cfop_target_block(const ir_node *irn) {
769 return get_irn_link(irn);
773 * Returns the target label for a control flow node.
775 static char *get_cfop_target(const ir_node *irn, char *buf) {
776 ir_node *bl = get_cfop_target_block(irn);
778 snprintf(buf, SNPRINTF_BUF_LEN, BLOCK_PREFIX("%ld"), get_irn_node_nr(bl));
782 /** Return the next block in Block schedule */
783 static ir_node *next_blk_sched(const ir_node *block) {
784 return get_irn_link(block);
788 * Returns the Proj with projection number proj and NOT mode_M
790 static ir_node *get_proj(const ir_node *irn, long proj) {
791 const ir_edge_t *edge;
794 assert(get_irn_mode(irn) == mode_T && "expected mode_T node");
796 foreach_out_edge(irn, edge) {
797 src = get_edge_src_irn(edge);
799 assert(is_Proj(src) && "Proj expected");
800 if (get_irn_mode(src) == mode_M)
803 if (get_Proj_proj(src) == proj)
810 * Emits the jump sequence for a conditional jump (cmp + jmp_true + jmp_false)
812 static void finish_CondJmp(FILE *F, const ir_node *irn, ir_mode *mode) {
813 const ir_node *proj1, *proj2 = NULL;
814 const ir_node *block, *next_bl = NULL;
815 char buf[SNPRINTF_BUF_LEN];
816 char cmd_buf[SNPRINTF_BUF_LEN];
817 char cmnt_buf[SNPRINTF_BUF_LEN];
820 /* get both Proj's */
821 proj1 = get_proj(irn, pn_Cond_true);
822 assert(proj1 && "CondJmp without true Proj");
824 proj2 = get_proj(irn, pn_Cond_false);
825 assert(proj2 && "CondJmp without false Proj");
827 /* for now, the code works for scheduled and non-schedules blocks */
828 block = get_nodes_block(irn);
830 /* we have a block schedule */
831 next_bl = next_blk_sched(block);
833 if (get_cfop_target_block(proj1) == next_bl) {
834 /* exchange both proj's so the second one can be omitted */
835 const ir_node *t = proj1;
840 /* the first Proj must always be created */
841 is_unsigned = mode_is_float(mode) || ! mode_is_signed(mode);
842 if (get_Proj_proj(proj1) == pn_Cond_true) {
843 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "j%s %s",
844 get_cmp_suffix(get_ia32_pncode(irn), is_unsigned),
845 get_cfop_target(proj1, buf));
846 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* cmp(a, b) == TRUE */");
849 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "j%s %s",
850 get_cmp_suffix(get_negated_pnc(get_ia32_pncode(irn), mode), is_unsigned),
851 get_cfop_target(proj1, buf));
852 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* cmp(a, b) == FALSE */");
856 /* the second Proj might be a fallthrough */
857 if (get_cfop_target_block(proj2) != next_bl) {
858 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "jmp %s", get_cfop_target(proj2, buf));
859 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* otherwise */");
863 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* fallthrough %s */", get_cfop_target(proj2, buf));
869 * Emits code for conditional jump.
871 static void CondJmp_emitter(const ir_node *irn, ia32_emit_env_t *env) {
873 char cmd_buf[SNPRINTF_BUF_LEN];
874 char cmnt_buf[SNPRINTF_BUF_LEN];
876 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "cmp %s", ia32_emit_binop(irn, env));
877 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F */", irn);
879 finish_CondJmp(F, irn, get_ia32_res_mode(irn));
883 * Emits code for conditional jump with two variables.
885 static void emit_ia32_CondJmp(const ir_node *irn, ia32_emit_env_t *env) {
886 CondJmp_emitter(irn, env);
890 * Emits code for conditional test and jump.
892 static void TestJmp_emitter(const ir_node *irn, ia32_emit_env_t *env) {
894 #define IA32_IS_IMMOP (is_ia32_ImmConst(irn) || is_ia32_ImmSymConst(irn))
897 const char *op1 = arch_register_get_name(get_in_reg(irn, 0));
898 const char *op2 = IA32_IS_IMMOP ? get_ia32_cnst(irn) : NULL;
899 char cmd_buf[SNPRINTF_BUF_LEN];
900 char cmnt_buf[SNPRINTF_BUF_LEN];
903 op2 = arch_register_get_name(get_in_reg(irn, 1));
905 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "test %%%s,%s%s ", op1, IA32_IS_IMMOP ? " " : " %", op2);
906 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F */", irn);
909 finish_CondJmp(F, irn, get_ia32_res_mode(irn));
915 * Emits code for conditional test and jump with two variables.
917 static void emit_ia32_TestJmp(const ir_node *irn, ia32_emit_env_t *env) {
918 TestJmp_emitter(irn, env);
921 static void emit_ia32_CJmp(const ir_node *irn, ia32_emit_env_t *env) {
923 char cmd_buf[SNPRINTF_BUF_LEN];
924 char cmnt_buf[SNPRINTF_BUF_LEN];
926 snprintf(cmd_buf, SNPRINTF_BUF_LEN, " ");
927 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F omitted redundant test */", irn);
929 finish_CondJmp(F, irn, get_ia32_res_mode(irn));
932 static void emit_ia32_CJmpAM(const ir_node *irn, ia32_emit_env_t *env) {
934 char cmd_buf[SNPRINTF_BUF_LEN];
935 char cmnt_buf[SNPRINTF_BUF_LEN];
937 snprintf(cmd_buf, SNPRINTF_BUF_LEN, " ");
938 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F omitted redundant test/cmp */", irn);
940 finish_CondJmp(F, irn, get_ia32_res_mode(irn));
944 * Emits code for conditional SSE floating point jump with two variables.
946 static void emit_ia32_xCondJmp(ir_node *irn, ia32_emit_env_t *env) {
948 char cmd_buf[SNPRINTF_BUF_LEN];
949 char cmnt_buf[SNPRINTF_BUF_LEN];
951 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "ucomis%M %s", irn, ia32_emit_binop(irn, env));
952 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F */", irn);
954 finish_CondJmp(F, irn, mode_F);
959 * Emits code for conditional x87 floating point jump with two variables.
961 static void emit_ia32_x87CondJmp(ir_node *irn, ia32_emit_env_t *env) {
963 char cmd_buf[SNPRINTF_BUF_LEN];
964 char cmnt_buf[SNPRINTF_BUF_LEN];
965 ia32_attr_t *attr = get_ia32_attr(irn);
966 const char *reg = attr->x87[1]->name;
967 const char *instr = "fcom";
970 switch (get_ia32_pncode(irn)) {
971 case iro_ia32_fcomrJmp:
973 case iro_ia32_fcomJmp:
977 case iro_ia32_fcomrpJmp:
979 case iro_ia32_fcompJmp:
982 case iro_ia32_fcomrppJmp:
984 case iro_ia32_fcomppJmp:
991 set_ia32_pncode(irn, (long)get_negated_pnc(get_ia32_pncode(irn), mode_Is));
993 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "%s %%%s", instr, reg);
994 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F */", irn);
996 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "fnstsw %%ax", irn);
997 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* Store x87 FPU Control Word */");
999 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "sahf");
1000 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* Store ah into flags */");
1003 finish_CondJmp(F, irn, mode_Is);
1006 static void CMov_emitter(ir_node *irn, ia32_emit_env_t *env) {
1008 const lc_arg_env_t *arg_env = ia32_get_arg_env();
1009 ir_mode *mode = get_irn_mode(get_irn_n(irn, 0));
1010 int is_unsigned = mode_is_float(mode) || ! mode_is_signed(mode);
1011 const char *cmp_suffix = get_cmp_suffix(get_ia32_pncode(irn), is_unsigned);
1012 int is_PsiCondCMov = is_ia32_PsiCondCMov(irn);
1014 char cmd_buf[SNPRINTF_BUF_LEN];
1015 char cmnt_buf[SNPRINTF_BUF_LEN];
1016 const arch_register_t *in1, *in2, *out;
1018 out = arch_get_irn_register(env->arch_env, irn);
1019 in1 = arch_get_irn_register(env->arch_env, get_irn_n(irn, 2 - is_PsiCondCMov));
1020 in2 = arch_get_irn_register(env->arch_env, get_irn_n(irn, 3 - is_PsiCondCMov));
1022 /* we have to emit the cmp first, because the destination register */
1023 /* could be one of the compare registers */
1024 if (is_ia32_CmpCMov(irn)) {
1025 lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "cmp %1S, %2S", irn, irn);
1027 else if (is_ia32_xCmpCMov(irn)) {
1028 lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "ucomis%M %1S, %2S", get_irn_n(irn, 0), irn, irn);
1030 else if (is_PsiCondCMov) {
1031 /* omit compare because flags are already set by And/Or */
1032 snprintf(cmd_buf, SNPRINTF_BUF_LEN, " ");
1035 assert(0 && "unsupported CMov");
1037 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* Psi condition */" );
1040 if (REGS_ARE_EQUAL(out, in2)) {
1041 /* best case: default in == out -> do nothing */
1043 else if (REGS_ARE_EQUAL(out, in1)) {
1044 /* true in == out -> need complement compare and exchange true and default in */
1045 ir_node *t = get_irn_n(irn, 2);
1046 set_irn_n(irn, 2, get_irn_n(irn, 3));
1047 set_irn_n(irn, 3, t);
1049 cmp_suffix = get_cmp_suffix(get_inversed_pnc(get_ia32_pncode(irn)), is_unsigned);
1053 /* out is different from in: need copy default -> out */
1054 lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "mov %1D, %4S", irn, irn);
1055 lc_esnprintf(arg_env, cmnt_buf, SNPRINTF_BUF_LEN, "/* copy default -> out */" );
1059 lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "cmov%s %1D, %3S", cmp_suffix, irn, irn);
1060 lc_esnprintf(arg_env, cmnt_buf, SNPRINTF_BUF_LEN, "/* condition is true case */" );
1064 static void emit_ia32_CmpCMov(ir_node *irn, ia32_emit_env_t *env) {
1065 CMov_emitter(irn, env);
1068 static void emit_ia32_PsiCondCMov(ir_node *irn, ia32_emit_env_t *env) {
1069 CMov_emitter(irn, env);
1072 static void emit_ia32_xCmpCMov(ir_node *irn, ia32_emit_env_t *env) {
1073 CMov_emitter(irn, env);
1076 static void Set_emitter(ir_node *irn, ir_mode *mode, ia32_emit_env_t *env) {
1078 const lc_arg_env_t *arg_env = ia32_get_arg_env();
1079 int is_unsigned = mode_is_float(mode) || ! mode_is_signed(mode);
1080 const char *cmp_suffix = get_cmp_suffix(get_ia32_pncode(irn), is_unsigned);
1081 const char *reg8bit;
1083 char cmd_buf[SNPRINTF_BUF_LEN];
1084 char cmnt_buf[SNPRINTF_BUF_LEN];
1085 const arch_register_t *out;
1087 out = arch_get_irn_register(env->arch_env, irn);
1088 reg8bit = ia32_get_mapped_reg_name(env->isa->regs_8bit, out);
1090 if (is_ia32_CmpSet(irn)) {
1091 lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "cmp %s", ia32_emit_binop(irn, env));
1093 else if (is_ia32_xCmpSet(irn)) {
1094 lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "ucomis%M %s", get_irn_n(irn, 2), ia32_emit_binop(irn, env));
1096 else if (is_ia32_PsiCondSet(irn)) {
1097 /* omit compare because flags are already set by And/Or */
1098 snprintf(cmd_buf, SNPRINTF_BUF_LEN, " ");
1101 assert(0 && "unsupported Set");
1103 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* calculate Psi condition */" );
1106 /* use mov to clear target because it doesn't affect the eflags */
1107 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "mov %%%s, 0", arch_register_get_name(out));
1108 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* clear target as set modifies only lower 8 bit */");
1111 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "set%s %%%s", cmp_suffix, reg8bit);
1112 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* set 1 iff true, 0 otherweise */" );
1116 static void emit_ia32_CmpSet(ir_node *irn, ia32_emit_env_t *env) {
1117 Set_emitter(irn, get_irn_mode(get_irn_n(irn, 2)), env);
1120 static void emit_ia32_PsiCondSet(ir_node *irn, ia32_emit_env_t *env) {
1121 Set_emitter(irn, get_irn_mode(get_irn_n(irn, 0)), env);
1124 static void emit_ia32_xCmpSet(ir_node *irn, ia32_emit_env_t *env) {
1125 Set_emitter(irn, get_irn_mode(get_irn_n(irn, 2)), env);
1128 static void emit_ia32_xCmp(ir_node *irn, ia32_emit_env_t *env) {
1130 const lc_arg_env_t *arg_env = ia32_get_arg_env();
1132 char cmd_buf[SNPRINTF_BUF_LEN];
1133 char cmnt_buf[SNPRINTF_BUF_LEN];
1135 switch (get_ia32_pncode(irn)) {
1136 case pn_Cmp_Leg: /* odered */
1139 case pn_Cmp_Uo: /* unordered */
1142 case pn_Cmp_Ue: /* == */
1145 case pn_Cmp_Ul: /* < */
1148 case pn_Cmp_Ule: /* <= */
1151 case pn_Cmp_Ug: /* > */
1154 case pn_Cmp_Uge: /* >= */
1157 case pn_Cmp_Ne: /* != */
1162 assert(sse_pnc >= 0 && "unsupported floating point compare");
1164 lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "cmps%M %s, %d", irn, ia32_emit_binop(irn, env), sse_pnc);
1165 lc_esnprintf(arg_env, cmnt_buf, SNPRINTF_BUF_LEN, "/* SSE compare with result in %1D */", irn);
1169 /*********************************************************
1172 * ___ _ __ ___ _| |_ _ _ _ _ __ ___ _ __ ___
1173 * / _ \ '_ ` _ \| | __| | | | | | '_ ` _ \| '_ \/ __|
1174 * | __/ | | | | | | |_ | | |_| | | | | | | |_) \__ \
1175 * \___|_| |_| |_|_|\__| | |\__,_|_| |_| |_| .__/|___/
1178 *********************************************************/
1180 /* jump table entry (target and corresponding number) */
1181 typedef struct _branch_t {
1186 /* jump table for switch generation */
1187 typedef struct _jmp_tbl_t {
1188 ir_node *defProj; /**< default target */
1189 int min_value; /**< smallest switch case */
1190 int max_value; /**< largest switch case */
1191 int num_branches; /**< number of jumps */
1192 char *label; /**< label of the jump table */
1193 branch_t *branches; /**< jump array */
1197 * Compare two variables of type branch_t. Used to sort all switch cases
1199 static int ia32_cmp_branch_t(const void *a, const void *b) {
1200 branch_t *b1 = (branch_t *)a;
1201 branch_t *b2 = (branch_t *)b;
1203 if (b1->value <= b2->value)
1210 * Emits code for a SwitchJmp (creates a jump table if
1211 * possible otherwise a cmp-jmp cascade). Port from
1214 static void emit_ia32_SwitchJmp(const ir_node *irn, ia32_emit_env_t *emit_env) {
1215 unsigned long interval;
1216 char buf[SNPRINTF_BUF_LEN];
1217 int last_value, i, pn;
1220 const ir_edge_t *edge;
1221 const lc_arg_env_t *env = ia32_get_arg_env();
1222 FILE *F = emit_env->out;
1223 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1225 /* fill the table structure */
1226 tbl.label = xmalloc(SNPRINTF_BUF_LEN);
1227 tbl.label = get_unique_label(tbl.label, SNPRINTF_BUF_LEN, ".TBL_");
1229 tbl.num_branches = get_irn_n_edges(irn);
1230 tbl.branches = xcalloc(tbl.num_branches, sizeof(tbl.branches[0]));
1231 tbl.min_value = INT_MAX;
1232 tbl.max_value = INT_MIN;
1235 /* go over all proj's and collect them */
1236 foreach_out_edge(irn, edge) {
1237 proj = get_edge_src_irn(edge);
1238 assert(is_Proj(proj) && "Only proj allowed at SwitchJmp");
1240 pn = get_Proj_proj(proj);
1242 /* create branch entry */
1243 tbl.branches[i].target = proj;
1244 tbl.branches[i].value = pn;
1246 tbl.min_value = pn < tbl.min_value ? pn : tbl.min_value;
1247 tbl.max_value = pn > tbl.max_value ? pn : tbl.max_value;
1249 /* check for default proj */
1250 if (pn == get_ia32_pncode(irn)) {
1251 assert(tbl.defProj == NULL && "found two defProjs at SwitchJmp");
1258 /* sort the branches by their number */
1259 qsort(tbl.branches, tbl.num_branches, sizeof(tbl.branches[0]), ia32_cmp_branch_t);
1261 /* two-complement's magic make this work without overflow */
1262 interval = tbl.max_value - tbl.min_value;
1264 /* emit the table */
1265 lc_esnprintf(env, cmd_buf, SNPRINTF_BUF_LEN, "cmp %1S, %u", irn, interval);
1266 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* compare for switch */");
1269 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "ja %s", get_cfop_target(tbl.defProj, buf));
1270 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* default jump if out of range */");
1273 if (tbl.num_branches > 1) {
1276 lc_esnprintf(env, cmd_buf, SNPRINTF_BUF_LEN, "jmp %s[%1S*4]", tbl.label, irn);
1277 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* get jump table entry as target */");
1280 ia32_switch_section(F, SECTION_RODATA);
1281 fprintf(F, "\t.align 4\n");
1283 fprintf(F, "%s:\n", tbl.label);
1285 snprintf(cmd_buf, SNPRINTF_BUF_LEN, ".long %s", get_cfop_target(tbl.branches[0].target, buf));
1286 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* case %d */", tbl.branches[0].value);
1289 last_value = tbl.branches[0].value;
1290 for (i = 1; i < tbl.num_branches; ++i) {
1291 while (++last_value < tbl.branches[i].value) {
1292 snprintf(cmd_buf, SNPRINTF_BUF_LEN, ".long %s", get_cfop_target(tbl.defProj, buf));
1293 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* default case */");
1296 snprintf(cmd_buf, SNPRINTF_BUF_LEN, ".long %s", get_cfop_target(tbl.branches[i].target, buf));
1297 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* case %d */", last_value);
1300 ia32_switch_section(F, SECTION_TEXT);
1303 /* one jump is enough */
1304 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "jmp %s", get_cfop_target(tbl.branches[0].target, buf));
1305 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* only one case given */");
1316 * Emits code for a unconditional jump.
1318 static void emit_Jmp(const ir_node *irn, ia32_emit_env_t *env) {
1319 ir_node *block, *next_bl;
1321 char buf[SNPRINTF_BUF_LEN], cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1323 /* for now, the code works for scheduled and non-schedules blocks */
1324 block = get_nodes_block(irn);
1326 /* we have a block schedule */
1327 next_bl = next_blk_sched(block);
1328 if (get_cfop_target_block(irn) != next_bl) {
1329 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "jmp %s", get_cfop_target(irn, buf));
1330 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F(%+F) */", irn, get_cfop_target_block(irn));
1334 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* fallthrough %s */", get_cfop_target(irn, buf));
1339 /****************************
1342 * _ __ _ __ ___ _ ___
1343 * | '_ \| '__/ _ \| |/ __|
1344 * | |_) | | | (_) | |\__ \
1345 * | .__/|_| \___/| ||___/
1348 ****************************/
1351 * Emits code for a proj -> node
1353 static void emit_Proj(const ir_node *irn, ia32_emit_env_t *env) {
1354 ir_node *pred = get_Proj_pred(irn);
1356 if (get_irn_op(pred) == op_Start) {
1357 switch(get_Proj_proj(irn)) {
1358 case pn_Start_X_initial_exec:
1367 /**********************************
1370 * | | ___ _ __ _ _| |_) |
1371 * | | / _ \| '_ \| | | | _ <
1372 * | |___| (_) | |_) | |_| | |_) |
1373 * \_____\___/| .__/ \__, |____/
1376 **********************************/
1379 * Emit movsb/w instructions to make mov count divideable by 4
1381 static void emit_CopyB_prolog(FILE *F, const ir_node *irn, int rem) {
1382 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1384 ir_fprintf(F, "\t/* memcopy prolog %+F */\n", irn);
1386 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "cld");
1387 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* copy direction forward */");
1392 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "movsb");
1393 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* memcopy remainder 1 */");
1397 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "movsw");
1398 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* memcopy remainder 2 */");
1402 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "movsb");
1403 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* memcopy remainder 3 */");
1405 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "movsw");
1406 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* memcopy remainder 3 */");
1414 * Emit rep movsd instruction for memcopy.
1416 static void emit_ia32_CopyB(const ir_node *irn, ia32_emit_env_t *emit_env) {
1417 FILE *F = emit_env->out;
1418 tarval *tv = get_ia32_Immop_tarval(irn);
1419 int rem = get_tarval_long(tv);
1420 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1422 emit_CopyB_prolog(F, irn, rem);
1424 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "rep movsd");
1425 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* memcopy */");
1430 * Emits unrolled memcopy.
1432 static void emit_ia32_CopyB_i(const ir_node *irn, ia32_emit_env_t *emit_env) {
1433 tarval *tv = get_ia32_Immop_tarval(irn);
1434 int size = get_tarval_long(tv);
1435 FILE *F = emit_env->out;
1436 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1438 emit_CopyB_prolog(F, irn, size & 0x3);
1442 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "movsd");
1443 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* memcopy unrolled */");
1450 /***************************
1454 * | | / _ \| '_ \ \ / /
1455 * | |___| (_) | | | \ V /
1456 * \_____\___/|_| |_|\_/
1458 ***************************/
1461 * Emit code for conversions (I, FP), (FP, I) and (FP, FP).
1463 static void emit_ia32_Conv_with_FP(const ir_node *irn, ia32_emit_env_t *emit_env) {
1464 FILE *F = emit_env->out;
1465 const lc_arg_env_t *env = ia32_get_arg_env();
1466 ir_mode *src_mode = get_ia32_src_mode(irn);
1467 ir_mode *tgt_mode = get_ia32_tgt_mode(irn);
1468 char *from, *to, buf[64];
1469 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1471 from = mode_is_float(src_mode) ? (get_mode_size_bits(src_mode) == 32 ? "ss" : "sd") : "si";
1472 to = mode_is_float(tgt_mode) ? (get_mode_size_bits(tgt_mode) == 32 ? "ss" : "sd") : "si";
1474 switch(get_ia32_op_type(irn)) {
1476 lc_esnprintf(env, buf, sizeof(buf), "%1D, %3S", irn, irn);
1478 case ia32_AddrModeS:
1479 lc_esnprintf(env, buf, sizeof(buf), "%1D, %s", irn, ia32_emit_am(irn, emit_env));
1482 assert(0 && "unsupported op type for Conv");
1485 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "cvt%s2%s %s", from, to, buf);
1486 lc_esnprintf(env, cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F(%+F, %+F) */", irn, src_mode, tgt_mode);
1490 static void emit_ia32_Conv_I2FP(const ir_node *irn, ia32_emit_env_t *emit_env) {
1491 emit_ia32_Conv_with_FP(irn, emit_env);
1494 static void emit_ia32_Conv_FP2I(const ir_node *irn, ia32_emit_env_t *emit_env) {
1495 emit_ia32_Conv_with_FP(irn, emit_env);
1498 static void emit_ia32_Conv_FP2FP(const ir_node *irn, ia32_emit_env_t *emit_env) {
1499 emit_ia32_Conv_with_FP(irn, emit_env);
1503 * Emits code for an Int conversion.
1505 static void emit_ia32_Conv_I2I(const ir_node *irn, ia32_emit_env_t *emit_env) {
1506 FILE *F = emit_env->out;
1507 const lc_arg_env_t *env = ia32_get_arg_env();
1508 char *move_cmd = "movzx";
1509 char *conv_cmd = NULL;
1510 ir_mode *src_mode = get_ia32_src_mode(irn);
1511 ir_mode *tgt_mode = get_ia32_tgt_mode(irn);
1513 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1514 const arch_register_t *in_reg, *out_reg;
1516 n = get_mode_size_bits(src_mode);
1517 m = get_mode_size_bits(tgt_mode);
1519 if (mode_is_signed(n < m ? src_mode : tgt_mode)) {
1521 if (n == 8 || m == 8)
1523 else if (n == 16 || m == 16)
1526 assert(0 && "unsupported Conv_I2I");
1529 switch(get_ia32_op_type(irn)) {
1531 in_reg = get_in_reg(irn, 2);
1532 out_reg = get_out_reg(irn, 0);
1534 if (REGS_ARE_EQUAL(in_reg, &ia32_gp_regs[REG_EAX]) &&
1535 REGS_ARE_EQUAL(out_reg, in_reg) &&
1536 mode_is_signed(n < m ? src_mode : tgt_mode))
1538 /* argument and result are both in EAX and */
1539 /* signedness is ok: -> use converts */
1540 lc_esnprintf(env, cmd_buf, SNPRINTF_BUF_LEN, "%s", conv_cmd);
1542 else if (REGS_ARE_EQUAL(out_reg, in_reg) &&
1543 ! mode_is_signed(n < m ? src_mode : tgt_mode))
1545 /* argument and result are in the same register */
1546 /* and signedness is ok: -> use and with mask */
1547 int mask = (1 << (n < m ? n : m)) - 1;
1548 lc_esnprintf(env, cmd_buf, SNPRINTF_BUF_LEN, "and %1D, 0x%x", irn, mask);
1551 /* use move w/o sign extension */
1552 lc_esnprintf(env, cmd_buf, SNPRINTF_BUF_LEN, "%s %1D, %%%s",
1553 move_cmd, irn, ia32_get_reg_name_for_mode(emit_env, n < m ? src_mode : tgt_mode, in_reg));
1557 case ia32_AddrModeS:
1558 lc_esnprintf(env, cmd_buf, SNPRINTF_BUF_LEN, "%s %1D, %s",
1559 move_cmd, irn, ia32_emit_am(irn, emit_env));
1562 assert(0 && "unsupported op type for Conv");
1565 lc_esnprintf(env, cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F(%d Bit mode_%F -> %d Bit mode_%F) */",
1566 irn, n, src_mode, m, tgt_mode);
1572 * Emits code for an 8Bit Int conversion.
1574 void emit_ia32_Conv_I2I8Bit(const ir_node *irn, ia32_emit_env_t *emit_env) {
1575 emit_ia32_Conv_I2I(irn, emit_env);
1579 /*******************************************
1582 * | |__ ___ _ __ ___ __| | ___ ___
1583 * | '_ \ / _ \ '_ \ / _ \ / _` |/ _ \/ __|
1584 * | |_) | __/ | | | (_) | (_| | __/\__ \
1585 * |_.__/ \___|_| |_|\___/ \__,_|\___||___/
1587 *******************************************/
1590 * Emits a backend call
1592 static void emit_be_Call(const ir_node *irn, ia32_emit_env_t *emit_env) {
1593 FILE *F = emit_env->out;
1594 entity *ent = be_Call_get_entity(irn);
1595 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1598 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "call %s", get_entity_ld_name(ent));
1601 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "call %1D", get_irn_n(irn, be_pos_Call_ptr));
1604 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F (be_Call) */", irn);
1610 * Emits code to increase stack pointer.
1612 static void emit_be_IncSP(const ir_node *irn, ia32_emit_env_t *emit_env) {
1613 FILE *F = emit_env->out;
1614 unsigned offs = be_get_IncSP_offset(irn);
1615 be_stack_dir_t dir = be_get_IncSP_direction(irn);
1616 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1619 if (dir == be_stack_dir_expand)
1620 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "sub %1S, %u", irn, offs);
1622 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "add %1S, %u", irn, offs);
1623 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F (IncSP) */", irn);
1626 snprintf(cmd_buf, SNPRINTF_BUF_LEN, " ");
1627 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* omitted %+F (IncSP) with 0 */", irn);
1634 * Emits code to set stack pointer.
1636 static void emit_be_SetSP(const ir_node *irn, ia32_emit_env_t *emit_env) {
1637 FILE *F = emit_env->out;
1638 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1640 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "mov %1D, %3S", irn, irn);
1641 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F (restore SP) */", irn);
1646 * Emits code for Copy/CopyKeep.
1648 static void Copy_emitter(const ir_node *irn, ir_node *op, ia32_emit_env_t *emit_env) {
1649 FILE *F = emit_env->out;
1650 const arch_env_t *aenv = emit_env->arch_env;
1651 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1653 if (REGS_ARE_EQUAL(arch_get_irn_register(aenv, irn), arch_get_irn_register(aenv, op)) ||
1654 be_is_unknown_reg(arch_get_irn_register(aenv, op)))
1657 if (mode_is_float(get_irn_mode(irn)))
1658 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "movs%M %1D, %1S", irn, irn, irn);
1660 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "mov %1D, %1S", irn, irn);
1661 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F */", irn);
1665 static void emit_be_Copy(const ir_node *irn, ia32_emit_env_t *emit_env) {
1666 Copy_emitter(irn, be_get_Copy_op(irn), emit_env);
1669 static void emit_be_CopyKeep(const ir_node *irn, ia32_emit_env_t *emit_env) {
1670 Copy_emitter(irn, be_get_CopyKeep_op(irn), emit_env);
1674 * Emits code for exchange.
1676 static void emit_be_Perm(const ir_node *irn, ia32_emit_env_t *emit_env) {
1677 FILE *F = emit_env->out;
1678 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1679 const arch_register_t *in1, *in2;
1680 const arch_register_class_t *cls1, *cls2;
1682 in1 = arch_get_irn_register(emit_env->arch_env, get_irn_n(irn, 0));
1683 in2 = arch_get_irn_register(emit_env->arch_env, get_irn_n(irn, 1));
1685 cls1 = arch_register_get_class(in1);
1686 cls2 = arch_register_get_class(in2);
1688 assert(cls1 == cls2 && "Register class mismatch at Perm");
1690 if (cls1 == &ia32_reg_classes[CLASS_ia32_gp]) {
1691 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "xchg %1S, %2S", irn, irn);
1693 else if (cls1 == &ia32_reg_classes[CLASS_ia32_xmm]) {
1694 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN,
1695 "pxor %1S, %2S\n\tpxor %2S, %1S\n\tpxor %1S, %2S", irn, irn, irn, irn, irn, irn);
1697 else if (cls1 == &ia32_reg_classes[CLASS_ia32_vfp]) {
1698 assert(0 && "Perm with vfp should not happen");
1700 else if (cls1 == &ia32_reg_classes[CLASS_ia32_st]) {
1701 assert(0 && "Perm with st(X) should not happen");
1704 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F(%1A, %2A) */", irn, irn, irn);
1709 * Emits code for Constant loading.
1711 static void emit_ia32_Const(const ir_node *n, ia32_emit_env_t *env) {
1713 char cmd_buf[256], cmnt_buf[256];
1714 const lc_arg_env_t *arg_env = ia32_get_arg_env();
1716 if (get_ia32_Immop_tarval(n) == get_tarval_null(get_irn_mode(n))) {
1717 const char *instr = "xor";
1718 if (env->isa->opt_arch == arch_pentium_4) {
1719 /* P4 prefers sub r, r, others xor r, r */
1722 lc_esnprintf(arg_env, cmd_buf, 256, "%s %1D, %1D ", instr, n, n);
1723 lc_esnprintf(arg_env, cmnt_buf, 256, "/* optimized mov 0 to register */");
1726 if (get_ia32_op_type(n) == ia32_SymConst) {
1727 lc_esnprintf(arg_env, cmd_buf, 256, "mov %1D, OFFSET FLAT:%C ", n, n);
1728 lc_esnprintf(arg_env, cmnt_buf, 256, "/* Move address of SymConst into register */");
1731 lc_esnprintf(arg_env, cmd_buf, 256, "mov %1D, %C ", n, n);
1732 lc_esnprintf(arg_env, cmnt_buf, 256, "/* Mov Const into register */");
1735 lc_efprintf(arg_env, F, "\t%-35s %-60s /* %+F (%+G) */\n", cmd_buf, cmnt_buf, n, n);
1738 static void emit_be_Return(const ir_node *n, ia32_emit_env_t *env) {
1740 const lc_arg_env_t *arg_env = ia32_get_arg_env();
1742 lc_efprintf(arg_env, F, "\t%-35s %-60s /* %+F (%+G) */\n", "ret", "/* be_Return */", n, n);
1747 /***********************************************************************************
1750 * _ __ ___ __ _ _ _ __ | |_ _ __ __ _ _ __ ___ _____ _____ _ __| | __
1751 * | '_ ` _ \ / _` | | '_ \ | _| '__/ _` | '_ ` _ \ / _ \ \ /\ / / _ \| '__| |/ /
1752 * | | | | | | (_| | | | | | | | | | | (_| | | | | | | __/\ V V / (_) | | | <
1753 * |_| |_| |_|\__,_|_|_| |_| |_| |_| \__,_|_| |_| |_|\___| \_/\_/ \___/|_| |_|\_\
1755 ***********************************************************************************/
1758 * Enters the emitter functions for handled nodes into the generic
1759 * pointer of an opcode.
1761 static void ia32_register_emitters(void) {
1763 #define IA32_EMIT2(a,b) op_ia32_##a->ops.generic = (op_func)emit_ia32_##b
1764 #define IA32_EMIT(a) IA32_EMIT2(a,a)
1765 #define EMIT(a) op_##a->ops.generic = (op_func)emit_##a
1766 #define BE_EMIT(a) op_be_##a->ops.generic = (op_func)emit_be_##a
1768 /* first clear the generic function pointer for all ops */
1769 clear_irp_opcodes_generic_func();
1771 /* register all emitter functions defined in spec */
1772 ia32_register_spec_emitters();
1774 /* other ia32 emitter functions */
1780 IA32_EMIT(PsiCondCMov);
1782 IA32_EMIT(PsiCondSet);
1783 IA32_EMIT(SwitchJmp);
1786 IA32_EMIT(Conv_I2FP);
1787 IA32_EMIT(Conv_FP2I);
1788 IA32_EMIT(Conv_FP2FP);
1789 IA32_EMIT(Conv_I2I);
1790 IA32_EMIT(Conv_I2I8Bit);
1794 IA32_EMIT(xCmpCMov);
1795 IA32_EMIT(xCondJmp);
1796 IA32_EMIT2(fcomJmp, x87CondJmp);
1797 IA32_EMIT2(fcompJmp, x87CondJmp);
1798 IA32_EMIT2(fcomppJmp, x87CondJmp);
1799 IA32_EMIT2(fcomrJmp, x87CondJmp);
1800 IA32_EMIT2(fcomrpJmp, x87CondJmp);
1801 IA32_EMIT2(fcomrppJmp, x87CondJmp);
1803 /* benode emitter */
1823 * Emits code for a node.
1825 static void ia32_emit_node(const ir_node *irn, void *env) {
1826 ia32_emit_env_t *emit_env = env;
1827 FILE *F = emit_env->out;
1828 ir_op *op = get_irn_op(irn);
1829 DEBUG_ONLY(firm_dbg_module_t *mod = emit_env->mod;)
1831 DBG((mod, LEVEL_1, "emitting code for %+F\n", irn));
1833 if (op->ops.generic) {
1834 void (*emit)(const ir_node *, void *) = (void (*)(const ir_node *, void *))op->ops.generic;
1838 ir_fprintf(F, "\t%35s /* %+F (%+G) */\n", " ", irn, irn);
1843 * Emits gas alignment directives
1845 static void ia32_emit_alignment(FILE *F, unsigned align, unsigned skip) {
1846 fprintf(F, "\t.p2align %u,,%u\n", align, skip);
1850 * Emits gas alignment directives for Functions depended on cpu architecture.
1852 static void ia32_emit_align_func(FILE *F, cpu_support cpu) {
1853 unsigned align; unsigned maximum_skip;
1855 /* gcc doesn't emit alignment for p4 ?*/
1856 if (cpu == arch_pentium_4)
1861 align = 2; maximum_skip = 3;
1864 align = 4; maximum_skip = 15;
1867 align = 5; maximum_skip = 31;
1870 align = 4; maximum_skip = 15;
1872 ia32_emit_alignment(F, align, maximum_skip);
1876 * Emits gas alignment directives for Labels depended on cpu architecture.
1878 static void ia32_emit_align_label(FILE *F, cpu_support cpu) {
1879 unsigned align; unsigned maximum_skip;
1881 /* gcc doesn't emit alignment for p4 ?*/
1882 if (cpu == arch_pentium_4)
1887 align = 2; maximum_skip = 3;
1890 align = 4; maximum_skip = 15;
1893 align = 5; maximum_skip = 7;
1896 align = 4; maximum_skip = 7;
1898 ia32_emit_alignment(F, align, maximum_skip);
1902 * Walks over the nodes in a block connected by scheduling edges
1903 * and emits code for each node.
1905 static void ia32_gen_block(ir_node *block, void *env) {
1906 ia32_emit_env_t *emit_env = env;
1908 int need_label = block != get_irg_start_block(get_irn_irg(block));
1910 if (! is_Block(block))
1913 if (need_label && (emit_env->cg->opt & IA32_OPT_EXTBB)) {
1914 /* if the extended block scheduler is used, only leader blocks need
1916 need_label = (block == get_extbb_leader(get_nodes_extbb(block)));
1920 ia32_emit_align_label(emit_env->out, emit_env->isa->opt_arch);
1921 fprintf(emit_env->out, BLOCK_PREFIX("%ld:\n"), get_irn_node_nr(block));
1924 sched_foreach(block, irn) {
1925 ia32_emit_node(irn, env);
1930 * Emits code for function start.
1932 static void ia32_emit_func_prolog(FILE *F, ir_graph *irg, cpu_support cpu) {
1933 entity *irg_ent = get_irg_entity(irg);
1934 const char *irg_name = get_entity_ld_name(irg_ent);
1937 ia32_switch_section(F, SECTION_TEXT);
1938 ia32_emit_align_func(F, cpu);
1939 if (get_entity_visibility(irg_ent) == visibility_external_visible) {
1940 fprintf(F, ".globl %s\n", irg_name);
1942 ia32_dump_function_object(F, irg_name);
1943 fprintf(F, "%s:\n", irg_name);
1947 * Emits code for function end
1949 static void ia32_emit_func_epilog(FILE *F, ir_graph *irg) {
1950 const char *irg_name = get_entity_ld_name(get_irg_entity(irg));
1952 ia32_dump_function_size(F, irg_name);
1958 * Sets labels for control flow nodes (jump target)
1959 * TODO: Jump optimization
1961 static void ia32_gen_labels(ir_node *block, void *env) {
1963 int n = get_Block_n_cfgpreds(block);
1965 for (n--; n >= 0; n--) {
1966 pred = get_Block_cfgpred(block, n);
1967 set_irn_link(pred, block);
1972 * Main driver. Emits the code for one routine.
1974 void ia32_gen_routine(FILE *F, ir_graph *irg, const ia32_code_gen_t *cg) {
1975 ia32_emit_env_t emit_env;
1979 emit_env.arch_env = cg->arch_env;
1981 emit_env.isa = (ia32_isa_t *)cg->arch_env->isa;
1982 FIRM_DBG_REGISTER(emit_env.mod, "firm.be.ia32.emitter");
1984 /* set the global arch_env (needed by print hooks) */
1985 arch_env = cg->arch_env;
1987 ia32_register_emitters();
1989 ia32_emit_func_prolog(F, irg, emit_env.isa->opt_arch);
1990 irg_block_walk_graph(irg, ia32_gen_labels, NULL, &emit_env);
1992 if ((cg->opt & IA32_OPT_EXTBB) && cg->blk_sched) {
1993 int i, n = ARR_LEN(cg->blk_sched);
1995 for (i = 0; i < n;) {
1998 block = cg->blk_sched[i];
2000 next_bl = i < n ? cg->blk_sched[i] : NULL;
2002 /* set here the link. the emitter expects to find the next block here */
2003 set_irn_link(block, next_bl);
2004 ia32_gen_block(block, &emit_env);
2008 /* "normal" block schedule: Note the get_next_block() returns the NUMBER of the block
2009 in the block schedule. As this number should NEVER be equal the next block,
2010 we does not need a clear block link here. */
2011 irg_walk_blkwise_graph(irg, NULL, ia32_gen_block, &emit_env);
2014 ia32_emit_func_epilog(F, irg);