2 * Copyright (C) 1995-2011 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This file implements the ia32 node emitter.
23 * @author Christian Wuerdig, Matthias Braun
25 * Summary table for x86 floatingpoint compares:
26 * (remember effect of unordered on x86: ZF=1, PF=1, CF=1)
34 * pnc_Leg => NP (ordered)
56 #include "iredges_t.h"
60 #include "raw_bitset.h"
69 #include "beemitter.h"
73 #include "ia32_emitter.h"
74 #include "ia32_common_transform.h"
75 #include "gen_ia32_emitter.h"
76 #include "gen_ia32_regalloc_if.h"
77 #include "ia32_nodes_attr.h"
78 #include "ia32_new_nodes.h"
79 #include "ia32_architecture.h"
80 #include "bearch_ia32_t.h"
82 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
84 static const ia32_isa_t *isa;
85 static char pic_base_label[128];
86 static ir_label_t exc_label_id;
87 static int mark_spill_reload = 0;
90 static bool sp_relative;
91 static int frame_type_size;
92 static int callframe_offset;
94 /** Return the next block in Block schedule */
95 static ir_node *get_prev_block_sched(const ir_node *block)
97 return (ir_node*)get_irn_link(block);
100 /** Checks if the current block is a fall-through target. */
101 static int is_fallthrough(const ir_node *cfgpred)
105 if (!is_Proj(cfgpred))
107 pred = get_Proj_pred(cfgpred);
108 if (is_ia32_SwitchJmp(pred))
115 * returns non-zero if the given block needs a label
116 * because of being a jump-target (and not a fall-through)
118 static int block_needs_label(const ir_node *block)
121 int n_cfgpreds = get_Block_n_cfgpreds(block);
123 if (get_Block_entity(block) != NULL)
126 if (n_cfgpreds == 0) {
128 } else if (n_cfgpreds == 1) {
129 ir_node *cfgpred = get_Block_cfgpred(block, 0);
130 ir_node *cfgpred_block = get_nodes_block(cfgpred);
132 if (get_prev_block_sched(block) == cfgpred_block
133 && is_fallthrough(cfgpred)) {
142 * Add a number to a prefix. This number will not be used a second time.
144 static char *get_unique_label(char *buf, size_t buflen, const char *prefix)
146 static unsigned long id = 0;
147 snprintf(buf, buflen, "%s%s%lu", be_gas_get_private_prefix(), prefix, ++id);
152 * Emit the name of the 8bit low register
154 static void emit_8bit_register(const arch_register_t *reg)
156 assert(reg->index == REG_GP_EAX || reg->index == REG_GP_EBX
157 || reg->index == REG_GP_ECX || reg->index == REG_GP_EDX);
160 be_emit_char(reg->name[1]); /* get the basic name of the register */
165 * Emit the name of the 8bit high register
167 static void emit_8bit_register_high(const arch_register_t *reg)
169 assert(reg->index == REG_GP_EAX || reg->index == REG_GP_EBX
170 || reg->index == REG_GP_ECX || reg->index == REG_GP_EDX);
173 be_emit_char(reg->name[1]); /* get the basic name of the register */
177 static void emit_16bit_register(const arch_register_t *reg)
180 be_emit_string(reg->name + 1); /* skip the 'e' prefix of the 32bit names */
184 * emit a register, possible shortened by a mode
186 * @param reg the register
187 * @param mode the mode of the register or NULL for full register
189 static void emit_register(const arch_register_t *reg, const ir_mode *mode)
192 int size = get_mode_size_bits(mode);
194 case 8: emit_8bit_register(reg); return;
195 case 16: emit_16bit_register(reg); return;
197 assert(mode_is_float(mode) || size == 32);
201 be_emit_string(reg->name);
204 static void ia32_emit_entity(ir_entity *entity, int no_pic_adjust)
206 be_gas_emit_entity(entity);
208 if (get_entity_owner(entity) == get_tls_type()) {
209 if (!entity_has_definition(entity)) {
210 be_emit_cstring("@INDNTPOFF");
212 be_emit_cstring("@NTPOFF");
216 if (do_pic && !no_pic_adjust) {
218 be_emit_string(pic_base_label);
222 static void emit_ia32_Immediate_no_prefix(const ir_node *node)
224 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(node);
226 if (attr->symconst != NULL) {
229 ia32_emit_entity(attr->symconst, attr->no_pic_adjust);
231 if (attr->symconst == NULL || attr->offset != 0) {
232 if (attr->symconst != NULL) {
233 be_emit_irprintf("%+d", attr->offset);
235 be_emit_irprintf("0x%X", attr->offset);
240 static void emit_ia32_Immediate(const ir_node *node)
243 emit_ia32_Immediate_no_prefix(node);
246 static void ia32_emit_mode_suffix_mode(const ir_mode *mode)
248 assert(mode_is_int(mode) || mode_is_reference(mode));
249 switch (get_mode_size_bits(mode)) {
250 case 8: be_emit_char('b'); return;
251 case 16: be_emit_char('w'); return;
252 case 32: be_emit_char('l'); return;
253 /* gas docu says q is the suffix but gcc, objdump and icc use ll
255 case 64: be_emit_cstring("ll"); return;
257 panic("Can't output mode_suffix for %+F", mode);
260 static void ia32_emit_x87_mode_suffix(ir_node const *const node)
264 /* we only need to emit the mode on address mode */
265 if (get_ia32_op_type(node) == ia32_Normal)
268 mode = get_ia32_ls_mode(node);
269 assert(mode != NULL);
271 if (mode_is_float(mode)) {
272 switch (get_mode_size_bits(mode)) {
273 case 32: be_emit_char('s'); return;
274 case 64: be_emit_char('l'); return;
275 /* long doubles have different sizes due to alignment on different
279 case 128: be_emit_char('t'); return;
282 assert(mode_is_int(mode) || mode_is_reference(mode));
283 switch (get_mode_size_bits(mode)) {
284 case 16: be_emit_char('s'); return;
285 case 32: be_emit_char('l'); return;
286 /* gas docu says q is the suffix but gcc, objdump and icc use ll
288 case 64: be_emit_cstring("ll"); return;
291 panic("Can't output mode_suffix for %+F", mode);
294 static char get_xmm_mode_suffix(ir_mode *mode)
296 assert(mode_is_float(mode));
297 switch (get_mode_size_bits(mode)) {
300 default: panic("Invalid XMM mode");
304 static void ia32_emit_xmm_mode_suffix(ir_node const *const node)
306 ir_mode *mode = get_ia32_ls_mode(node);
307 assert(mode != NULL);
308 be_emit_char(get_xmm_mode_suffix(mode));
312 * Returns the target block for a control flow node.
314 static ir_node *get_cfop_target_block(const ir_node *irn)
316 assert(get_irn_mode(irn) == mode_X);
317 return (ir_node*)get_irn_link(irn);
321 * Emits the target label for a control flow node.
323 static void ia32_emit_cfop_target(const ir_node *node)
325 ir_node *block = get_cfop_target_block(node);
326 be_gas_emit_block_name(block);
330 * Emit the suffix for a compare instruction.
332 static void ia32_emit_condition_code(ia32_condition_code_t cc)
335 case ia32_cc_overflow: be_emit_cstring("o"); return;
336 case ia32_cc_not_overflow: be_emit_cstring("no"); return;
337 case ia32_cc_float_below:
338 case ia32_cc_float_unordered_below:
339 case ia32_cc_below: be_emit_cstring("b"); return;
340 case ia32_cc_float_above_equal:
341 case ia32_cc_float_unordered_above_equal:
342 case ia32_cc_above_equal: be_emit_cstring("ae"); return;
343 case ia32_cc_float_equal:
344 case ia32_cc_equal: be_emit_cstring("e"); return;
345 case ia32_cc_float_not_equal:
346 case ia32_cc_not_equal: be_emit_cstring("ne"); return;
347 case ia32_cc_float_below_equal:
348 case ia32_cc_float_unordered_below_equal:
349 case ia32_cc_below_equal: be_emit_cstring("be"); return;
350 case ia32_cc_float_above:
351 case ia32_cc_float_unordered_above:
352 case ia32_cc_above: be_emit_cstring("a"); return;
353 case ia32_cc_sign: be_emit_cstring("s"); return;
354 case ia32_cc_not_sign: be_emit_cstring("ns"); return;
355 case ia32_cc_parity: be_emit_cstring("p"); return;
356 case ia32_cc_not_parity: be_emit_cstring("np"); return;
357 case ia32_cc_less: be_emit_cstring("l"); return;
358 case ia32_cc_greater_equal: be_emit_cstring("ge"); return;
359 case ia32_cc_less_equal: be_emit_cstring("le"); return;
360 case ia32_cc_greater: be_emit_cstring("g"); return;
361 case ia32_cc_float_parity_cases:
362 case ia32_cc_additional_float_cases:
365 panic("Invalid ia32 condition code");
368 typedef enum ia32_emit_mod_t {
370 EMIT_RESPECT_LS = 1U << 0,
371 EMIT_ALTERNATE_AM = 1U << 1,
373 EMIT_HIGH_REG = 1U << 3,
374 EMIT_LOW_REG = 1U << 4,
375 EMIT_16BIT_REG = 1U << 5
377 ENUM_BITSET(ia32_emit_mod_t)
380 * Emits address mode.
382 static void ia32_emit_am(ir_node const *const node)
384 ir_entity *ent = get_ia32_am_sc(node);
385 int offs = get_ia32_am_offs_int(node);
386 ir_node *base = get_irn_n(node, n_ia32_base);
387 int has_base = !is_ia32_NoReg_GP(base);
388 ir_node *idx = get_irn_n(node, n_ia32_index);
389 int has_index = !is_ia32_NoReg_GP(idx);
391 /* just to be sure... */
392 assert(!is_ia32_use_frame(node) || get_ia32_frame_ent(node) != NULL);
394 if (get_ia32_am_tls_segment(node))
395 be_emit_cstring("%gs:");
399 const ia32_attr_t *attr = get_ia32_attr_const(node);
400 if (is_ia32_am_sc_sign(node))
402 ia32_emit_entity(ent, attr->data.am_sc_no_pic_adjust);
405 /* also handle special case if nothing is set */
406 if (offs != 0 || (ent == NULL && !has_base && !has_index)) {
408 be_emit_irprintf("%+d", offs);
410 be_emit_irprintf("%d", offs);
414 if (has_base || has_index) {
419 const arch_register_t *reg = arch_get_irn_register_in(node, n_ia32_base);
420 emit_register(reg, NULL);
423 /* emit index + scale */
425 const arch_register_t *reg = arch_get_irn_register_in(node, n_ia32_index);
428 emit_register(reg, NULL);
430 scale = get_ia32_am_scale(node);
432 be_emit_irprintf(",%d", 1 << scale);
439 static ia32_condition_code_t determine_final_cc(ir_node const *node, int flags_pos, ia32_condition_code_t cc);
441 void ia32_emitf(ir_node const *const node, char const *fmt, ...)
448 const char *start = fmt;
449 ia32_emit_mod_t mod = EMIT_NONE;
451 while (*fmt != '%' && *fmt != '\n' && *fmt != '\0')
454 be_emit_string_len(start, fmt - start);
459 be_emit_write_line();
473 case '*': mod |= EMIT_ALTERNATE_AM; break;
474 case '#': mod |= EMIT_RESPECT_LS; break;
475 case 'l': mod |= EMIT_LONG; break;
476 case '>': mod |= EMIT_HIGH_REG; break;
477 case '<': mod |= EMIT_LOW_REG; break;
478 case '^': mod |= EMIT_16BIT_REG; break;
487 arch_register_t const *reg;
497 if (get_ia32_op_type(node) == ia32_Normal) {
498 ia32_x87_attr_t const *const attr = get_ia32_x87_attr_const(node);
499 char const *const fmt = attr->res_in_reg ? "%%st, %%%s" : "%%%s, %%st";
500 be_emit_irprintf(fmt, attr->reg->name);
508 if (mod & EMIT_ALTERNATE_AM)
514 reg = va_arg(ap, const arch_register_t*);
515 if (get_ia32_op_type(node) == ia32_Normal) {
522 if (get_ia32_op_type(node) == ia32_Normal) {
529 default: goto unknown;
535 imm = get_irn_n(node, n_ia32_binary_right);
536 if (is_ia32_Immediate(imm)) {
537 emit_ia32_Immediate(imm);
538 be_emit_cstring(", ");
539 if (get_ia32_op_type(node) == ia32_Normal) {
540 goto destination_operand;
545 if (get_ia32_op_type(node) == ia32_Normal) {
546 reg = arch_get_irn_register_in(node, n_ia32_binary_right);
547 emit_register(reg, get_ia32_ls_mode(node));
551 be_emit_cstring(", ");
553 reg = arch_get_irn_register_in(node, n_ia32_binary_left);
554 emit_register(reg, get_ia32_ls_mode(node));
559 if (*fmt < '0' || '9' < *fmt)
561 reg = arch_get_irn_register_out(node, *fmt++ - '0');
566 ia32_emit_x87_mode_suffix(node);
567 } else if (*fmt == 'P') {
568 ia32_x87_attr_t const *const attr = get_ia32_x87_attr_const(node);
571 } else if (*fmt == 'R') {
572 /* NOTE: Work around a gas quirk for non-commutative operations if the
573 * destination register is not %st0. In this case r/non-r is swapped.
574 * %st0 = %st0 - %st1 -> fsub %st1, %st0 (as expected)
575 * %st0 = %st1 - %st0 -> fsubr %st1, %st0 (as expected)
576 * %st1 = %st0 - %st1 -> fsub %st0, %st1 (expected: fsubr)
577 * %st1 = %st1 - %st0 -> fsubr %st0, %st1 (expected: fsub)
578 * In fact this corresponds to the encoding of the instruction:
579 * - The r suffix selects whether %st0 is on the left (no r) or on the
580 * right (r) side of the executed operation.
581 * - The placement of %st0 selects whether the result is written to
582 * %st0 (right) or the other register (left).
583 * This means that it is sufficient to test whether the operands are
584 * permuted. In particular it is not necessary to consider wether the
585 * result is to be placed into the explicit register operand. */
586 if (get_ia32_x87_attr_const(node)->attr.data.ins_permuted)
588 } else if (*fmt == 'X') {
589 ia32_emit_xmm_mode_suffix(node);
590 } else if (*fmt == '0') {
592 be_emit_string(get_ia32_x87_attr_const(node)->reg->name);
602 if (!(mod & EMIT_ALTERNATE_AM))
604 emit_ia32_Immediate_no_prefix(imm);
608 ia32_emit_cfop_target(node);
612 ir_mode *mode = get_ia32_ls_mode(node);
615 if (mod & EMIT_RESPECT_LS) {
616 if (get_mode_size_bits(mode) == 32)
618 be_emit_char(mode_is_signed(mode) ? 's' : 'z');
620 ia32_emit_mode_suffix_mode(mode);
625 ia32_condition_code_t cc;
628 cc = (ia32_condition_code_t)va_arg(ap, int);
629 } else if ('0' <= *fmt && *fmt <= '9') {
630 cc = get_ia32_condcode(node);
631 cc = determine_final_cc(node, *fmt - '0', cc);
636 ia32_emit_condition_code(cc);
641 reg = va_arg(ap, const arch_register_t*);
643 if (mod & EMIT_ALTERNATE_AM)
645 if (mod & EMIT_HIGH_REG) {
646 emit_8bit_register_high(reg);
647 } else if (mod & EMIT_LOW_REG) {
648 emit_8bit_register(reg);
649 } else if (mod & EMIT_16BIT_REG) {
650 emit_16bit_register(reg);
652 emit_register(reg, mod & EMIT_RESPECT_LS ? get_ia32_ls_mode(node) : NULL);
660 if (*fmt < '0' || '9' < *fmt)
664 imm = get_irn_n(node, pos);
665 if (is_ia32_Immediate(imm)) {
668 reg = arch_get_irn_register_in(node, pos);
674 const char *str = va_arg(ap, const char*);
680 if (mod & EMIT_LONG) {
681 unsigned long num = va_arg(ap, unsigned long);
682 be_emit_irprintf("%lu", num);
684 unsigned num = va_arg(ap, unsigned);
685 be_emit_irprintf("%u", num);
690 if (mod & EMIT_LONG) {
691 long num = va_arg(ap, long);
692 be_emit_irprintf("%ld", num);
694 int num = va_arg(ap, int);
695 be_emit_irprintf("%d", num);
701 panic("unknown format conversion");
705 be_emit_finish_line_gas(node);
709 static void emit_ia32_IMul(const ir_node *node)
711 ir_node *left = get_irn_n(node, n_ia32_IMul_left);
712 const arch_register_t *out_reg = arch_get_irn_register_out(node, pn_ia32_IMul_res);
714 /* do we need the 3-address form? */
715 if (is_ia32_NoReg_GP(left) ||
716 arch_get_irn_register_in(node, n_ia32_IMul_left) != out_reg) {
717 ia32_emitf(node, "imul%M %#S4, %#AS3, %#D0");
719 ia32_emitf(node, "imul%M %#AS4, %#S3");
724 * walks up a tree of copies/perms/spills/reloads to find the original value
725 * that is moved around
727 static ir_node *find_original_value(ir_node *node)
729 if (irn_visited(node))
732 mark_irn_visited(node);
733 if (be_is_Copy(node)) {
734 return find_original_value(be_get_Copy_op(node));
735 } else if (be_is_CopyKeep(node)) {
736 return find_original_value(be_get_CopyKeep_op(node));
737 } else if (is_Proj(node)) {
738 ir_node *pred = get_Proj_pred(node);
739 if (be_is_Perm(pred)) {
740 return find_original_value(get_irn_n(pred, get_Proj_proj(node)));
741 } else if (be_is_MemPerm(pred)) {
742 return find_original_value(get_irn_n(pred, get_Proj_proj(node) + 1));
743 } else if (is_ia32_Load(pred)) {
744 return find_original_value(get_irn_n(pred, n_ia32_Load_mem));
745 } else if (is_ia32_Store(pred)) {
746 return find_original_value(get_irn_n(pred, n_ia32_Store_val));
750 } else if (is_Phi(node)) {
752 arity = get_irn_arity(node);
753 for (i = 0; i < arity; ++i) {
754 ir_node *in = get_irn_n(node, i);
755 ir_node *res = find_original_value(in);
766 static ia32_condition_code_t determine_final_cc(const ir_node *node,
767 int flags_pos, ia32_condition_code_t cc)
769 ir_node *flags = get_irn_n(node, flags_pos);
770 const ia32_attr_t *flags_attr;
771 flags = skip_Proj(flags);
773 if (is_ia32_Sahf(flags)) {
774 ir_node *cmp = get_irn_n(flags, n_ia32_Sahf_val);
775 if (!(is_ia32_FucomFnstsw(cmp) || is_ia32_FucomppFnstsw(cmp) || is_ia32_FtstFnstsw(cmp))) {
776 inc_irg_visited(current_ir_graph);
777 cmp = find_original_value(cmp);
779 assert(is_ia32_FucomFnstsw(cmp) || is_ia32_FucomppFnstsw(cmp) || is_ia32_FtstFnstsw(cmp));
782 flags_attr = get_ia32_attr_const(cmp);
784 flags_attr = get_ia32_attr_const(flags);
787 if (flags_attr->data.ins_permuted)
788 cc = ia32_invert_condition_code(cc);
793 * Emits an exception label for a given node.
795 static void ia32_emit_exc_label(const ir_node *node)
797 be_emit_string(be_gas_insn_label_prefix());
798 be_emit_irprintf("%lu", get_ia32_exc_label_id(node));
801 static int can_be_fallthrough(const ir_node *node)
803 ir_node *target_block = get_cfop_target_block(node);
804 ir_node *block = get_nodes_block(node);
805 return get_prev_block_sched(target_block) == block;
809 * Emits the jump sequence for a conditional jump (cmp + jmp_true + jmp_false)
811 static void emit_ia32_Jcc(const ir_node *node)
813 int need_parity_label = 0;
814 ia32_condition_code_t cc = get_ia32_condcode(node);
816 cc = determine_final_cc(node, 0, cc);
819 ir_node const *proj_true = be_get_Proj_for_pn(node, pn_ia32_Jcc_true);
820 assert(proj_true && "Jcc without true Proj");
822 ir_node const *proj_false = be_get_Proj_for_pn(node, pn_ia32_Jcc_false);
823 assert(proj_false && "Jcc without false Proj");
825 if (can_be_fallthrough(proj_true)) {
826 /* exchange both proj's so the second one can be omitted */
827 const ir_node *t = proj_true;
829 proj_true = proj_false;
831 cc = ia32_negate_condition_code(cc);
834 if (cc & ia32_cc_float_parity_cases) {
835 /* Some floating point comparisons require a test of the parity flag,
836 * which indicates that the result is unordered */
837 if (cc & ia32_cc_negated) {
838 ia32_emitf(proj_true, "jp %L");
840 /* we need a local label if the false proj is a fallthrough
841 * as the falseblock might have no label emitted then */
842 if (can_be_fallthrough(proj_false)) {
843 need_parity_label = 1;
844 ia32_emitf(proj_false, "jp 1f");
846 ia32_emitf(proj_false, "jp %L");
850 ia32_emitf(proj_true, "j%PX %L", (int)cc);
851 if (need_parity_label) {
852 be_emit_cstring("1:\n");
853 be_emit_write_line();
856 /* the second Proj might be a fallthrough */
857 if (can_be_fallthrough(proj_false)) {
858 if (be_options.verbose_asm)
859 ia32_emitf(proj_false, "/* fallthrough to %L */");
861 ia32_emitf(proj_false, "jmp %L");
866 * Emits an ia32 Setcc. This is mostly easy but some floating point compares
869 static void emit_ia32_Setcc(const ir_node *node)
871 const arch_register_t *dreg = arch_get_irn_register_out(node, pn_ia32_Setcc_res);
873 ia32_condition_code_t cc = get_ia32_condcode(node);
874 cc = determine_final_cc(node, n_ia32_Setcc_eflags, cc);
875 if (cc & ia32_cc_float_parity_cases) {
876 if (cc & ia32_cc_negated) {
877 ia32_emitf(node, "set%PX %<R", (int)cc, dreg);
878 ia32_emitf(node, "setp %>R", dreg);
879 ia32_emitf(node, "orb %>R, %<R", dreg, dreg);
881 ia32_emitf(node, "set%PX %<R", (int)cc, dreg);
882 ia32_emitf(node, "setnp %>R", dreg);
883 ia32_emitf(node, "andb %>R, %<R", dreg, dreg);
886 ia32_emitf(node, "set%PX %#R", (int)cc, dreg);
890 static void emit_ia32_CMovcc(const ir_node *node)
892 const ia32_attr_t *attr = get_ia32_attr_const(node);
893 const arch_register_t *out = arch_get_irn_register_out(node, pn_ia32_res);
894 ia32_condition_code_t cc = get_ia32_condcode(node);
895 const arch_register_t *in_true;
896 const arch_register_t *in_false;
898 cc = determine_final_cc(node, n_ia32_CMovcc_eflags, cc);
899 /* although you can't set ins_permuted in the constructor it might still
900 * be set by memory operand folding
901 * Permuting inputs of a cmov means the condition is negated!
903 if (attr->data.ins_permuted)
904 cc = ia32_negate_condition_code(cc);
906 in_true = arch_get_irn_register(get_irn_n(node, n_ia32_CMovcc_val_true));
907 in_false = arch_get_irn_register(get_irn_n(node, n_ia32_CMovcc_val_false));
909 /* should be same constraint fullfilled? */
910 if (out == in_false) {
911 /* yes -> nothing to do */
912 } else if (out == in_true) {
913 const arch_register_t *tmp;
915 assert(get_ia32_op_type(node) == ia32_Normal);
917 cc = ia32_negate_condition_code(cc);
924 ia32_emitf(node, "movl %R, %R", in_false, out);
927 if (cc & ia32_cc_float_parity_cases) {
928 panic("CMov with floatingpoint compare/parity not supported yet");
931 ia32_emitf(node, "cmov%PX %#AR, %#R", (int)cc, in_true, out);
935 * Emits code for a SwitchJmp
937 static void emit_ia32_SwitchJmp(const ir_node *node)
939 ir_entity *jump_table = get_ia32_am_sc(node);
940 const ir_switch_table *table = get_ia32_switch_table(node);
942 ia32_emitf(node, "jmp %*AM");
943 be_emit_jump_table(node, table, jump_table, get_cfop_target_block);
947 * Emits code for a unconditional jump.
949 static void emit_ia32_Jmp(const ir_node *node)
951 /* we have a block schedule */
952 if (can_be_fallthrough(node)) {
953 if (be_options.verbose_asm)
954 ia32_emitf(node, "/* fallthrough to %L */");
956 ia32_emitf(node, "jmp %L");
961 * Emit an inline assembler operand.
963 * @param node the ia32_ASM node
964 * @param s points to the operand (a %c)
966 * @return pointer to the first char in s NOT in the current operand
968 static const char* emit_asm_operand(const ir_node *node, const char *s)
970 const ia32_attr_t *ia32_attr = get_ia32_attr_const(node);
971 const ia32_asm_attr_t *attr = CONST_CAST_IA32_ATTR(ia32_asm_attr_t,
973 const arch_register_t *reg;
974 const ia32_asm_reg_t *asm_regs = attr->register_map;
975 const ia32_asm_reg_t *asm_reg;
984 /* parse modifiers */
987 ir_fprintf(stderr, "Warning: asm text (%+F) ends with %%\n", node);
1013 "Warning: asm text (%+F) contains unknown modifier '%c' for asm op\n",
1020 if (sscanf(s, "%d%n", &num, &p) != 1) {
1021 ir_fprintf(stderr, "Warning: Couldn't parse assembler operand (%+F)\n",
1028 if (num < 0 || ARR_LEN(asm_regs) <= (size_t)num) {
1030 "Error: Custom assembler references invalid input/output (%+F)\n",
1034 asm_reg = & asm_regs[num];
1035 assert(asm_reg->valid);
1038 if (asm_reg->use_input == 0) {
1039 reg = arch_get_irn_register_out(node, asm_reg->inout_pos);
1041 ir_node *pred = get_irn_n(node, asm_reg->inout_pos);
1043 /* might be an immediate value */
1044 if (is_ia32_Immediate(pred)) {
1045 emit_ia32_Immediate(pred);
1048 reg = arch_get_irn_register_in(node, asm_reg->inout_pos);
1052 "Warning: no register assigned for %d asm op (%+F)\n",
1057 /* Emit the register. */
1058 if (asm_reg->memory) {
1060 emit_register(reg, NULL);
1064 case '\0': emit_register(reg, asm_reg->mode); break;
1065 case 'b': emit_8bit_register(reg); break;
1066 case 'h': emit_8bit_register_high(reg); break;
1067 case 'w': emit_16bit_register(reg); break;
1068 default: panic("Invalid asm op modifier");
1076 * Emits code for an ASM pseudo op.
1078 static void emit_ia32_Asm(const ir_node *node)
1080 const void *gen_attr = get_irn_generic_attr_const(node);
1081 const ia32_asm_attr_t *attr
1082 = CONST_CAST_IA32_ATTR(ia32_asm_attr_t, gen_attr);
1083 ident *asm_text = attr->asm_text;
1084 const char *s = get_id_str(asm_text);
1086 be_emit_cstring("#APP\n");
1087 be_emit_write_line();
1094 s = emit_asm_operand(node, s);
1100 be_emit_cstring("\n#NO_APP\n");
1101 be_emit_write_line();
1106 * Emit movsb/w instructions to make mov count divideable by 4
1108 static void emit_CopyB_prolog(unsigned size)
1111 ia32_emitf(NULL, "movsb");
1113 ia32_emitf(NULL, "movsw");
1117 * Emit rep movsd instruction for memcopy.
1119 static void emit_ia32_CopyB(const ir_node *node)
1121 unsigned size = get_ia32_copyb_size(node);
1123 emit_CopyB_prolog(size);
1124 ia32_emitf(node, "rep movsd");
1128 * Emits unrolled memcopy.
1130 static void emit_ia32_CopyB_i(const ir_node *node)
1132 unsigned size = get_ia32_copyb_size(node);
1134 emit_CopyB_prolog(size);
1138 ia32_emitf(NULL, "movsd");
1144 * Emit code for conversions (I, FP), (FP, I) and (FP, FP).
1146 static void emit_ia32_Conv_with_FP(const ir_node *node, const char* conv_f,
1149 ir_mode *ls_mode = get_ia32_ls_mode(node);
1150 int ls_bits = get_mode_size_bits(ls_mode);
1151 const char *conv = ls_bits == 32 ? conv_f : conv_d;
1153 ia32_emitf(node, "cvt%s %AS3, %D0", conv);
1156 static void emit_ia32_Conv_I2FP(const ir_node *node)
1158 emit_ia32_Conv_with_FP(node, "si2ss", "si2sd");
1161 static void emit_ia32_Conv_FP2I(const ir_node *node)
1163 emit_ia32_Conv_with_FP(node, "ss2si", "sd2si");
1166 static void emit_ia32_Conv_FP2FP(const ir_node *node)
1168 emit_ia32_Conv_with_FP(node, "sd2ss", "ss2sd");
1172 * Emits code to increase stack pointer.
1174 static void emit_be_IncSP(const ir_node *node)
1176 int offs = be_get_IncSP_offset(node);
1182 ia32_emitf(node, "subl $%u, %D0", offs);
1184 ia32_emitf(node, "addl $%u, %D0", -offs);
1189 * Emits code for Copy/CopyKeep.
1191 static void Copy_emitter(const ir_node *node, const ir_node *op)
1193 const arch_register_t *in = arch_get_irn_register(op);
1194 const arch_register_t *out = arch_get_irn_register(node);
1199 /* copies of fp nodes aren't real... */
1200 if (in->reg_class == &ia32_reg_classes[CLASS_ia32_fp])
1203 ia32_emitf(node, "movl %R, %R", in, out);
1206 static void emit_be_Copy(const ir_node *node)
1208 Copy_emitter(node, be_get_Copy_op(node));
1211 static void emit_be_CopyKeep(const ir_node *node)
1213 Copy_emitter(node, be_get_CopyKeep_op(node));
1217 * Emits code for exchange.
1219 static void emit_be_Perm(const ir_node *node)
1221 const arch_register_t *in0, *in1;
1223 in0 = arch_get_irn_register(get_irn_n(node, 0));
1224 in1 = arch_get_irn_register(get_irn_n(node, 1));
1226 arch_register_class_t const *const cls0 = in0->reg_class;
1227 assert(cls0 == in1->reg_class && "Register class mismatch at Perm");
1229 if (cls0 == &ia32_reg_classes[CLASS_ia32_gp]) {
1230 ia32_emitf(node, "xchg %R, %R", in1, in0);
1231 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_xmm]) {
1232 ia32_emitf(NULL, "xorpd %R, %R", in1, in0);
1233 ia32_emitf(NULL, "xorpd %R, %R", in0, in1);
1234 ia32_emitf(node, "xorpd %R, %R", in1, in0);
1235 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_fp]) {
1238 panic("unexpected register class in be_Perm (%+F)", node);
1242 /* helper function for emit_ia32_Minus64Bit */
1243 static void emit_mov(const ir_node* node, const arch_register_t *src, const arch_register_t *dst)
1245 ia32_emitf(node, "movl %R, %R", src, dst);
1248 /* helper function for emit_ia32_Minus64Bit */
1249 static void emit_neg(const ir_node* node, const arch_register_t *reg)
1251 ia32_emitf(node, "negl %R", reg);
1254 /* helper function for emit_ia32_Minus64Bit */
1255 static void emit_sbb0(const ir_node* node, const arch_register_t *reg)
1257 ia32_emitf(node, "sbbl $0, %R", reg);
1260 /* helper function for emit_ia32_Minus64Bit */
1261 static void emit_sbb(const ir_node* node, const arch_register_t *src, const arch_register_t *dst)
1263 ia32_emitf(node, "sbbl %R, %R", src, dst);
1266 /* helper function for emit_ia32_Minus64Bit */
1267 static void emit_xchg(const ir_node* node, const arch_register_t *src, const arch_register_t *dst)
1269 ia32_emitf(node, "xchgl %R, %R", src, dst);
1272 /* helper function for emit_ia32_Minus64Bit */
1273 static void emit_zero(const ir_node* node, const arch_register_t *reg)
1275 ia32_emitf(node, "xorl %R, %R", reg, reg);
1278 static void emit_ia32_Minus64Bit(const ir_node *node)
1280 const arch_register_t *in_lo = arch_get_irn_register_in(node, 0);
1281 const arch_register_t *in_hi = arch_get_irn_register_in(node, 1);
1282 const arch_register_t *out_lo = arch_get_irn_register_out(node, 0);
1283 const arch_register_t *out_hi = arch_get_irn_register_out(node, 1);
1285 if (out_lo == in_lo) {
1286 if (out_hi != in_hi) {
1287 /* a -> a, b -> d */
1290 /* a -> a, b -> b */
1293 } else if (out_lo == in_hi) {
1294 if (out_hi == in_lo) {
1295 /* a -> b, b -> a */
1296 emit_xchg(node, in_lo, in_hi);
1299 /* a -> b, b -> d */
1300 emit_mov(node, in_hi, out_hi);
1301 emit_mov(node, in_lo, out_lo);
1305 if (out_hi == in_lo) {
1306 /* a -> c, b -> a */
1307 emit_mov(node, in_lo, out_lo);
1309 } else if (out_hi == in_hi) {
1310 /* a -> c, b -> b */
1311 emit_mov(node, in_lo, out_lo);
1314 /* a -> c, b -> d */
1315 emit_mov(node, in_lo, out_lo);
1321 emit_neg( node, out_hi);
1322 emit_neg( node, out_lo);
1323 emit_sbb0(node, out_hi);
1327 emit_zero(node, out_hi);
1328 emit_neg( node, out_lo);
1329 emit_sbb( node, in_hi, out_hi);
1332 static void emit_ia32_GetEIP(const ir_node *node)
1334 ia32_emitf(node, "call %s", pic_base_label);
1335 be_emit_irprintf("%s:\n", pic_base_label);
1336 be_emit_write_line();
1337 ia32_emitf(node, "popl %D0");
1340 static void emit_ia32_ClimbFrame(const ir_node *node)
1342 const ia32_climbframe_attr_t *attr = get_ia32_climbframe_attr_const(node);
1344 ia32_emitf(node, "movl %S0, %D0");
1345 ia32_emitf(node, "movl $%u, %S1", attr->count);
1346 be_gas_emit_block_name(node);
1347 be_emit_cstring(":\n");
1348 be_emit_write_line();
1349 ia32_emitf(node, "movl (%D0), %D0");
1350 ia32_emitf(node, "dec %S1");
1351 be_emit_cstring("\tjnz ");
1352 be_gas_emit_block_name(node);
1353 be_emit_finish_line_gas(node);
1356 static void emit_be_Return(const ir_node *node)
1358 unsigned pop = be_Return_get_pop(node);
1360 if (pop > 0 || be_Return_get_emit_pop(node)) {
1361 ia32_emitf(node, "ret $%u", pop);
1363 ia32_emitf(node, "ret");
1369 * Enters the emitter functions for handled nodes into the generic
1370 * pointer of an opcode.
1372 static void ia32_register_emitters(void)
1374 #define IA32_EMIT(a) be_set_emitter(op_ia32_##a, emit_ia32_##a)
1375 #define EMIT(a) be_set_emitter(op_##a, emit_##a)
1376 #define IGN(a) be_set_emitter(op_##a, be_emit_nothing)
1377 #define BE_EMIT(a) be_set_emitter(op_be_##a, emit_be_##a)
1378 #define BE_IGN(a) be_set_emitter(op_be_##a, be_emit_nothing)
1380 /* first clear the generic function pointer for all ops */
1381 ir_clear_opcodes_generic_func();
1383 /* register all emitter functions defined in spec */
1384 ia32_register_spec_emitters();
1386 /* other ia32 emitter functions */
1389 IA32_EMIT(Conv_FP2FP);
1390 IA32_EMIT(Conv_FP2I);
1391 IA32_EMIT(Conv_I2FP);
1398 IA32_EMIT(Minus64Bit);
1399 IA32_EMIT(SwitchJmp);
1400 IA32_EMIT(ClimbFrame);
1403 /* benode emitter */
1423 * Assign and emit an exception label if the current instruction can fail.
1425 static void ia32_assign_exc_label(ir_node *node)
1427 /* assign a new ID to the instruction */
1428 set_ia32_exc_label_id(node, ++exc_label_id);
1430 ia32_emit_exc_label(node);
1432 be_emit_pad_comment();
1433 be_emit_cstring("/* exception to Block ");
1434 ia32_emit_cfop_target(node);
1435 be_emit_cstring(" */\n");
1436 be_emit_write_line();
1440 * Emits code for a node.
1442 static void ia32_emit_node(ir_node *node)
1444 DBG((dbg, LEVEL_1, "emitting code for %+F\n", node));
1446 if (is_ia32_irn(node)) {
1447 if (get_ia32_exc_label(node)) {
1448 /* emit the exception label of this instruction */
1449 ia32_assign_exc_label(node);
1451 if (mark_spill_reload) {
1452 if (is_ia32_is_spill(node)) {
1453 ia32_emitf(NULL, "xchg %ebx, %ebx /* spill mark */");
1455 if (is_ia32_is_reload(node)) {
1456 ia32_emitf(NULL, "xchg %edx, %edx /* reload mark */");
1458 if (is_ia32_is_remat(node)) {
1459 ia32_emitf(NULL, "xchg %ecx, %ecx /* remat mark */");
1467 int sp_change = arch_get_sp_bias(node);
1468 if (sp_change != 0) {
1469 assert(sp_change != SP_BIAS_RESET);
1470 callframe_offset += sp_change;
1471 be_dwarf_callframe_offset(callframe_offset);
1477 * Emits gas alignment directives
1479 static void ia32_emit_alignment(unsigned align, unsigned skip)
1481 ia32_emitf(NULL, ".p2align %u,,%u", align, skip);
1485 * Emits gas alignment directives for Labels depended on cpu architecture.
1487 static void ia32_emit_align_label(void)
1489 unsigned align = ia32_cg_config.label_alignment;
1490 unsigned maximum_skip = ia32_cg_config.label_alignment_max_skip;
1491 ia32_emit_alignment(align, maximum_skip);
1495 * Test whether a block should be aligned.
1496 * For cpus in the P4/Athlon class it is useful to align jump labels to
1497 * 16 bytes. However we should only do that if the alignment nops before the
1498 * label aren't executed more often than we have jumps to the label.
1500 static int should_align_block(const ir_node *block)
1502 static const double DELTA = .0001;
1503 ir_node *prev = get_prev_block_sched(block);
1504 double prev_freq = 0; /**< execfreq of the fallthrough block */
1505 double jmp_freq = 0; /**< execfreq of all non-fallthrough blocks */
1509 if (ia32_cg_config.label_alignment_factor <= 0)
1512 block_freq = get_block_execfreq(block);
1513 if (block_freq < DELTA)
1516 n_cfgpreds = get_Block_n_cfgpreds(block);
1517 for (i = 0; i < n_cfgpreds; ++i) {
1518 const ir_node *pred = get_Block_cfgpred_block(block, i);
1519 double pred_freq = get_block_execfreq(pred);
1522 prev_freq += pred_freq;
1524 jmp_freq += pred_freq;
1528 if (prev_freq < DELTA && !(jmp_freq < DELTA))
1531 jmp_freq /= prev_freq;
1533 return jmp_freq > ia32_cg_config.label_alignment_factor;
1537 * Emit the block header for a block.
1539 * @param block the block
1540 * @param prev_block the previous block
1542 static void ia32_emit_block_header(ir_node *block)
1544 ir_graph *const irg = get_Block_irg(block);
1545 if (block == get_irg_end_block(irg))
1548 if (ia32_cg_config.label_alignment > 0) {
1549 /* align the current block if:
1550 * a) if should be aligned due to its execution frequency
1551 * b) there is no fall-through here
1553 if (should_align_block(block)) {
1554 ia32_emit_align_label();
1556 /* if the predecessor block has no fall-through,
1557 we can always align the label. */
1559 int has_fallthrough = 0;
1561 for (i = get_Block_n_cfgpreds(block) - 1; i >= 0; --i) {
1562 ir_node *cfg_pred = get_Block_cfgpred(block, i);
1563 if (can_be_fallthrough(cfg_pred)) {
1564 has_fallthrough = 1;
1569 if (!has_fallthrough)
1570 ia32_emit_align_label();
1574 int const need_label = block_needs_label(block);
1575 be_gas_begin_block(block, need_label);
1579 * Walks over the nodes in a block connected by scheduling edges
1580 * and emits code for each node.
1582 static void ia32_gen_block(ir_node *block)
1584 ia32_emit_block_header(block);
1587 ir_graph *irg = get_irn_irg(block);
1588 callframe_offset = 4; /* 4 bytes for the return address */
1589 /* ESP guessing, TODO perform a real ESP simulation */
1590 if (block != get_irg_start_block(irg)) {
1591 callframe_offset += frame_type_size;
1593 be_dwarf_callframe_offset(callframe_offset);
1596 /* emit the contents of the block */
1597 be_dwarf_location(get_irn_dbg_info(block));
1598 sched_foreach(block, node) {
1599 ia32_emit_node(node);
1603 typedef struct exc_entry {
1604 ir_node *exc_instr; /** The instruction that can issue an exception. */
1605 ir_node *block; /** The block to call then. */
1610 * Sets labels for control flow nodes (jump target).
1611 * Links control predecessors to there destination blocks.
1613 static void ia32_gen_labels(ir_node *block, void *data)
1615 exc_entry **exc_list = (exc_entry**)data;
1619 for (n = get_Block_n_cfgpreds(block) - 1; n >= 0; --n) {
1620 pred = get_Block_cfgpred(block, n);
1621 set_irn_link(pred, block);
1623 pred = skip_Proj(pred);
1624 if (is_ia32_irn(pred) && get_ia32_exc_label(pred)) {
1629 ARR_APP1(exc_entry, *exc_list, e);
1630 set_irn_link(pred, block);
1636 * Compare two exception_entries.
1638 static int cmp_exc_entry(const void *a, const void *b)
1640 const exc_entry *ea = (const exc_entry*)a;
1641 const exc_entry *eb = (const exc_entry*)b;
1643 if (get_ia32_exc_label_id(ea->exc_instr) < get_ia32_exc_label_id(eb->exc_instr))
1648 static parameter_dbg_info_t *construct_parameter_infos(ir_graph *irg)
1650 ir_entity *entity = get_irg_entity(irg);
1651 ir_type *type = get_entity_type(entity);
1652 size_t n_params = get_method_n_params(type);
1653 be_stack_layout_t *layout = be_get_irg_stack_layout(irg);
1654 ir_type *arg_type = layout->arg_type;
1655 size_t n_members = get_compound_n_members(arg_type);
1656 parameter_dbg_info_t *infos = XMALLOCNZ(parameter_dbg_info_t, n_params);
1659 for (i = 0; i < n_members; ++i) {
1660 ir_entity *member = get_compound_member(arg_type, i);
1662 if (!is_parameter_entity(member))
1664 param = get_entity_parameter_number(member);
1665 if (param == IR_VA_START_PARAMETER_NUMBER)
1667 assert(infos[param].entity == NULL && infos[param].reg == NULL);
1668 infos[param].reg = NULL;
1669 infos[param].entity = member;
1676 * Main driver. Emits the code for one routine.
1678 void ia32_gen_routine(ir_graph *irg)
1680 ir_entity *entity = get_irg_entity(irg);
1681 exc_entry *exc_list = NEW_ARR_F(exc_entry, 0);
1682 const arch_env_t *arch_env = be_get_irg_arch_env(irg);
1683 ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
1684 ir_node **blk_sched = irg_data->blk_sched;
1685 be_stack_layout_t *layout = be_get_irg_stack_layout(irg);
1686 parameter_dbg_info_t *infos;
1689 isa = (ia32_isa_t*) arch_env;
1690 do_pic = be_options.pic;
1692 be_gas_elf_type_char = '@';
1694 ia32_register_emitters();
1696 get_unique_label(pic_base_label, sizeof(pic_base_label), "PIC_BASE");
1698 infos = construct_parameter_infos(irg);
1699 be_gas_emit_function_prolog(entity, ia32_cg_config.function_alignment,
1703 sp_relative = layout->sp_relative;
1704 if (layout->sp_relative) {
1705 ir_type *frame_type = get_irg_frame_type(irg);
1706 frame_type_size = get_type_size_bytes(frame_type);
1707 be_dwarf_callframe_register(&ia32_registers[REG_ESP]);
1709 /* well not entirely correct here, we should emit this after the
1710 * "movl esp, ebp" */
1711 be_dwarf_callframe_register(&ia32_registers[REG_EBP]);
1712 /* TODO: do not hardcode the following */
1713 be_dwarf_callframe_offset(8);
1714 be_dwarf_callframe_spilloffset(&ia32_registers[REG_EBP], -8);
1717 /* we use links to point to target blocks */
1718 ir_reserve_resources(irg, IR_RESOURCE_IRN_LINK);
1719 irg_block_walk_graph(irg, ia32_gen_labels, NULL, &exc_list);
1721 /* initialize next block links */
1722 n = ARR_LEN(blk_sched);
1723 for (i = 0; i < n; ++i) {
1724 ir_node *block = blk_sched[i];
1725 ir_node *prev = i > 0 ? blk_sched[i-1] : NULL;
1727 set_irn_link(block, prev);
1730 for (i = 0; i < n; ++i) {
1731 ir_node *block = blk_sched[i];
1733 ia32_gen_block(block);
1736 be_gas_emit_function_epilog(entity);
1738 ir_free_resources(irg, IR_RESOURCE_IRN_LINK);
1740 /* Sort the exception table using the exception label id's.
1741 Those are ascending with ascending addresses. */
1742 qsort(exc_list, ARR_LEN(exc_list), sizeof(exc_list[0]), cmp_exc_entry);
1746 for (e = 0; e < ARR_LEN(exc_list); ++e) {
1747 be_emit_cstring("\t.long ");
1748 ia32_emit_exc_label(exc_list[e].exc_instr);
1750 be_emit_cstring("\t.long ");
1751 be_gas_emit_block_name(exc_list[e].block);
1755 DEL_ARR_F(exc_list);
1758 static const lc_opt_table_entry_t ia32_emitter_options[] = {
1759 LC_OPT_ENT_BOOL("mark_spill_reload", "mark spills and reloads with ud opcodes", &mark_spill_reload),
1763 /* ==== Experimental binary emitter ==== */
1765 static unsigned char reg_gp_map[N_ia32_gp_REGS];
1766 //static unsigned char reg_mmx_map[N_ia32_mmx_REGS];
1767 //static unsigned char reg_sse_map[N_ia32_xmm_REGS];
1769 static void build_reg_map(void)
1771 reg_gp_map[REG_GP_EAX] = 0x0;
1772 reg_gp_map[REG_GP_ECX] = 0x1;
1773 reg_gp_map[REG_GP_EDX] = 0x2;
1774 reg_gp_map[REG_GP_EBX] = 0x3;
1775 reg_gp_map[REG_GP_ESP] = 0x4;
1776 reg_gp_map[REG_GP_EBP] = 0x5;
1777 reg_gp_map[REG_GP_ESI] = 0x6;
1778 reg_gp_map[REG_GP_EDI] = 0x7;
1781 /** Returns the encoding for a pnc field. */
1782 static unsigned char pnc2cc(ia32_condition_code_t cc)
1788 OP_8 = 0x00, /* 8bit operation. */
1789 OP_16_32 = 0x01, /* 16/32bit operation. */
1790 OP_IMM8 = 0x02, /* 8bit immediate, which gets sign extended for 16/32bit operation. */
1791 OP_16_32_IMM8 = 0x03, /* 16/32bit operation with sign extended 8bit immediate. */
1794 /** The mod encoding of the ModR/M */
1796 MOD_IND = 0x00, /**< [reg1] */
1797 MOD_IND_BYTE_OFS = 0x40, /**< [reg1 + byte ofs] */
1798 MOD_IND_WORD_OFS = 0x80, /**< [reg1 + word ofs] */
1799 MOD_REG = 0xC0 /**< reg1 */
1802 /** create R/M encoding for ModR/M */
1803 #define ENC_RM(x) (x)
1804 /** create REG encoding for ModR/M */
1805 #define ENC_REG(x) ((x) << 3)
1807 /** create encoding for a SIB byte */
1808 #define ENC_SIB(scale, index, base) ((scale) << 6 | (index) << 3 | (base))
1810 /* Node: The following routines are supposed to append bytes, words, dwords
1811 to the output stream.
1812 Currently the implementation is stupid in that it still creates output
1813 for an "assembler" in the form of .byte, .long
1814 We will change this when enough infrastructure is there to create complete
1815 machine code in memory/object files */
1817 static void bemit8(const unsigned char byte)
1819 be_emit_irprintf("\t.byte 0x%x\n", byte);
1820 be_emit_write_line();
1823 static void bemit16(const unsigned short u16)
1825 be_emit_irprintf("\t.word 0x%x\n", u16);
1826 be_emit_write_line();
1829 static void bemit32(const unsigned u32)
1831 be_emit_irprintf("\t.long 0x%x\n", u32);
1832 be_emit_write_line();
1836 * Emit address of an entity. If @p is_relative is true then a relative
1837 * offset from behind the address to the entity is created.
1839 static void bemit_entity(ir_entity *entity, bool entity_sign, int offset,
1842 if (entity == NULL) {
1847 /* the final version should remember the position in the bytestream
1848 and patch it with the correct address at linktime... */
1849 be_emit_cstring("\t.long ");
1852 be_gas_emit_entity(entity);
1854 if (get_entity_owner(entity) == get_tls_type()) {
1855 if (!entity_has_definition(entity)) {
1856 be_emit_cstring("@INDNTPOFF");
1858 be_emit_cstring("@NTPOFF");
1863 be_emit_cstring("-.");
1868 be_emit_irprintf("%+d", offset);
1871 be_emit_write_line();
1874 static void bemit_jmp_destination(const ir_node *dest_block)
1876 be_emit_cstring("\t.long ");
1877 be_gas_emit_block_name(dest_block);
1878 be_emit_cstring(" - . - 4\n");
1879 be_emit_write_line();
1882 /* end emit routines, all emitters following here should only use the functions
1885 typedef enum reg_modifier {
1890 /** Create a ModR/M byte for src1,src2 registers */
1891 static void bemit_modrr(const arch_register_t *src1,
1892 const arch_register_t *src2)
1894 unsigned char modrm = MOD_REG;
1895 modrm |= ENC_RM(reg_gp_map[src1->index]);
1896 modrm |= ENC_REG(reg_gp_map[src2->index]);
1900 /** Create a ModR/M8 byte for src1,src2 registers */
1901 static void bemit_modrr8(reg_modifier_t high_part1, const arch_register_t *src1,
1902 reg_modifier_t high_part2, const arch_register_t *src2)
1904 unsigned char modrm = MOD_REG;
1905 modrm |= ENC_RM(reg_gp_map[src1->index] + (high_part1 == REG_HIGH ? 4 : 0));
1906 modrm |= ENC_REG(reg_gp_map[src2->index] + (high_part2 == REG_HIGH ? 4 : 0));
1910 /** Create a ModR/M byte for one register and extension */
1911 static void bemit_modru(const arch_register_t *reg, unsigned ext)
1913 unsigned char modrm = MOD_REG;
1915 modrm |= ENC_RM(reg_gp_map[reg->index]);
1916 modrm |= ENC_REG(ext);
1920 /** Create a ModR/M8 byte for one register */
1921 static void bemit_modrm8(reg_modifier_t high_part, const arch_register_t *reg)
1923 unsigned char modrm = MOD_REG;
1924 assert(reg_gp_map[reg->index] < 4);
1925 modrm |= ENC_RM(reg_gp_map[reg->index] + (high_part == REG_HIGH ? 4 : 0));
1931 * Calculate the size of an signed immediate in bytes.
1933 * @param offset an offset
1935 static unsigned get_signed_imm_size(int offset)
1937 if (-128 <= offset && offset < 128) {
1939 } else if (-32768 <= offset && offset < 32768) {
1947 * Emit an address mode.
1949 * @param reg content of the reg field: either a register index or an opcode extension
1950 * @param node the node
1952 static void bemit_mod_am(unsigned reg, const ir_node *node)
1954 ir_entity *ent = get_ia32_am_sc(node);
1955 int offs = get_ia32_am_offs_int(node);
1956 ir_node *base = get_irn_n(node, n_ia32_base);
1957 int has_base = !is_ia32_NoReg_GP(base);
1958 ir_node *idx = get_irn_n(node, n_ia32_index);
1959 int has_index = !is_ia32_NoReg_GP(idx);
1962 unsigned emitoffs = 0;
1963 bool emitsib = false;
1966 /* set the mod part depending on displacement */
1968 modrm |= MOD_IND_WORD_OFS;
1970 } else if (offs == 0) {
1973 } else if (-128 <= offs && offs < 128) {
1974 modrm |= MOD_IND_BYTE_OFS;
1977 modrm |= MOD_IND_WORD_OFS;
1982 const arch_register_t *base_reg = arch_get_irn_register(base);
1983 base_enc = reg_gp_map[base_reg->index];
1985 /* Use the EBP encoding + MOD_IND if NO base register. There is
1986 * always a 32bit offset present in this case. */
1992 /* Determine if we need a SIB byte. */
1994 const arch_register_t *reg_index = arch_get_irn_register(idx);
1995 int scale = get_ia32_am_scale(node);
1997 /* R/M set to ESP means SIB in 32bit mode. */
1998 modrm |= ENC_RM(0x04);
1999 sib = ENC_SIB(scale, reg_gp_map[reg_index->index], base_enc);
2001 } else if (base_enc == 0x04) {
2002 /* for the above reason we are forced to emit a SIB when base is ESP.
2003 * Only the base is used, index must be ESP too, which means no index.
2005 modrm |= ENC_RM(0x04);
2006 sib = ENC_SIB(0, 0x04, 0x04);
2009 modrm |= ENC_RM(base_enc);
2012 /* We are forced to emit an 8bit offset as EBP base without offset is a
2013 * special case for SIB without base register. */
2014 if (base_enc == 0x05 && emitoffs == 0) {
2015 modrm |= MOD_IND_BYTE_OFS;
2019 modrm |= ENC_REG(reg);
2025 /* emit displacement */
2026 if (emitoffs == 8) {
2027 bemit8((unsigned) offs);
2028 } else if (emitoffs == 32) {
2029 bemit_entity(ent, is_ia32_am_sc_sign(node), offs, false);
2034 * Emit a binop with a immediate operand.
2036 * @param node the node to emit
2037 * @param opcode_eax the opcode for the op eax, imm variant
2038 * @param opcode the opcode for the reg, imm variant
2039 * @param ruval the opcode extension for opcode
2041 static void bemit_binop_with_imm(
2042 const ir_node *node,
2043 unsigned char opcode_ax,
2044 unsigned char opcode, unsigned char ruval)
2046 /* Use in-reg, because some instructions (cmp, test) have no out-reg. */
2047 const ir_node *op = get_irn_n(node, n_ia32_binary_right);
2048 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(op);
2051 /* Some instructions (test) have no short form with 32bit value + 8bit
2053 if (attr->symconst != NULL || opcode & OP_IMM8) {
2056 /* check for sign extension */
2057 size = get_signed_imm_size(attr->offset);
2062 bemit8(opcode | OP_16_32_IMM8);
2063 /* cmp has this special mode */
2064 if (get_ia32_op_type(node) == ia32_Normal) {
2065 const arch_register_t *reg = arch_get_irn_register_in(node, n_ia32_binary_left);
2066 bemit_modru(reg, ruval);
2068 bemit_mod_am(ruval, node);
2070 bemit8((unsigned char)attr->offset);
2074 if (get_ia32_op_type(node) == ia32_Normal) {
2075 /* check for eax variant: this variant is shorter for 32bit immediates only */
2076 const arch_register_t *reg = arch_get_irn_register_in(node, n_ia32_binary_left);
2077 if (reg->index == REG_GP_EAX) {
2081 bemit_modru(reg, ruval);
2085 bemit_mod_am(ruval, node);
2087 bemit_entity(attr->symconst, attr->sc_sign, attr->offset, false);
2090 panic("invalid imm size?!?");
2096 static void bemit_binop_2(const ir_node *node, unsigned code)
2098 const arch_register_t *out = arch_get_irn_register_in(node, n_ia32_binary_left);
2100 if (get_ia32_op_type(node) == ia32_Normal) {
2101 const arch_register_t *op2 = arch_get_irn_register_in(node, n_ia32_binary_right);
2102 bemit_modrr(op2, out);
2104 bemit_mod_am(reg_gp_map[out->index], node);
2111 static void bemit_binop(const ir_node *node, const unsigned char opcodes[4])
2113 ir_node *right = get_irn_n(node, n_ia32_binary_right);
2114 if (is_ia32_Immediate(right)) {
2115 bemit_binop_with_imm(node, opcodes[1], opcodes[2], opcodes[3]);
2117 bemit_binop_2(node, opcodes[0]);
2124 static void bemit_unop(const ir_node *node, unsigned char code, unsigned char ext, int input)
2127 if (get_ia32_op_type(node) == ia32_Normal) {
2128 const arch_register_t *in = arch_get_irn_register_in(node, input);
2129 bemit_modru(in, ext);
2131 bemit_mod_am(ext, node);
2135 static void bemit_unop_reg(const ir_node *node, unsigned char code, int input)
2137 const arch_register_t *out = arch_get_irn_register_out(node, 0);
2138 bemit_unop(node, code, reg_gp_map[out->index], input);
2141 static void bemit_unop_mem(const ir_node *node, unsigned char code, unsigned char ext)
2143 unsigned size = get_mode_size_bits(get_ia32_ls_mode(node));
2146 bemit8(size == 8 ? code : code + 1);
2147 bemit_mod_am(ext, node);
2150 static void bemit_0f_unop_reg(ir_node const *const node, unsigned char const code, int const input)
2153 bemit_unop_reg(node, code, input);
2156 static void bemit_immediate(const ir_node *node, bool relative)
2158 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(node);
2159 bemit_entity(attr->symconst, attr->sc_sign, attr->offset, relative);
2162 static void bemit_copy(const ir_node *copy)
2164 const arch_register_t *in = arch_get_irn_register_in(copy, 0);
2165 const arch_register_t *out = arch_get_irn_register_out(copy, 0);
2169 /* copies of fp nodes aren't real... */
2170 if (in->reg_class == &ia32_reg_classes[CLASS_ia32_fp])
2173 assert(in->reg_class == &ia32_reg_classes[CLASS_ia32_gp]);
2175 bemit_modrr(in, out);
2178 static void bemit_perm(const ir_node *node)
2180 const arch_register_t *in0 = arch_get_irn_register(get_irn_n(node, 0));
2181 const arch_register_t *in1 = arch_get_irn_register(get_irn_n(node, 1));
2182 const arch_register_class_t *cls0 = in0->reg_class;
2184 assert(cls0 == in1->reg_class && "Register class mismatch at Perm");
2186 if (cls0 == &ia32_reg_classes[CLASS_ia32_gp]) {
2187 if (in0->index == REG_GP_EAX) {
2188 bemit8(0x90 + reg_gp_map[in1->index]);
2189 } else if (in1->index == REG_GP_EAX) {
2190 bemit8(0x90 + reg_gp_map[in0->index]);
2193 bemit_modrr(in0, in1);
2195 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_xmm]) {
2196 panic("unimplemented"); // TODO implement
2197 //ia32_emitf(NULL, "xorpd %R, %R", in1, in0);
2198 //ia32_emitf(NULL, "xorpd %R, %R", in0, in1);
2199 //ia32_emitf(node, "xorpd %R, %R", in1, in0);
2200 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_fp]) {
2203 panic("unexpected register class in be_Perm (%+F)", node);
2207 static void bemit_xor0(const ir_node *node)
2209 const arch_register_t *out = arch_get_irn_register_out(node, 0);
2211 bemit_modrr(out, out);
2214 static void bemit_mov_const(const ir_node *node)
2216 const arch_register_t *out = arch_get_irn_register_out(node, 0);
2217 bemit8(0xB8 + reg_gp_map[out->index]);
2218 bemit_immediate(node, false);
2222 * Creates a function for a Binop with 3 possible encodings.
2224 #define BINOP(op, op0, op1, op2, op2_ext) \
2225 static void bemit_ ## op(const ir_node *node) { \
2226 static const unsigned char op ## _codes[] = {op0, op1, op2, op2_ext}; \
2227 bemit_binop(node, op ## _codes); \
2230 /* insn def eax,imm imm */
2231 BINOP(add, 0x03, 0x05, 0x81, 0)
2232 BINOP(or, 0x0B, 0x0D, 0x81, 1)
2233 BINOP(adc, 0x13, 0x15, 0x81, 2)
2234 BINOP(sbb, 0x1B, 0x1D, 0x81, 3)
2235 BINOP(and, 0x23, 0x25, 0x81, 4)
2236 BINOP(sub, 0x2B, 0x2D, 0x81, 5)
2237 BINOP(xor, 0x33, 0x35, 0x81, 6)
2238 BINOP(test, 0x85, 0xA9, 0xF7, 0)
2240 #define BINOPMEM(op, ext) \
2241 static void bemit_##op(const ir_node *node) \
2244 unsigned size = get_mode_size_bits(get_ia32_ls_mode(node)); \
2247 val = get_irn_n(node, n_ia32_unary_op); \
2248 if (is_ia32_Immediate(val)) { \
2249 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(val); \
2250 int offset = attr->offset; \
2251 if (attr->symconst == NULL && get_signed_imm_size(offset) == 1) { \
2253 bemit_mod_am(ext, node); \
2257 bemit_mod_am(ext, node); \
2261 bemit_entity(attr->symconst, attr->sc_sign, offset, false); \
2265 bemit8(ext << 3 | 1); \
2266 bemit_mod_am(reg_gp_map[arch_get_irn_register(val)->index], node); \
2270 static void bemit_##op##8bit(const ir_node *node) \
2272 ir_node *val = get_irn_n(node, n_ia32_unary_op); \
2273 if (is_ia32_Immediate(val)) { \
2275 bemit_mod_am(ext, node); \
2276 bemit8(get_ia32_immediate_attr_const(val)->offset); \
2279 bemit_mod_am(reg_gp_map[arch_get_irn_register(val)->index], node); \
2291 * Creates a function for an Unop with code /ext encoding.
2293 #define UNOP(op, code, ext, input) \
2294 static void bemit_ ## op(const ir_node *node) { \
2295 bemit_unop(node, code, ext, input); \
2298 UNOP(not, 0xF7, 2, n_ia32_Not_val)
2299 UNOP(neg, 0xF7, 3, n_ia32_Neg_val)
2300 UNOP(mul, 0xF7, 4, n_ia32_Mul_right)
2301 UNOP(imul1op, 0xF7, 5, n_ia32_IMul1OP_right)
2302 UNOP(div, 0xF7, 6, n_ia32_Div_divisor)
2303 UNOP(idiv, 0xF7, 7, n_ia32_IDiv_divisor)
2305 /* TODO: am support for IJmp */
2306 UNOP(ijmp, 0xFF, 4, n_ia32_IJmp_target)
2308 #define SHIFT(op, ext) \
2309 static void bemit_##op(const ir_node *node) \
2311 const arch_register_t *out = arch_get_irn_register_out(node, 0); \
2312 ir_node *count = get_irn_n(node, 1); \
2313 if (is_ia32_Immediate(count)) { \
2314 int offset = get_ia32_immediate_attr_const(count)->offset; \
2315 if (offset == 1) { \
2317 bemit_modru(out, ext); \
2320 bemit_modru(out, ext); \
2325 bemit_modru(out, ext); \
2329 static void bemit_##op##mem(const ir_node *node) \
2332 unsigned size = get_mode_size_bits(get_ia32_ls_mode(node)); \
2335 count = get_irn_n(node, 1); \
2336 if (is_ia32_Immediate(count)) { \
2337 int offset = get_ia32_immediate_attr_const(count)->offset; \
2338 if (offset == 1) { \
2339 bemit8(size == 8 ? 0xD0 : 0xD1); \
2340 bemit_mod_am(ext, node); \
2342 bemit8(size == 8 ? 0xC0 : 0xC1); \
2343 bemit_mod_am(ext, node); \
2347 bemit8(size == 8 ? 0xD2 : 0xD3); \
2348 bemit_mod_am(ext, node); \
2358 static void bemit_shld(const ir_node *node)
2360 const arch_register_t *in = arch_get_irn_register_in(node, n_ia32_ShlD_val_low);
2361 const arch_register_t *out = arch_get_irn_register_out(node, pn_ia32_ShlD_res);
2362 ir_node *count = get_irn_n(node, n_ia32_ShlD_count);
2364 if (is_ia32_Immediate(count)) {
2366 bemit_modrr(out, in);
2367 bemit8(get_ia32_immediate_attr_const(count)->offset);
2370 bemit_modrr(out, in);
2374 static void bemit_shrd(const ir_node *node)
2376 const arch_register_t *in = arch_get_irn_register_in(node, n_ia32_ShrD_val_low);
2377 const arch_register_t *out = arch_get_irn_register_out(node, pn_ia32_ShrD_res);
2378 ir_node *count = get_irn_n(node, n_ia32_ShrD_count);
2380 if (is_ia32_Immediate(count)) {
2382 bemit_modrr(out, in);
2383 bemit8(get_ia32_immediate_attr_const(count)->offset);
2386 bemit_modrr(out, in);
2390 static void bemit_sbb0(ir_node const *const node)
2392 arch_register_t const *const out = arch_get_irn_register_out(node, pn_ia32_Sbb0_res);
2393 unsigned char const reg = reg_gp_map[out->index];
2395 bemit8(MOD_REG | ENC_REG(reg) | ENC_RM(reg));
2399 * binary emitter for setcc.
2401 static void bemit_setcc(const ir_node *node)
2403 const arch_register_t *dreg = arch_get_irn_register_out(node, pn_ia32_Setcc_res);
2405 ia32_condition_code_t cc = get_ia32_condcode(node);
2406 cc = determine_final_cc(node, n_ia32_Setcc_eflags, cc);
2407 if (cc & ia32_cc_float_parity_cases) {
2408 if (cc & ia32_cc_negated) {
2411 bemit8(0x90 | pnc2cc(cc));
2412 bemit_modrm8(REG_LOW, dreg);
2417 bemit_modrm8(REG_HIGH, dreg);
2419 /* orb %>dreg, %<dreg */
2421 bemit_modrr8(REG_LOW, dreg, REG_HIGH, dreg);
2425 bemit8(0x90 | pnc2cc(cc));
2426 bemit_modrm8(REG_LOW, dreg);
2431 bemit_modrm8(REG_HIGH, dreg);
2433 /* andb %>dreg, %<dreg */
2435 bemit_modrr8(REG_LOW, dreg, REG_HIGH, dreg);
2440 bemit8(0x90 | pnc2cc(cc));
2441 bemit_modrm8(REG_LOW, dreg);
2445 static void bemit_bsf(ir_node const *const node)
2447 bemit_0f_unop_reg(node, 0xBC, n_ia32_Bsf_operand);
2450 static void bemit_bsr(ir_node const *const node)
2452 bemit_0f_unop_reg(node, 0xBD, n_ia32_Bsr_operand);
2455 static void bemit_bswap(ir_node const *const node)
2458 bemit_modru(arch_get_irn_register_out(node, pn_ia32_Bswap_res), 1);
2461 static void bemit_bt(ir_node const *const node)
2464 arch_register_t const *const lreg = arch_get_irn_register_in(node, n_ia32_Bt_left);
2465 ir_node const *const right = get_irn_n(node, n_ia32_Bt_right);
2466 if (is_ia32_Immediate(right)) {
2467 ia32_immediate_attr_t const *const attr = get_ia32_immediate_attr_const(right);
2468 int const offset = attr->offset;
2469 assert(!attr->symconst);
2470 assert(get_signed_imm_size(offset) == 1);
2472 bemit_modru(lreg, 4);
2476 bemit_modrr(lreg, arch_get_irn_register(right));
2480 static void bemit_cmovcc(const ir_node *node)
2482 const ia32_attr_t *attr = get_ia32_attr_const(node);
2483 int ins_permuted = attr->data.ins_permuted;
2484 const arch_register_t *out = arch_get_irn_register_out(node, pn_ia32_res);
2485 ia32_condition_code_t cc = get_ia32_condcode(node);
2486 const arch_register_t *in_true;
2487 const arch_register_t *in_false;
2489 cc = determine_final_cc(node, n_ia32_CMovcc_eflags, cc);
2491 in_true = arch_get_irn_register(get_irn_n(node, n_ia32_CMovcc_val_true));
2492 in_false = arch_get_irn_register(get_irn_n(node, n_ia32_CMovcc_val_false));
2494 /* should be same constraint fullfilled? */
2495 if (out == in_false) {
2496 /* yes -> nothing to do */
2497 } else if (out == in_true) {
2498 assert(get_ia32_op_type(node) == ia32_Normal);
2499 ins_permuted = !ins_permuted;
2503 bemit8(0x8B); // mov %in_false, %out
2504 bemit_modrr(in_false, out);
2508 cc = ia32_negate_condition_code(cc);
2510 if (cc & ia32_cc_float_parity_cases)
2511 panic("cmov can't handle parity float cases");
2514 bemit8(0x40 | pnc2cc(cc));
2515 if (get_ia32_op_type(node) == ia32_Normal) {
2516 bemit_modrr(in_true, out);
2518 bemit_mod_am(reg_gp_map[out->index], node);
2522 static void bemit_cmp(const ir_node *node)
2524 unsigned ls_size = get_mode_size_bits(get_ia32_ls_mode(node));
2530 right = get_irn_n(node, n_ia32_binary_right);
2531 if (is_ia32_Immediate(right)) {
2532 /* Use in-reg, because some instructions (cmp, test) have no out-reg. */
2533 const ir_node *op = get_irn_n(node, n_ia32_binary_right);
2534 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(op);
2537 if (attr->symconst != NULL) {
2540 /* check for sign extension */
2541 size = get_signed_imm_size(attr->offset);
2546 bemit8(0x80 | OP_16_32_IMM8);
2547 /* cmp has this special mode */
2548 if (get_ia32_op_type(node) == ia32_Normal) {
2549 const arch_register_t *reg = arch_get_irn_register_in(node, n_ia32_binary_left);
2550 bemit_modru(reg, 7);
2552 bemit_mod_am(7, node);
2554 bemit8((unsigned char)attr->offset);
2558 /* check for eax variant: this variant is shorter for 32bit immediates only */
2559 if (get_ia32_op_type(node) == ia32_Normal) {
2560 const arch_register_t *reg = arch_get_irn_register_in(node, n_ia32_binary_left);
2561 if (reg->index == REG_GP_EAX) {
2565 bemit_modru(reg, 7);
2569 bemit_mod_am(7, node);
2571 if (ls_size == 16) {
2572 bemit16(attr->offset);
2574 bemit_entity(attr->symconst, attr->sc_sign, attr->offset, false);
2578 panic("invalid imm size?!?");
2580 const arch_register_t *out = arch_get_irn_register_in(node, n_ia32_binary_left);
2582 if (get_ia32_op_type(node) == ia32_Normal) {
2583 const arch_register_t *op2 = arch_get_irn_register_in(node, n_ia32_binary_right);
2584 bemit_modrr(op2, out);
2586 bemit_mod_am(reg_gp_map[out->index], node);
2591 static void bemit_cmp8bit(const ir_node *node)
2593 ir_node *right = get_irn_n(node, n_ia32_binary_right);
2594 if (is_ia32_Immediate(right)) {
2595 if (get_ia32_op_type(node) == ia32_Normal) {
2596 const arch_register_t *out = arch_get_irn_register_in(node, n_ia32_Cmp_left);
2597 if (out->index == REG_GP_EAX) {
2601 bemit_modru(out, 7);
2605 bemit_mod_am(7, node);
2607 bemit8(get_ia32_immediate_attr_const(right)->offset);
2609 const arch_register_t *out = arch_get_irn_register_in(node, n_ia32_Cmp_left);
2611 if (get_ia32_op_type(node) == ia32_Normal) {
2612 const arch_register_t *in = arch_get_irn_register_in(node, n_ia32_Cmp_right);
2613 bemit_modrr(out, in);
2615 bemit_mod_am(reg_gp_map[out->index], node);
2620 static void bemit_test8bit(const ir_node *node)
2622 ir_node *right = get_irn_n(node, n_ia32_Test8Bit_right);
2623 if (is_ia32_Immediate(right)) {
2624 if (get_ia32_op_type(node) == ia32_Normal) {
2625 const arch_register_t *out = arch_get_irn_register_in(node, n_ia32_Test8Bit_left);
2626 if (out->index == REG_GP_EAX) {
2630 bemit_modru(out, 0);
2634 bemit_mod_am(0, node);
2636 bemit8(get_ia32_immediate_attr_const(right)->offset);
2638 const arch_register_t *out = arch_get_irn_register_in(node, n_ia32_Test8Bit_left);
2640 if (get_ia32_op_type(node) == ia32_Normal) {
2641 const arch_register_t *in = arch_get_irn_register_in(node, n_ia32_Test8Bit_right);
2642 bemit_modrr(out, in);
2644 bemit_mod_am(reg_gp_map[out->index], node);
2649 static void bemit_imul(const ir_node *node)
2651 ir_node *right = get_irn_n(node, n_ia32_IMul_right);
2652 /* Do we need the immediate form? */
2653 if (is_ia32_Immediate(right)) {
2654 int imm = get_ia32_immediate_attr_const(right)->offset;
2655 if (get_signed_imm_size(imm) == 1) {
2656 bemit_unop_reg(node, 0x6B, n_ia32_IMul_left);
2659 bemit_unop_reg(node, 0x69, n_ia32_IMul_left);
2663 bemit_0f_unop_reg(node, 0xAF, n_ia32_IMul_right);
2667 static void bemit_dec(const ir_node *node)
2669 const arch_register_t *out = arch_get_irn_register_out(node, pn_ia32_Dec_res);
2670 bemit8(0x48 + reg_gp_map[out->index]);
2673 static void bemit_inc(const ir_node *node)
2675 const arch_register_t *out = arch_get_irn_register_out(node, pn_ia32_Inc_res);
2676 bemit8(0x40 + reg_gp_map[out->index]);
2679 #define UNOPMEM(op, code, ext) \
2680 static void bemit_##op(const ir_node *node) \
2682 bemit_unop_mem(node, code, ext); \
2685 UNOPMEM(notmem, 0xF6, 2)
2686 UNOPMEM(negmem, 0xF6, 3)
2687 UNOPMEM(incmem, 0xFE, 0)
2688 UNOPMEM(decmem, 0xFE, 1)
2690 static void bemit_ldtls(const ir_node *node)
2692 const arch_register_t *out = arch_get_irn_register_out(node, 0);
2694 bemit8(0x65); // gs:
2695 if (out->index == REG_GP_EAX) {
2696 bemit8(0xA1); // movl 0, %eax
2698 bemit8(0x8B); // movl 0, %reg
2699 bemit8(MOD_IND | ENC_REG(reg_gp_map[out->index]) | ENC_RM(0x05));
2707 static void bemit_lea(const ir_node *node)
2709 const arch_register_t *out = arch_get_irn_register_out(node, 0);
2711 bemit_mod_am(reg_gp_map[out->index], node);
2714 /* helper function for bemit_minus64bit */
2715 static void bemit_helper_mov(const arch_register_t *src, const arch_register_t *dst)
2717 bemit8(0x8B); // movl %src, %dst
2718 bemit_modrr(src, dst);
2721 /* helper function for bemit_minus64bit */
2722 static void bemit_helper_neg(const arch_register_t *reg)
2724 bemit8(0xF7); // negl %reg
2725 bemit_modru(reg, 3);
2728 /* helper function for bemit_minus64bit */
2729 static void bemit_helper_sbb0(const arch_register_t *reg)
2731 bemit8(0x83); // sbbl $0, %reg
2732 bemit_modru(reg, 3);
2736 /* helper function for bemit_minus64bit */
2737 static void bemit_helper_sbb(const arch_register_t *src, const arch_register_t *dst)
2739 bemit8(0x1B); // sbbl %src, %dst
2740 bemit_modrr(src, dst);
2743 /* helper function for bemit_minus64bit */
2744 static void bemit_helper_xchg(const arch_register_t *src, const arch_register_t *dst)
2746 if (src->index == REG_GP_EAX) {
2747 bemit8(0x90 + reg_gp_map[dst->index]); // xchgl %eax, %dst
2748 } else if (dst->index == REG_GP_EAX) {
2749 bemit8(0x90 + reg_gp_map[src->index]); // xchgl %src, %eax
2751 bemit8(0x87); // xchgl %src, %dst
2752 bemit_modrr(src, dst);
2756 /* helper function for bemit_minus64bit */
2757 static void bemit_helper_zero(const arch_register_t *reg)
2759 bemit8(0x33); // xorl %reg, %reg
2760 bemit_modrr(reg, reg);
2763 static void bemit_minus64bit(const ir_node *node)
2765 const arch_register_t *in_lo = arch_get_irn_register_in(node, 0);
2766 const arch_register_t *in_hi = arch_get_irn_register_in(node, 1);
2767 const arch_register_t *out_lo = arch_get_irn_register_out(node, 0);
2768 const arch_register_t *out_hi = arch_get_irn_register_out(node, 1);
2770 if (out_lo == in_lo) {
2771 if (out_hi != in_hi) {
2772 /* a -> a, b -> d */
2775 /* a -> a, b -> b */
2778 } else if (out_lo == in_hi) {
2779 if (out_hi == in_lo) {
2780 /* a -> b, b -> a */
2781 bemit_helper_xchg(in_lo, in_hi);
2784 /* a -> b, b -> d */
2785 bemit_helper_mov(in_hi, out_hi);
2786 bemit_helper_mov(in_lo, out_lo);
2790 if (out_hi == in_lo) {
2791 /* a -> c, b -> a */
2792 bemit_helper_mov(in_lo, out_lo);
2794 } else if (out_hi == in_hi) {
2795 /* a -> c, b -> b */
2796 bemit_helper_mov(in_lo, out_lo);
2799 /* a -> c, b -> d */
2800 bemit_helper_mov(in_lo, out_lo);
2806 bemit_helper_neg( out_hi);
2807 bemit_helper_neg( out_lo);
2808 bemit_helper_sbb0(out_hi);
2812 bemit_helper_zero(out_hi);
2813 bemit_helper_neg( out_lo);
2814 bemit_helper_sbb( in_hi, out_hi);
2818 * Emit a single opcode.
2820 #define EMIT_SINGLEOP(op, code) \
2821 static void bemit_ ## op(const ir_node *node) { \
2826 //EMIT_SINGLEOP(daa, 0x27)
2827 //EMIT_SINGLEOP(das, 0x2F)
2828 //EMIT_SINGLEOP(aaa, 0x37)
2829 //EMIT_SINGLEOP(aas, 0x3F)
2830 //EMIT_SINGLEOP(nop, 0x90)
2831 EMIT_SINGLEOP(cwtl, 0x98)
2832 EMIT_SINGLEOP(cltd, 0x99)
2833 //EMIT_SINGLEOP(fwait, 0x9B)
2834 EMIT_SINGLEOP(sahf, 0x9E)
2835 //EMIT_SINGLEOP(popf, 0x9D)
2836 EMIT_SINGLEOP(leave, 0xC9)
2837 EMIT_SINGLEOP(int3, 0xCC)
2838 //EMIT_SINGLEOP(iret, 0xCF)
2839 //EMIT_SINGLEOP(xlat, 0xD7)
2840 //EMIT_SINGLEOP(lock, 0xF0)
2841 EMIT_SINGLEOP(rep, 0xF3)
2842 //EMIT_SINGLEOP(halt, 0xF4)
2843 EMIT_SINGLEOP(cmc, 0xF5)
2844 EMIT_SINGLEOP(stc, 0xF9)
2845 //EMIT_SINGLEOP(cli, 0xFA)
2846 //EMIT_SINGLEOP(sti, 0xFB)
2847 //EMIT_SINGLEOP(std, 0xFD)
2850 * Emits a MOV out, [MEM].
2852 static void bemit_load(const ir_node *node)
2854 const arch_register_t *out = arch_get_irn_register_out(node, 0);
2856 if (out->index == REG_GP_EAX) {
2857 ir_node *base = get_irn_n(node, n_ia32_base);
2858 int has_base = !is_ia32_NoReg_GP(base);
2859 ir_node *idx = get_irn_n(node, n_ia32_index);
2860 int has_index = !is_ia32_NoReg_GP(idx);
2861 if (!has_base && !has_index) {
2862 ir_entity *ent = get_ia32_am_sc(node);
2863 int offs = get_ia32_am_offs_int(node);
2864 /* load from constant address to EAX can be encoded
2867 bemit_entity(ent, 0, offs, false);
2872 bemit_mod_am(reg_gp_map[out->index], node);
2876 * Emits a MOV [mem], in.
2878 static void bemit_store(const ir_node *node)
2880 const ir_node *value = get_irn_n(node, n_ia32_Store_val);
2881 unsigned size = get_mode_size_bits(get_ia32_ls_mode(node));
2883 if (is_ia32_Immediate(value)) {
2886 bemit_mod_am(0, node);
2887 bemit8(get_ia32_immediate_attr_const(value)->offset);
2888 } else if (size == 16) {
2891 bemit_mod_am(0, node);
2892 bemit16(get_ia32_immediate_attr_const(value)->offset);
2895 bemit_mod_am(0, node);
2896 bemit_immediate(value, false);
2899 const arch_register_t *in = arch_get_irn_register_in(node, n_ia32_Store_val);
2901 if (in->index == REG_GP_EAX) {
2902 ir_node *base = get_irn_n(node, n_ia32_base);
2903 int has_base = !is_ia32_NoReg_GP(base);
2904 ir_node *idx = get_irn_n(node, n_ia32_index);
2905 int has_index = !is_ia32_NoReg_GP(idx);
2906 if (!has_base && !has_index) {
2907 ir_entity *ent = get_ia32_am_sc(node);
2908 int offs = get_ia32_am_offs_int(node);
2909 /* store to constant address from EAX can be encoded as
2910 * 0xA2/0xA3 [offset]*/
2918 bemit_entity(ent, 0, offs, false);
2930 bemit_mod_am(reg_gp_map[in->index], node);
2934 static void bemit_conv_i2i(const ir_node *node)
2939 ir_mode *const smaller_mode = get_ia32_ls_mode(node);
2940 unsigned opcode = 0xB6;
2941 if (mode_is_signed(smaller_mode)) opcode |= 0x08;
2942 if (get_mode_size_bits(smaller_mode) == 16) opcode |= 0x01;
2943 bemit_0f_unop_reg(node, opcode, n_ia32_Conv_I2I_val);
2946 static void bemit_popcnt(ir_node const *const node)
2949 bemit_0f_unop_reg(node, 0xB8, n_ia32_Popcnt_operand);
2955 static void bemit_push(const ir_node *node)
2957 const ir_node *value = get_irn_n(node, n_ia32_Push_val);
2959 if (is_ia32_Immediate(value)) {
2960 const ia32_immediate_attr_t *attr
2961 = get_ia32_immediate_attr_const(value);
2962 unsigned size = get_signed_imm_size(attr->offset);
2968 bemit8((unsigned char)attr->offset);
2973 bemit_immediate(value, false);
2976 } else if (is_ia32_NoReg_GP(value)) {
2978 bemit_mod_am(6, node);
2980 const arch_register_t *reg = arch_get_irn_register_in(node, n_ia32_Push_val);
2981 bemit8(0x50 + reg_gp_map[reg->index]);
2988 static void bemit_pop(const ir_node *node)
2990 const arch_register_t *reg = arch_get_irn_register_out(node, pn_ia32_Pop_res);
2991 bemit8(0x58 + reg_gp_map[reg->index]);
2994 static void bemit_popmem(const ir_node *node)
2997 bemit_mod_am(0, node);
3000 static void bemit_call(const ir_node *node)
3002 ir_node *proc = get_irn_n(node, n_ia32_Call_addr);
3004 if (is_ia32_Immediate(proc)) {
3006 bemit_immediate(proc, true);
3008 bemit_unop(node, 0xFF, 2, n_ia32_Call_addr);
3012 static void bemit_jmp(const ir_node *dest_block)
3015 bemit_jmp_destination(dest_block);
3018 static void bemit_jump(const ir_node *node)
3020 if (can_be_fallthrough(node))
3023 bemit_jmp(get_cfop_target_block(node));
3026 static void bemit_jcc(ia32_condition_code_t pnc, const ir_node *dest_block)
3028 unsigned char cc = pnc2cc(pnc);
3031 bemit_jmp_destination(dest_block);
3034 static void bemit_jp(bool odd, const ir_node *dest_block)
3038 bemit_jmp_destination(dest_block);
3041 static void bemit_ia32_jcc(const ir_node *node)
3043 ia32_condition_code_t cc = get_ia32_condcode(node);
3044 const ir_node *dest_true;
3045 const ir_node *dest_false;
3047 cc = determine_final_cc(node, 0, cc);
3049 /* get both Projs */
3050 ir_node const *proj_true = be_get_Proj_for_pn(node, pn_ia32_Jcc_true);
3051 assert(proj_true && "Jcc without true Proj");
3053 ir_node const *proj_false = be_get_Proj_for_pn(node, pn_ia32_Jcc_false);
3054 assert(proj_false && "Jcc without false Proj");
3056 if (can_be_fallthrough(proj_true)) {
3057 /* exchange both proj's so the second one can be omitted */
3058 const ir_node *t = proj_true;
3060 proj_true = proj_false;
3062 cc = ia32_negate_condition_code(cc);
3065 dest_true = get_cfop_target_block(proj_true);
3066 dest_false = get_cfop_target_block(proj_false);
3068 if (cc & ia32_cc_float_parity_cases) {
3069 /* Some floating point comparisons require a test of the parity flag,
3070 * which indicates that the result is unordered */
3071 if (cc & ia32_cc_negated) {
3072 bemit_jp(false, dest_true);
3074 /* we need a local label if the false proj is a fallthrough
3075 * as the falseblock might have no label emitted then */
3076 if (can_be_fallthrough(proj_false)) {
3078 bemit8(0x06); // jp + 6
3080 bemit_jp(false, dest_false);
3084 bemit_jcc(cc, dest_true);
3086 /* the second Proj might be a fallthrough */
3087 if (can_be_fallthrough(proj_false)) {
3088 /* it's a fallthrough */
3090 bemit_jmp(dest_false);
3094 static void bemit_switchjmp(const ir_node *node)
3096 ir_entity *jump_table = get_ia32_am_sc(node);
3097 const ir_switch_table *table = get_ia32_switch_table(node);
3099 bemit8(0xFF); // jmp *tbl.label(,%in,4)
3100 bemit_mod_am(0x05, node);
3102 be_emit_jump_table(node, table, jump_table, get_cfop_target_block);
3108 static void bemit_return(const ir_node *node)
3110 unsigned pop = be_Return_get_pop(node);
3111 if (pop > 0 || be_Return_get_emit_pop(node)) {
3113 assert(pop <= 0xffff);
3120 static void bemit_subsp(const ir_node *node)
3122 const arch_register_t *out;
3125 /* mov %esp, %out */
3127 out = arch_get_irn_register_out(node, 1);
3128 bemit8(MOD_REG | ENC_REG(reg_gp_map[out->index]) | ENC_RM(0x04));
3131 static void bemit_incsp(const ir_node *node)
3134 const arch_register_t *reg;
3138 offs = be_get_IncSP_offset(node);
3149 size = get_signed_imm_size(offs);
3150 bemit8(size == 1 ? 0x83 : 0x81);
3152 reg = arch_get_irn_register_out(node, 0);
3153 bemit_modru(reg, ext);
3162 static void bemit_copybi(const ir_node *node)
3164 unsigned size = get_ia32_copyb_size(node);
3166 bemit8(0xA4); // movsb
3169 bemit8(0xA5); // movsw
3173 bemit8(0xA5); // movsl
3177 static void bemit_fbinop(ir_node const *const node, unsigned const op_fwd, unsigned const op_rev)
3179 ia32_x87_attr_t const *const attr = get_ia32_x87_attr_const(node);
3180 unsigned const op = attr->attr.data.ins_permuted ? op_rev : op_fwd;
3181 if (get_ia32_op_type(node) == ia32_Normal) {
3182 assert(!attr->pop || attr->res_in_reg);
3184 unsigned char op0 = 0xD8;
3185 if (attr->res_in_reg) op0 |= 0x04;
3186 if (attr->pop) op0 |= 0x02;
3189 bemit8(MOD_REG | ENC_REG(op) | ENC_RM(attr->reg->index));
3194 unsigned const size = get_mode_size_bits(get_ia32_ls_mode(node));
3195 bemit8(size == 32 ? 0xD8 : 0xDC);
3196 bemit_mod_am(op, node);
3200 static void bemit_fop_reg(ir_node const *const node, unsigned char const op0, unsigned char const op1)
3203 bemit8(op1 + get_ia32_x87_attr_const(node)->reg->index);
3206 static void bemit_fabs(const ir_node *node)
3214 static void bemit_fadd(const ir_node *node)
3216 bemit_fbinop(node, 0, 0);
3219 static void bemit_fchs(const ir_node *node)
3227 static void bemit_fdiv(const ir_node *node)
3229 bemit_fbinop(node, 6, 7);
3232 static void bemit_ffreep(ir_node const *const node)
3234 bemit_fop_reg(node, 0xDF, 0xC0);
3237 static void bemit_fild(const ir_node *node)
3239 switch (get_mode_size_bits(get_ia32_ls_mode(node))) {
3241 bemit8(0xDF); // filds
3242 bemit_mod_am(0, node);
3246 bemit8(0xDB); // fildl
3247 bemit_mod_am(0, node);
3251 bemit8(0xDF); // fildll
3252 bemit_mod_am(5, node);
3256 panic("invalid mode size");
3260 static void bemit_fist(const ir_node *node)
3263 unsigned const size = get_mode_size_bits(get_ia32_ls_mode(node));
3265 case 16: bemit8(0xDF); op = 2; break; // fist[p]s
3266 case 32: bemit8(0xDB); op = 2; break; // fist[p]l
3267 case 64: bemit8(0xDF); op = 6; break; // fistpll
3268 default: panic("invalid mode size");
3270 if (get_ia32_x87_attr_const(node)->pop)
3272 // There is only a pop variant for 64 bit integer store.
3273 assert(size < 64 || get_ia32_x87_attr_const(node)->pop);
3274 bemit_mod_am(op, node);
3277 static void bemit_fisttp(ir_node const *const node)
3279 switch (get_mode_size_bits(get_ia32_ls_mode(node))) {
3280 case 16: bemit8(0xDF); break; // fisttps
3281 case 32: bemit8(0xDB); break; // fisttpl
3282 case 64: bemit8(0xDD); break; // fisttpll
3283 default: panic("Invalid mode size");
3285 bemit_mod_am(1, node);
3288 static void bemit_fld(const ir_node *node)
3290 switch (get_mode_size_bits(get_ia32_ls_mode(node))) {
3292 bemit8(0xD9); // flds
3293 bemit_mod_am(0, node);
3297 bemit8(0xDD); // fldl
3298 bemit_mod_am(0, node);
3303 bemit8(0xDB); // fldt
3304 bemit_mod_am(5, node);
3308 panic("invalid mode size");
3312 static void bemit_fld1(const ir_node *node)
3316 bemit8(0xE8); // fld1
3319 static void bemit_fldcw(const ir_node *node)
3321 bemit8(0xD9); // fldcw
3322 bemit_mod_am(5, node);
3325 static void bemit_fldz(const ir_node *node)
3329 bemit8(0xEE); // fldz
3332 static void bemit_fmul(const ir_node *node)
3334 bemit_fbinop(node, 1, 1);
3337 static void bemit_fpop(const ir_node *node)
3339 bemit_fop_reg(node, 0xDD, 0xD8);
3342 static void bemit_fpush(const ir_node *node)
3344 bemit_fop_reg(node, 0xD9, 0xC0);
3347 static void bemit_fpushcopy(const ir_node *node)
3349 bemit_fop_reg(node, 0xD9, 0xC0);
3352 static void bemit_fst(const ir_node *node)
3355 unsigned const size = get_mode_size_bits(get_ia32_ls_mode(node));
3357 case 32: bemit8(0xD9); op = 2; break; // fst[p]s
3358 case 64: bemit8(0xDD); op = 2; break; // fst[p]l
3360 case 96: bemit8(0xDB); op = 6; break; // fstpt
3361 default: panic("invalid mode size");
3363 if (get_ia32_x87_attr_const(node)->pop)
3365 // There is only a pop variant for long double store.
3366 assert(size < 80 || get_ia32_x87_attr_const(node)->pop);
3367 bemit_mod_am(op, node);
3370 static void bemit_fsub(const ir_node *node)
3372 bemit_fbinop(node, 4, 5);
3375 static void bemit_fnstcw(const ir_node *node)
3377 bemit8(0xD9); // fnstcw
3378 bemit_mod_am(7, node);
3381 static void bemit_fnstsw(void)
3383 bemit8(0xDF); // fnstsw %ax
3387 static void bemit_ftstfnstsw(const ir_node *node)
3391 bemit8(0xD9); // ftst
3396 static void bemit_fucomi(const ir_node *node)
3398 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
3399 bemit8(attr->pop ? 0xDF : 0xDB); // fucom[p]i
3400 bemit8(0xE8 + attr->reg->index);
3403 static void bemit_fucomfnstsw(const ir_node *node)
3405 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
3406 bemit8(0xDD); // fucom[p]
3407 bemit8((attr->pop ? 0xE8 : 0xE0) + attr->reg->index);
3411 static void bemit_fucomppfnstsw(const ir_node *node)
3415 bemit8(0xDA); // fucompp
3420 static void bemit_fxch(const ir_node *node)
3422 bemit_fop_reg(node, 0xD9, 0xC8);
3425 static void ia32_register_binary_emitters(void)
3427 /* first clear the generic function pointer for all ops */
3428 ir_clear_opcodes_generic_func();
3430 /* benode emitter */
3431 be_set_emitter(op_be_Copy, bemit_copy);
3432 be_set_emitter(op_be_CopyKeep, bemit_copy);
3433 be_set_emitter(op_be_IncSP, bemit_incsp);
3434 be_set_emitter(op_be_Perm, bemit_perm);
3435 be_set_emitter(op_be_Return, bemit_return);
3436 be_set_emitter(op_ia32_Adc, bemit_adc);
3437 be_set_emitter(op_ia32_Add, bemit_add);
3438 be_set_emitter(op_ia32_AddMem, bemit_addmem);
3439 be_set_emitter(op_ia32_AddMem8Bit, bemit_addmem8bit);
3440 be_set_emitter(op_ia32_And, bemit_and);
3441 be_set_emitter(op_ia32_AndMem, bemit_andmem);
3442 be_set_emitter(op_ia32_AndMem8Bit, bemit_andmem8bit);
3443 be_set_emitter(op_ia32_Asm, emit_ia32_Asm); // TODO implement binary emitter
3444 be_set_emitter(op_ia32_Breakpoint, bemit_int3);
3445 be_set_emitter(op_ia32_Bsf, bemit_bsf);
3446 be_set_emitter(op_ia32_Bsr, bemit_bsr);
3447 be_set_emitter(op_ia32_Bswap, bemit_bswap);
3448 be_set_emitter(op_ia32_Bt, bemit_bt);
3449 be_set_emitter(op_ia32_CMovcc, bemit_cmovcc);
3450 be_set_emitter(op_ia32_Call, bemit_call);
3451 be_set_emitter(op_ia32_Cltd, bemit_cltd);
3452 be_set_emitter(op_ia32_Cmc, bemit_cmc);
3453 be_set_emitter(op_ia32_Cmp, bemit_cmp);
3454 be_set_emitter(op_ia32_Cmp8Bit, bemit_cmp8bit);
3455 be_set_emitter(op_ia32_Const, bemit_mov_const);
3456 be_set_emitter(op_ia32_Conv_I2I, bemit_conv_i2i);
3457 be_set_emitter(op_ia32_Conv_I2I8Bit, bemit_conv_i2i);
3458 be_set_emitter(op_ia32_CopyB_i, bemit_copybi);
3459 be_set_emitter(op_ia32_Cwtl, bemit_cwtl);
3460 be_set_emitter(op_ia32_Dec, bemit_dec);
3461 be_set_emitter(op_ia32_DecMem, bemit_decmem);
3462 be_set_emitter(op_ia32_Div, bemit_div);
3463 be_set_emitter(op_ia32_FldCW, bemit_fldcw);
3464 be_set_emitter(op_ia32_FnstCW, bemit_fnstcw);
3465 be_set_emitter(op_ia32_FtstFnstsw, bemit_ftstfnstsw);
3466 be_set_emitter(op_ia32_FucomFnstsw, bemit_fucomfnstsw);
3467 be_set_emitter(op_ia32_Fucomi, bemit_fucomi);
3468 be_set_emitter(op_ia32_FucomppFnstsw, bemit_fucomppfnstsw);
3469 be_set_emitter(op_ia32_IDiv, bemit_idiv);
3470 be_set_emitter(op_ia32_IJmp, bemit_ijmp);
3471 be_set_emitter(op_ia32_IMul, bemit_imul);
3472 be_set_emitter(op_ia32_IMul1OP, bemit_imul1op);
3473 be_set_emitter(op_ia32_Inc, bemit_inc);
3474 be_set_emitter(op_ia32_IncMem, bemit_incmem);
3475 be_set_emitter(op_ia32_Jcc, bemit_ia32_jcc);
3476 be_set_emitter(op_ia32_Jmp, bemit_jump);
3477 be_set_emitter(op_ia32_LdTls, bemit_ldtls);
3478 be_set_emitter(op_ia32_Lea, bemit_lea);
3479 be_set_emitter(op_ia32_Leave, bemit_leave);
3480 be_set_emitter(op_ia32_Load, bemit_load);
3481 be_set_emitter(op_ia32_Minus64Bit, bemit_minus64bit);
3482 be_set_emitter(op_ia32_Mul, bemit_mul);
3483 be_set_emitter(op_ia32_Neg, bemit_neg);
3484 be_set_emitter(op_ia32_NegMem, bemit_negmem);
3485 be_set_emitter(op_ia32_Not, bemit_not);
3486 be_set_emitter(op_ia32_NotMem, bemit_notmem);
3487 be_set_emitter(op_ia32_Or, bemit_or);
3488 be_set_emitter(op_ia32_OrMem, bemit_ormem);
3489 be_set_emitter(op_ia32_OrMem8Bit, bemit_ormem8bit);
3490 be_set_emitter(op_ia32_Pop, bemit_pop);
3491 be_set_emitter(op_ia32_PopEbp, bemit_pop);
3492 be_set_emitter(op_ia32_PopMem, bemit_popmem);
3493 be_set_emitter(op_ia32_Popcnt, bemit_popcnt);
3494 be_set_emitter(op_ia32_Push, bemit_push);
3495 be_set_emitter(op_ia32_RepPrefix, bemit_rep);
3496 be_set_emitter(op_ia32_Rol, bemit_rol);
3497 be_set_emitter(op_ia32_RolMem, bemit_rolmem);
3498 be_set_emitter(op_ia32_Ror, bemit_ror);
3499 be_set_emitter(op_ia32_RorMem, bemit_rormem);
3500 be_set_emitter(op_ia32_Sahf, bemit_sahf);
3501 be_set_emitter(op_ia32_Sar, bemit_sar);
3502 be_set_emitter(op_ia32_SarMem, bemit_sarmem);
3503 be_set_emitter(op_ia32_Sbb, bemit_sbb);
3504 be_set_emitter(op_ia32_Sbb0, bemit_sbb0);
3505 be_set_emitter(op_ia32_Setcc, bemit_setcc);
3506 be_set_emitter(op_ia32_Shl, bemit_shl);
3507 be_set_emitter(op_ia32_ShlD, bemit_shld);
3508 be_set_emitter(op_ia32_ShlMem, bemit_shlmem);
3509 be_set_emitter(op_ia32_Shr, bemit_shr);
3510 be_set_emitter(op_ia32_ShrD, bemit_shrd);
3511 be_set_emitter(op_ia32_ShrMem, bemit_shrmem);
3512 be_set_emitter(op_ia32_Stc, bemit_stc);
3513 be_set_emitter(op_ia32_Store, bemit_store);
3514 be_set_emitter(op_ia32_Store8Bit, bemit_store);
3515 be_set_emitter(op_ia32_Sub, bemit_sub);
3516 be_set_emitter(op_ia32_SubMem, bemit_submem);
3517 be_set_emitter(op_ia32_SubMem8Bit, bemit_submem8bit);
3518 be_set_emitter(op_ia32_SubSP, bemit_subsp);
3519 be_set_emitter(op_ia32_SwitchJmp, bemit_switchjmp);
3520 be_set_emitter(op_ia32_Test, bemit_test);
3521 be_set_emitter(op_ia32_Test8Bit, bemit_test8bit);
3522 be_set_emitter(op_ia32_Xor, bemit_xor);
3523 be_set_emitter(op_ia32_Xor0, bemit_xor0);
3524 be_set_emitter(op_ia32_XorMem, bemit_xormem);
3525 be_set_emitter(op_ia32_XorMem8Bit, bemit_xormem8bit);
3526 be_set_emitter(op_ia32_fabs, bemit_fabs);
3527 be_set_emitter(op_ia32_fadd, bemit_fadd);
3528 be_set_emitter(op_ia32_fchs, bemit_fchs);
3529 be_set_emitter(op_ia32_fdiv, bemit_fdiv);
3530 be_set_emitter(op_ia32_ffreep, bemit_ffreep);
3531 be_set_emitter(op_ia32_fild, bemit_fild);
3532 be_set_emitter(op_ia32_fist, bemit_fist);
3533 be_set_emitter(op_ia32_fisttp, bemit_fisttp);
3534 be_set_emitter(op_ia32_fld, bemit_fld);
3535 be_set_emitter(op_ia32_fld1, bemit_fld1);
3536 be_set_emitter(op_ia32_fldz, bemit_fldz);
3537 be_set_emitter(op_ia32_fmul, bemit_fmul);
3538 be_set_emitter(op_ia32_fpop, bemit_fpop);
3539 be_set_emitter(op_ia32_fpush, bemit_fpush);
3540 be_set_emitter(op_ia32_fpushCopy, bemit_fpushcopy);
3541 be_set_emitter(op_ia32_fst, bemit_fst);
3542 be_set_emitter(op_ia32_fsub, bemit_fsub);
3543 be_set_emitter(op_ia32_fxch, bemit_fxch);
3545 /* ignore the following nodes */
3546 be_set_emitter(op_Phi, be_emit_nothing);
3547 be_set_emitter(op_be_Keep, be_emit_nothing);
3548 be_set_emitter(op_be_Start, be_emit_nothing);
3549 be_set_emitter(op_ia32_ProduceVal, be_emit_nothing);
3550 be_set_emitter(op_ia32_Unknown, be_emit_nothing);
3553 static void gen_binary_block(ir_node *block)
3555 ia32_emit_block_header(block);
3557 /* emit the contents of the block */
3558 sched_foreach(block, node) {
3559 ia32_emit_node(node);
3563 void ia32_gen_binary_routine(ir_graph *irg)
3565 ir_entity *entity = get_irg_entity(irg);
3566 const arch_env_t *arch_env = be_get_irg_arch_env(irg);
3567 ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
3568 ir_node **blk_sched = irg_data->blk_sched;
3570 parameter_dbg_info_t *infos;
3572 isa = (ia32_isa_t*) arch_env;
3574 ia32_register_binary_emitters();
3576 infos = construct_parameter_infos(irg);
3577 be_gas_emit_function_prolog(entity, ia32_cg_config.function_alignment,
3581 /* we use links to point to target blocks */
3582 ir_reserve_resources(irg, IR_RESOURCE_IRN_LINK);
3583 irg_block_walk_graph(irg, ia32_gen_labels, NULL, NULL);
3585 /* initialize next block links */
3586 n = ARR_LEN(blk_sched);
3587 for (i = 0; i < n; ++i) {
3588 ir_node *block = blk_sched[i];
3589 ir_node *prev = i > 0 ? blk_sched[i-1] : NULL;
3591 set_irn_link(block, prev);
3594 for (i = 0; i < n; ++i) {
3595 ir_node *block = blk_sched[i];
3596 gen_binary_block(block);
3599 be_gas_emit_function_epilog(entity);
3601 ir_free_resources(irg, IR_RESOURCE_IRN_LINK);
3605 void ia32_init_emitter(void)
3607 lc_opt_entry_t *be_grp;
3608 lc_opt_entry_t *ia32_grp;
3610 be_grp = lc_opt_get_grp(firm_opt_get_root(), "be");
3611 ia32_grp = lc_opt_get_grp(be_grp, "ia32");
3613 lc_opt_add_table(ia32_grp, ia32_emitter_options);
3617 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.emitter");