2 * Copyright (C) 1995-2011 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This file implements the ia32 node emitter.
23 * @author Christian Wuerdig, Matthias Braun
25 * Summary table for x86 floatingpoint compares:
26 * (remember effect of unordered on x86: ZF=1, PF=1, CF=1)
34 * pnc_Leg => NP (ordered)
56 #include "iredges_t.h"
60 #include "raw_bitset.h"
69 #include "beemitter.h"
73 #include "ia32_emitter.h"
74 #include "ia32_common_transform.h"
75 #include "gen_ia32_emitter.h"
76 #include "gen_ia32_regalloc_if.h"
77 #include "ia32_nodes_attr.h"
78 #include "ia32_new_nodes.h"
79 #include "ia32_architecture.h"
80 #include "bearch_ia32_t.h"
82 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
84 static const ia32_isa_t *isa;
85 static char pic_base_label[128];
86 static ir_label_t exc_label_id;
87 static int mark_spill_reload = 0;
90 static bool sp_relative;
91 static int frame_type_size;
92 static int callframe_offset;
94 /** Return the next block in Block schedule */
95 static ir_node *get_prev_block_sched(const ir_node *block)
97 return (ir_node*)get_irn_link(block);
100 /** Checks if the current block is a fall-through target. */
101 static int is_fallthrough(const ir_node *cfgpred)
105 if (!is_Proj(cfgpred))
107 pred = get_Proj_pred(cfgpred);
108 if (is_ia32_SwitchJmp(pred))
115 * returns non-zero if the given block needs a label
116 * because of being a jump-target (and not a fall-through)
118 static int block_needs_label(const ir_node *block)
121 int n_cfgpreds = get_Block_n_cfgpreds(block);
123 if (get_Block_entity(block) != NULL)
126 if (n_cfgpreds == 0) {
128 } else if (n_cfgpreds == 1) {
129 ir_node *cfgpred = get_Block_cfgpred(block, 0);
130 ir_node *cfgpred_block = get_nodes_block(cfgpred);
132 if (get_prev_block_sched(block) == cfgpred_block
133 && is_fallthrough(cfgpred)) {
142 * Add a number to a prefix. This number will not be used a second time.
144 static char *get_unique_label(char *buf, size_t buflen, const char *prefix)
146 static unsigned long id = 0;
147 snprintf(buf, buflen, "%s%s%lu", be_gas_get_private_prefix(), prefix, ++id);
152 * Emit the name of the 8bit low register
154 static void emit_8bit_register(const arch_register_t *reg)
156 const char *reg_name = arch_register_get_name(reg);
157 assert(reg->index == REG_GP_EAX || reg->index == REG_GP_EBX
158 || reg->index == REG_GP_ECX || reg->index == REG_GP_EDX);
161 be_emit_char(reg_name[1]); /* get the basic name of the register */
166 * Emit the name of the 8bit high register
168 static void emit_8bit_register_high(const arch_register_t *reg)
170 const char *reg_name = arch_register_get_name(reg);
171 assert(reg->index == REG_GP_EAX || reg->index == REG_GP_EBX
172 || reg->index == REG_GP_ECX || reg->index == REG_GP_EDX);
175 be_emit_char(reg_name[1]); /* get the basic name of the register */
179 static void emit_16bit_register(const arch_register_t *reg)
181 const char *reg_name = arch_register_get_name(reg);
184 be_emit_string(reg_name+1); /* skip the 'e' prefix of the 32bit names */
188 * emit a register, possible shortened by a mode
190 * @param reg the register
191 * @param mode the mode of the register or NULL for full register
193 static void emit_register(const arch_register_t *reg, const ir_mode *mode)
195 const char *reg_name;
198 int size = get_mode_size_bits(mode);
200 case 8: emit_8bit_register(reg); return;
201 case 16: emit_16bit_register(reg); return;
203 assert(mode_is_float(mode) || size == 32);
206 reg_name = arch_register_get_name(reg);
209 be_emit_string(reg_name);
212 static void ia32_emit_entity(ir_entity *entity, int no_pic_adjust)
214 be_gas_emit_entity(entity);
216 if (get_entity_owner(entity) == get_tls_type()) {
217 if (!entity_has_definition(entity)) {
218 be_emit_cstring("@INDNTPOFF");
220 be_emit_cstring("@NTPOFF");
224 if (do_pic && !no_pic_adjust) {
226 be_emit_string(pic_base_label);
230 static void emit_ia32_Immediate_no_prefix(const ir_node *node)
232 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(node);
234 if (attr->symconst != NULL) {
237 ia32_emit_entity(attr->symconst, attr->no_pic_adjust);
239 if (attr->symconst == NULL || attr->offset != 0) {
240 if (attr->symconst != NULL) {
241 be_emit_irprintf("%+d", attr->offset);
243 be_emit_irprintf("0x%X", attr->offset);
248 static void emit_ia32_Immediate(const ir_node *node)
251 emit_ia32_Immediate_no_prefix(node);
254 static void ia32_emit_mode_suffix_mode(const ir_mode *mode)
256 assert(mode_is_int(mode) || mode_is_reference(mode));
257 switch (get_mode_size_bits(mode)) {
258 case 8: be_emit_char('b'); return;
259 case 16: be_emit_char('w'); return;
260 case 32: be_emit_char('l'); return;
261 /* gas docu says q is the suffix but gcc, objdump and icc use ll
263 case 64: be_emit_cstring("ll"); return;
265 panic("Can't output mode_suffix for %+F", mode);
268 static void ia32_emit_x87_mode_suffix(ir_node const *const node)
272 /* we only need to emit the mode on address mode */
273 if (get_ia32_op_type(node) == ia32_Normal)
276 mode = get_ia32_ls_mode(node);
277 assert(mode != NULL);
279 if (mode_is_float(mode)) {
280 switch (get_mode_size_bits(mode)) {
281 case 32: be_emit_char('s'); return;
282 case 64: be_emit_char('l'); return;
283 /* long doubles have different sizes due to alignment on different
287 case 128: be_emit_char('t'); return;
290 assert(mode_is_int(mode) || mode_is_reference(mode));
291 switch (get_mode_size_bits(mode)) {
292 case 16: be_emit_char('s'); return;
293 case 32: be_emit_char('l'); return;
294 /* gas docu says q is the suffix but gcc, objdump and icc use ll
296 case 64: be_emit_cstring("ll"); return;
299 panic("Can't output mode_suffix for %+F", mode);
302 static char get_xmm_mode_suffix(ir_mode *mode)
304 assert(mode_is_float(mode));
305 switch (get_mode_size_bits(mode)) {
308 default: panic("Invalid XMM mode");
312 static void ia32_emit_xmm_mode_suffix(ir_node const *const node)
314 ir_mode *mode = get_ia32_ls_mode(node);
315 assert(mode != NULL);
316 be_emit_char(get_xmm_mode_suffix(mode));
320 * Returns the target block for a control flow node.
322 static ir_node *get_cfop_target_block(const ir_node *irn)
324 assert(get_irn_mode(irn) == mode_X);
325 return (ir_node*)get_irn_link(irn);
329 * Emits the target label for a control flow node.
331 static void ia32_emit_cfop_target(const ir_node *node)
333 ir_node *block = get_cfop_target_block(node);
334 be_gas_emit_block_name(block);
338 * Emit the suffix for a compare instruction.
340 static void ia32_emit_condition_code(ia32_condition_code_t cc)
343 case ia32_cc_overflow: be_emit_cstring("o"); return;
344 case ia32_cc_not_overflow: be_emit_cstring("no"); return;
345 case ia32_cc_float_below:
346 case ia32_cc_float_unordered_below:
347 case ia32_cc_below: be_emit_cstring("b"); return;
348 case ia32_cc_float_above_equal:
349 case ia32_cc_float_unordered_above_equal:
350 case ia32_cc_above_equal: be_emit_cstring("ae"); return;
351 case ia32_cc_float_equal:
352 case ia32_cc_equal: be_emit_cstring("e"); return;
353 case ia32_cc_float_not_equal:
354 case ia32_cc_not_equal: be_emit_cstring("ne"); return;
355 case ia32_cc_float_below_equal:
356 case ia32_cc_float_unordered_below_equal:
357 case ia32_cc_below_equal: be_emit_cstring("be"); return;
358 case ia32_cc_float_above:
359 case ia32_cc_float_unordered_above:
360 case ia32_cc_above: be_emit_cstring("a"); return;
361 case ia32_cc_sign: be_emit_cstring("s"); return;
362 case ia32_cc_not_sign: be_emit_cstring("ns"); return;
363 case ia32_cc_parity: be_emit_cstring("p"); return;
364 case ia32_cc_not_parity: be_emit_cstring("np"); return;
365 case ia32_cc_less: be_emit_cstring("l"); return;
366 case ia32_cc_greater_equal: be_emit_cstring("ge"); return;
367 case ia32_cc_less_equal: be_emit_cstring("le"); return;
368 case ia32_cc_greater: be_emit_cstring("g"); return;
369 case ia32_cc_float_parity_cases:
370 case ia32_cc_additional_float_cases:
373 panic("Invalid ia32 condition code");
376 typedef enum ia32_emit_mod_t {
378 EMIT_RESPECT_LS = 1U << 0,
379 EMIT_ALTERNATE_AM = 1U << 1,
381 EMIT_HIGH_REG = 1U << 3,
382 EMIT_LOW_REG = 1U << 4,
383 EMIT_16BIT_REG = 1U << 5
385 ENUM_BITSET(ia32_emit_mod_t)
388 * Emits address mode.
390 static void ia32_emit_am(ir_node const *const node)
392 ir_entity *ent = get_ia32_am_sc(node);
393 int offs = get_ia32_am_offs_int(node);
394 ir_node *base = get_irn_n(node, n_ia32_base);
395 int has_base = !is_ia32_NoReg_GP(base);
396 ir_node *idx = get_irn_n(node, n_ia32_index);
397 int has_index = !is_ia32_NoReg_GP(idx);
399 /* just to be sure... */
400 assert(!is_ia32_use_frame(node) || get_ia32_frame_ent(node) != NULL);
402 if (get_ia32_am_tls_segment(node))
403 be_emit_cstring("%gs:");
407 const ia32_attr_t *attr = get_ia32_attr_const(node);
408 if (is_ia32_am_sc_sign(node))
410 ia32_emit_entity(ent, attr->data.am_sc_no_pic_adjust);
413 /* also handle special case if nothing is set */
414 if (offs != 0 || (ent == NULL && !has_base && !has_index)) {
416 be_emit_irprintf("%+d", offs);
418 be_emit_irprintf("%d", offs);
422 if (has_base || has_index) {
427 const arch_register_t *reg = arch_get_irn_register_in(node, n_ia32_base);
428 emit_register(reg, NULL);
431 /* emit index + scale */
433 const arch_register_t *reg = arch_get_irn_register_in(node, n_ia32_index);
436 emit_register(reg, NULL);
438 scale = get_ia32_am_scale(node);
440 be_emit_irprintf(",%d", 1 << scale);
447 static ia32_condition_code_t determine_final_cc(ir_node const *node, int flags_pos, ia32_condition_code_t cc);
449 void ia32_emitf(ir_node const *const node, char const *fmt, ...)
456 const char *start = fmt;
457 ia32_emit_mod_t mod = EMIT_NONE;
459 while (*fmt != '%' && *fmt != '\n' && *fmt != '\0')
462 be_emit_string_len(start, fmt - start);
467 be_emit_write_line();
481 case '*': mod |= EMIT_ALTERNATE_AM; break;
482 case '#': mod |= EMIT_RESPECT_LS; break;
483 case 'l': mod |= EMIT_LONG; break;
484 case '>': mod |= EMIT_HIGH_REG; break;
485 case '<': mod |= EMIT_LOW_REG; break;
486 case '^': mod |= EMIT_16BIT_REG; break;
495 arch_register_t const *reg;
505 if (get_ia32_op_type(node) == ia32_AddrModeS) {
508 assert(get_ia32_op_type(node) == ia32_Normal);
509 ia32_x87_attr_t const *const x87_attr = get_ia32_x87_attr_const(node);
510 arch_register_t const *const in1 = x87_attr->x87[0];
511 arch_register_t const * in = x87_attr->x87[1];
512 arch_register_t const * out = x87_attr->x87[2];
515 } else if (out == in) {
518 be_emit_irprintf("%%%s, %%%s", arch_register_get_name(in), arch_register_get_name(out));
524 if (mod & EMIT_ALTERNATE_AM)
530 reg = va_arg(ap, const arch_register_t*);
531 if (get_ia32_op_type(node) == ia32_AddrModeS) {
538 if (get_ia32_op_type(node) == ia32_AddrModeS) {
542 assert(get_ia32_op_type(node) == ia32_Normal);
546 default: goto unknown;
552 imm = get_irn_n(node, n_ia32_binary_right);
553 if (is_ia32_Immediate(imm)) {
554 emit_ia32_Immediate(imm);
555 be_emit_cstring(", ");
556 if (get_ia32_op_type(node) == ia32_AddrModeS) {
559 assert(get_ia32_op_type(node) == ia32_Normal);
560 reg = arch_get_irn_register_in(node, n_ia32_binary_left);
561 emit_register(reg, get_ia32_ls_mode(node));
564 if (get_ia32_op_type(node) == ia32_AddrModeS) {
567 assert(get_ia32_op_type(node) == ia32_Normal);
568 reg = arch_get_irn_register_in(node, n_ia32_binary_right);
569 emit_register(reg, get_ia32_ls_mode(node));
571 be_emit_cstring(", ");
572 reg = arch_get_irn_register_in(node, n_ia32_binary_left);
573 emit_register(reg, get_ia32_ls_mode(node));
578 if (*fmt < '0' || '9' <= *fmt)
580 reg = arch_get_irn_register_out(node, *fmt++ - '0');
586 ia32_emit_x87_mode_suffix(node);
587 } else if (*fmt == 'X') {
589 ia32_emit_xmm_mode_suffix(node);
590 } else if ('0' <= *fmt && *fmt <= '3') {
591 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
593 be_emit_string(attr->x87[*fmt++ - '0']->name);
602 if (!(mod & EMIT_ALTERNATE_AM))
604 emit_ia32_Immediate_no_prefix(imm);
608 ia32_emit_cfop_target(node);
612 ir_mode *mode = get_ia32_ls_mode(node);
615 if (mod & EMIT_RESPECT_LS) {
616 if (get_mode_size_bits(mode) == 32)
618 be_emit_char(mode_is_signed(mode) ? 's' : 'z');
620 ia32_emit_mode_suffix_mode(mode);
625 ia32_condition_code_t cc;
628 cc = (ia32_condition_code_t)va_arg(ap, int);
629 } else if ('0' <= *fmt && *fmt <= '9') {
630 cc = get_ia32_condcode(node);
631 cc = determine_final_cc(node, *fmt - '0', cc);
635 ia32_emit_condition_code(cc);
640 reg = va_arg(ap, const arch_register_t*);
642 if (mod & EMIT_ALTERNATE_AM)
644 if (mod & EMIT_HIGH_REG) {
645 emit_8bit_register_high(reg);
646 } else if (mod & EMIT_LOW_REG) {
647 emit_8bit_register(reg);
648 } else if (mod & EMIT_16BIT_REG) {
649 emit_16bit_register(reg);
651 emit_register(reg, mod & EMIT_RESPECT_LS ? get_ia32_ls_mode(node) : NULL);
659 if (*fmt < '0' || '9' <= *fmt)
663 imm = get_irn_n(node, pos);
664 if (is_ia32_Immediate(imm)) {
667 reg = arch_get_irn_register_in(node, pos);
673 const char *str = va_arg(ap, const char*);
679 if (mod & EMIT_LONG) {
680 unsigned long num = va_arg(ap, unsigned long);
681 be_emit_irprintf("%lu", num);
683 unsigned num = va_arg(ap, unsigned);
684 be_emit_irprintf("%u", num);
689 if (mod & EMIT_LONG) {
690 long num = va_arg(ap, long);
691 be_emit_irprintf("%ld", num);
693 int num = va_arg(ap, int);
694 be_emit_irprintf("%d", num);
700 panic("unknown format conversion in ia32_emitf()");
704 be_emit_finish_line_gas(node);
708 static void emit_ia32_IMul(const ir_node *node)
710 ir_node *left = get_irn_n(node, n_ia32_IMul_left);
711 const arch_register_t *out_reg = arch_get_irn_register_out(node, pn_ia32_IMul_res);
713 /* do we need the 3-address form? */
714 if (is_ia32_NoReg_GP(left) ||
715 arch_get_irn_register_in(node, n_ia32_IMul_left) != out_reg) {
716 ia32_emitf(node, "imul%M %#S4, %#AS3, %#D0");
718 ia32_emitf(node, "imul%M %#AS4, %#S3");
723 * walks up a tree of copies/perms/spills/reloads to find the original value
724 * that is moved around
726 static ir_node *find_original_value(ir_node *node)
728 if (irn_visited(node))
731 mark_irn_visited(node);
732 if (be_is_Copy(node)) {
733 return find_original_value(be_get_Copy_op(node));
734 } else if (be_is_CopyKeep(node)) {
735 return find_original_value(be_get_CopyKeep_op(node));
736 } else if (is_Proj(node)) {
737 ir_node *pred = get_Proj_pred(node);
738 if (be_is_Perm(pred)) {
739 return find_original_value(get_irn_n(pred, get_Proj_proj(node)));
740 } else if (be_is_MemPerm(pred)) {
741 return find_original_value(get_irn_n(pred, get_Proj_proj(node) + 1));
742 } else if (is_ia32_Load(pred)) {
743 return find_original_value(get_irn_n(pred, n_ia32_Load_mem));
744 } else if (is_ia32_Store(pred)) {
745 return find_original_value(get_irn_n(pred, n_ia32_Store_val));
749 } else if (is_Phi(node)) {
751 arity = get_irn_arity(node);
752 for (i = 0; i < arity; ++i) {
753 ir_node *in = get_irn_n(node, i);
754 ir_node *res = find_original_value(in);
765 static ia32_condition_code_t determine_final_cc(const ir_node *node,
766 int flags_pos, ia32_condition_code_t cc)
768 ir_node *flags = get_irn_n(node, flags_pos);
769 const ia32_attr_t *flags_attr;
770 flags = skip_Proj(flags);
772 if (is_ia32_Sahf(flags)) {
773 ir_node *cmp = get_irn_n(flags, n_ia32_Sahf_val);
774 if (!(is_ia32_FucomFnstsw(cmp) || is_ia32_FucompFnstsw(cmp)
775 || is_ia32_FucomppFnstsw(cmp) || is_ia32_FtstFnstsw(cmp))) {
776 inc_irg_visited(current_ir_graph);
777 cmp = find_original_value(cmp);
779 assert(is_ia32_FucomFnstsw(cmp) || is_ia32_FucompFnstsw(cmp)
780 || is_ia32_FucomppFnstsw(cmp) || is_ia32_FtstFnstsw(cmp));
783 flags_attr = get_ia32_attr_const(cmp);
785 flags_attr = get_ia32_attr_const(flags);
788 if (flags_attr->data.ins_permuted)
789 cc = ia32_invert_condition_code(cc);
794 * Emits an exception label for a given node.
796 static void ia32_emit_exc_label(const ir_node *node)
798 be_emit_string(be_gas_insn_label_prefix());
799 be_emit_irprintf("%lu", get_ia32_exc_label_id(node));
803 * Returns the Proj with projection number proj and NOT mode_M
805 static ir_node *get_proj(const ir_node *node, long proj)
809 assert(get_irn_mode(node) == mode_T && "expected mode_T node");
811 foreach_out_edge(node, edge) {
812 src = get_edge_src_irn(edge);
814 assert(is_Proj(src) && "Proj expected");
815 if (get_irn_mode(src) == mode_M)
818 if (get_Proj_proj(src) == proj)
824 static int can_be_fallthrough(const ir_node *node)
826 ir_node *target_block = get_cfop_target_block(node);
827 ir_node *block = get_nodes_block(node);
828 return get_prev_block_sched(target_block) == block;
832 * Emits the jump sequence for a conditional jump (cmp + jmp_true + jmp_false)
834 static void emit_ia32_Jcc(const ir_node *node)
836 int need_parity_label = 0;
837 ia32_condition_code_t cc = get_ia32_condcode(node);
838 const ir_node *proj_true;
839 const ir_node *proj_false;
841 cc = determine_final_cc(node, 0, cc);
844 proj_true = get_proj(node, pn_ia32_Jcc_true);
845 assert(proj_true && "Jcc without true Proj");
847 proj_false = get_proj(node, pn_ia32_Jcc_false);
848 assert(proj_false && "Jcc without false Proj");
850 if (can_be_fallthrough(proj_true)) {
851 /* exchange both proj's so the second one can be omitted */
852 const ir_node *t = proj_true;
854 proj_true = proj_false;
856 cc = ia32_negate_condition_code(cc);
859 if (cc & ia32_cc_float_parity_cases) {
860 /* Some floating point comparisons require a test of the parity flag,
861 * which indicates that the result is unordered */
862 if (cc & ia32_cc_negated) {
863 ia32_emitf(proj_true, "jp %L");
865 /* we need a local label if the false proj is a fallthrough
866 * as the falseblock might have no label emitted then */
867 if (can_be_fallthrough(proj_false)) {
868 need_parity_label = 1;
869 ia32_emitf(proj_false, "jp 1f");
871 ia32_emitf(proj_false, "jp %L");
875 ia32_emitf(proj_true, "j%PX %L", (int)cc);
876 if (need_parity_label) {
877 be_emit_cstring("1:\n");
878 be_emit_write_line();
881 /* the second Proj might be a fallthrough */
882 if (can_be_fallthrough(proj_false)) {
883 if (be_options.verbose_asm)
884 ia32_emitf(proj_false, "/* fallthrough to %L */");
886 ia32_emitf(proj_false, "jmp %L");
891 * Emits an ia32 Setcc. This is mostly easy but some floating point compares
894 static void emit_ia32_Setcc(const ir_node *node)
896 const arch_register_t *dreg = arch_get_irn_register_out(node, pn_ia32_Setcc_res);
898 ia32_condition_code_t cc = get_ia32_condcode(node);
899 cc = determine_final_cc(node, n_ia32_Setcc_eflags, cc);
900 if (cc & ia32_cc_float_parity_cases) {
901 if (cc & ia32_cc_negated) {
902 ia32_emitf(node, "set%PX %<R", (int)cc, dreg);
903 ia32_emitf(node, "setp %>R", dreg);
904 ia32_emitf(node, "orb %>R, %<R", dreg, dreg);
906 ia32_emitf(node, "set%PX %<R", (int)cc, dreg);
907 ia32_emitf(node, "setnp %>R", dreg);
908 ia32_emitf(node, "andb %>R, %<R", dreg, dreg);
911 ia32_emitf(node, "set%PX %#R", (int)cc, dreg);
915 static void emit_ia32_CMovcc(const ir_node *node)
917 const ia32_attr_t *attr = get_ia32_attr_const(node);
918 const arch_register_t *out = arch_get_irn_register_out(node, pn_ia32_res);
919 ia32_condition_code_t cc = get_ia32_condcode(node);
920 const arch_register_t *in_true;
921 const arch_register_t *in_false;
923 cc = determine_final_cc(node, n_ia32_CMovcc_eflags, cc);
924 /* although you can't set ins_permuted in the constructor it might still
925 * be set by memory operand folding
926 * Permuting inputs of a cmov means the condition is negated!
928 if (attr->data.ins_permuted)
929 cc = ia32_negate_condition_code(cc);
931 in_true = arch_get_irn_register(get_irn_n(node, n_ia32_CMovcc_val_true));
932 in_false = arch_get_irn_register(get_irn_n(node, n_ia32_CMovcc_val_false));
934 /* should be same constraint fullfilled? */
935 if (out == in_false) {
936 /* yes -> nothing to do */
937 } else if (out == in_true) {
938 const arch_register_t *tmp;
940 assert(get_ia32_op_type(node) == ia32_Normal);
942 cc = ia32_negate_condition_code(cc);
949 ia32_emitf(node, "movl %R, %R", in_false, out);
952 if (cc & ia32_cc_float_parity_cases) {
953 panic("CMov with floatingpoint compare/parity not supported yet");
956 ia32_emitf(node, "cmov%PX %#AR, %#R", (int)cc, in_true, out);
960 * Emits code for a SwitchJmp
962 static void emit_ia32_SwitchJmp(const ir_node *node)
964 ir_entity *jump_table = get_ia32_am_sc(node);
965 const ir_switch_table *table = get_ia32_switch_table(node);
967 ia32_emitf(node, "jmp %*AM");
968 be_emit_jump_table(node, table, jump_table, get_cfop_target_block);
972 * Emits code for a unconditional jump.
974 static void emit_ia32_Jmp(const ir_node *node)
976 /* we have a block schedule */
977 if (can_be_fallthrough(node)) {
978 if (be_options.verbose_asm)
979 ia32_emitf(node, "/* fallthrough to %L */");
981 ia32_emitf(node, "jmp %L");
986 * Emit an inline assembler operand.
988 * @param node the ia32_ASM node
989 * @param s points to the operand (a %c)
991 * @return pointer to the first char in s NOT in the current operand
993 static const char* emit_asm_operand(const ir_node *node, const char *s)
995 const ia32_attr_t *ia32_attr = get_ia32_attr_const(node);
996 const ia32_asm_attr_t *attr = CONST_CAST_IA32_ATTR(ia32_asm_attr_t,
998 const arch_register_t *reg;
999 const ia32_asm_reg_t *asm_regs = attr->register_map;
1000 const ia32_asm_reg_t *asm_reg;
1009 /* parse modifiers */
1012 ir_fprintf(stderr, "Warning: asm text (%+F) ends with %%\n", node);
1037 "Warning: asm text (%+F) contains unknown modifier '%c' for asm op\n",
1044 if (sscanf(s, "%d%n", &num, &p) != 1) {
1045 ir_fprintf(stderr, "Warning: Couldn't parse assembler operand (%+F)\n",
1052 if (num < 0 || ARR_LEN(asm_regs) <= (size_t)num) {
1054 "Error: Custom assembler references invalid input/output (%+F)\n",
1058 asm_reg = & asm_regs[num];
1059 assert(asm_reg->valid);
1062 if (asm_reg->use_input == 0) {
1063 reg = arch_get_irn_register_out(node, asm_reg->inout_pos);
1065 ir_node *pred = get_irn_n(node, asm_reg->inout_pos);
1067 /* might be an immediate value */
1068 if (is_ia32_Immediate(pred)) {
1069 emit_ia32_Immediate(pred);
1072 reg = arch_get_irn_register_in(node, asm_reg->inout_pos);
1076 "Warning: no register assigned for %d asm op (%+F)\n",
1081 if (asm_reg->memory) {
1086 if (modifier != 0) {
1089 emit_8bit_register(reg);
1092 emit_8bit_register_high(reg);
1095 emit_16bit_register(reg);
1098 panic("Invalid asm op modifier");
1101 emit_register(reg, asm_reg->memory ? mode_Iu : asm_reg->mode);
1104 if (asm_reg->memory) {
1112 * Emits code for an ASM pseudo op.
1114 static void emit_ia32_Asm(const ir_node *node)
1116 const void *gen_attr = get_irn_generic_attr_const(node);
1117 const ia32_asm_attr_t *attr
1118 = CONST_CAST_IA32_ATTR(ia32_asm_attr_t, gen_attr);
1119 ident *asm_text = attr->asm_text;
1120 const char *s = get_id_str(asm_text);
1122 be_emit_cstring("#APP\n");
1123 be_emit_write_line();
1130 s = emit_asm_operand(node, s);
1136 be_emit_cstring("\n#NO_APP\n");
1137 be_emit_write_line();
1142 * Emit movsb/w instructions to make mov count divideable by 4
1144 static void emit_CopyB_prolog(unsigned size)
1147 ia32_emitf(NULL, "movsb");
1149 ia32_emitf(NULL, "movsw");
1153 * Emit rep movsd instruction for memcopy.
1155 static void emit_ia32_CopyB(const ir_node *node)
1157 unsigned size = get_ia32_copyb_size(node);
1159 emit_CopyB_prolog(size);
1160 ia32_emitf(node, "rep movsd");
1164 * Emits unrolled memcopy.
1166 static void emit_ia32_CopyB_i(const ir_node *node)
1168 unsigned size = get_ia32_copyb_size(node);
1170 emit_CopyB_prolog(size);
1174 ia32_emitf(NULL, "movsd");
1180 * Emit code for conversions (I, FP), (FP, I) and (FP, FP).
1182 static void emit_ia32_Conv_with_FP(const ir_node *node, const char* conv_f,
1185 ir_mode *ls_mode = get_ia32_ls_mode(node);
1186 int ls_bits = get_mode_size_bits(ls_mode);
1187 const char *conv = ls_bits == 32 ? conv_f : conv_d;
1189 ia32_emitf(node, "cvt%s %AS3, %D0", conv);
1192 static void emit_ia32_Conv_I2FP(const ir_node *node)
1194 emit_ia32_Conv_with_FP(node, "si2ss", "si2sd");
1197 static void emit_ia32_Conv_FP2I(const ir_node *node)
1199 emit_ia32_Conv_with_FP(node, "ss2si", "sd2si");
1202 static void emit_ia32_Conv_FP2FP(const ir_node *node)
1204 emit_ia32_Conv_with_FP(node, "sd2ss", "ss2sd");
1208 * Emits code to increase stack pointer.
1210 static void emit_be_IncSP(const ir_node *node)
1212 int offs = be_get_IncSP_offset(node);
1218 ia32_emitf(node, "subl $%u, %D0", offs);
1220 ia32_emitf(node, "addl $%u, %D0", -offs);
1225 * Emits code for Copy/CopyKeep.
1227 static void Copy_emitter(const ir_node *node, const ir_node *op)
1229 const arch_register_t *in = arch_get_irn_register(op);
1230 const arch_register_t *out = arch_get_irn_register(node);
1235 /* copies of vf nodes aren't real... */
1236 if (arch_register_get_class(in) == &ia32_reg_classes[CLASS_ia32_vfp])
1239 ia32_emitf(node, "movl %R, %R", in, out);
1242 static void emit_be_Copy(const ir_node *node)
1244 Copy_emitter(node, be_get_Copy_op(node));
1247 static void emit_be_CopyKeep(const ir_node *node)
1249 Copy_emitter(node, be_get_CopyKeep_op(node));
1253 * Emits code for exchange.
1255 static void emit_be_Perm(const ir_node *node)
1257 const arch_register_t *in0, *in1;
1258 const arch_register_class_t *cls0, *cls1;
1260 in0 = arch_get_irn_register(get_irn_n(node, 0));
1261 in1 = arch_get_irn_register(get_irn_n(node, 1));
1263 cls0 = arch_register_get_class(in0);
1264 cls1 = arch_register_get_class(in1);
1266 assert(cls0 == cls1 && "Register class mismatch at Perm");
1268 if (cls0 == &ia32_reg_classes[CLASS_ia32_gp]) {
1269 ia32_emitf(node, "xchg %R, %R", in1, in0);
1270 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_xmm]) {
1271 ia32_emitf(NULL, "xorpd %R, %R", in1, in0);
1272 ia32_emitf(NULL, "xorpd %R, %R", in0, in1);
1273 ia32_emitf(node, "xorpd %R, %R", in1, in0);
1274 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_vfp]) {
1276 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_st]) {
1279 panic("unexpected register class in be_Perm (%+F)", node);
1283 /* helper function for emit_ia32_Minus64Bit */
1284 static void emit_mov(const ir_node* node, const arch_register_t *src, const arch_register_t *dst)
1286 ia32_emitf(node, "movl %R, %R", src, dst);
1289 /* helper function for emit_ia32_Minus64Bit */
1290 static void emit_neg(const ir_node* node, const arch_register_t *reg)
1292 ia32_emitf(node, "negl %R", reg);
1295 /* helper function for emit_ia32_Minus64Bit */
1296 static void emit_sbb0(const ir_node* node, const arch_register_t *reg)
1298 ia32_emitf(node, "sbbl $0, %R", reg);
1301 /* helper function for emit_ia32_Minus64Bit */
1302 static void emit_sbb(const ir_node* node, const arch_register_t *src, const arch_register_t *dst)
1304 ia32_emitf(node, "sbbl %R, %R", src, dst);
1307 /* helper function for emit_ia32_Minus64Bit */
1308 static void emit_xchg(const ir_node* node, const arch_register_t *src, const arch_register_t *dst)
1310 ia32_emitf(node, "xchgl %R, %R", src, dst);
1313 /* helper function for emit_ia32_Minus64Bit */
1314 static void emit_zero(const ir_node* node, const arch_register_t *reg)
1316 ia32_emitf(node, "xorl %R, %R", reg, reg);
1319 static void emit_ia32_Minus64Bit(const ir_node *node)
1321 const arch_register_t *in_lo = arch_get_irn_register_in(node, 0);
1322 const arch_register_t *in_hi = arch_get_irn_register_in(node, 1);
1323 const arch_register_t *out_lo = arch_get_irn_register_out(node, 0);
1324 const arch_register_t *out_hi = arch_get_irn_register_out(node, 1);
1326 if (out_lo == in_lo) {
1327 if (out_hi != in_hi) {
1328 /* a -> a, b -> d */
1331 /* a -> a, b -> b */
1334 } else if (out_lo == in_hi) {
1335 if (out_hi == in_lo) {
1336 /* a -> b, b -> a */
1337 emit_xchg(node, in_lo, in_hi);
1340 /* a -> b, b -> d */
1341 emit_mov(node, in_hi, out_hi);
1342 emit_mov(node, in_lo, out_lo);
1346 if (out_hi == in_lo) {
1347 /* a -> c, b -> a */
1348 emit_mov(node, in_lo, out_lo);
1350 } else if (out_hi == in_hi) {
1351 /* a -> c, b -> b */
1352 emit_mov(node, in_lo, out_lo);
1355 /* a -> c, b -> d */
1356 emit_mov(node, in_lo, out_lo);
1362 emit_neg( node, out_hi);
1363 emit_neg( node, out_lo);
1364 emit_sbb0(node, out_hi);
1368 emit_zero(node, out_hi);
1369 emit_neg( node, out_lo);
1370 emit_sbb( node, in_hi, out_hi);
1373 static void emit_ia32_GetEIP(const ir_node *node)
1375 ia32_emitf(node, "call %s", pic_base_label);
1376 be_emit_irprintf("%s:\n", pic_base_label);
1377 be_emit_write_line();
1378 ia32_emitf(node, "popl %D0");
1381 static void emit_ia32_ClimbFrame(const ir_node *node)
1383 const ia32_climbframe_attr_t *attr = get_ia32_climbframe_attr_const(node);
1385 ia32_emitf(node, "movl %S0, %D0");
1386 ia32_emitf(node, "movl $%u, %S1", attr->count);
1387 be_gas_emit_block_name(node);
1388 be_emit_cstring(":\n");
1389 be_emit_write_line();
1390 ia32_emitf(node, "movl (%D0), %D0");
1391 ia32_emitf(node, "dec %S1");
1392 be_emit_cstring("\tjnz ");
1393 be_gas_emit_block_name(node);
1394 be_emit_finish_line_gas(node);
1397 static void emit_be_Return(const ir_node *node)
1399 unsigned pop = be_Return_get_pop(node);
1401 if (pop > 0 || be_Return_get_emit_pop(node)) {
1402 ia32_emitf(node, "ret $%u", pop);
1404 ia32_emitf(node, "ret");
1408 static void emit_Nothing(const ir_node *node)
1415 * Enters the emitter functions for handled nodes into the generic
1416 * pointer of an opcode.
1418 static void ia32_register_emitters(void)
1420 #define IA32_EMIT(a) op_ia32_##a->ops.generic = (op_func)emit_ia32_##a
1421 #define EMIT(a) op_##a->ops.generic = (op_func)emit_##a
1422 #define IGN(a) op_##a->ops.generic = (op_func)emit_Nothing
1423 #define BE_EMIT(a) op_be_##a->ops.generic = (op_func)emit_be_##a
1424 #define BE_IGN(a) op_be_##a->ops.generic = (op_func)emit_Nothing
1426 /* first clear the generic function pointer for all ops */
1427 ir_clear_opcodes_generic_func();
1429 /* register all emitter functions defined in spec */
1430 ia32_register_spec_emitters();
1432 /* other ia32 emitter functions */
1435 IA32_EMIT(Conv_FP2FP);
1436 IA32_EMIT(Conv_FP2I);
1437 IA32_EMIT(Conv_I2FP);
1444 IA32_EMIT(Minus64Bit);
1445 IA32_EMIT(SwitchJmp);
1446 IA32_EMIT(ClimbFrame);
1449 /* benode emitter */
1468 typedef void (*emit_func_ptr) (const ir_node *);
1471 * Assign and emit an exception label if the current instruction can fail.
1473 static void ia32_assign_exc_label(ir_node *node)
1475 /* assign a new ID to the instruction */
1476 set_ia32_exc_label_id(node, ++exc_label_id);
1478 ia32_emit_exc_label(node);
1480 be_emit_pad_comment();
1481 be_emit_cstring("/* exception to Block ");
1482 ia32_emit_cfop_target(node);
1483 be_emit_cstring(" */\n");
1484 be_emit_write_line();
1488 * Emits code for a node.
1490 static void ia32_emit_node(ir_node *node)
1492 ir_op *op = get_irn_op(node);
1494 DBG((dbg, LEVEL_1, "emitting code for %+F\n", node));
1496 if (is_ia32_irn(node)) {
1497 if (get_ia32_exc_label(node)) {
1498 /* emit the exception label of this instruction */
1499 ia32_assign_exc_label(node);
1501 if (mark_spill_reload) {
1502 if (is_ia32_is_spill(node)) {
1503 ia32_emitf(NULL, "xchg %ebx, %ebx /* spill mark */");
1505 if (is_ia32_is_reload(node)) {
1506 ia32_emitf(NULL, "xchg %edx, %edx /* reload mark */");
1508 if (is_ia32_is_remat(node)) {
1509 ia32_emitf(NULL, "xchg %ecx, %ecx /* remat mark */");
1513 if (op->ops.generic) {
1514 emit_func_ptr func = (emit_func_ptr) op->ops.generic;
1516 be_dwarf_location(get_irn_dbg_info(node));
1521 ir_fprintf(stderr, "Error: No emit handler for node %+F (%+G, graph %+F)\n", node, node, current_ir_graph);
1526 int sp_change = arch_get_sp_bias(node);
1527 if (sp_change != 0) {
1528 assert(sp_change != SP_BIAS_RESET);
1529 callframe_offset += sp_change;
1530 be_dwarf_callframe_offset(callframe_offset);
1536 * Emits gas alignment directives
1538 static void ia32_emit_alignment(unsigned align, unsigned skip)
1540 ia32_emitf(NULL, ".p2align %u,,%u", align, skip);
1544 * Emits gas alignment directives for Labels depended on cpu architecture.
1546 static void ia32_emit_align_label(void)
1548 unsigned align = ia32_cg_config.label_alignment;
1549 unsigned maximum_skip = ia32_cg_config.label_alignment_max_skip;
1550 ia32_emit_alignment(align, maximum_skip);
1554 * Test whether a block should be aligned.
1555 * For cpus in the P4/Athlon class it is useful to align jump labels to
1556 * 16 bytes. However we should only do that if the alignment nops before the
1557 * label aren't executed more often than we have jumps to the label.
1559 static int should_align_block(const ir_node *block)
1561 static const double DELTA = .0001;
1562 ir_graph *irg = get_irn_irg(block);
1563 ir_exec_freq *exec_freq = be_get_irg_exec_freq(irg);
1564 ir_node *prev = get_prev_block_sched(block);
1566 double prev_freq = 0; /**< execfreq of the fallthrough block */
1567 double jmp_freq = 0; /**< execfreq of all non-fallthrough blocks */
1570 if (exec_freq == NULL)
1572 if (ia32_cg_config.label_alignment_factor <= 0)
1575 block_freq = get_block_execfreq(exec_freq, block);
1576 if (block_freq < DELTA)
1579 n_cfgpreds = get_Block_n_cfgpreds(block);
1580 for (i = 0; i < n_cfgpreds; ++i) {
1581 const ir_node *pred = get_Block_cfgpred_block(block, i);
1582 double pred_freq = get_block_execfreq(exec_freq, pred);
1585 prev_freq += pred_freq;
1587 jmp_freq += pred_freq;
1591 if (prev_freq < DELTA && !(jmp_freq < DELTA))
1594 jmp_freq /= prev_freq;
1596 return jmp_freq > ia32_cg_config.label_alignment_factor;
1600 * Emit the block header for a block.
1602 * @param block the block
1603 * @param prev_block the previous block
1605 static void ia32_emit_block_header(ir_node *block)
1607 ir_graph *irg = current_ir_graph;
1608 int need_label = block_needs_label(block);
1610 if (block == get_irg_end_block(irg))
1613 if (ia32_cg_config.label_alignment > 0) {
1614 /* align the current block if:
1615 * a) if should be aligned due to its execution frequency
1616 * b) there is no fall-through here
1618 if (should_align_block(block)) {
1619 ia32_emit_align_label();
1621 /* if the predecessor block has no fall-through,
1622 we can always align the label. */
1624 int has_fallthrough = 0;
1626 for (i = get_Block_n_cfgpreds(block) - 1; i >= 0; --i) {
1627 ir_node *cfg_pred = get_Block_cfgpred(block, i);
1628 if (can_be_fallthrough(cfg_pred)) {
1629 has_fallthrough = 1;
1634 if (!has_fallthrough)
1635 ia32_emit_align_label();
1639 be_gas_begin_block(block, need_label);
1643 * Walks over the nodes in a block connected by scheduling edges
1644 * and emits code for each node.
1646 static void ia32_gen_block(ir_node *block)
1648 ia32_emit_block_header(block);
1651 ir_graph *irg = get_irn_irg(block);
1652 callframe_offset = 4; /* 4 bytes for the return address */
1653 /* ESP guessing, TODO perform a real ESP simulation */
1654 if (block != get_irg_start_block(irg)) {
1655 callframe_offset += frame_type_size;
1657 be_dwarf_callframe_offset(callframe_offset);
1660 /* emit the contents of the block */
1661 be_dwarf_location(get_irn_dbg_info(block));
1662 sched_foreach(block, node) {
1663 ia32_emit_node(node);
1667 typedef struct exc_entry {
1668 ir_node *exc_instr; /** The instruction that can issue an exception. */
1669 ir_node *block; /** The block to call then. */
1674 * Sets labels for control flow nodes (jump target).
1675 * Links control predecessors to there destination blocks.
1677 static void ia32_gen_labels(ir_node *block, void *data)
1679 exc_entry **exc_list = (exc_entry**)data;
1683 for (n = get_Block_n_cfgpreds(block) - 1; n >= 0; --n) {
1684 pred = get_Block_cfgpred(block, n);
1685 set_irn_link(pred, block);
1687 pred = skip_Proj(pred);
1688 if (is_ia32_irn(pred) && get_ia32_exc_label(pred)) {
1693 ARR_APP1(exc_entry, *exc_list, e);
1694 set_irn_link(pred, block);
1700 * Compare two exception_entries.
1702 static int cmp_exc_entry(const void *a, const void *b)
1704 const exc_entry *ea = (const exc_entry*)a;
1705 const exc_entry *eb = (const exc_entry*)b;
1707 if (get_ia32_exc_label_id(ea->exc_instr) < get_ia32_exc_label_id(eb->exc_instr))
1712 static parameter_dbg_info_t *construct_parameter_infos(ir_graph *irg)
1714 ir_entity *entity = get_irg_entity(irg);
1715 ir_type *type = get_entity_type(entity);
1716 size_t n_params = get_method_n_params(type);
1717 be_stack_layout_t *layout = be_get_irg_stack_layout(irg);
1718 ir_type *arg_type = layout->arg_type;
1719 size_t n_members = get_compound_n_members(arg_type);
1720 parameter_dbg_info_t *infos = XMALLOCNZ(parameter_dbg_info_t, n_params);
1723 for (i = 0; i < n_members; ++i) {
1724 ir_entity *member = get_compound_member(arg_type, i);
1726 if (!is_parameter_entity(member))
1728 param = get_entity_parameter_number(member);
1729 if (param == IR_VA_START_PARAMETER_NUMBER)
1731 assert(infos[param].entity == NULL && infos[param].reg == NULL);
1732 infos[param].reg = NULL;
1733 infos[param].entity = member;
1740 * Main driver. Emits the code for one routine.
1742 void ia32_gen_routine(ir_graph *irg)
1744 ir_entity *entity = get_irg_entity(irg);
1745 exc_entry *exc_list = NEW_ARR_F(exc_entry, 0);
1746 const arch_env_t *arch_env = be_get_irg_arch_env(irg);
1747 ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
1748 ir_node **blk_sched = irg_data->blk_sched;
1749 be_stack_layout_t *layout = be_get_irg_stack_layout(irg);
1750 parameter_dbg_info_t *infos;
1753 isa = (ia32_isa_t*) arch_env;
1754 do_pic = be_options.pic;
1756 be_gas_elf_type_char = '@';
1758 ia32_register_emitters();
1760 get_unique_label(pic_base_label, sizeof(pic_base_label), "PIC_BASE");
1762 infos = construct_parameter_infos(irg);
1763 be_gas_emit_function_prolog(entity, ia32_cg_config.function_alignment,
1767 sp_relative = layout->sp_relative;
1768 if (layout->sp_relative) {
1769 ir_type *frame_type = get_irg_frame_type(irg);
1770 frame_type_size = get_type_size_bytes(frame_type);
1771 be_dwarf_callframe_register(&ia32_registers[REG_ESP]);
1773 /* well not entirely correct here, we should emit this after the
1774 * "movl esp, ebp" */
1775 be_dwarf_callframe_register(&ia32_registers[REG_EBP]);
1776 /* TODO: do not hardcode the following */
1777 be_dwarf_callframe_offset(8);
1778 be_dwarf_callframe_spilloffset(&ia32_registers[REG_EBP], -8);
1781 /* we use links to point to target blocks */
1782 ir_reserve_resources(irg, IR_RESOURCE_IRN_LINK);
1783 irg_block_walk_graph(irg, ia32_gen_labels, NULL, &exc_list);
1785 /* initialize next block links */
1786 n = ARR_LEN(blk_sched);
1787 for (i = 0; i < n; ++i) {
1788 ir_node *block = blk_sched[i];
1789 ir_node *prev = i > 0 ? blk_sched[i-1] : NULL;
1791 set_irn_link(block, prev);
1794 for (i = 0; i < n; ++i) {
1795 ir_node *block = blk_sched[i];
1797 ia32_gen_block(block);
1800 be_gas_emit_function_epilog(entity);
1802 ir_free_resources(irg, IR_RESOURCE_IRN_LINK);
1804 /* Sort the exception table using the exception label id's.
1805 Those are ascending with ascending addresses. */
1806 qsort(exc_list, ARR_LEN(exc_list), sizeof(exc_list[0]), cmp_exc_entry);
1810 for (e = 0; e < ARR_LEN(exc_list); ++e) {
1811 be_emit_cstring("\t.long ");
1812 ia32_emit_exc_label(exc_list[e].exc_instr);
1814 be_emit_cstring("\t.long ");
1815 be_gas_emit_block_name(exc_list[e].block);
1819 DEL_ARR_F(exc_list);
1822 static const lc_opt_table_entry_t ia32_emitter_options[] = {
1823 LC_OPT_ENT_BOOL("mark_spill_reload", "mark spills and reloads with ud opcodes", &mark_spill_reload),
1827 /* ==== Experimental binary emitter ==== */
1829 static unsigned char reg_gp_map[N_ia32_gp_REGS];
1830 //static unsigned char reg_mmx_map[N_ia32_mmx_REGS];
1831 //static unsigned char reg_sse_map[N_ia32_xmm_REGS];
1833 static void build_reg_map(void)
1835 reg_gp_map[REG_GP_EAX] = 0x0;
1836 reg_gp_map[REG_GP_ECX] = 0x1;
1837 reg_gp_map[REG_GP_EDX] = 0x2;
1838 reg_gp_map[REG_GP_EBX] = 0x3;
1839 reg_gp_map[REG_GP_ESP] = 0x4;
1840 reg_gp_map[REG_GP_EBP] = 0x5;
1841 reg_gp_map[REG_GP_ESI] = 0x6;
1842 reg_gp_map[REG_GP_EDI] = 0x7;
1845 /** Returns the encoding for a pnc field. */
1846 static unsigned char pnc2cc(ia32_condition_code_t cc)
1851 /** Sign extension bit values for binops */
1853 UNSIGNED_IMM = 0, /**< unsigned immediate */
1854 SIGNEXT_IMM = 2, /**< sign extended immediate */
1857 /** The mod encoding of the ModR/M */
1859 MOD_IND = 0x00, /**< [reg1] */
1860 MOD_IND_BYTE_OFS = 0x40, /**< [reg1 + byte ofs] */
1861 MOD_IND_WORD_OFS = 0x80, /**< [reg1 + word ofs] */
1862 MOD_REG = 0xC0 /**< reg1 */
1865 /** create R/M encoding for ModR/M */
1866 #define ENC_RM(x) (x)
1867 /** create REG encoding for ModR/M */
1868 #define ENC_REG(x) ((x) << 3)
1870 /** create encoding for a SIB byte */
1871 #define ENC_SIB(scale, index, base) ((scale) << 6 | (index) << 3 | (base))
1873 /* Node: The following routines are supposed to append bytes, words, dwords
1874 to the output stream.
1875 Currently the implementation is stupid in that it still creates output
1876 for an "assembler" in the form of .byte, .long
1877 We will change this when enough infrastructure is there to create complete
1878 machine code in memory/object files */
1880 static void bemit8(const unsigned char byte)
1882 be_emit_irprintf("\t.byte 0x%x\n", byte);
1883 be_emit_write_line();
1886 static void bemit16(const unsigned short u16)
1888 be_emit_irprintf("\t.word 0x%x\n", u16);
1889 be_emit_write_line();
1892 static void bemit32(const unsigned u32)
1894 be_emit_irprintf("\t.long 0x%x\n", u32);
1895 be_emit_write_line();
1899 * Emit address of an entity. If @p is_relative is true then a relative
1900 * offset from behind the address to the entity is created.
1902 static void bemit_entity(ir_entity *entity, bool entity_sign, int offset,
1905 if (entity == NULL) {
1910 /* the final version should remember the position in the bytestream
1911 and patch it with the correct address at linktime... */
1912 be_emit_cstring("\t.long ");
1915 be_gas_emit_entity(entity);
1917 if (get_entity_owner(entity) == get_tls_type()) {
1918 if (!entity_has_definition(entity)) {
1919 be_emit_cstring("@INDNTPOFF");
1921 be_emit_cstring("@NTPOFF");
1926 be_emit_cstring("-.");
1931 be_emit_irprintf("%+d", offset);
1934 be_emit_write_line();
1937 static void bemit_jmp_destination(const ir_node *dest_block)
1939 be_emit_cstring("\t.long ");
1940 be_gas_emit_block_name(dest_block);
1941 be_emit_cstring(" - . - 4\n");
1942 be_emit_write_line();
1945 /* end emit routines, all emitters following here should only use the functions
1948 typedef enum reg_modifier {
1953 /** Create a ModR/M byte for src1,src2 registers */
1954 static void bemit_modrr(const arch_register_t *src1,
1955 const arch_register_t *src2)
1957 unsigned char modrm = MOD_REG;
1958 modrm |= ENC_RM(reg_gp_map[src1->index]);
1959 modrm |= ENC_REG(reg_gp_map[src2->index]);
1963 /** Create a ModR/M8 byte for src1,src2 registers */
1964 static void bemit_modrr8(reg_modifier_t high_part1, const arch_register_t *src1,
1965 reg_modifier_t high_part2, const arch_register_t *src2)
1967 unsigned char modrm = MOD_REG;
1968 modrm |= ENC_RM(reg_gp_map[src1->index] + (high_part1 == REG_HIGH ? 4 : 0));
1969 modrm |= ENC_REG(reg_gp_map[src2->index] + (high_part2 == REG_HIGH ? 4 : 0));
1973 /** Create a ModR/M byte for one register and extension */
1974 static void bemit_modru(const arch_register_t *reg, unsigned ext)
1976 unsigned char modrm = MOD_REG;
1978 modrm |= ENC_RM(reg_gp_map[reg->index]);
1979 modrm |= ENC_REG(ext);
1983 /** Create a ModR/M8 byte for one register */
1984 static void bemit_modrm8(reg_modifier_t high_part, const arch_register_t *reg)
1986 unsigned char modrm = MOD_REG;
1987 assert(reg_gp_map[reg->index] < 4);
1988 modrm |= ENC_RM(reg_gp_map[reg->index] + (high_part == REG_HIGH ? 4 : 0));
1994 * Calculate the size of an signed immediate in bytes.
1996 * @param offset an offset
1998 static unsigned get_signed_imm_size(int offset)
2000 if (-128 <= offset && offset < 128) {
2002 } else if (-32768 <= offset && offset < 32768) {
2010 * Emit an address mode.
2012 * @param reg content of the reg field: either a register index or an opcode extension
2013 * @param node the node
2015 static void bemit_mod_am(unsigned reg, const ir_node *node)
2017 ir_entity *ent = get_ia32_am_sc(node);
2018 int offs = get_ia32_am_offs_int(node);
2019 ir_node *base = get_irn_n(node, n_ia32_base);
2020 int has_base = !is_ia32_NoReg_GP(base);
2021 ir_node *idx = get_irn_n(node, n_ia32_index);
2022 int has_index = !is_ia32_NoReg_GP(idx);
2025 unsigned emitoffs = 0;
2026 bool emitsib = false;
2029 /* set the mod part depending on displacement */
2031 modrm |= MOD_IND_WORD_OFS;
2033 } else if (offs == 0) {
2036 } else if (-128 <= offs && offs < 128) {
2037 modrm |= MOD_IND_BYTE_OFS;
2040 modrm |= MOD_IND_WORD_OFS;
2045 const arch_register_t *base_reg = arch_get_irn_register(base);
2046 base_enc = reg_gp_map[base_reg->index];
2048 /* Use the EBP encoding + MOD_IND if NO base register. There is
2049 * always a 32bit offset present in this case. */
2055 /* Determine if we need a SIB byte. */
2057 const arch_register_t *reg_index = arch_get_irn_register(idx);
2058 int scale = get_ia32_am_scale(node);
2060 /* R/M set to ESP means SIB in 32bit mode. */
2061 modrm |= ENC_RM(0x04);
2062 sib = ENC_SIB(scale, reg_gp_map[reg_index->index], base_enc);
2064 } else if (base_enc == 0x04) {
2065 /* for the above reason we are forced to emit a SIB when base is ESP.
2066 * Only the base is used, index must be ESP too, which means no index.
2068 modrm |= ENC_RM(0x04);
2069 sib = ENC_SIB(0, 0x04, 0x04);
2072 modrm |= ENC_RM(base_enc);
2075 /* We are forced to emit an 8bit offset as EBP base without offset is a
2076 * special case for SIB without base register. */
2077 if (base_enc == 0x05 && emitoffs == 0) {
2078 modrm |= MOD_IND_BYTE_OFS;
2082 modrm |= ENC_REG(reg);
2088 /* emit displacement */
2089 if (emitoffs == 8) {
2090 bemit8((unsigned) offs);
2091 } else if (emitoffs == 32) {
2092 bemit_entity(ent, is_ia32_am_sc_sign(node), offs, false);
2097 * Emit a binop with a immediate operand.
2099 * @param node the node to emit
2100 * @param opcode_eax the opcode for the op eax, imm variant
2101 * @param opcode the opcode for the reg, imm variant
2102 * @param ruval the opcode extension for opcode
2104 static void bemit_binop_with_imm(
2105 const ir_node *node,
2106 unsigned char opcode_ax,
2107 unsigned char opcode, unsigned char ruval)
2109 /* Use in-reg, because some instructions (cmp, test) have no out-reg. */
2110 const ir_node *op = get_irn_n(node, n_ia32_binary_right);
2111 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(op);
2114 /* Some instructions (test) have no short form with 32bit value + 8bit
2116 if (attr->symconst != NULL || opcode & SIGNEXT_IMM) {
2119 /* check for sign extension */
2120 size = get_signed_imm_size(attr->offset);
2125 bemit8(opcode | SIGNEXT_IMM);
2126 /* cmp has this special mode */
2127 if (get_ia32_op_type(node) == ia32_AddrModeS) {
2128 bemit_mod_am(ruval, node);
2130 const arch_register_t *reg = arch_get_irn_register_in(node, n_ia32_binary_left);
2131 bemit_modru(reg, ruval);
2133 bemit8((unsigned char)attr->offset);
2137 /* check for eax variant: this variant is shorter for 32bit immediates only */
2138 if (get_ia32_op_type(node) == ia32_AddrModeS) {
2140 bemit_mod_am(ruval, node);
2142 const arch_register_t *reg = arch_get_irn_register_in(node, n_ia32_binary_left);
2143 if (reg->index == REG_GP_EAX) {
2147 bemit_modru(reg, ruval);
2150 bemit_entity(attr->symconst, attr->sc_sign, attr->offset, false);
2153 panic("invalid imm size?!?");
2159 static void bemit_binop_2(const ir_node *node, unsigned code)
2161 const arch_register_t *out = arch_get_irn_register_in(node, n_ia32_binary_left);
2163 if (get_ia32_op_type(node) == ia32_Normal) {
2164 const arch_register_t *op2 = arch_get_irn_register_in(node, n_ia32_binary_right);
2165 bemit_modrr(op2, out);
2167 bemit_mod_am(reg_gp_map[out->index], node);
2174 static void bemit_binop(const ir_node *node, const unsigned char opcodes[4])
2176 ir_node *right = get_irn_n(node, n_ia32_binary_right);
2177 if (is_ia32_Immediate(right)) {
2178 bemit_binop_with_imm(node, opcodes[1], opcodes[2], opcodes[3]);
2180 bemit_binop_2(node, opcodes[0]);
2187 static void bemit_unop(const ir_node *node, unsigned char code, unsigned char ext, int input)
2190 if (get_ia32_op_type(node) == ia32_Normal) {
2191 const arch_register_t *in = arch_get_irn_register_in(node, input);
2192 bemit_modru(in, ext);
2194 bemit_mod_am(ext, node);
2198 static void bemit_unop_reg(const ir_node *node, unsigned char code, int input)
2200 const arch_register_t *out = arch_get_irn_register_out(node, 0);
2201 bemit_unop(node, code, reg_gp_map[out->index], input);
2204 static void bemit_unop_mem(const ir_node *node, unsigned char code, unsigned char ext)
2206 unsigned size = get_mode_size_bits(get_ia32_ls_mode(node));
2209 bemit8(size == 8 ? code : code + 1);
2210 bemit_mod_am(ext, node);
2213 static void bemit_immediate(const ir_node *node, bool relative)
2215 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(node);
2216 bemit_entity(attr->symconst, attr->sc_sign, attr->offset, relative);
2219 static void bemit_copy(const ir_node *copy)
2221 const arch_register_t *in = arch_get_irn_register_in(copy, 0);
2222 const arch_register_t *out = arch_get_irn_register_out(copy, 0);
2226 /* copies of vf nodes aren't real... */
2227 if (arch_register_get_class(in) == &ia32_reg_classes[CLASS_ia32_vfp])
2230 assert(arch_register_get_class(in) == &ia32_reg_classes[CLASS_ia32_gp]);
2232 bemit_modrr(in, out);
2235 static void bemit_perm(const ir_node *node)
2237 const arch_register_t *in0 = arch_get_irn_register(get_irn_n(node, 0));
2238 const arch_register_t *in1 = arch_get_irn_register(get_irn_n(node, 1));
2239 const arch_register_class_t *cls0 = arch_register_get_class(in0);
2241 assert(cls0 == arch_register_get_class(in1) && "Register class mismatch at Perm");
2243 if (cls0 == &ia32_reg_classes[CLASS_ia32_gp]) {
2244 if (in0->index == REG_GP_EAX) {
2245 bemit8(0x90 + reg_gp_map[in1->index]);
2246 } else if (in1->index == REG_GP_EAX) {
2247 bemit8(0x90 + reg_gp_map[in0->index]);
2250 bemit_modrr(in0, in1);
2252 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_xmm]) {
2253 panic("unimplemented"); // TODO implement
2254 //ia32_emitf(NULL, "xorpd %R, %R", in1, in0);
2255 //ia32_emitf(NULL, "xorpd %R, %R", in0, in1);
2256 //ia32_emitf(node, "xorpd %R, %R", in1, in0);
2257 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_vfp]) {
2259 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_st]) {
2262 panic("unexpected register class in be_Perm (%+F)", node);
2266 static void bemit_xor0(const ir_node *node)
2268 const arch_register_t *out = arch_get_irn_register_out(node, 0);
2270 bemit_modrr(out, out);
2273 static void bemit_mov_const(const ir_node *node)
2275 const arch_register_t *out = arch_get_irn_register_out(node, 0);
2276 bemit8(0xB8 + reg_gp_map[out->index]);
2277 bemit_immediate(node, false);
2281 * Creates a function for a Binop with 3 possible encodings.
2283 #define BINOP(op, op0, op1, op2, op2_ext) \
2284 static void bemit_ ## op(const ir_node *node) { \
2285 static const unsigned char op ## _codes[] = {op0, op1, op2, op2_ext}; \
2286 bemit_binop(node, op ## _codes); \
2289 /* insn def eax,imm imm */
2290 BINOP(add, 0x03, 0x05, 0x81, 0)
2291 BINOP(or, 0x0B, 0x0D, 0x81, 1)
2292 BINOP(adc, 0x13, 0x15, 0x81, 2)
2293 BINOP(sbb, 0x1B, 0x1D, 0x81, 3)
2294 BINOP(and, 0x23, 0x25, 0x81, 4)
2295 BINOP(sub, 0x2B, 0x2D, 0x81, 5)
2296 BINOP(xor, 0x33, 0x35, 0x81, 6)
2297 BINOP(test, 0x85, 0xA9, 0xF7, 0)
2299 #define BINOPMEM(op, ext) \
2300 static void bemit_##op(const ir_node *node) \
2303 unsigned size = get_mode_size_bits(get_ia32_ls_mode(node)); \
2306 val = get_irn_n(node, n_ia32_unary_op); \
2307 if (is_ia32_Immediate(val)) { \
2308 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(val); \
2309 int offset = attr->offset; \
2310 if (attr->symconst == NULL && get_signed_imm_size(offset) == 1) { \
2312 bemit_mod_am(ext, node); \
2316 bemit_mod_am(ext, node); \
2320 bemit_entity(attr->symconst, attr->sc_sign, offset, false); \
2324 bemit8(ext << 3 | 1); \
2325 bemit_mod_am(reg_gp_map[arch_get_irn_register_out(val, 0)->index], node); \
2329 static void bemit_##op##8bit(const ir_node *node) \
2331 ir_node *val = get_irn_n(node, n_ia32_unary_op); \
2332 if (is_ia32_Immediate(val)) { \
2334 bemit_mod_am(ext, node); \
2335 bemit8(get_ia32_immediate_attr_const(val)->offset); \
2338 bemit_mod_am(reg_gp_map[arch_get_irn_register_out(val, 0)->index], node); \
2350 * Creates a function for an Unop with code /ext encoding.
2352 #define UNOP(op, code, ext, input) \
2353 static void bemit_ ## op(const ir_node *node) { \
2354 bemit_unop(node, code, ext, input); \
2357 UNOP(not, 0xF7, 2, n_ia32_Not_val)
2358 UNOP(neg, 0xF7, 3, n_ia32_Neg_val)
2359 UNOP(mul, 0xF7, 4, n_ia32_Mul_right)
2360 UNOP(imul1op, 0xF7, 5, n_ia32_IMul1OP_right)
2361 UNOP(div, 0xF7, 6, n_ia32_Div_divisor)
2362 UNOP(idiv, 0xF7, 7, n_ia32_IDiv_divisor)
2364 /* TODO: am support for IJmp */
2365 UNOP(ijmp, 0xFF, 4, n_ia32_IJmp_target)
2367 #define SHIFT(op, ext) \
2368 static void bemit_##op(const ir_node *node) \
2370 const arch_register_t *out = arch_get_irn_register_out(node, 0); \
2371 ir_node *count = get_irn_n(node, 1); \
2372 if (is_ia32_Immediate(count)) { \
2373 int offset = get_ia32_immediate_attr_const(count)->offset; \
2374 if (offset == 1) { \
2376 bemit_modru(out, ext); \
2379 bemit_modru(out, ext); \
2384 bemit_modru(out, ext); \
2388 static void bemit_##op##mem(const ir_node *node) \
2391 unsigned size = get_mode_size_bits(get_ia32_ls_mode(node)); \
2394 count = get_irn_n(node, 1); \
2395 if (is_ia32_Immediate(count)) { \
2396 int offset = get_ia32_immediate_attr_const(count)->offset; \
2397 if (offset == 1) { \
2398 bemit8(size == 8 ? 0xD0 : 0xD1); \
2399 bemit_mod_am(ext, node); \
2401 bemit8(size == 8 ? 0xC0 : 0xC1); \
2402 bemit_mod_am(ext, node); \
2406 bemit8(size == 8 ? 0xD2 : 0xD3); \
2407 bemit_mod_am(ext, node); \
2417 static void bemit_shld(const ir_node *node)
2419 const arch_register_t *in = arch_get_irn_register_in(node, n_ia32_ShlD_val_low);
2420 const arch_register_t *out = arch_get_irn_register_out(node, pn_ia32_ShlD_res);
2421 ir_node *count = get_irn_n(node, n_ia32_ShlD_count);
2423 if (is_ia32_Immediate(count)) {
2425 bemit_modrr(out, in);
2426 bemit8(get_ia32_immediate_attr_const(count)->offset);
2429 bemit_modrr(out, in);
2433 static void bemit_shrd(const ir_node *node)
2435 const arch_register_t *in = arch_get_irn_register_in(node, n_ia32_ShrD_val_low);
2436 const arch_register_t *out = arch_get_irn_register_out(node, pn_ia32_ShrD_res);
2437 ir_node *count = get_irn_n(node, n_ia32_ShrD_count);
2439 if (is_ia32_Immediate(count)) {
2441 bemit_modrr(out, in);
2442 bemit8(get_ia32_immediate_attr_const(count)->offset);
2445 bemit_modrr(out, in);
2450 * binary emitter for setcc.
2452 static void bemit_setcc(const ir_node *node)
2454 const arch_register_t *dreg = arch_get_irn_register_out(node, pn_ia32_Setcc_res);
2456 ia32_condition_code_t cc = get_ia32_condcode(node);
2457 cc = determine_final_cc(node, n_ia32_Setcc_eflags, cc);
2458 if (cc & ia32_cc_float_parity_cases) {
2459 if (cc & ia32_cc_negated) {
2462 bemit8(0x90 | pnc2cc(cc));
2463 bemit_modrm8(REG_LOW, dreg);
2468 bemit_modrm8(REG_HIGH, dreg);
2470 /* orb %>dreg, %<dreg */
2472 bemit_modrr8(REG_LOW, dreg, REG_HIGH, dreg);
2476 bemit8(0x90 | pnc2cc(cc));
2477 bemit_modrm8(REG_LOW, dreg);
2482 bemit_modrm8(REG_HIGH, dreg);
2484 /* andb %>dreg, %<dreg */
2486 bemit_modrr8(REG_LOW, dreg, REG_HIGH, dreg);
2491 bemit8(0x90 | pnc2cc(cc));
2492 bemit_modrm8(REG_LOW, dreg);
2496 static void bemit_cmovcc(const ir_node *node)
2498 const ia32_attr_t *attr = get_ia32_attr_const(node);
2499 int ins_permuted = attr->data.ins_permuted;
2500 const arch_register_t *out = arch_get_irn_register_out(node, pn_ia32_res);
2501 ia32_condition_code_t cc = get_ia32_condcode(node);
2502 const arch_register_t *in_true;
2503 const arch_register_t *in_false;
2505 cc = determine_final_cc(node, n_ia32_CMovcc_eflags, cc);
2507 in_true = arch_get_irn_register(get_irn_n(node, n_ia32_CMovcc_val_true));
2508 in_false = arch_get_irn_register(get_irn_n(node, n_ia32_CMovcc_val_false));
2510 /* should be same constraint fullfilled? */
2511 if (out == in_false) {
2512 /* yes -> nothing to do */
2513 } else if (out == in_true) {
2514 assert(get_ia32_op_type(node) == ia32_Normal);
2515 ins_permuted = !ins_permuted;
2519 bemit8(0x8B); // mov %in_false, %out
2520 bemit_modrr(in_false, out);
2524 cc = ia32_negate_condition_code(cc);
2526 if (cc & ia32_cc_float_parity_cases)
2527 panic("cmov can't handle parity float cases");
2530 bemit8(0x40 | pnc2cc(cc));
2531 if (get_ia32_op_type(node) == ia32_Normal) {
2532 bemit_modrr(in_true, out);
2534 bemit_mod_am(reg_gp_map[out->index], node);
2538 static void bemit_cmp(const ir_node *node)
2540 unsigned ls_size = get_mode_size_bits(get_ia32_ls_mode(node));
2546 right = get_irn_n(node, n_ia32_binary_right);
2547 if (is_ia32_Immediate(right)) {
2548 /* Use in-reg, because some instructions (cmp, test) have no out-reg. */
2549 const ir_node *op = get_irn_n(node, n_ia32_binary_right);
2550 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(op);
2553 if (attr->symconst != NULL) {
2556 /* check for sign extension */
2557 size = get_signed_imm_size(attr->offset);
2562 bemit8(0x81 | SIGNEXT_IMM);
2563 /* cmp has this special mode */
2564 if (get_ia32_op_type(node) == ia32_AddrModeS) {
2565 bemit_mod_am(7, node);
2567 const arch_register_t *reg = arch_get_irn_register_in(node, n_ia32_binary_left);
2568 bemit_modru(reg, 7);
2570 bemit8((unsigned char)attr->offset);
2574 /* check for eax variant: this variant is shorter for 32bit immediates only */
2575 if (get_ia32_op_type(node) == ia32_AddrModeS) {
2577 bemit_mod_am(7, node);
2579 const arch_register_t *reg = arch_get_irn_register_in(node, n_ia32_binary_left);
2580 if (reg->index == REG_GP_EAX) {
2584 bemit_modru(reg, 7);
2587 if (ls_size == 16) {
2588 bemit16(attr->offset);
2590 bemit_entity(attr->symconst, attr->sc_sign, attr->offset, false);
2594 panic("invalid imm size?!?");
2596 const arch_register_t *out = arch_get_irn_register_in(node, n_ia32_binary_left);
2598 if (get_ia32_op_type(node) == ia32_Normal) {
2599 const arch_register_t *op2 = arch_get_irn_register_in(node, n_ia32_binary_right);
2600 bemit_modrr(op2, out);
2602 bemit_mod_am(reg_gp_map[out->index], node);
2607 static void bemit_cmp8bit(const ir_node *node)
2609 ir_node *right = get_irn_n(node, n_ia32_binary_right);
2610 if (is_ia32_Immediate(right)) {
2611 if (get_ia32_op_type(node) == ia32_Normal) {
2612 const arch_register_t *out = arch_get_irn_register_in(node, n_ia32_Cmp_left);
2613 if (out->index == REG_GP_EAX) {
2617 bemit_modru(out, 7);
2621 bemit_mod_am(7, node);
2623 bemit8(get_ia32_immediate_attr_const(right)->offset);
2625 const arch_register_t *out = arch_get_irn_register_in(node, n_ia32_Cmp_left);
2627 if (get_ia32_op_type(node) == ia32_Normal) {
2628 const arch_register_t *in = arch_get_irn_register_in(node, n_ia32_Cmp_right);
2629 bemit_modrr(out, in);
2631 bemit_mod_am(reg_gp_map[out->index], node);
2636 static void bemit_test8bit(const ir_node *node)
2638 ir_node *right = get_irn_n(node, n_ia32_Test8Bit_right);
2639 if (is_ia32_Immediate(right)) {
2640 if (get_ia32_op_type(node) == ia32_Normal) {
2641 const arch_register_t *out = arch_get_irn_register_in(node, n_ia32_Test8Bit_left);
2642 if (out->index == REG_GP_EAX) {
2646 bemit_modru(out, 0);
2650 bemit_mod_am(0, node);
2652 bemit8(get_ia32_immediate_attr_const(right)->offset);
2654 const arch_register_t *out = arch_get_irn_register_in(node, n_ia32_Test8Bit_left);
2656 if (get_ia32_op_type(node) == ia32_Normal) {
2657 const arch_register_t *in = arch_get_irn_register_in(node, n_ia32_Test8Bit_right);
2658 bemit_modrr(out, in);
2660 bemit_mod_am(reg_gp_map[out->index], node);
2665 static void bemit_imul(const ir_node *node)
2667 ir_node *right = get_irn_n(node, n_ia32_IMul_right);
2668 /* Do we need the immediate form? */
2669 if (is_ia32_Immediate(right)) {
2670 int imm = get_ia32_immediate_attr_const(right)->offset;
2671 if (get_signed_imm_size(imm) == 1) {
2672 bemit_unop_reg(node, 0x6B, n_ia32_IMul_left);
2675 bemit_unop_reg(node, 0x69, n_ia32_IMul_left);
2680 bemit_unop_reg(node, 0xAF, n_ia32_IMul_right);
2684 static void bemit_dec(const ir_node *node)
2686 const arch_register_t *out = arch_get_irn_register_out(node, pn_ia32_Dec_res);
2687 bemit8(0x48 + reg_gp_map[out->index]);
2690 static void bemit_inc(const ir_node *node)
2692 const arch_register_t *out = arch_get_irn_register_out(node, pn_ia32_Inc_res);
2693 bemit8(0x40 + reg_gp_map[out->index]);
2696 #define UNOPMEM(op, code, ext) \
2697 static void bemit_##op(const ir_node *node) \
2699 bemit_unop_mem(node, code, ext); \
2702 UNOPMEM(notmem, 0xF6, 2)
2703 UNOPMEM(negmem, 0xF6, 3)
2704 UNOPMEM(incmem, 0xFE, 0)
2705 UNOPMEM(decmem, 0xFE, 1)
2707 static void bemit_ldtls(const ir_node *node)
2709 const arch_register_t *out = arch_get_irn_register_out(node, 0);
2711 bemit8(0x65); // gs:
2712 if (out->index == REG_GP_EAX) {
2713 bemit8(0xA1); // movl 0, %eax
2715 bemit8(0x8B); // movl 0, %reg
2716 bemit8(MOD_IND | ENC_REG(reg_gp_map[out->index]) | ENC_RM(0x05));
2724 static void bemit_lea(const ir_node *node)
2726 const arch_register_t *out = arch_get_irn_register_out(node, 0);
2728 bemit_mod_am(reg_gp_map[out->index], node);
2731 /* helper function for bemit_minus64bit */
2732 static void bemit_helper_mov(const arch_register_t *src, const arch_register_t *dst)
2734 bemit8(0x8B); // movl %src, %dst
2735 bemit_modrr(src, dst);
2738 /* helper function for bemit_minus64bit */
2739 static void bemit_helper_neg(const arch_register_t *reg)
2741 bemit8(0xF7); // negl %reg
2742 bemit_modru(reg, 3);
2745 /* helper function for bemit_minus64bit */
2746 static void bemit_helper_sbb0(const arch_register_t *reg)
2748 bemit8(0x83); // sbbl $0, %reg
2749 bemit_modru(reg, 3);
2753 /* helper function for bemit_minus64bit */
2754 static void bemit_helper_sbb(const arch_register_t *src, const arch_register_t *dst)
2756 bemit8(0x1B); // sbbl %src, %dst
2757 bemit_modrr(src, dst);
2760 /* helper function for bemit_minus64bit */
2761 static void bemit_helper_xchg(const arch_register_t *src, const arch_register_t *dst)
2763 if (src->index == REG_GP_EAX) {
2764 bemit8(0x90 + reg_gp_map[dst->index]); // xchgl %eax, %dst
2765 } else if (dst->index == REG_GP_EAX) {
2766 bemit8(0x90 + reg_gp_map[src->index]); // xchgl %src, %eax
2768 bemit8(0x87); // xchgl %src, %dst
2769 bemit_modrr(src, dst);
2773 /* helper function for bemit_minus64bit */
2774 static void bemit_helper_zero(const arch_register_t *reg)
2776 bemit8(0x33); // xorl %reg, %reg
2777 bemit_modrr(reg, reg);
2780 static void bemit_minus64bit(const ir_node *node)
2782 const arch_register_t *in_lo = arch_get_irn_register_in(node, 0);
2783 const arch_register_t *in_hi = arch_get_irn_register_in(node, 1);
2784 const arch_register_t *out_lo = arch_get_irn_register_out(node, 0);
2785 const arch_register_t *out_hi = arch_get_irn_register_out(node, 1);
2787 if (out_lo == in_lo) {
2788 if (out_hi != in_hi) {
2789 /* a -> a, b -> d */
2792 /* a -> a, b -> b */
2795 } else if (out_lo == in_hi) {
2796 if (out_hi == in_lo) {
2797 /* a -> b, b -> a */
2798 bemit_helper_xchg(in_lo, in_hi);
2801 /* a -> b, b -> d */
2802 bemit_helper_mov(in_hi, out_hi);
2803 bemit_helper_mov(in_lo, out_lo);
2807 if (out_hi == in_lo) {
2808 /* a -> c, b -> a */
2809 bemit_helper_mov(in_lo, out_lo);
2811 } else if (out_hi == in_hi) {
2812 /* a -> c, b -> b */
2813 bemit_helper_mov(in_lo, out_lo);
2816 /* a -> c, b -> d */
2817 bemit_helper_mov(in_lo, out_lo);
2823 bemit_helper_neg( out_hi);
2824 bemit_helper_neg( out_lo);
2825 bemit_helper_sbb0(out_hi);
2829 bemit_helper_zero(out_hi);
2830 bemit_helper_neg( out_lo);
2831 bemit_helper_sbb( in_hi, out_hi);
2835 * Emit a single opcode.
2837 #define EMIT_SINGLEOP(op, code) \
2838 static void bemit_ ## op(const ir_node *node) { \
2843 //EMIT_SINGLEOP(daa, 0x27)
2844 //EMIT_SINGLEOP(das, 0x2F)
2845 //EMIT_SINGLEOP(aaa, 0x37)
2846 //EMIT_SINGLEOP(aas, 0x3F)
2847 //EMIT_SINGLEOP(nop, 0x90)
2848 EMIT_SINGLEOP(cwtl, 0x98)
2849 EMIT_SINGLEOP(cltd, 0x99)
2850 //EMIT_SINGLEOP(fwait, 0x9B)
2851 EMIT_SINGLEOP(sahf, 0x9E)
2852 //EMIT_SINGLEOP(popf, 0x9D)
2853 EMIT_SINGLEOP(leave, 0xC9)
2854 EMIT_SINGLEOP(int3, 0xCC)
2855 //EMIT_SINGLEOP(iret, 0xCF)
2856 //EMIT_SINGLEOP(xlat, 0xD7)
2857 //EMIT_SINGLEOP(lock, 0xF0)
2858 EMIT_SINGLEOP(rep, 0xF3)
2859 //EMIT_SINGLEOP(halt, 0xF4)
2860 EMIT_SINGLEOP(cmc, 0xF5)
2861 EMIT_SINGLEOP(stc, 0xF9)
2862 //EMIT_SINGLEOP(cli, 0xFA)
2863 //EMIT_SINGLEOP(sti, 0xFB)
2864 //EMIT_SINGLEOP(std, 0xFD)
2867 * Emits a MOV out, [MEM].
2869 static void bemit_load(const ir_node *node)
2871 const arch_register_t *out = arch_get_irn_register_out(node, 0);
2873 if (out->index == REG_GP_EAX) {
2874 ir_node *base = get_irn_n(node, n_ia32_base);
2875 int has_base = !is_ia32_NoReg_GP(base);
2876 ir_node *idx = get_irn_n(node, n_ia32_index);
2877 int has_index = !is_ia32_NoReg_GP(idx);
2878 if (!has_base && !has_index) {
2879 ir_entity *ent = get_ia32_am_sc(node);
2880 int offs = get_ia32_am_offs_int(node);
2881 /* load from constant address to EAX can be encoded
2884 bemit_entity(ent, 0, offs, false);
2889 bemit_mod_am(reg_gp_map[out->index], node);
2893 * Emits a MOV [mem], in.
2895 static void bemit_store(const ir_node *node)
2897 const ir_node *value = get_irn_n(node, n_ia32_Store_val);
2898 unsigned size = get_mode_size_bits(get_ia32_ls_mode(node));
2900 if (is_ia32_Immediate(value)) {
2903 bemit_mod_am(0, node);
2904 bemit8(get_ia32_immediate_attr_const(value)->offset);
2905 } else if (size == 16) {
2908 bemit_mod_am(0, node);
2909 bemit16(get_ia32_immediate_attr_const(value)->offset);
2912 bemit_mod_am(0, node);
2913 bemit_immediate(value, false);
2916 const arch_register_t *in = arch_get_irn_register_in(node, n_ia32_Store_val);
2918 if (in->index == REG_GP_EAX) {
2919 ir_node *base = get_irn_n(node, n_ia32_base);
2920 int has_base = !is_ia32_NoReg_GP(base);
2921 ir_node *idx = get_irn_n(node, n_ia32_index);
2922 int has_index = !is_ia32_NoReg_GP(idx);
2923 if (!has_base && !has_index) {
2924 ir_entity *ent = get_ia32_am_sc(node);
2925 int offs = get_ia32_am_offs_int(node);
2926 /* store to constant address from EAX can be encoded as
2927 * 0xA2/0xA3 [offset]*/
2935 bemit_entity(ent, 0, offs, false);
2947 bemit_mod_am(reg_gp_map[in->index], node);
2951 static void bemit_conv_i2i(const ir_node *node)
2953 ir_mode *smaller_mode = get_ia32_ls_mode(node);
2962 if (mode_is_signed(smaller_mode)) opcode |= 0x08;
2963 if (get_mode_size_bits(smaller_mode) == 16) opcode |= 0x01;
2964 bemit_unop_reg(node, opcode, n_ia32_Conv_I2I_val);
2970 static void bemit_push(const ir_node *node)
2972 const ir_node *value = get_irn_n(node, n_ia32_Push_val);
2974 if (is_ia32_Immediate(value)) {
2975 const ia32_immediate_attr_t *attr
2976 = get_ia32_immediate_attr_const(value);
2977 unsigned size = get_signed_imm_size(attr->offset);
2983 bemit8((unsigned char)attr->offset);
2988 bemit_immediate(value, false);
2991 } else if (is_ia32_NoReg_GP(value)) {
2993 bemit_mod_am(6, node);
2995 const arch_register_t *reg = arch_get_irn_register_in(node, n_ia32_Push_val);
2996 bemit8(0x50 + reg_gp_map[reg->index]);
3003 static void bemit_pop(const ir_node *node)
3005 const arch_register_t *reg = arch_get_irn_register_out(node, pn_ia32_Pop_res);
3006 bemit8(0x58 + reg_gp_map[reg->index]);
3009 static void bemit_popmem(const ir_node *node)
3012 bemit_mod_am(0, node);
3015 static void bemit_call(const ir_node *node)
3017 ir_node *proc = get_irn_n(node, n_ia32_Call_addr);
3019 if (is_ia32_Immediate(proc)) {
3021 bemit_immediate(proc, true);
3023 bemit_unop(node, 0xFF, 2, n_ia32_Call_addr);
3027 static void bemit_jmp(const ir_node *dest_block)
3030 bemit_jmp_destination(dest_block);
3033 static void bemit_jump(const ir_node *node)
3035 if (can_be_fallthrough(node))
3038 bemit_jmp(get_cfop_target_block(node));
3041 static void bemit_jcc(ia32_condition_code_t pnc, const ir_node *dest_block)
3043 unsigned char cc = pnc2cc(pnc);
3046 bemit_jmp_destination(dest_block);
3049 static void bemit_jp(bool odd, const ir_node *dest_block)
3053 bemit_jmp_destination(dest_block);
3056 static void bemit_ia32_jcc(const ir_node *node)
3058 ia32_condition_code_t cc = get_ia32_condcode(node);
3059 const ir_node *proj_true;
3060 const ir_node *proj_false;
3061 const ir_node *dest_true;
3062 const ir_node *dest_false;
3064 cc = determine_final_cc(node, 0, cc);
3066 /* get both Projs */
3067 proj_true = get_proj(node, pn_ia32_Jcc_true);
3068 assert(proj_true && "Jcc without true Proj");
3070 proj_false = get_proj(node, pn_ia32_Jcc_false);
3071 assert(proj_false && "Jcc without false Proj");
3073 if (can_be_fallthrough(proj_true)) {
3074 /* exchange both proj's so the second one can be omitted */
3075 const ir_node *t = proj_true;
3077 proj_true = proj_false;
3079 cc = ia32_negate_condition_code(cc);
3082 dest_true = get_cfop_target_block(proj_true);
3083 dest_false = get_cfop_target_block(proj_false);
3085 if (cc & ia32_cc_float_parity_cases) {
3086 /* Some floating point comparisons require a test of the parity flag,
3087 * which indicates that the result is unordered */
3088 if (cc & ia32_cc_negated) {
3089 bemit_jp(false, dest_true);
3091 /* we need a local label if the false proj is a fallthrough
3092 * as the falseblock might have no label emitted then */
3093 if (can_be_fallthrough(proj_false)) {
3095 bemit8(0x06); // jp + 6
3097 bemit_jp(false, dest_false);
3101 bemit_jcc(cc, dest_true);
3103 /* the second Proj might be a fallthrough */
3104 if (can_be_fallthrough(proj_false)) {
3105 /* it's a fallthrough */
3107 bemit_jmp(dest_false);
3111 static void bemit_switchjmp(const ir_node *node)
3113 ir_entity *jump_table = get_ia32_am_sc(node);
3114 const ir_switch_table *table = get_ia32_switch_table(node);
3116 bemit8(0xFF); // jmp *tbl.label(,%in,4)
3117 bemit_mod_am(0x05, node);
3119 be_emit_jump_table(node, table, jump_table, get_cfop_target_block);
3125 static void bemit_return(const ir_node *node)
3127 unsigned pop = be_Return_get_pop(node);
3128 if (pop > 0 || be_Return_get_emit_pop(node)) {
3130 assert(pop <= 0xffff);
3137 static void bemit_subsp(const ir_node *node)
3139 const arch_register_t *out;
3142 /* mov %esp, %out */
3144 out = arch_get_irn_register_out(node, 1);
3145 bemit8(MOD_REG | ENC_REG(reg_gp_map[out->index]) | ENC_RM(0x04));
3148 static void bemit_incsp(const ir_node *node)
3151 const arch_register_t *reg;
3155 offs = be_get_IncSP_offset(node);
3166 size = get_signed_imm_size(offs);
3167 bemit8(size == 1 ? 0x83 : 0x81);
3169 reg = arch_get_irn_register_out(node, 0);
3170 bemit_modru(reg, ext);
3179 static void bemit_copybi(const ir_node *node)
3181 unsigned size = get_ia32_copyb_size(node);
3183 bemit8(0xA4); // movsb
3186 bemit8(0xA5); // movsw
3190 bemit8(0xA5); // movsl
3194 static void bemit_fbinop(const ir_node *node, unsigned code, unsigned code_to)
3196 if (get_ia32_op_type(node) == ia32_Normal) {
3197 const ia32_x87_attr_t *x87_attr = get_ia32_x87_attr_const(node);
3198 const arch_register_t *in1 = x87_attr->x87[0];
3199 const arch_register_t *in = x87_attr->x87[1];
3200 const arch_register_t *out = x87_attr->x87[2];
3204 } else if (out == in) {
3208 if (out->index == 0) {
3210 bemit8(MOD_REG | ENC_REG(code) | ENC_RM(in->index));
3213 bemit8(MOD_REG | ENC_REG(code_to) | ENC_RM(out->index));
3216 if (get_mode_size_bits(get_ia32_ls_mode(node)) == 32) {
3221 bemit_mod_am(code, node);
3225 static void bemit_fbinopp(const ir_node *node, unsigned const code)
3227 const ia32_x87_attr_t *x87_attr = get_ia32_x87_attr_const(node);
3228 const arch_register_t *out = x87_attr->x87[2];
3230 bemit8(code + out->index);
3233 static void bemit_fabs(const ir_node *node)
3241 static void bemit_fadd(const ir_node *node)
3243 bemit_fbinop(node, 0, 0);
3246 static void bemit_faddp(const ir_node *node)
3248 bemit_fbinopp(node, 0xC0);
3251 static void bemit_fchs(const ir_node *node)
3259 static void bemit_fdiv(const ir_node *node)
3261 bemit_fbinop(node, 6, 7);
3264 static void bemit_fdivp(const ir_node *node)
3266 bemit_fbinopp(node, 0xF8);
3269 static void bemit_fdivr(const ir_node *node)
3271 bemit_fbinop(node, 7, 6);
3274 static void bemit_fdivrp(const ir_node *node)
3276 bemit_fbinopp(node, 0xF0);
3279 static void bemit_fild(const ir_node *node)
3281 switch (get_mode_size_bits(get_ia32_ls_mode(node))) {
3283 bemit8(0xDF); // filds
3284 bemit_mod_am(0, node);
3288 bemit8(0xDB); // fildl
3289 bemit_mod_am(0, node);
3293 bemit8(0xDF); // fildll
3294 bemit_mod_am(5, node);
3298 panic("invalid mode size");
3302 static void bemit_fist(const ir_node *node)
3304 switch (get_mode_size_bits(get_ia32_ls_mode(node))) {
3306 bemit8(0xDF); // fists
3310 bemit8(0xDB); // fistl
3314 panic("invalid mode size");
3316 bemit_mod_am(2, node);
3319 static void bemit_fistp(const ir_node *node)
3321 switch (get_mode_size_bits(get_ia32_ls_mode(node))) {
3323 bemit8(0xDF); // fistps
3324 bemit_mod_am(3, node);
3328 bemit8(0xDB); // fistpl
3329 bemit_mod_am(3, node);
3333 bemit8(0xDF); // fistpll
3334 bemit_mod_am(7, node);
3338 panic("invalid mode size");
3342 static void bemit_fld(const ir_node *node)
3344 switch (get_mode_size_bits(get_ia32_ls_mode(node))) {
3346 bemit8(0xD9); // flds
3347 bemit_mod_am(0, node);
3351 bemit8(0xDD); // fldl
3352 bemit_mod_am(0, node);
3357 bemit8(0xDB); // fldt
3358 bemit_mod_am(5, node);
3362 panic("invalid mode size");
3366 static void bemit_fld1(const ir_node *node)
3370 bemit8(0xE8); // fld1
3373 static void bemit_fldcw(const ir_node *node)
3375 bemit8(0xD9); // fldcw
3376 bemit_mod_am(5, node);
3379 static void bemit_fldz(const ir_node *node)
3383 bemit8(0xEE); // fldz
3386 static void bemit_fmul(const ir_node *node)
3388 bemit_fbinop(node, 1, 1);
3391 static void bemit_fmulp(const ir_node *node)
3393 bemit_fbinopp(node, 0xC8);
3396 static void bemit_fpop(const ir_node *node)
3398 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
3400 bemit8(0xD8 + attr->x87[0]->index);
3403 static void bemit_fpush(const ir_node *node)
3405 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
3407 bemit8(0xC0 + attr->x87[0]->index);
3410 static void bemit_fpushcopy(const ir_node *node)
3412 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
3414 bemit8(0xC0 + attr->x87[0]->index);
3417 static void bemit_fst(const ir_node *node)
3419 switch (get_mode_size_bits(get_ia32_ls_mode(node))) {
3421 bemit8(0xD9); // fsts
3425 bemit8(0xDD); // fstl
3429 panic("invalid mode size");
3431 bemit_mod_am(2, node);
3434 static void bemit_fstp(const ir_node *node)
3436 switch (get_mode_size_bits(get_ia32_ls_mode(node))) {
3438 bemit8(0xD9); // fstps
3439 bemit_mod_am(3, node);
3443 bemit8(0xDD); // fstpl
3444 bemit_mod_am(3, node);
3449 bemit8(0xDB); // fstpt
3450 bemit_mod_am(7, node);
3454 panic("invalid mode size");
3458 static void bemit_fsub(const ir_node *node)
3460 bemit_fbinop(node, 4, 5);
3463 static void bemit_fsubp(const ir_node *node)
3465 bemit_fbinopp(node, 0xE8);
3468 static void bemit_fsubr(const ir_node *node)
3470 bemit_fbinop(node, 5, 4);
3473 static void bemit_fsubrp(const ir_node *node)
3475 bemit_fbinopp(node, 0xE0);
3478 static void bemit_fnstcw(const ir_node *node)
3480 bemit8(0xD9); // fnstcw
3481 bemit_mod_am(7, node);
3484 static void bemit_fnstsw(void)
3486 bemit8(0xDF); // fnstsw %ax
3490 static void bemit_ftstfnstsw(const ir_node *node)
3494 bemit8(0xD9); // ftst
3499 static void bemit_fucomi(const ir_node *node)
3501 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
3502 bemit8(0xDB); // fucomi
3503 bemit8(0xE8 + attr->x87[1]->index);
3506 static void bemit_fucomip(const ir_node *node)
3508 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
3509 bemit8(0xDF); // fucomip
3510 bemit8(0xE8 + attr->x87[1]->index);
3513 static void bemit_fucomfnstsw(const ir_node *node)
3515 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
3516 bemit8(0xDD); // fucom
3517 bemit8(0xE0 + attr->x87[1]->index);
3521 static void bemit_fucompfnstsw(const ir_node *node)
3523 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
3524 bemit8(0xDD); // fucomp
3525 bemit8(0xE8 + attr->x87[1]->index);
3529 static void bemit_fucomppfnstsw(const ir_node *node)
3533 bemit8(0xDA); // fucompp
3538 static void bemit_fxch(const ir_node *node)
3540 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
3542 bemit8(0xC8 + attr->x87[0]->index);
3546 * The type of a emitter function.
3548 typedef void (*emit_func) (const ir_node *);
3551 * Set a node emitter. Make it a bit more type safe.
3553 static void register_emitter(ir_op *op, emit_func func)
3555 op->ops.generic = (op_func) func;
3558 static void ia32_register_binary_emitters(void)
3560 /* first clear the generic function pointer for all ops */
3561 ir_clear_opcodes_generic_func();
3563 /* benode emitter */
3564 register_emitter(op_be_Copy, bemit_copy);
3565 register_emitter(op_be_CopyKeep, bemit_copy);
3566 register_emitter(op_be_IncSP, bemit_incsp);
3567 register_emitter(op_be_Perm, bemit_perm);
3568 register_emitter(op_be_Return, bemit_return);
3569 register_emitter(op_ia32_Adc, bemit_adc);
3570 register_emitter(op_ia32_Add, bemit_add);
3571 register_emitter(op_ia32_AddMem, bemit_addmem);
3572 register_emitter(op_ia32_AddMem8Bit, bemit_addmem8bit);
3573 register_emitter(op_ia32_And, bemit_and);
3574 register_emitter(op_ia32_AndMem, bemit_andmem);
3575 register_emitter(op_ia32_AndMem8Bit, bemit_andmem8bit);
3576 register_emitter(op_ia32_Breakpoint, bemit_int3);
3577 register_emitter(op_ia32_CMovcc, bemit_cmovcc);
3578 register_emitter(op_ia32_Call, bemit_call);
3579 register_emitter(op_ia32_Cltd, bemit_cltd);
3580 register_emitter(op_ia32_Cmc, bemit_cmc);
3581 register_emitter(op_ia32_Cmp, bemit_cmp);
3582 register_emitter(op_ia32_Cmp8Bit, bemit_cmp8bit);
3583 register_emitter(op_ia32_Const, bemit_mov_const);
3584 register_emitter(op_ia32_Conv_I2I, bemit_conv_i2i);
3585 register_emitter(op_ia32_Conv_I2I8Bit, bemit_conv_i2i);
3586 register_emitter(op_ia32_CopyB_i, bemit_copybi);
3587 register_emitter(op_ia32_Cwtl, bemit_cwtl);
3588 register_emitter(op_ia32_Dec, bemit_dec);
3589 register_emitter(op_ia32_DecMem, bemit_decmem);
3590 register_emitter(op_ia32_Div, bemit_div);
3591 register_emitter(op_ia32_FldCW, bemit_fldcw);
3592 register_emitter(op_ia32_FnstCW, bemit_fnstcw);
3593 register_emitter(op_ia32_FtstFnstsw, bemit_ftstfnstsw);
3594 register_emitter(op_ia32_FucomFnstsw, bemit_fucomfnstsw);
3595 register_emitter(op_ia32_Fucomi, bemit_fucomi);
3596 register_emitter(op_ia32_FucompFnstsw, bemit_fucompfnstsw);
3597 register_emitter(op_ia32_Fucompi, bemit_fucomip);
3598 register_emitter(op_ia32_FucomppFnstsw, bemit_fucomppfnstsw);
3599 register_emitter(op_ia32_IDiv, bemit_idiv);
3600 register_emitter(op_ia32_IJmp, bemit_ijmp);
3601 register_emitter(op_ia32_IMul, bemit_imul);
3602 register_emitter(op_ia32_IMul1OP, bemit_imul1op);
3603 register_emitter(op_ia32_Inc, bemit_inc);
3604 register_emitter(op_ia32_IncMem, bemit_incmem);
3605 register_emitter(op_ia32_Jcc, bemit_ia32_jcc);
3606 register_emitter(op_ia32_Jmp, bemit_jump);
3607 register_emitter(op_ia32_LdTls, bemit_ldtls);
3608 register_emitter(op_ia32_Lea, bemit_lea);
3609 register_emitter(op_ia32_Leave, bemit_leave);
3610 register_emitter(op_ia32_Load, bemit_load);
3611 register_emitter(op_ia32_Minus64Bit, bemit_minus64bit);
3612 register_emitter(op_ia32_Mul, bemit_mul);
3613 register_emitter(op_ia32_Neg, bemit_neg);
3614 register_emitter(op_ia32_NegMem, bemit_negmem);
3615 register_emitter(op_ia32_Not, bemit_not);
3616 register_emitter(op_ia32_NotMem, bemit_notmem);
3617 register_emitter(op_ia32_Or, bemit_or);
3618 register_emitter(op_ia32_OrMem, bemit_ormem);
3619 register_emitter(op_ia32_OrMem8Bit, bemit_ormem8bit);
3620 register_emitter(op_ia32_Pop, bemit_pop);
3621 register_emitter(op_ia32_PopEbp, bemit_pop);
3622 register_emitter(op_ia32_PopMem, bemit_popmem);
3623 register_emitter(op_ia32_Push, bemit_push);
3624 register_emitter(op_ia32_RepPrefix, bemit_rep);
3625 register_emitter(op_ia32_Rol, bemit_rol);
3626 register_emitter(op_ia32_RolMem, bemit_rolmem);
3627 register_emitter(op_ia32_Ror, bemit_ror);
3628 register_emitter(op_ia32_RorMem, bemit_rormem);
3629 register_emitter(op_ia32_Sahf, bemit_sahf);
3630 register_emitter(op_ia32_Sar, bemit_sar);
3631 register_emitter(op_ia32_SarMem, bemit_sarmem);
3632 register_emitter(op_ia32_Sbb, bemit_sbb);
3633 register_emitter(op_ia32_Setcc, bemit_setcc);
3634 register_emitter(op_ia32_Shl, bemit_shl);
3635 register_emitter(op_ia32_ShlD, bemit_shld);
3636 register_emitter(op_ia32_ShlMem, bemit_shlmem);
3637 register_emitter(op_ia32_Shr, bemit_shr);
3638 register_emitter(op_ia32_ShrD, bemit_shrd);
3639 register_emitter(op_ia32_ShrMem, bemit_shrmem);
3640 register_emitter(op_ia32_Stc, bemit_stc);
3641 register_emitter(op_ia32_Store, bemit_store);
3642 register_emitter(op_ia32_Store8Bit, bemit_store);
3643 register_emitter(op_ia32_Sub, bemit_sub);
3644 register_emitter(op_ia32_SubMem, bemit_submem);
3645 register_emitter(op_ia32_SubMem8Bit, bemit_submem8bit);
3646 register_emitter(op_ia32_SubSP, bemit_subsp);
3647 register_emitter(op_ia32_SwitchJmp, bemit_switchjmp);
3648 register_emitter(op_ia32_Test, bemit_test);
3649 register_emitter(op_ia32_Test8Bit, bemit_test8bit);
3650 register_emitter(op_ia32_Xor, bemit_xor);
3651 register_emitter(op_ia32_Xor0, bemit_xor0);
3652 register_emitter(op_ia32_XorMem, bemit_xormem);
3653 register_emitter(op_ia32_XorMem8Bit, bemit_xormem8bit);
3654 register_emitter(op_ia32_fabs, bemit_fabs);
3655 register_emitter(op_ia32_fadd, bemit_fadd);
3656 register_emitter(op_ia32_faddp, bemit_faddp);
3657 register_emitter(op_ia32_fchs, bemit_fchs);
3658 register_emitter(op_ia32_fdiv, bemit_fdiv);
3659 register_emitter(op_ia32_fdivp, bemit_fdivp);
3660 register_emitter(op_ia32_fdivr, bemit_fdivr);
3661 register_emitter(op_ia32_fdivrp, bemit_fdivrp);
3662 register_emitter(op_ia32_fild, bemit_fild);
3663 register_emitter(op_ia32_fist, bemit_fist);
3664 register_emitter(op_ia32_fistp, bemit_fistp);
3665 register_emitter(op_ia32_fld, bemit_fld);
3666 register_emitter(op_ia32_fld1, bemit_fld1);
3667 register_emitter(op_ia32_fldz, bemit_fldz);
3668 register_emitter(op_ia32_fmul, bemit_fmul);
3669 register_emitter(op_ia32_fmulp, bemit_fmulp);
3670 register_emitter(op_ia32_fpop, bemit_fpop);
3671 register_emitter(op_ia32_fpush, bemit_fpush);
3672 register_emitter(op_ia32_fpushCopy, bemit_fpushcopy);
3673 register_emitter(op_ia32_fst, bemit_fst);
3674 register_emitter(op_ia32_fstp, bemit_fstp);
3675 register_emitter(op_ia32_fsub, bemit_fsub);
3676 register_emitter(op_ia32_fsubp, bemit_fsubp);
3677 register_emitter(op_ia32_fsubr, bemit_fsubr);
3678 register_emitter(op_ia32_fsubrp, bemit_fsubrp);
3679 register_emitter(op_ia32_fxch, bemit_fxch);
3681 /* ignore the following nodes */
3682 register_emitter(op_ia32_ProduceVal, emit_Nothing);
3683 register_emitter(op_be_Keep, emit_Nothing);
3684 register_emitter(op_be_Start, emit_Nothing);
3685 register_emitter(op_Phi, emit_Nothing);
3686 register_emitter(op_Start, emit_Nothing);
3689 static void gen_binary_block(ir_node *block)
3691 ia32_emit_block_header(block);
3693 /* emit the contents of the block */
3694 sched_foreach(block, node) {
3695 ia32_emit_node(node);
3699 void ia32_gen_binary_routine(ir_graph *irg)
3701 ir_entity *entity = get_irg_entity(irg);
3702 const arch_env_t *arch_env = be_get_irg_arch_env(irg);
3703 ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
3704 ir_node **blk_sched = irg_data->blk_sched;
3706 parameter_dbg_info_t *infos;
3708 isa = (ia32_isa_t*) arch_env;
3710 ia32_register_binary_emitters();
3712 infos = construct_parameter_infos(irg);
3713 be_gas_emit_function_prolog(entity, ia32_cg_config.function_alignment,
3717 /* we use links to point to target blocks */
3718 ir_reserve_resources(irg, IR_RESOURCE_IRN_LINK);
3719 irg_block_walk_graph(irg, ia32_gen_labels, NULL, NULL);
3721 /* initialize next block links */
3722 n = ARR_LEN(blk_sched);
3723 for (i = 0; i < n; ++i) {
3724 ir_node *block = blk_sched[i];
3725 ir_node *prev = i > 0 ? blk_sched[i-1] : NULL;
3727 set_irn_link(block, prev);
3730 for (i = 0; i < n; ++i) {
3731 ir_node *block = blk_sched[i];
3732 gen_binary_block(block);
3735 be_gas_emit_function_epilog(entity);
3737 ir_free_resources(irg, IR_RESOURCE_IRN_LINK);
3741 void ia32_init_emitter(void)
3743 lc_opt_entry_t *be_grp;
3744 lc_opt_entry_t *ia32_grp;
3746 be_grp = lc_opt_get_grp(firm_opt_get_root(), "be");
3747 ia32_grp = lc_opt_get_grp(be_grp, "ia32");
3749 lc_opt_add_table(ia32_grp, ia32_emitter_options);
3753 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.emitter");