2 * This file implements the node emitter.
3 * @author Christian Wuerdig
22 #include "iredges_t.h"
25 #include "../besched_t.h"
26 #include "../benode_t.h"
28 #include "../be_dbgout.h"
30 #include "ia32_emitter.h"
31 #include "gen_ia32_emitter.h"
32 #include "gen_ia32_regalloc_if.h"
33 #include "ia32_nodes_attr.h"
34 #include "ia32_new_nodes.h"
35 #include "ia32_map_regs.h"
36 #include "bearch_ia32_t.h"
38 #define BLOCK_PREFIX(x) ".L" x
40 #define SNPRINTF_BUF_LEN 128
42 /* global arch_env for lc_printf functions */
43 static const arch_env_t *arch_env = NULL;
45 /** by default, we generate assembler code for the Linux gas */
46 asm_flavour_t asm_flavour = ASM_LINUX_GAS;
49 * Switch to a new section
51 void ia32_switch_section(FILE *F, section_t sec) {
52 static section_t curr_sec = NO_SECTION;
53 static const char *text[ASM_MAX][SECTION_MAX] = {
59 ".section\t.tbss,\"awT\",@nobits",
60 ".section\t.ctors,\"aw\",@progbits"
65 ".section .rdata,\"dr\"",
67 ".section\t.tbss,\"awT\",@nobits",
68 ".section\t.ctors,\"aw\",@progbits"
87 fprintf(F, "\t%s\n", text[asm_flavour][sec]);
95 static void ia32_dump_function_object(FILE *F, const char *name)
97 switch (asm_flavour) {
99 fprintf(F, "\t.type\t%s, @function\n", name);
102 fprintf(F, "\t.def\t%s;\t.scl\t2;\t.type\t32;\t.endef\n", name);
109 static void ia32_dump_function_size(FILE *F, const char *name)
111 switch (asm_flavour) {
113 fprintf(F, "\t.size\t%s, .-%s\n", name, name);
120 /*************************************************************
122 * (_) | | / _| | | | |
123 * _ __ _ __ _ _ __ | |_| |_ | |__ ___| |_ __ ___ _ __
124 * | '_ \| '__| | '_ \| __| _| | '_ \ / _ \ | '_ \ / _ \ '__|
125 * | |_) | | | | | | | |_| | | | | | __/ | |_) | __/ |
126 * | .__/|_| |_|_| |_|\__|_| |_| |_|\___|_| .__/ \___|_|
129 *************************************************************/
131 static INLINE int be_is_unknown_reg(const arch_register_t *reg) {
133 REGS_ARE_EQUAL(reg, &ia32_gp_regs[REG_GP_UKNWN]) || \
134 REGS_ARE_EQUAL(reg, &ia32_xmm_regs[REG_XMM_UKNWN]) || \
135 REGS_ARE_EQUAL(reg, &ia32_vfp_regs[REG_VFP_UKNWN]);
139 * returns true if a node has x87 registers
141 static INLINE int has_x87_register(const ir_node *n) {
142 return is_irn_machine_user(n, 0);
145 /* We always pass the ir_node which is a pointer. */
146 static int ia32_get_arg_type(const lc_arg_occ_t *occ) {
147 return lc_arg_type_ptr;
152 * Returns the register at in position pos.
154 static const arch_register_t *get_in_reg(const ir_node *irn, int pos) {
156 const arch_register_t *reg = NULL;
158 assert(get_irn_arity(irn) > pos && "Invalid IN position");
160 /* The out register of the operator at position pos is the
161 in register we need. */
162 op = get_irn_n(irn, pos);
164 reg = arch_get_irn_register(arch_env, op);
166 assert(reg && "no in register found");
168 /* in case of unknown: just return a register */
169 if (REGS_ARE_EQUAL(reg, &ia32_gp_regs[REG_GP_UKNWN]))
170 reg = &ia32_gp_regs[REG_EAX];
171 else if (REGS_ARE_EQUAL(reg, &ia32_xmm_regs[REG_XMM_UKNWN]))
172 reg = &ia32_xmm_regs[REG_XMM0];
173 else if (REGS_ARE_EQUAL(reg, &ia32_vfp_regs[REG_VFP_UKNWN]))
174 reg = &ia32_vfp_regs[REG_VF0];
180 * Returns the register at out position pos.
182 static const arch_register_t *get_out_reg(const ir_node *irn, int pos) {
184 const arch_register_t *reg = NULL;
186 /* 1st case: irn is not of mode_T, so it has only */
187 /* one OUT register -> good */
188 /* 2nd case: irn is of mode_T -> collect all Projs and ask the */
189 /* Proj with the corresponding projnum for the register */
191 if (get_irn_mode(irn) != mode_T) {
192 reg = arch_get_irn_register(arch_env, irn);
194 else if (is_ia32_irn(irn)) {
195 reg = get_ia32_out_reg(irn, pos);
198 const ir_edge_t *edge;
200 foreach_out_edge(irn, edge) {
201 proj = get_edge_src_irn(edge);
202 assert(is_Proj(proj) && "non-Proj from mode_T node");
203 if (get_Proj_proj(proj) == pos) {
204 reg = arch_get_irn_register(arch_env, proj);
210 assert(reg && "no out register found");
220 * Returns the name of the in register at position pos.
222 static const char *get_ia32_reg_name(ir_node *irn, int pos, enum io_direction in_out) {
223 const arch_register_t *reg;
225 if (in_out == IN_REG) {
226 reg = get_in_reg(irn, pos);
228 if (reg->reg_class == &ia32_reg_classes[CLASS_ia32_vfp]) {
229 /* FIXME: works for binop only */
230 assert(2 <= pos && pos <= 3);
231 reg = get_ia32_attr(irn)->x87[pos - 2];
235 /* destination address mode nodes don't have outputs */
236 if (is_ia32_irn(irn) && get_ia32_op_type(irn) == ia32_AddrModeD) {
240 reg = get_out_reg(irn, pos);
241 if (reg->reg_class == &ia32_reg_classes[CLASS_ia32_vfp])
242 reg = get_ia32_attr(irn)->x87[pos + 2];
244 return arch_register_get_name(reg);
248 * Get the register name for a node.
250 static int ia32_get_reg_name(lc_appendable_t *app,
251 const lc_arg_occ_t *occ, const lc_arg_value_t *arg)
254 ir_node *irn = arg->v_ptr;
255 int nr = occ->width - 1;
258 return lc_appendable_snadd(app, "(null)", 6);
260 buf = get_ia32_reg_name(irn, nr, occ->conversion == 'S' ? IN_REG : OUT_REG);
262 /* append the stupid % to register names */
263 lc_appendable_chadd(app, '%');
264 return lc_appendable_snadd(app, buf, strlen(buf));
268 * Get the x87 register name for a node.
270 static int ia32_get_x87_name(lc_appendable_t *app,
271 const lc_arg_occ_t *occ, const lc_arg_value_t *arg)
274 ir_node *irn = arg->v_ptr;
275 int nr = occ->width - 1;
279 return lc_appendable_snadd(app, "(null)", 6);
281 attr = get_ia32_attr(irn);
282 buf = attr->x87[nr]->name;
283 lc_appendable_chadd(app, '%');
284 return lc_appendable_snadd(app, buf, strlen(buf));
288 * Returns the tarval, offset or scale of an ia32 as a string.
290 static int ia32_const_to_str(lc_appendable_t *app,
291 const lc_arg_occ_t *occ, const lc_arg_value_t *arg)
294 ir_node *irn = arg->v_ptr;
297 return lc_arg_append(app, occ, "(null)", 6);
299 if (occ->conversion == 'C') {
300 buf = get_ia32_cnst(irn);
303 buf = get_ia32_am_offs(irn);
306 return buf ? lc_appendable_snadd(app, buf, strlen(buf)) : 0;
310 * Determines the SSE suffix depending on the mode.
312 static int ia32_get_mode_suffix(lc_appendable_t *app,
313 const lc_arg_occ_t *occ, const lc_arg_value_t *arg)
315 ir_node *irn = arg->v_ptr;
316 ir_mode *mode = get_irn_mode(irn);
318 if (mode == mode_T) {
319 mode = get_ia32_res_mode(irn);
321 mode = get_ia32_ls_mode(irn);
325 return lc_arg_append(app, occ, "(null)", 6);
327 if (mode_is_float(mode)) {
328 return lc_appendable_chadd(app, get_mode_size_bits(mode) == 32 ? 's' : 'd');
331 return lc_appendable_chadd(app, mode_is_signed(mode) ? 's' : 'z');
336 * Return the ia32 printf arg environment.
337 * We use the firm environment with some additional handlers.
339 const lc_arg_env_t *ia32_get_arg_env(void) {
340 static lc_arg_env_t *env = NULL;
342 static const lc_arg_handler_t ia32_reg_handler = { ia32_get_arg_type, ia32_get_reg_name };
343 static const lc_arg_handler_t ia32_const_handler = { ia32_get_arg_type, ia32_const_to_str };
344 static const lc_arg_handler_t ia32_mode_handler = { ia32_get_arg_type, ia32_get_mode_suffix };
345 static const lc_arg_handler_t ia32_x87_handler = { ia32_get_arg_type, ia32_get_x87_name };
348 /* extend the firm printer */
349 env = firm_get_arg_env();
351 lc_arg_register(env, "ia32:sreg", 'S', &ia32_reg_handler);
352 lc_arg_register(env, "ia32:dreg", 'D', &ia32_reg_handler);
353 lc_arg_register(env, "ia32:cnst", 'C', &ia32_const_handler);
354 lc_arg_register(env, "ia32:offs", 'O', &ia32_const_handler);
355 lc_arg_register(env, "ia32:mode", 'M', &ia32_mode_handler);
356 lc_arg_register(env, "ia32:x87", 'X', &ia32_x87_handler);
362 static const char *ia32_get_reg_name_for_mode(ia32_emit_env_t *env, ir_mode *mode, const arch_register_t *reg) {
363 switch(get_mode_size_bits(mode)) {
365 return ia32_get_mapped_reg_name(env->isa->regs_8bit, reg);
367 return ia32_get_mapped_reg_name(env->isa->regs_16bit, reg);
369 return (char *)arch_register_get_name(reg);
374 * Emits registers and/or address mode of a binary operation.
376 const char *ia32_emit_binop(const ir_node *n, ia32_emit_env_t *env) {
377 static char *buf = NULL;
379 /* verify that this function is never called on non-AM supporting operations */
380 //assert(get_ia32_am_support(n) != ia32_am_None && "emit binop expects addressmode support");
382 #define PRODUCES_RESULT(n) \
383 (!(is_ia32_St(n) || \
384 is_ia32_Store8Bit(n) || \
385 is_ia32_CondJmp(n) || \
386 is_ia32_xCondJmp(n) || \
387 is_ia32_CmpSet(n) || \
388 is_ia32_xCmpSet(n) || \
389 is_ia32_SwitchJmp(n)))
392 buf = xcalloc(1, SNPRINTF_BUF_LEN);
395 memset(buf, 0, SNPRINTF_BUF_LEN);
398 switch(get_ia32_op_type(n)) {
400 if (is_ia32_ImmConst(n)) {
401 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%3S, %s", n, get_ia32_cnst(n));
403 else if (is_ia32_ImmSymConst(n)) {
404 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%3S, OFFSET FLAT:%s", n, get_ia32_cnst(n));
407 const arch_register_t *in1 = get_in_reg(n, 2);
408 const arch_register_t *in2 = get_in_reg(n, 3);
409 const arch_register_t *out = PRODUCES_RESULT(n) ? get_out_reg(n, 0) : NULL;
410 const arch_register_t *in;
413 in = out ? (REGS_ARE_EQUAL(out, in2) ? in1 : in2) : in2;
414 out = out ? out : in1;
415 in_name = arch_register_get_name(in);
417 if (is_ia32_emit_cl(n)) {
418 assert(REGS_ARE_EQUAL(&ia32_gp_regs[REG_ECX], in) && "shift operation needs ecx");
422 snprintf(buf, SNPRINTF_BUF_LEN, "%%%s, %%%s", arch_register_get_name(out), in_name);
426 if (is_ia32_ImmConst(n) || is_ia32_ImmSymConst(n)) {
427 assert(! PRODUCES_RESULT(n) && "Source AM with Const must not produce result");
428 snprintf(buf, SNPRINTF_BUF_LEN, "%s, %s", get_ia32_cnst(n), ia32_emit_am(n, env));
431 if (PRODUCES_RESULT(n)) {
432 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%1D, %s", n, ia32_emit_am(n, env));
435 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%3S, %s", n, ia32_emit_am(n, env));
440 if (is_ia32_ImmConst(n) || is_ia32_ImmSymConst(n)) {
441 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%s,%s%s",
442 ia32_emit_am(n, env),
443 is_ia32_ImmSymConst(n) ? " OFFSET FLAT:" : " ", /* In case of a symconst we must add OFFSET to */
444 get_ia32_cnst(n)); /* tell the assembler to store it's address. */
447 const arch_register_t *in1 = get_in_reg(n, get_irn_arity(n) == 5 ? 3 : 2);
448 ir_mode *mode = get_ia32_res_mode(n);
451 mode = mode ? mode : get_ia32_ls_mode(n);
452 in_name = ia32_get_reg_name_for_mode(env, mode, in1);
454 if (is_ia32_emit_cl(n)) {
455 assert(REGS_ARE_EQUAL(&ia32_gp_regs[REG_ECX], in1) && "shift operation needs ecx");
459 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%s, %%%s", ia32_emit_am(n, env), in_name);
463 assert(0 && "unsupported op type");
466 #undef PRODUCES_RESULT
472 * Returns the xxx PTR string for a given mode
474 * @param mode the mode
475 * @param x87_insn if non-zero returns the string for a x87 instruction
476 * else for a SSE instruction
478 static const char *pointer_size(ir_mode *mode, int x87_insn)
481 switch (get_mode_size_bits(mode)) {
482 case 8: return "BYTE PTR";
483 case 16: return "WORD PTR";
484 case 32: return "DWORD PTR";
490 case 96: return "XWORD PTR";
491 default: return NULL;
498 * Emits registers and/or address mode of a binary operation.
500 const char *ia32_emit_x87_binop(const ir_node *n, ia32_emit_env_t *env) {
501 static char *buf = NULL;
503 /* verify that this function is never called on non-AM supporting operations */
504 //assert(get_ia32_am_support(n) != ia32_am_None && "emit binop expects addressmode support");
507 buf = xcalloc(1, SNPRINTF_BUF_LEN);
510 memset(buf, 0, SNPRINTF_BUF_LEN);
513 switch(get_ia32_op_type(n)) {
515 if (is_ia32_ImmConst(n) || is_ia32_ImmSymConst(n)) {
516 ir_mode *mode = get_ia32_ls_mode(n);
517 const char *p = pointer_size(mode, 1);
518 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%s %s", p, get_ia32_cnst(n));
521 ia32_attr_t *attr = get_ia32_attr(n);
522 const arch_register_t *in1 = attr->x87[0];
523 const arch_register_t *in2 = attr->x87[1];
524 const arch_register_t *out = attr->x87[2];
525 const arch_register_t *in;
528 in = out ? (REGS_ARE_EQUAL(out, in2) ? in1 : in2) : in2;
529 out = out ? out : in1;
530 in_name = arch_register_get_name(in);
532 snprintf(buf, SNPRINTF_BUF_LEN, "%%%s, %%%s", arch_register_get_name(out), in_name);
537 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%s", ia32_emit_am(n, env));
540 assert(0 && "unsupported op type");
547 * Emits registers and/or address mode of a unary operation.
549 const char *ia32_emit_unop(const ir_node *n, ia32_emit_env_t *env) {
550 static char *buf = NULL;
553 buf = xcalloc(1, SNPRINTF_BUF_LEN);
556 memset(buf, 0, SNPRINTF_BUF_LEN);
559 switch(get_ia32_op_type(n)) {
561 if (is_ia32_ImmConst(n)) {
562 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%C", n);
564 else if (is_ia32_ImmSymConst(n)) {
565 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "OFFSET FLAT:%C", n);
568 if (is_ia32_MulS(n) || is_ia32_Mulh(n)) {
569 /* MulS and Mulh implicitly multiply by EAX */
570 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%4S", n);
571 } else if(is_ia32_Push(n)) {
572 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%3S", n);
574 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%1D", n);
579 assert(!is_ia32_Push(n));
580 snprintf(buf, SNPRINTF_BUF_LEN, "%s", ia32_emit_am(n, env));
584 Mulh is emitted via emit_unop
585 imul [MEM] means EDX:EAX <- EAX * [MEM]
587 assert((is_ia32_Mulh(n) || is_ia32_MulS(n) || is_ia32_Push(n)) && "Only MulS and Mulh can have AM source as unop");
588 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%s", ia32_emit_am(n, env));
591 assert(0 && "unsupported op type");
598 * Emits address mode.
600 const char *ia32_emit_am(const ir_node *n, ia32_emit_env_t *env) {
601 ia32_am_flavour_t am_flav = get_ia32_am_flavour(n);
605 static struct obstack *obst = NULL;
606 ir_mode *mode = get_ia32_ls_mode(n);
608 if (! is_ia32_Lea(n))
609 assert(mode && "AM node must have ls_mode attribute set.");
612 obst = xcalloc(1, sizeof(*obst));
615 obstack_free(obst, NULL);
618 /* obstack_free with NULL results in an uninitialized obstack */
621 p = pointer_size(mode, has_x87_register(n) || is_ia32_GetST0(n) || is_ia32_SetST0(n));
623 obstack_printf(obst, "%s ", p);
625 /* emit address mode symconst */
626 if (get_ia32_am_sc(n)) {
627 if (is_ia32_am_sc_sign(n))
628 obstack_printf(obst, "-");
629 obstack_printf(obst, "%s", get_id_str(get_ia32_am_sc(n)));
632 if (am_flav & ia32_B) {
633 obstack_printf(obst, "[");
634 lc_eoprintf(ia32_get_arg_env(), obst, "%1S", n);
638 if (am_flav & ia32_I) {
640 obstack_printf(obst, "+");
643 obstack_printf(obst, "[");
646 lc_eoprintf(ia32_get_arg_env(), obst, "%2S", n);
648 if (am_flav & ia32_S) {
649 obstack_printf(obst, "*%d", 1 << get_ia32_am_scale(n));
655 if (am_flav & ia32_O) {
656 s = get_ia32_am_offs(n);
659 /* omit explicit + if there was no base or index */
661 obstack_printf(obst, "[");
666 obstack_printf(obst, s);
672 obstack_printf(obst, "] ");
674 obstack_1grow(obst, '\0');
675 s = obstack_finish(obst);
683 const char *ia32_emit_adr(const ir_node *irn, ia32_emit_env_t *env)
685 static char buf[SNPRINTF_BUF_LEN];
686 ir_mode *mode = get_ia32_ls_mode(irn);
687 const char *adr = get_ia32_cnst(irn);
688 const char *pref = pointer_size(mode, has_x87_register(irn));
690 snprintf(buf, SNPRINTF_BUF_LEN, "%s %s", pref ? pref : "", adr);
695 * Formated print of commands and comments.
697 static void ia32_fprintf_format(FILE *F, const ir_node *irn, char *cmd_buf, char *cmnt_buf) {
699 const char *name = irn ? be_retrieve_dbg_info(get_irn_dbg_info((ir_node *)irn), &lineno) : NULL;
702 fprintf(F, "\t%-35s %-60s /* %s:%u */\n", cmd_buf, cmnt_buf, name, lineno);
704 fprintf(F, "\t%-35s %-60s\n", cmd_buf, cmnt_buf);
710 * Add a number to a prefix. This number will not be used a second time.
712 static char *get_unique_label(char *buf, size_t buflen, const char *prefix) {
713 static unsigned long id = 0;
714 snprintf(buf, buflen, "%s%lu", prefix, ++id);
720 /*************************************************
723 * ___ _ __ ___ _| |_ ___ ___ _ __ __| |
724 * / _ \ '_ ` _ \| | __| / __/ _ \| '_ \ / _` |
725 * | __/ | | | | | | |_ | (_| (_) | | | | (_| |
726 * \___|_| |_| |_|_|\__| \___\___/|_| |_|\__,_|
728 *************************************************/
731 #define IA32_DO_EMIT(irn) ia32_fprintf_format(F, irn, cmd_buf, cmnt_buf)
734 * coding of conditions
736 struct cmp2conditon_t {
742 * positive conditions for signed compares
744 static const struct cmp2conditon_t cmp2condition_s[] = {
745 { NULL, pn_Cmp_False }, /* always false */
746 { "e", pn_Cmp_Eq }, /* == */
747 { "l", pn_Cmp_Lt }, /* < */
748 { "le", pn_Cmp_Le }, /* <= */
749 { "g", pn_Cmp_Gt }, /* > */
750 { "ge", pn_Cmp_Ge }, /* >= */
751 { "ne", pn_Cmp_Lg }, /* != */
752 { "ordered", pn_Cmp_Leg }, /* Floating point: ordered */
753 { "unordered", pn_Cmp_Uo }, /* FLoting point: unordered */
754 { "e", pn_Cmp_Ue }, /* Floating point: unordered or == */
755 { "b", pn_Cmp_Ul }, /* Floating point: unordered or < */
756 { "be", pn_Cmp_Ule }, /* Floating point: unordered or <= */
757 { "a", pn_Cmp_Ug }, /* Floating point: unordered or > */
758 { "ae", pn_Cmp_Uge }, /* Floating point: unordered or >= */
759 { "ne", pn_Cmp_Ne }, /* Floating point: unordered or != */
760 { NULL, pn_Cmp_True }, /* always true */
764 * positive conditions for unsigned compares
766 static const struct cmp2conditon_t cmp2condition_u[] = {
767 { NULL, pn_Cmp_False }, /* always false */
768 { "e", pn_Cmp_Eq }, /* == */
769 { "b", pn_Cmp_Lt }, /* < */
770 { "be", pn_Cmp_Le }, /* <= */
771 { "a", pn_Cmp_Gt }, /* > */
772 { "ae", pn_Cmp_Ge }, /* >= */
773 { "ne", pn_Cmp_Lg }, /* != */
774 { "ordered", pn_Cmp_Leg }, /* Floating point: ordered */
775 { "unordered", pn_Cmp_Uo }, /* FLoting point: unordered */
776 { "e", pn_Cmp_Ue }, /* Floating point: unordered or == */
777 { "b", pn_Cmp_Ul }, /* Floating point: unordered or < */
778 { "be", pn_Cmp_Ule }, /* Floating point: unordered or <= */
779 { "a", pn_Cmp_Ug }, /* Floating point: unordered or > */
780 { "ae", pn_Cmp_Uge }, /* Floating point: unordered or >= */
781 { "ne", pn_Cmp_Ne }, /* Floating point: unordered or != */
782 { NULL, pn_Cmp_True }, /* always true */
786 * returns the condition code
788 static const char *get_cmp_suffix(int cmp_code, int unsigned_cmp)
790 assert(cmp2condition_s[cmp_code].num == cmp_code);
791 assert(cmp2condition_u[cmp_code].num == cmp_code);
793 return unsigned_cmp ? cmp2condition_u[cmp_code & 7].name : cmp2condition_s[cmp_code & 7].name;
797 * Returns the target block for a control flow node.
799 static ir_node *get_cfop_target_block(const ir_node *irn) {
800 return get_irn_link(irn);
804 * Returns the target label for a control flow node.
806 static char *get_cfop_target(const ir_node *irn, char *buf) {
807 ir_node *bl = get_cfop_target_block(irn);
809 snprintf(buf, SNPRINTF_BUF_LEN, BLOCK_PREFIX("%ld"), get_irn_node_nr(bl));
813 /** Return the next block in Block schedule */
814 static ir_node *next_blk_sched(const ir_node *block) {
815 return get_irn_link(block);
819 * Returns the Proj with projection number proj and NOT mode_M
821 static ir_node *get_proj(const ir_node *irn, long proj) {
822 const ir_edge_t *edge;
825 assert(get_irn_mode(irn) == mode_T && "expected mode_T node");
827 foreach_out_edge(irn, edge) {
828 src = get_edge_src_irn(edge);
830 assert(is_Proj(src) && "Proj expected");
831 if (get_irn_mode(src) == mode_M)
834 if (get_Proj_proj(src) == proj)
841 * Emits the jump sequence for a conditional jump (cmp + jmp_true + jmp_false)
843 static void finish_CondJmp(FILE *F, const ir_node *irn, ir_mode *mode) {
844 const ir_node *proj_true;
845 const ir_node *proj_false;
846 const ir_node *block;
847 const ir_node *next_block;
848 char buf[SNPRINTF_BUF_LEN];
849 char cmd_buf[SNPRINTF_BUF_LEN];
850 char cmnt_buf[SNPRINTF_BUF_LEN];
855 /* get both Proj's */
856 proj_true = get_proj(irn, pn_Cond_true);
857 assert(proj_true && "CondJmp without true Proj");
859 proj_false = get_proj(irn, pn_Cond_false);
860 assert(proj_false && "CondJmp without false Proj");
862 pnc = get_ia32_pncode(irn);
864 /* for now, the code works for scheduled and non-schedules blocks */
865 block = get_nodes_block(irn);
867 /* we have a block schedule */
868 next_block = next_blk_sched(block);
870 if (get_cfop_target_block(proj_true) == next_block) {
871 /* exchange both proj's so the second one can be omitted */
872 const ir_node *t = proj_true;
873 proj_true = proj_false;
877 pnc = get_negated_pnc(pnc, mode);
880 /* the first Proj must always be created */
881 is_unsigned = mode_is_float(mode) || ! mode_is_signed(mode);
882 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "j%s %s",
883 get_cmp_suffix(pnc, is_unsigned),
884 get_cfop_target(proj_true, buf));
885 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* %s(a, b) %s*/",
886 get_pnc_string(pnc), flipped ? "(was flipped)" : "");
889 /* the second Proj might be a fallthrough */
890 if (get_cfop_target_block(proj_false) != next_block) {
891 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "jmp %s", get_cfop_target(proj_false, buf));
892 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* otherwise */");
896 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* fallthrough %s */", get_cfop_target(proj_false, buf));
902 * Emits code for conditional jump.
904 static void CondJmp_emitter(const ir_node *irn, ia32_emit_env_t *env) {
906 char cmd_buf[SNPRINTF_BUF_LEN];
907 char cmnt_buf[SNPRINTF_BUF_LEN];
909 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "cmp %s", ia32_emit_binop(irn, env));
910 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F */", irn);
912 finish_CondJmp(F, irn, get_ia32_res_mode(irn));
916 * Emits code for conditional jump with two variables.
918 static void emit_ia32_CondJmp(const ir_node *irn, ia32_emit_env_t *env) {
919 CondJmp_emitter(irn, env);
923 * Emits code for conditional test and jump.
925 static void TestJmp_emitter(const ir_node *irn, ia32_emit_env_t *env) {
927 #define IA32_IS_IMMOP (is_ia32_ImmConst(irn) || is_ia32_ImmSymConst(irn))
930 const char *op1 = arch_register_get_name(get_in_reg(irn, 0));
931 const char *op2 = IA32_IS_IMMOP ? get_ia32_cnst(irn) : NULL;
932 char cmd_buf[SNPRINTF_BUF_LEN];
933 char cmnt_buf[SNPRINTF_BUF_LEN];
936 op2 = arch_register_get_name(get_in_reg(irn, 1));
938 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "test %%%s,%s%s ", op1, IA32_IS_IMMOP ? " " : " %", op2);
939 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F */", irn);
942 finish_CondJmp(F, irn, get_ia32_res_mode(irn));
948 * Emits code for conditional test and jump with two variables.
950 static void emit_ia32_TestJmp(const ir_node *irn, ia32_emit_env_t *env) {
951 TestJmp_emitter(irn, env);
954 static void emit_ia32_CJmp(const ir_node *irn, ia32_emit_env_t *env) {
956 char cmd_buf[SNPRINTF_BUF_LEN];
957 char cmnt_buf[SNPRINTF_BUF_LEN];
959 snprintf(cmd_buf, SNPRINTF_BUF_LEN, " ");
960 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F omitted redundant test */", irn);
962 finish_CondJmp(F, irn, get_ia32_res_mode(irn));
965 static void emit_ia32_CJmpAM(const ir_node *irn, ia32_emit_env_t *env) {
967 char cmd_buf[SNPRINTF_BUF_LEN];
968 char cmnt_buf[SNPRINTF_BUF_LEN];
970 snprintf(cmd_buf, SNPRINTF_BUF_LEN, " ");
971 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F omitted redundant test/cmp */", irn);
973 finish_CondJmp(F, irn, get_ia32_res_mode(irn));
977 * Emits code for conditional SSE floating point jump with two variables.
979 static void emit_ia32_xCondJmp(ir_node *irn, ia32_emit_env_t *env) {
981 char cmd_buf[SNPRINTF_BUF_LEN];
982 char cmnt_buf[SNPRINTF_BUF_LEN];
984 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "ucomis%M %s", irn, ia32_emit_binop(irn, env));
985 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F */", irn);
987 finish_CondJmp(F, irn, mode_F);
992 * Emits code for conditional x87 floating point jump with two variables.
994 static void emit_ia32_x87CondJmp(ir_node *irn, ia32_emit_env_t *env) {
996 char cmd_buf[SNPRINTF_BUF_LEN];
997 char cmnt_buf[SNPRINTF_BUF_LEN];
998 ia32_attr_t *attr = get_ia32_attr(irn);
999 const char *reg = attr->x87[1]->name;
1000 const char *instr = "fcom";
1003 switch (get_ia32_irn_opcode(irn)) {
1004 case iro_ia32_fcomrJmp:
1006 case iro_ia32_fcomJmp:
1010 case iro_ia32_fcomrpJmp:
1012 case iro_ia32_fcompJmp:
1015 case iro_ia32_fcomrppJmp:
1017 case iro_ia32_fcomppJmp:
1024 set_ia32_pncode(irn, (long)get_inversed_pnc(get_ia32_pncode(irn)));
1026 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "%s %s%s", instr, reg[0] == '\0' ? "" : "%", reg);
1027 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F */", irn);
1029 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "fnstsw %%ax", irn);
1030 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* Store x87 FPU Control Word */");
1032 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "sahf");
1033 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* Store ah into flags */");
1036 /* the compare flags must be evaluated using carry , ie unsigned */
1037 finish_CondJmp(F, irn, mode_Iu);
1040 static void CMov_emitter(ir_node *irn, ia32_emit_env_t *env) {
1042 const lc_arg_env_t *arg_env = ia32_get_arg_env();
1043 ir_mode *mode = get_irn_mode(get_irn_n(irn, 0));
1044 int is_unsigned = mode_is_float(mode) || ! mode_is_signed(mode);
1045 const char *cmp_suffix = get_cmp_suffix(get_ia32_pncode(irn), is_unsigned);
1046 int is_PsiCondCMov = is_ia32_PsiCondCMov(irn);
1047 int idx_left = 2 - is_PsiCondCMov;
1048 int idx_right = 3 - is_PsiCondCMov;
1050 char cmd_buf[SNPRINTF_BUF_LEN];
1051 char cmnt_buf[SNPRINTF_BUF_LEN];
1052 const arch_register_t *in1, *in2, *out;
1054 out = arch_get_irn_register(env->arch_env, irn);
1055 in1 = arch_get_irn_register(env->arch_env, get_irn_n(irn, idx_left));
1056 in2 = arch_get_irn_register(env->arch_env, get_irn_n(irn, idx_right));
1058 /* we have to emit the cmp first, because the destination register */
1059 /* could be one of the compare registers */
1060 if (is_ia32_CmpCMov(irn)) {
1061 lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "cmp %1S, %2S", irn, irn);
1063 else if (is_ia32_xCmpCMov(irn)) {
1064 lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "ucomis%M %1S, %2S", get_irn_n(irn, 0), irn, irn);
1066 else if (is_PsiCondCMov) {
1067 /* omit compare because flags are already set by And/Or */
1068 lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "test %1S, %1S", irn, irn);
1071 assert(0 && "unsupported CMov");
1073 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* Psi condition */" );
1076 if (REGS_ARE_EQUAL(out, in2)) {
1077 /* best case: default in == out -> do nothing */
1079 else if (REGS_ARE_EQUAL(out, in1)) {
1080 /* true in == out -> need complement compare and exchange true and default in */
1081 ir_node *t = get_irn_n(irn, idx_left);
1082 set_irn_n(irn, idx_left, get_irn_n(irn, idx_right));
1083 set_irn_n(irn, idx_right, t);
1085 cmp_suffix = get_cmp_suffix(get_negated_pnc(get_ia32_pncode(irn), get_irn_mode(irn)), is_unsigned);
1089 /* out is different from in: need copy default -> out */
1091 lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "mov %1D, %3S", irn, irn);
1093 lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "mov %1D, %4S", irn, irn);
1095 lc_esnprintf(arg_env, cmnt_buf, SNPRINTF_BUF_LEN, "/* copy default -> out */" );
1100 lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "cmov%s %1D, %2S", cmp_suffix, irn, irn);
1102 lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "cmov%s %1D, %3S", cmp_suffix, irn, irn);
1104 lc_esnprintf(arg_env, cmnt_buf, SNPRINTF_BUF_LEN, "/* condition is true case */" );
1108 static void emit_ia32_CmpCMov(ir_node *irn, ia32_emit_env_t *env) {
1109 CMov_emitter(irn, env);
1112 static void emit_ia32_PsiCondCMov(ir_node *irn, ia32_emit_env_t *env) {
1113 CMov_emitter(irn, env);
1116 static void emit_ia32_xCmpCMov(ir_node *irn, ia32_emit_env_t *env) {
1117 CMov_emitter(irn, env);
1120 static void Set_emitter(ir_node *irn, ir_mode *mode, ia32_emit_env_t *env) {
1122 const lc_arg_env_t *arg_env = ia32_get_arg_env();
1123 int is_unsigned = mode_is_float(mode) || ! mode_is_signed(mode);
1124 const char *cmp_suffix = get_cmp_suffix(get_ia32_pncode(irn), is_unsigned);
1125 const char *reg8bit;
1127 char cmd_buf[SNPRINTF_BUF_LEN];
1128 char cmnt_buf[SNPRINTF_BUF_LEN];
1129 const arch_register_t *out;
1131 out = arch_get_irn_register(env->arch_env, irn);
1132 reg8bit = ia32_get_mapped_reg_name(env->isa->regs_8bit, out);
1134 if (is_ia32_CmpSet(irn)) {
1135 lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "cmp %s", ia32_emit_binop(irn, env));
1137 else if (is_ia32_xCmpSet(irn)) {
1138 lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "ucomis%M %s", get_irn_n(irn, 2), ia32_emit_binop(irn, env));
1140 else if (is_ia32_PsiCondSet(irn)) {
1141 /* omit compare because flags are already set by And/Or */
1142 snprintf(cmd_buf, SNPRINTF_BUF_LEN, " ");
1145 assert(0 && "unsupported Set");
1147 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* calculate Psi condition */" );
1150 /* use mov to clear target because it doesn't affect the eflags */
1151 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "mov %%%s, 0", arch_register_get_name(out));
1152 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* clear target as set modifies only lower 8 bit */");
1155 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "set%s %%%s", cmp_suffix, reg8bit);
1156 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* set 1 iff true, 0 otherweise */" );
1160 static void emit_ia32_CmpSet(ir_node *irn, ia32_emit_env_t *env) {
1161 Set_emitter(irn, get_irn_mode(get_irn_n(irn, 2)), env);
1164 static void emit_ia32_PsiCondSet(ir_node *irn, ia32_emit_env_t *env) {
1165 Set_emitter(irn, get_irn_mode(get_irn_n(irn, 0)), env);
1168 static void emit_ia32_xCmpSet(ir_node *irn, ia32_emit_env_t *env) {
1169 Set_emitter(irn, get_irn_mode(get_irn_n(irn, 2)), env);
1172 static void emit_ia32_xCmp(ir_node *irn, ia32_emit_env_t *env) {
1174 const lc_arg_env_t *arg_env = ia32_get_arg_env();
1176 long pnc = get_ia32_pncode(irn);
1177 long unord = pnc & pn_Cmp_Uo;
1178 char cmd_buf[SNPRINTF_BUF_LEN];
1179 char cmnt_buf[SNPRINTF_BUF_LEN];
1182 case pn_Cmp_Leg: /* odered */
1185 case pn_Cmp_Uo: /* unordered */
1189 case pn_Cmp_Eq: /* == */
1193 case pn_Cmp_Lt: /* < */
1197 case pn_Cmp_Le: /* <= */
1201 case pn_Cmp_Gt: /* > */
1205 case pn_Cmp_Ge: /* >= */
1209 case pn_Cmp_Lg: /* != */
1214 assert(sse_pnc >= 0 && "unsupported compare");
1216 if (unord && sse_pnc != 3) {
1218 We need a separate compare against unordered.
1219 Quick and Dirty solution:
1220 - get some memory on stack
1224 - and result and stored result
1227 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "sub %%esp, 8");
1228 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* reserve some space for unordered compare result */");
1230 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "cmpsd %s, 3", ia32_emit_binop(irn, env));
1231 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* SSE compare: unordered */");
1233 lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "movsd [%%esp], %1D", irn);
1234 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* store compare result */");
1238 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "cmpsd %s, %d", ia32_emit_binop(irn, env), sse_pnc);
1239 lc_esnprintf(arg_env, cmnt_buf, SNPRINTF_BUF_LEN, "/* SSE compare (%+F) with result in %1D */", irn, irn);
1242 if (unord && sse_pnc != 3) {
1243 lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "andpd %1D, [%%esp]", irn);
1244 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* build the final result */");
1246 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "add %%esp, 8");
1247 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* free allocated space */");
1252 /*********************************************************
1255 * ___ _ __ ___ _| |_ _ _ _ _ __ ___ _ __ ___
1256 * / _ \ '_ ` _ \| | __| | | | | | '_ ` _ \| '_ \/ __|
1257 * | __/ | | | | | | |_ | | |_| | | | | | | |_) \__ \
1258 * \___|_| |_| |_|_|\__| | |\__,_|_| |_| |_| .__/|___/
1261 *********************************************************/
1263 /* jump table entry (target and corresponding number) */
1264 typedef struct _branch_t {
1269 /* jump table for switch generation */
1270 typedef struct _jmp_tbl_t {
1271 ir_node *defProj; /**< default target */
1272 int min_value; /**< smallest switch case */
1273 int max_value; /**< largest switch case */
1274 int num_branches; /**< number of jumps */
1275 char *label; /**< label of the jump table */
1276 branch_t *branches; /**< jump array */
1280 * Compare two variables of type branch_t. Used to sort all switch cases
1282 static int ia32_cmp_branch_t(const void *a, const void *b) {
1283 branch_t *b1 = (branch_t *)a;
1284 branch_t *b2 = (branch_t *)b;
1286 if (b1->value <= b2->value)
1293 * Emits code for a SwitchJmp (creates a jump table if
1294 * possible otherwise a cmp-jmp cascade). Port from
1297 static void emit_ia32_SwitchJmp(const ir_node *irn, ia32_emit_env_t *emit_env) {
1298 unsigned long interval;
1299 char buf[SNPRINTF_BUF_LEN];
1300 int last_value, i, pn;
1303 const ir_edge_t *edge;
1304 const lc_arg_env_t *env = ia32_get_arg_env();
1305 FILE *F = emit_env->out;
1306 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1308 /* fill the table structure */
1309 tbl.label = xmalloc(SNPRINTF_BUF_LEN);
1310 tbl.label = get_unique_label(tbl.label, SNPRINTF_BUF_LEN, ".TBL_");
1312 tbl.num_branches = get_irn_n_edges(irn);
1313 tbl.branches = xcalloc(tbl.num_branches, sizeof(tbl.branches[0]));
1314 tbl.min_value = INT_MAX;
1315 tbl.max_value = INT_MIN;
1318 /* go over all proj's and collect them */
1319 foreach_out_edge(irn, edge) {
1320 proj = get_edge_src_irn(edge);
1321 assert(is_Proj(proj) && "Only proj allowed at SwitchJmp");
1323 pn = get_Proj_proj(proj);
1325 /* create branch entry */
1326 tbl.branches[i].target = proj;
1327 tbl.branches[i].value = pn;
1329 tbl.min_value = pn < tbl.min_value ? pn : tbl.min_value;
1330 tbl.max_value = pn > tbl.max_value ? pn : tbl.max_value;
1332 /* check for default proj */
1333 if (pn == get_ia32_pncode(irn)) {
1334 assert(tbl.defProj == NULL && "found two defProjs at SwitchJmp");
1341 /* sort the branches by their number */
1342 qsort(tbl.branches, tbl.num_branches, sizeof(tbl.branches[0]), ia32_cmp_branch_t);
1344 /* two-complement's magic make this work without overflow */
1345 interval = tbl.max_value - tbl.min_value;
1347 /* emit the table */
1348 lc_esnprintf(env, cmd_buf, SNPRINTF_BUF_LEN, "cmp %1S, %u", irn, interval);
1349 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* compare for switch */");
1352 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "ja %s", get_cfop_target(tbl.defProj, buf));
1353 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* default jump if out of range */");
1356 if (tbl.num_branches > 1) {
1359 lc_esnprintf(env, cmd_buf, SNPRINTF_BUF_LEN, "jmp %s[%1S*4]", tbl.label, irn);
1360 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* get jump table entry as target */");
1363 ia32_switch_section(F, SECTION_RODATA);
1364 fprintf(F, "\t.align 4\n");
1366 fprintf(F, "%s:\n", tbl.label);
1368 snprintf(cmd_buf, SNPRINTF_BUF_LEN, ".long %s", get_cfop_target(tbl.branches[0].target, buf));
1369 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* case %d */", tbl.branches[0].value);
1372 last_value = tbl.branches[0].value;
1373 for (i = 1; i < tbl.num_branches; ++i) {
1374 while (++last_value < tbl.branches[i].value) {
1375 snprintf(cmd_buf, SNPRINTF_BUF_LEN, ".long %s", get_cfop_target(tbl.defProj, buf));
1376 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* default case */");
1379 snprintf(cmd_buf, SNPRINTF_BUF_LEN, ".long %s", get_cfop_target(tbl.branches[i].target, buf));
1380 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* case %d */", last_value);
1383 ia32_switch_section(F, SECTION_TEXT);
1386 /* one jump is enough */
1387 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "jmp %s", get_cfop_target(tbl.branches[0].target, buf));
1388 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* only one case given */");
1399 * Emits code for a unconditional jump.
1401 static void emit_Jmp(const ir_node *irn, ia32_emit_env_t *env) {
1402 ir_node *block, *next_bl;
1404 char buf[SNPRINTF_BUF_LEN], cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1406 /* for now, the code works for scheduled and non-schedules blocks */
1407 block = get_nodes_block(irn);
1409 /* we have a block schedule */
1410 next_bl = next_blk_sched(block);
1411 if (get_cfop_target_block(irn) != next_bl) {
1412 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "jmp %s", get_cfop_target(irn, buf));
1413 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F(%+F) */", irn, get_cfop_target_block(irn));
1417 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* fallthrough %s */", get_cfop_target(irn, buf));
1422 /****************************
1425 * _ __ _ __ ___ _ ___
1426 * | '_ \| '__/ _ \| |/ __|
1427 * | |_) | | | (_) | |\__ \
1428 * | .__/|_| \___/| ||___/
1431 ****************************/
1434 * Emits code for a proj -> node
1436 static void emit_Proj(const ir_node *irn, ia32_emit_env_t *env) {
1437 ir_node *pred = get_Proj_pred(irn);
1439 if (get_irn_op(pred) == op_Start) {
1440 switch(get_Proj_proj(irn)) {
1441 case pn_Start_X_initial_exec:
1450 /**********************************
1453 * | | ___ _ __ _ _| |_) |
1454 * | | / _ \| '_ \| | | | _ <
1455 * | |___| (_) | |_) | |_| | |_) |
1456 * \_____\___/| .__/ \__, |____/
1459 **********************************/
1462 * Emit movsb/w instructions to make mov count divideable by 4
1464 static void emit_CopyB_prolog(FILE *F, const ir_node *irn, int rem) {
1465 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1467 ir_fprintf(F, "\t/* memcopy prolog %+F */\n", irn);
1469 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "cld");
1470 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* copy direction forward */");
1475 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "movsb");
1476 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* memcopy remainder 1 */");
1480 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "movsw");
1481 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* memcopy remainder 2 */");
1485 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "movsb");
1486 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* memcopy remainder 3 */");
1488 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "movsw");
1489 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* memcopy remainder 3 */");
1497 * Emit rep movsd instruction for memcopy.
1499 static void emit_ia32_CopyB(const ir_node *irn, ia32_emit_env_t *emit_env) {
1500 FILE *F = emit_env->out;
1501 tarval *tv = get_ia32_Immop_tarval(irn);
1502 int rem = get_tarval_long(tv);
1503 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1505 emit_CopyB_prolog(F, irn, rem);
1507 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "rep movsd");
1508 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* memcopy */");
1513 * Emits unrolled memcopy.
1515 static void emit_ia32_CopyB_i(const ir_node *irn, ia32_emit_env_t *emit_env) {
1516 tarval *tv = get_ia32_Immop_tarval(irn);
1517 int size = get_tarval_long(tv);
1518 FILE *F = emit_env->out;
1519 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1521 emit_CopyB_prolog(F, irn, size & 0x3);
1525 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "movsd");
1526 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* memcopy unrolled */");
1533 /***************************
1537 * | | / _ \| '_ \ \ / /
1538 * | |___| (_) | | | \ V /
1539 * \_____\___/|_| |_|\_/
1541 ***************************/
1544 * Emit code for conversions (I, FP), (FP, I) and (FP, FP).
1546 static void emit_ia32_Conv_with_FP(const ir_node *irn, ia32_emit_env_t *emit_env) {
1547 FILE *F = emit_env->out;
1548 const lc_arg_env_t *env = ia32_get_arg_env();
1549 ir_mode *src_mode = get_ia32_src_mode(irn);
1550 ir_mode *tgt_mode = get_ia32_tgt_mode(irn);
1551 char *from, *to, buf[64];
1552 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1554 from = mode_is_float(src_mode) ? (get_mode_size_bits(src_mode) == 32 ? "ss" : "sd") : "si";
1555 to = mode_is_float(tgt_mode) ? (get_mode_size_bits(tgt_mode) == 32 ? "ss" : "sd") : "si";
1557 switch(get_ia32_op_type(irn)) {
1559 lc_esnprintf(env, buf, sizeof(buf), "%1D, %3S", irn, irn);
1561 case ia32_AddrModeS:
1562 lc_esnprintf(env, buf, sizeof(buf), "%1D, %s", irn, ia32_emit_am(irn, emit_env));
1565 assert(0 && "unsupported op type for Conv");
1568 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "cvt%s2%s %s", from, to, buf);
1569 lc_esnprintf(env, cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F(%+F, %+F) */", irn, src_mode, tgt_mode);
1573 static void emit_ia32_Conv_I2FP(const ir_node *irn, ia32_emit_env_t *emit_env) {
1574 emit_ia32_Conv_with_FP(irn, emit_env);
1577 static void emit_ia32_Conv_FP2I(const ir_node *irn, ia32_emit_env_t *emit_env) {
1578 emit_ia32_Conv_with_FP(irn, emit_env);
1581 static void emit_ia32_Conv_FP2FP(const ir_node *irn, ia32_emit_env_t *emit_env) {
1582 emit_ia32_Conv_with_FP(irn, emit_env);
1586 * Emits code for an Int conversion.
1588 static void emit_ia32_Conv_I2I(const ir_node *irn, ia32_emit_env_t *emit_env) {
1589 FILE *F = emit_env->out;
1590 const lc_arg_env_t *env = ia32_get_arg_env();
1591 char *move_cmd = "movzx";
1592 char *conv_cmd = NULL;
1593 ir_mode *src_mode = get_ia32_src_mode(irn);
1594 ir_mode *tgt_mode = get_ia32_tgt_mode(irn);
1596 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1597 const arch_register_t *in_reg, *out_reg;
1599 n = get_mode_size_bits(src_mode);
1600 m = get_mode_size_bits(tgt_mode);
1602 if (mode_is_signed(n < m ? src_mode : tgt_mode)) {
1604 if (n == 8 || m == 8)
1606 else if (n == 16 || m == 16)
1609 printf("%d -> %d unsupported\n", n, m);
1610 assert(0 && "unsupported Conv_I2I");
1614 switch(get_ia32_op_type(irn)) {
1616 in_reg = get_in_reg(irn, 2);
1617 out_reg = get_out_reg(irn, 0);
1619 if (REGS_ARE_EQUAL(in_reg, &ia32_gp_regs[REG_EAX]) &&
1620 REGS_ARE_EQUAL(out_reg, in_reg) &&
1621 mode_is_signed(n < m ? src_mode : tgt_mode))
1623 /* argument and result are both in EAX and */
1624 /* signedness is ok: -> use converts */
1625 lc_esnprintf(env, cmd_buf, SNPRINTF_BUF_LEN, "%s", conv_cmd);
1627 else if (REGS_ARE_EQUAL(out_reg, in_reg) &&
1628 ! mode_is_signed(n < m ? src_mode : tgt_mode))
1630 /* argument and result are in the same register */
1631 /* and signedness is ok: -> use and with mask */
1632 int mask = (1 << (n < m ? n : m)) - 1;
1633 lc_esnprintf(env, cmd_buf, SNPRINTF_BUF_LEN, "and %1D, 0x%x", irn, mask);
1636 /* use move w/o sign extension */
1637 lc_esnprintf(env, cmd_buf, SNPRINTF_BUF_LEN, "%s %1D, %%%s",
1638 move_cmd, irn, ia32_get_reg_name_for_mode(emit_env, n < m ? src_mode : tgt_mode, in_reg));
1642 case ia32_AddrModeS:
1643 lc_esnprintf(env, cmd_buf, SNPRINTF_BUF_LEN, "%s %1D, %s",
1644 move_cmd, irn, ia32_emit_am(irn, emit_env));
1647 assert(0 && "unsupported op type for Conv");
1650 lc_esnprintf(env, cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F(%d Bit mode_%F -> %d Bit mode_%F) */",
1651 irn, n, src_mode, m, tgt_mode);
1657 * Emits code for an 8Bit Int conversion.
1659 void emit_ia32_Conv_I2I8Bit(const ir_node *irn, ia32_emit_env_t *emit_env) {
1660 emit_ia32_Conv_I2I(irn, emit_env);
1664 /*******************************************
1667 * | |__ ___ _ __ ___ __| | ___ ___
1668 * | '_ \ / _ \ '_ \ / _ \ / _` |/ _ \/ __|
1669 * | |_) | __/ | | | (_) | (_| | __/\__ \
1670 * |_.__/ \___|_| |_|\___/ \__,_|\___||___/
1672 *******************************************/
1675 * Emits a backend call
1677 static void emit_be_Call(const ir_node *irn, ia32_emit_env_t *emit_env) {
1678 FILE *F = emit_env->out;
1679 entity *ent = be_Call_get_entity(irn);
1680 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1683 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "call %s", get_entity_ld_name(ent));
1686 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "call %1D", get_irn_n(irn, be_pos_Call_ptr));
1689 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F (be_Call) */", irn);
1695 * Emits code to increase stack pointer.
1697 static void emit_be_IncSP(const ir_node *irn, ia32_emit_env_t *emit_env) {
1698 FILE *F = emit_env->out;
1699 int offs = be_get_IncSP_offset(irn);
1700 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1704 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "sub %1S, %u", irn, offs);
1706 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "add %1S, %u", irn, -offs);
1707 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F (IncSP) */", irn);
1710 snprintf(cmd_buf, SNPRINTF_BUF_LEN, " ");
1711 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* omitted %+F (IncSP) with 0 */", irn);
1718 * Emits code to set stack pointer.
1720 static void emit_be_SetSP(const ir_node *irn, ia32_emit_env_t *emit_env) {
1721 FILE *F = emit_env->out;
1722 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1724 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "mov %1D, %3S", irn, irn);
1725 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F (restore SP) */", irn);
1730 * Emits code for Copy/CopyKeep.
1732 static void Copy_emitter(const ir_node *irn, ir_node *op, ia32_emit_env_t *emit_env) {
1733 FILE *F = emit_env->out;
1734 const arch_env_t *aenv = emit_env->arch_env;
1735 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1737 if (REGS_ARE_EQUAL(arch_get_irn_register(aenv, irn), arch_get_irn_register(aenv, op)) ||
1738 be_is_unknown_reg(arch_get_irn_register(aenv, op)))
1741 if (mode_is_float(get_irn_mode(irn)))
1742 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "movs%M %1D, %1S", irn, irn, irn);
1744 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "mov %1D, %1S", irn, irn);
1745 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F */", irn);
1749 static void emit_be_Copy(const ir_node *irn, ia32_emit_env_t *emit_env) {
1750 Copy_emitter(irn, be_get_Copy_op(irn), emit_env);
1753 static void emit_be_CopyKeep(const ir_node *irn, ia32_emit_env_t *emit_env) {
1754 Copy_emitter(irn, be_get_CopyKeep_op(irn), emit_env);
1758 * Emits code for exchange.
1760 static void emit_be_Perm(const ir_node *irn, ia32_emit_env_t *emit_env) {
1761 FILE *F = emit_env->out;
1762 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1763 const arch_register_t *in1, *in2;
1764 const arch_register_class_t *cls1, *cls2;
1766 in1 = arch_get_irn_register(emit_env->arch_env, get_irn_n(irn, 0));
1767 in2 = arch_get_irn_register(emit_env->arch_env, get_irn_n(irn, 1));
1769 cls1 = arch_register_get_class(in1);
1770 cls2 = arch_register_get_class(in2);
1772 assert(cls1 == cls2 && "Register class mismatch at Perm");
1774 if (cls1 == &ia32_reg_classes[CLASS_ia32_gp]) {
1775 if(emit_env->isa->opt_arch == arch_athlon) {
1776 // xchg commands are Vector path on athlons and therefore stall the DirectPath pipeline
1777 // it is nearly always beneficial to use the 3 xor trick instead of an xchg
1779 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "xor %1S, %2S", irn, irn);
1781 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "xor %2S, %1S", irn, irn);
1783 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "xor %1S, %2S", irn, irn);
1785 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "xchg %1S, %2S", irn, irn);
1788 else if (cls1 == &ia32_reg_classes[CLASS_ia32_xmm]) {
1789 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN,
1790 "pxor %1S, %2S\n\tpxor %2S, %1S\n\tpxor %1S, %2S", irn, irn, irn, irn, irn, irn);
1792 else if (cls1 == &ia32_reg_classes[CLASS_ia32_vfp]) {
1796 else if (cls1 == &ia32_reg_classes[CLASS_ia32_st]) {
1801 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F(%1A, %2A) */", irn, irn, irn);
1806 * Emits code for Constant loading.
1808 static void emit_ia32_Const(const ir_node *n, ia32_emit_env_t *env) {
1810 char cmd_buf[256], cmnt_buf[256];
1811 const lc_arg_env_t *arg_env = ia32_get_arg_env();
1812 ir_mode *mode = get_irn_mode(n);
1813 tarval *tv = get_ia32_Immop_tarval(n);
1815 if (get_ia32_op_type(n) == ia32_SymConst) {
1816 lc_esnprintf(arg_env, cmd_buf, 256, "mov %1D, OFFSET FLAT:%C ", n, n);
1817 lc_esnprintf(arg_env, cmnt_buf, 256, "/* Move address of SymConst into register */");
1819 assert(mode == get_tarval_mode(tv));
1820 /* beware: in some rare cases mode is mode_b which has no tarval_null() */
1821 if (tv == get_tarval_b_false() || tv == get_tarval_null(mode)) {
1822 const char *instr = "xor";
1823 if (env->isa->opt_arch == arch_pentium_4) {
1824 /* P4 prefers sub r, r, others xor r, r */
1827 lc_esnprintf(arg_env, cmd_buf, 256, "%s %1D, %1D ", instr, n, n);
1828 lc_esnprintf(arg_env, cmnt_buf, 256, "/* optimized mov 0 to register */");
1830 lc_esnprintf(arg_env, cmd_buf, 256, "mov %1D, %C ", n, n);
1831 lc_esnprintf(arg_env, cmnt_buf, 256, "/* Mov Const into register */");
1834 lc_efprintf(arg_env, F, "\t%-35s %-60s /* %+F (%+G) */\n", cmd_buf, cmnt_buf, n, n);
1838 * Emits code to increase stack pointer.
1840 static void emit_ia32_AddSP(const ir_node *irn, ia32_emit_env_t *emit_env) {
1841 FILE *F = emit_env->out;
1842 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1844 if (is_ia32_ImmConst(irn)) {
1845 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "sub %1D, %C", irn, irn);
1847 else if (is_ia32_ImmSymConst(irn)) {
1848 if (get_ia32_op_type(irn) == ia32_Normal)
1849 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "sub %1D, OFFSET_FLAT:%C", irn, irn);
1850 else /* source address mode */
1851 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "sub %1D, [%s%s]", irn, get_id_str(get_ia32_am_sc(irn)), get_ia32_am_offs(irn));
1854 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "sub %1D, %2S", irn, irn);
1856 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* reserve space on stack */");
1862 * Emits code to increase stack pointer.
1864 static void emit_ia32_SubSP(const ir_node *irn, ia32_emit_env_t *emit_env) {
1865 FILE *F = emit_env->out;
1866 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1868 if (is_ia32_ImmConst(irn)) {
1869 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "add %1D, %C", irn, irn);
1871 else if (is_ia32_ImmSymConst(irn)) {
1872 if (get_ia32_op_type(irn) == ia32_Normal)
1873 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "add %1D, OFFSET_FLAT:%C", irn, irn);
1874 else /* source address mode */
1875 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "add %1D, [%s%s]", irn, get_id_str(get_ia32_am_sc(irn)), get_ia32_am_offs(irn));
1878 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "add %1D, %2S", irn, irn);
1880 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* free space on stack */");
1886 * Emits code to load the TLS base
1888 static void emit_ia32_LdTls(const ir_node *irn, ia32_emit_env_t *emit_env) {
1889 FILE *F = emit_env->out;
1890 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1892 switch (asm_flavour) {
1894 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "mov %1D, DWORD PTR %%gs:0", irn);
1897 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "mov %1D, DWORD PTR %%gs:0", irn);
1900 assert(0 && "unsupported TLS");
1903 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* get thread local storage base */");
1908 static void emit_be_Return(const ir_node *n, ia32_emit_env_t *env) {
1910 const lc_arg_env_t *arg_env = ia32_get_arg_env();
1912 lc_efprintf(arg_env, F, "\t%-35s %-60s /* %+F (%+G) */\n", "ret", "/* be_Return */", n, n);
1915 static void emit_Nothing(const ir_node *n, ia32_emit_env_t *env) {
1918 ir_fprintf(F, "\t%35s /* %+F (%+G) */\n", " ", n, n);
1922 /***********************************************************************************
1925 * _ __ ___ __ _ _ _ __ | |_ _ __ __ _ _ __ ___ _____ _____ _ __| | __
1926 * | '_ ` _ \ / _` | | '_ \ | _| '__/ _` | '_ ` _ \ / _ \ \ /\ / / _ \| '__| |/ /
1927 * | | | | | | (_| | | | | | | | | | | (_| | | | | | | __/\ V V / (_) | | | <
1928 * |_| |_| |_|\__,_|_|_| |_| |_| |_| \__,_|_| |_| |_|\___| \_/\_/ \___/|_| |_|\_\
1930 ***********************************************************************************/
1933 * Enters the emitter functions for handled nodes into the generic
1934 * pointer of an opcode.
1936 static void ia32_register_emitters(void) {
1938 #define IA32_EMIT2(a,b) op_ia32_##a->ops.generic = (op_func)emit_ia32_##b
1939 #define IA32_EMIT(a) IA32_EMIT2(a,a)
1940 #define EMIT(a) op_##a->ops.generic = (op_func)emit_##a
1941 #define IGN(a) op_##a->ops.generic = (op_func)emit_Nothing
1942 #define BE_EMIT(a) op_be_##a->ops.generic = (op_func)emit_be_##a
1943 #define BE_IGN(a) op_be_##a->ops.generic = (op_func)emit_Nothing
1945 /* first clear the generic function pointer for all ops */
1946 clear_irp_opcodes_generic_func();
1948 /* register all emitter functions defined in spec */
1949 ia32_register_spec_emitters();
1951 /* other ia32 emitter functions */
1957 IA32_EMIT(PsiCondCMov);
1959 IA32_EMIT(PsiCondSet);
1960 IA32_EMIT(SwitchJmp);
1963 IA32_EMIT(Conv_I2FP);
1964 IA32_EMIT(Conv_FP2I);
1965 IA32_EMIT(Conv_FP2FP);
1966 IA32_EMIT(Conv_I2I);
1967 IA32_EMIT(Conv_I2I8Bit);
1974 IA32_EMIT(xCmpCMov);
1975 IA32_EMIT(xCondJmp);
1976 IA32_EMIT2(fcomJmp, x87CondJmp);
1977 IA32_EMIT2(fcompJmp, x87CondJmp);
1978 IA32_EMIT2(fcomppJmp, x87CondJmp);
1979 IA32_EMIT2(fcomrJmp, x87CondJmp);
1980 IA32_EMIT2(fcomrpJmp, x87CondJmp);
1981 IA32_EMIT2(fcomrppJmp, x87CondJmp);
1983 /* benode emitter */
2009 static const char *last_name = NULL;
2010 static unsigned last_line = -1;
2011 static unsigned num = -1;
2014 * Emit the debug support for node irn.
2016 static void ia32_emit_dbg(const ir_node *irn, ia32_emit_env_t *env) {
2017 dbg_info *db = get_irn_dbg_info(irn);
2019 const char *fname = be_retrieve_dbg_info(db, &lineno);
2022 if (last_name != fname) {
2024 be_dbg_include_begin(env->cg->birg->main_env->db_handle, fname);
2027 if (last_line != lineno) {
2031 snprintf(name, sizeof(name), ".LM%u", ++num);
2033 be_dbg_line(env->cg->birg->main_env->db_handle, lineno, name);
2034 fprintf(F, "%s:\n", name);
2040 * Emits code for a node.
2042 static void ia32_emit_node(const ir_node *irn, void *env) {
2043 ia32_emit_env_t *emit_env = env;
2044 ir_op *op = get_irn_op(irn);
2045 DEBUG_ONLY(firm_dbg_module_t *mod = emit_env->mod;)
2047 DBG((mod, LEVEL_1, "emitting code for %+F\n", irn));
2049 if (op->ops.generic) {
2050 void (*emit)(const ir_node *, void *) = (void (*)(const ir_node *, void *))op->ops.generic;
2051 ia32_emit_dbg(irn, emit_env);
2055 emit_Nothing(irn, env);
2056 ir_fprintf(stderr, "Warning: No emit handler for node %+F (%+G)\n", irn, irn);
2061 * Emits gas alignment directives
2063 static void ia32_emit_alignment(FILE *F, unsigned align, unsigned skip) {
2064 fprintf(F, "\t.p2align %u,,%u\n", align, skip);
2068 * Emits gas alignment directives for Functions depended on cpu architecture.
2070 static void ia32_emit_align_func(FILE *F, cpu_support cpu) {
2072 unsigned maximum_skip;
2087 maximum_skip = (1 << align) - 1;
2088 ia32_emit_alignment(F, align, maximum_skip);
2092 * Emits gas alignment directives for Labels depended on cpu architecture.
2094 static void ia32_emit_align_label(FILE *F, cpu_support cpu) {
2095 unsigned align; unsigned maximum_skip;
2110 maximum_skip = (1 << align) - 1;
2111 ia32_emit_alignment(F, align, maximum_skip);
2114 static int is_first_loop_block(ir_node *block, ir_node *prev_block, ia32_emit_env_t *env) {
2115 exec_freq_t *execfreqs = env->cg->birg->execfreqs;
2116 double block_freq, prev_freq;
2117 static const double DELTA = .0001;
2118 cpu_support cpu = env->isa->opt_arch;
2120 if(execfreqs == NULL)
2122 if(cpu == arch_i386 || cpu == arch_i486)
2125 block_freq = get_block_execfreq(execfreqs, block);
2126 prev_freq = get_block_execfreq(execfreqs, prev_block);
2128 if(block_freq < DELTA || prev_freq < DELTA)
2131 block_freq /= prev_freq;
2135 case arch_athlon_64:
2137 return block_freq > 3;
2142 return block_freq > 2;
2146 * Walks over the nodes in a block connected by scheduling edges
2147 * and emits code for each node.
2149 static void ia32_gen_block(ir_node *block, ir_node *last_block, void *env) {
2150 ia32_emit_env_t *emit_env = env;
2152 int need_label = block != get_irg_start_block(get_irn_irg(block));
2153 FILE *F = emit_env->out;
2155 if (! is_Block(block))
2158 if (need_label && (emit_env->cg->opt & IA32_OPT_EXTBB)) {
2159 /* if the extended block scheduler is used, only leader blocks need
2161 need_label = (block == get_extbb_leader(get_nodes_extbb(block)));
2165 char cmd_buf[SNPRINTF_BUF_LEN];
2169 // align the loop headers
2170 if(!is_first_loop_block(block, last_block, emit_env)) {
2172 // align blocks where the previous block has no fallthrough
2173 arity = get_irn_arity(block);
2174 for(i = 0; i < arity; ++i) {
2175 ir_node *predblock = get_Block_cfgpred_block(block, i);
2176 if(predblock == last_block) {
2184 ia32_emit_align_label(emit_env->out, emit_env->isa->opt_arch);
2186 ir_snprintf(cmd_buf, sizeof(cmd_buf), BLOCK_PREFIX("%d:"),
2187 get_irn_node_nr(block));
2188 fprintf(F, "%-43s ", cmd_buf);
2190 /* emit list of pred blocks in comment */
2191 fprintf(F, "/* preds:");
2193 arity = get_irn_arity(block);
2194 for(i = 0; i < arity; ++i) {
2195 ir_node *predblock = get_Block_cfgpred_block(block, i);
2196 fprintf(F, " %ld", get_irn_node_nr(predblock));
2198 fprintf(F, " */\n");
2201 /* emit the contents of the block */
2202 ia32_emit_dbg(block, env);
2203 sched_foreach(block, irn) {
2204 ia32_emit_node(irn, env);
2209 * Emits code for function start.
2211 static void ia32_emit_func_prolog(FILE *F, ir_graph *irg, ia32_emit_env_t *emit_env) {
2212 entity *irg_ent = get_irg_entity(irg);
2213 const char *irg_name = get_entity_ld_name(irg_ent);
2214 cpu_support cpu = emit_env->isa->opt_arch;
2215 const be_irg_t *birg = emit_env->cg->birg;
2218 ia32_switch_section(F, SECTION_TEXT);
2219 be_dbg_method_begin(birg->main_env->db_handle, irg_ent, be_abi_get_stack_layout(birg->abi));
2220 ia32_emit_align_func(F, cpu);
2221 if (get_entity_visibility(irg_ent) == visibility_external_visible) {
2222 fprintf(F, ".globl %s\n", irg_name);
2224 ia32_dump_function_object(F, irg_name);
2225 fprintf(F, "%s:\n", irg_name);
2229 * Emits code for function end
2231 static void ia32_emit_func_epilog(FILE *F, ir_graph *irg, ia32_emit_env_t *emit_env) {
2232 const char *irg_name = get_entity_ld_name(get_irg_entity(irg));
2233 const be_irg_t *birg = emit_env->cg->birg;
2235 ia32_dump_function_size(F, irg_name);
2236 be_dbg_method_end(birg->main_env->db_handle);
2242 * Sets labels for control flow nodes (jump target)
2243 * TODO: Jump optimization
2245 static void ia32_gen_labels(ir_node *block, void *env) {
2247 int n = get_Block_n_cfgpreds(block);
2249 for (n--; n >= 0; n--) {
2250 pred = get_Block_cfgpred(block, n);
2251 set_irn_link(pred, block);
2256 * Main driver. Emits the code for one routine.
2258 void ia32_gen_routine(FILE *F, ir_graph *irg, const ia32_code_gen_t *cg) {
2259 ia32_emit_env_t emit_env;
2261 ir_node *last_block = NULL;
2264 emit_env.arch_env = cg->arch_env;
2266 emit_env.isa = (ia32_isa_t *)cg->arch_env->isa;
2267 FIRM_DBG_REGISTER(emit_env.mod, "firm.be.ia32.emitter");
2269 /* set the global arch_env (needed by print hooks) */
2270 arch_env = cg->arch_env;
2272 ia32_register_emitters();
2274 ia32_emit_func_prolog(F, irg, &emit_env);
2275 irg_block_walk_graph(irg, ia32_gen_labels, NULL, &emit_env);
2277 if ((cg->opt & IA32_OPT_EXTBB) && cg->blk_sched) {
2278 int i, n = ARR_LEN(cg->blk_sched);
2280 for (i = 0; i < n;) {
2283 block = cg->blk_sched[i];
2285 next_bl = i < n ? cg->blk_sched[i] : NULL;
2287 /* set here the link. the emitter expects to find the next block here */
2288 set_irn_link(block, next_bl);
2289 ia32_gen_block(block, last_block, &emit_env);
2294 /* "normal" block schedule: Note the get_next_block() returns the NUMBER of the block
2295 in the block schedule. As this number should NEVER be equal the next block,
2296 we does not need a clear block link here. */
2298 //irg_walk_blkwise_graph(irg, NULL, ia32_gen_block, &emit_env);
2302 ia32_emit_func_epilog(F, irg, &emit_env);