2 * This file implements the node emitter.
3 * @author Christian Wuerdig
22 #include "iredges_t.h"
24 #include "../besched_t.h"
25 #include "../benode_t.h"
27 #include "ia32_emitter.h"
28 #include "gen_ia32_emitter.h"
29 #include "gen_ia32_regalloc_if.h"
30 #include "ia32_nodes_attr.h"
31 #include "ia32_new_nodes.h"
32 #include "ia32_map_regs.h"
33 #include "bearch_ia32_t.h"
35 #define BLOCK_PREFIX(x) ".L" x
37 #define SNPRINTF_BUF_LEN 128
39 /* global arch_env for lc_printf functions */
40 static const arch_env_t *arch_env = NULL;
42 /** by default, we generate assembler code for the Linux gas */
43 asm_flavour_t asm_flavour = ASM_LINUX_GAS;
46 * Switch to a new section
48 void ia32_switch_section(FILE *F, section_t sec) {
49 static section_t curr_sec = NO_SECTION;
50 static const char *text[ASM_MAX][SECTION_MAX] = {
56 ".section\t.tbss,\"awT\",@nobits",
57 ".section\t.ctors,\"aw\",@progbits"
62 ".section .rdata,\"dr\"",
64 ".section\t.tbss,\"awT\",@nobits",
65 ".section\t.ctors,\"aw\",@progbits"
83 fprintf(F, "\t%s\n", text[asm_flavour][sec]);
91 static void ia32_dump_function_object(FILE *F, const char *name)
93 switch (asm_flavour) {
95 fprintf(F, "\t.type\t%s, @function\n", name);
98 fprintf(F, "\t.def\t%s;\t.scl\t2;\t.type\t32;\t.endef\n", name);
105 static void ia32_dump_function_size(FILE *F, const char *name)
107 switch (asm_flavour) {
109 fprintf(F, "\t.size\t%s, .-%s\n", name, name);
116 /*************************************************************
118 * (_) | | / _| | | | |
119 * _ __ _ __ _ _ __ | |_| |_ | |__ ___| |_ __ ___ _ __
120 * | '_ \| '__| | '_ \| __| _| | '_ \ / _ \ | '_ \ / _ \ '__|
121 * | |_) | | | | | | | |_| | | | | | __/ | |_) | __/ |
122 * | .__/|_| |_|_| |_|\__|_| |_| |_|\___|_| .__/ \___|_|
125 *************************************************************/
127 static INLINE int be_is_unknown_reg(const arch_register_t *reg) {
129 REGS_ARE_EQUAL(reg, &ia32_gp_regs[REG_GP_UKNWN]) || \
130 REGS_ARE_EQUAL(reg, &ia32_xmm_regs[REG_XMM_UKNWN]) || \
131 REGS_ARE_EQUAL(reg, &ia32_vfp_regs[REG_VFP_UKNWN]);
135 * returns true if a node has x87 registers
137 static INLINE int has_x87_register(const ir_node *n) {
138 return is_irn_machine_user(n, 0);
141 /* We always pass the ir_node which is a pointer. */
142 static int ia32_get_arg_type(const lc_arg_occ_t *occ) {
143 return lc_arg_type_ptr;
148 * Returns the register at in position pos.
150 static const arch_register_t *get_in_reg(const ir_node *irn, int pos) {
152 const arch_register_t *reg = NULL;
154 assert(get_irn_arity(irn) > pos && "Invalid IN position");
156 /* The out register of the operator at position pos is the
157 in register we need. */
158 op = get_irn_n(irn, pos);
160 reg = arch_get_irn_register(arch_env, op);
162 assert(reg && "no in register found");
164 /* in case of unknown: just return a register */
165 if (REGS_ARE_EQUAL(reg, &ia32_gp_regs[REG_GP_UKNWN]))
166 reg = &ia32_gp_regs[REG_EAX];
167 else if (REGS_ARE_EQUAL(reg, &ia32_xmm_regs[REG_XMM_UKNWN]))
168 reg = &ia32_xmm_regs[REG_XMM0];
169 else if (REGS_ARE_EQUAL(reg, &ia32_vfp_regs[REG_VFP_UKNWN]))
170 reg = &ia32_vfp_regs[REG_VF0];
176 * Returns the register at out position pos.
178 static const arch_register_t *get_out_reg(const ir_node *irn, int pos) {
180 const arch_register_t *reg = NULL;
182 /* 1st case: irn is not of mode_T, so it has only */
183 /* one OUT register -> good */
184 /* 2nd case: irn is of mode_T -> collect all Projs and ask the */
185 /* Proj with the corresponding projnum for the register */
187 if (get_irn_mode(irn) != mode_T) {
188 reg = arch_get_irn_register(arch_env, irn);
190 else if (is_ia32_irn(irn)) {
191 reg = get_ia32_out_reg(irn, pos);
194 const ir_edge_t *edge;
196 foreach_out_edge(irn, edge) {
197 proj = get_edge_src_irn(edge);
198 assert(is_Proj(proj) && "non-Proj from mode_T node");
199 if (get_Proj_proj(proj) == pos) {
200 reg = arch_get_irn_register(arch_env, proj);
206 assert(reg && "no out register found");
216 * Returns the name of the in register at position pos.
218 static const char *get_ia32_reg_name(ir_node *irn, int pos, enum io_direction in_out) {
219 const arch_register_t *reg;
221 if (in_out == IN_REG) {
222 reg = get_in_reg(irn, pos);
224 if (reg->reg_class == &ia32_reg_classes[CLASS_ia32_vfp]) {
225 /* FIXME: works for binop only */
226 assert(2 <= pos && pos <= 3);
227 reg = get_ia32_attr(irn)->x87[pos - 2];
231 /* destination address mode nodes don't have outputs */
232 if (is_ia32_irn(irn) && get_ia32_op_type(irn) == ia32_AddrModeD) {
236 reg = get_out_reg(irn, pos);
237 if (reg->reg_class == &ia32_reg_classes[CLASS_ia32_vfp])
238 reg = get_ia32_attr(irn)->x87[pos + 2];
240 return arch_register_get_name(reg);
244 * Get the register name for a node.
246 static int ia32_get_reg_name(lc_appendable_t *app,
247 const lc_arg_occ_t *occ, const lc_arg_value_t *arg)
250 ir_node *irn = arg->v_ptr;
251 int nr = occ->width - 1;
254 return lc_appendable_snadd(app, "(null)", 6);
256 buf = get_ia32_reg_name(irn, nr, occ->conversion == 'S' ? IN_REG : OUT_REG);
258 /* append the stupid % to register names */
259 lc_appendable_chadd(app, '%');
260 return lc_appendable_snadd(app, buf, strlen(buf));
264 * Get the x87 register name for a node.
266 static int ia32_get_x87_name(lc_appendable_t *app,
267 const lc_arg_occ_t *occ, const lc_arg_value_t *arg)
270 ir_node *irn = arg->v_ptr;
271 int nr = occ->width - 1;
275 return lc_appendable_snadd(app, "(null)", 6);
277 attr = get_ia32_attr(irn);
278 buf = attr->x87[nr]->name;
279 lc_appendable_chadd(app, '%');
280 return lc_appendable_snadd(app, buf, strlen(buf));
284 * Returns the tarval, offset or scale of an ia32 as a string.
286 static int ia32_const_to_str(lc_appendable_t *app,
287 const lc_arg_occ_t *occ, const lc_arg_value_t *arg)
290 ir_node *irn = arg->v_ptr;
293 return lc_arg_append(app, occ, "(null)", 6);
295 if (occ->conversion == 'C') {
296 buf = get_ia32_cnst(irn);
299 buf = get_ia32_am_offs(irn);
302 return buf ? lc_appendable_snadd(app, buf, strlen(buf)) : 0;
306 * Determines the SSE suffix depending on the mode.
308 static int ia32_get_mode_suffix(lc_appendable_t *app,
309 const lc_arg_occ_t *occ, const lc_arg_value_t *arg)
311 ir_node *irn = arg->v_ptr;
312 ir_mode *mode = get_irn_mode(irn);
314 if (mode == mode_T) {
315 mode = get_ia32_res_mode(irn);
317 mode = get_ia32_ls_mode(irn);
321 return lc_arg_append(app, occ, "(null)", 6);
323 if (mode_is_float(mode)) {
324 return lc_appendable_chadd(app, get_mode_size_bits(mode) == 32 ? 's' : 'd');
327 return lc_appendable_chadd(app, mode_is_signed(mode) ? 's' : 'z');
332 * Return the ia32 printf arg environment.
333 * We use the firm environment with some additional handlers.
335 const lc_arg_env_t *ia32_get_arg_env(void) {
336 static lc_arg_env_t *env = NULL;
338 static const lc_arg_handler_t ia32_reg_handler = { ia32_get_arg_type, ia32_get_reg_name };
339 static const lc_arg_handler_t ia32_const_handler = { ia32_get_arg_type, ia32_const_to_str };
340 static const lc_arg_handler_t ia32_mode_handler = { ia32_get_arg_type, ia32_get_mode_suffix };
341 static const lc_arg_handler_t ia32_x87_handler = { ia32_get_arg_type, ia32_get_x87_name };
344 /* extend the firm printer */
345 env = firm_get_arg_env();
347 lc_arg_register(env, "ia32:sreg", 'S', &ia32_reg_handler);
348 lc_arg_register(env, "ia32:dreg", 'D', &ia32_reg_handler);
349 lc_arg_register(env, "ia32:cnst", 'C', &ia32_const_handler);
350 lc_arg_register(env, "ia32:offs", 'O', &ia32_const_handler);
351 lc_arg_register(env, "ia32:mode", 'M', &ia32_mode_handler);
352 lc_arg_register(env, "ia32:x87", 'X', &ia32_x87_handler);
358 static const char *ia32_get_reg_name_for_mode(ia32_emit_env_t *env, ir_mode *mode, const arch_register_t *reg) {
359 switch(get_mode_size_bits(mode)) {
361 return ia32_get_mapped_reg_name(env->isa->regs_8bit, reg);
363 return ia32_get_mapped_reg_name(env->isa->regs_16bit, reg);
365 return (char *)arch_register_get_name(reg);
370 * Emits registers and/or address mode of a binary operation.
372 const char *ia32_emit_binop(const ir_node *n, ia32_emit_env_t *env) {
373 static char *buf = NULL;
375 /* verify that this function is never called on non-AM supporting operations */
376 //assert(get_ia32_am_support(n) != ia32_am_None && "emit binop expects addressmode support");
378 #define PRODUCES_RESULT(n) \
379 (!(is_ia32_St(n) || \
380 is_ia32_Store8Bit(n) || \
381 is_ia32_CondJmp(n) || \
382 is_ia32_xCondJmp(n) || \
383 is_ia32_CmpSet(n) || \
384 is_ia32_xCmpSet(n) || \
385 is_ia32_SwitchJmp(n)))
388 buf = xcalloc(1, SNPRINTF_BUF_LEN);
391 memset(buf, 0, SNPRINTF_BUF_LEN);
394 switch(get_ia32_op_type(n)) {
396 if (is_ia32_ImmConst(n)) {
397 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%3S, %s", n, get_ia32_cnst(n));
399 else if (is_ia32_ImmSymConst(n)) {
400 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%3S, OFFSET FLAT:%s", n, get_ia32_cnst(n));
403 const arch_register_t *in1 = get_in_reg(n, 2);
404 const arch_register_t *in2 = get_in_reg(n, 3);
405 const arch_register_t *out = PRODUCES_RESULT(n) ? get_out_reg(n, 0) : NULL;
406 const arch_register_t *in;
409 in = out ? (REGS_ARE_EQUAL(out, in2) ? in1 : in2) : in2;
410 out = out ? out : in1;
411 in_name = arch_register_get_name(in);
413 if (is_ia32_emit_cl(n)) {
414 assert(REGS_ARE_EQUAL(&ia32_gp_regs[REG_ECX], in) && "shift operation needs ecx");
418 snprintf(buf, SNPRINTF_BUF_LEN, "%%%s, %%%s", arch_register_get_name(out), in_name);
422 if (is_ia32_ImmConst(n) || is_ia32_ImmSymConst(n)) {
423 assert(! PRODUCES_RESULT(n) && "Source AM with Const must not produce result");
424 snprintf(buf, SNPRINTF_BUF_LEN, "%s, %s", get_ia32_cnst(n), ia32_emit_am(n, env));
427 if (PRODUCES_RESULT(n)) {
428 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%1D, %s", n, ia32_emit_am(n, env));
431 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%3S, %s", n, ia32_emit_am(n, env));
436 if (is_ia32_ImmConst(n) || is_ia32_ImmSymConst(n)) {
437 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%s,%s%s",
438 ia32_emit_am(n, env),
439 is_ia32_ImmSymConst(n) ? " OFFSET FLAT:" : " ", /* In case of a symconst we must add OFFSET to */
440 get_ia32_cnst(n)); /* tell the assembler to store it's address. */
443 const arch_register_t *in1 = get_in_reg(n, get_irn_arity(n) == 5 ? 3 : 2);
444 ir_mode *mode = get_ia32_res_mode(n);
447 mode = mode ? mode : get_ia32_ls_mode(n);
448 in_name = ia32_get_reg_name_for_mode(env, mode, in1);
450 if (is_ia32_emit_cl(n)) {
451 assert(REGS_ARE_EQUAL(&ia32_gp_regs[REG_ECX], in1) && "shift operation needs ecx");
455 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%s, %%%s", ia32_emit_am(n, env), in_name);
459 assert(0 && "unsupported op type");
462 #undef PRODUCES_RESULT
468 * Returns the xxx PTR string for a given mode
470 * @param mode the mode
471 * @param x87_insn if non-zero returns the string for a x87 instruction
472 * else for a SSE instruction
474 static const char *pointer_size(ir_mode *mode, int x87_insn)
477 switch (get_mode_size_bits(mode)) {
478 case 8: return "BYTE PTR";
479 case 16: return "WORD PTR";
480 case 32: return "DWORD PTR";
486 case 96: return "XWORD PTR";
487 default: return NULL;
494 * Emits registers and/or address mode of a binary operation.
496 const char *ia32_emit_x87_binop(const ir_node *n, ia32_emit_env_t *env) {
497 static char *buf = NULL;
499 /* verify that this function is never called on non-AM supporting operations */
500 //assert(get_ia32_am_support(n) != ia32_am_None && "emit binop expects addressmode support");
503 buf = xcalloc(1, SNPRINTF_BUF_LEN);
506 memset(buf, 0, SNPRINTF_BUF_LEN);
509 switch(get_ia32_op_type(n)) {
511 if (is_ia32_ImmConst(n) || is_ia32_ImmSymConst(n)) {
512 ir_mode *mode = get_ia32_ls_mode(n);
513 const char *p = pointer_size(mode, 1);
514 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%s %s", p, get_ia32_cnst(n));
517 ia32_attr_t *attr = get_ia32_attr(n);
518 const arch_register_t *in1 = attr->x87[0];
519 const arch_register_t *in2 = attr->x87[1];
520 const arch_register_t *out = attr->x87[2];
521 const arch_register_t *in;
524 in = out ? (REGS_ARE_EQUAL(out, in2) ? in1 : in2) : in2;
525 out = out ? out : in1;
526 in_name = arch_register_get_name(in);
528 snprintf(buf, SNPRINTF_BUF_LEN, "%%%s, %%%s", arch_register_get_name(out), in_name);
533 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%s", ia32_emit_am(n, env));
536 assert(0 && "unsupported op type");
543 * Emits registers and/or address mode of a unary operation.
545 const char *ia32_emit_unop(const ir_node *n, ia32_emit_env_t *env) {
546 static char *buf = NULL;
549 buf = xcalloc(1, SNPRINTF_BUF_LEN);
552 memset(buf, 0, SNPRINTF_BUF_LEN);
555 switch(get_ia32_op_type(n)) {
557 if (is_ia32_ImmConst(n) || is_ia32_ImmSymConst(n)) {
558 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%C", n);
561 if (is_ia32_MulS(n) || is_ia32_Mulh(n)) {
562 /* MulS and Mulh implicitly multiply by EAX */
563 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%4S", n);
566 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%1D", n);
570 snprintf(buf, SNPRINTF_BUF_LEN, "%s", ia32_emit_am(n, env));
574 Mulh is emitted via emit_unop
575 imul [MEM] means EDX:EAX <- EAX * [MEM]
577 assert((is_ia32_Mulh(n) || is_ia32_MulS(n)) && "Only MulS and Mulh can have AM source as unop");
578 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%s", ia32_emit_am(n, env));
581 assert(0 && "unsupported op type");
588 * Emits address mode.
590 const char *ia32_emit_am(const ir_node *n, ia32_emit_env_t *env) {
591 ia32_am_flavour_t am_flav = get_ia32_am_flavour(n);
595 static struct obstack *obst = NULL;
596 ir_mode *mode = get_ia32_ls_mode(n);
598 if (! is_ia32_Lea(n))
599 assert(mode && "AM node must have ls_mode attribute set.");
602 obst = xcalloc(1, sizeof(*obst));
605 obstack_free(obst, NULL);
608 /* obstack_free with NULL results in an uninitialized obstack */
611 p = pointer_size(mode, has_x87_register(n) || is_ia32_GetST0(n) || is_ia32_SetST0(n));
613 obstack_printf(obst, "%s ", p);
615 /* emit address mode symconst */
616 if (get_ia32_am_sc(n)) {
617 if (is_ia32_am_sc_sign(n))
618 obstack_printf(obst, "-");
619 obstack_printf(obst, "%s", get_id_str(get_ia32_am_sc(n)));
622 if (am_flav & ia32_B) {
623 obstack_printf(obst, "[");
624 lc_eoprintf(ia32_get_arg_env(), obst, "%1S", n);
628 if (am_flav & ia32_I) {
630 obstack_printf(obst, "+");
633 obstack_printf(obst, "[");
636 lc_eoprintf(ia32_get_arg_env(), obst, "%2S", n);
638 if (am_flav & ia32_S) {
639 obstack_printf(obst, "*%d", 1 << get_ia32_am_scale(n));
645 if (am_flav & ia32_O) {
646 s = get_ia32_am_offs(n);
649 /* omit explicit + if there was no base or index */
651 obstack_printf(obst, "[");
656 obstack_printf(obst, s);
662 obstack_printf(obst, "] ");
664 obstack_1grow(obst, '\0');
665 s = obstack_finish(obst);
673 const char *ia32_emit_adr(const ir_node *irn, ia32_emit_env_t *env)
675 static char buf[SNPRINTF_BUF_LEN];
676 ir_mode *mode = get_ia32_ls_mode(irn);
677 const char *adr = get_ia32_cnst(irn);
678 const char *pref = pointer_size(mode, has_x87_register(irn));
680 snprintf(buf, SNPRINTF_BUF_LEN, "%s %s", pref ? pref : "", adr);
685 * Formated print of commands and comments.
687 static void ia32_fprintf_format(FILE *F, const ir_node *irn, char *cmd_buf, char *cmnt_buf) {
689 const char *name = irn ? be_retrieve_dbg_info(get_irn_dbg_info((ir_node *)irn), &lineno) : NULL;
692 fprintf(F, "\t%-35s %-60s /* %s:%u */\n", cmd_buf, cmnt_buf, name, lineno);
694 fprintf(F, "\t%-35s %-60s\n", cmd_buf, cmnt_buf);
700 * Add a number to a prefix. This number will not be used a second time.
702 static char *get_unique_label(char *buf, size_t buflen, const char *prefix) {
703 static unsigned long id = 0;
704 snprintf(buf, buflen, "%s%lu", prefix, ++id);
710 /*************************************************
713 * ___ _ __ ___ _| |_ ___ ___ _ __ __| |
714 * / _ \ '_ ` _ \| | __| / __/ _ \| '_ \ / _` |
715 * | __/ | | | | | | |_ | (_| (_) | | | | (_| |
716 * \___|_| |_| |_|_|\__| \___\___/|_| |_|\__,_|
718 *************************************************/
721 #define IA32_DO_EMIT(irn) ia32_fprintf_format(F, irn, cmd_buf, cmnt_buf)
724 * coding of conditions
726 struct cmp2conditon_t {
732 * positive conditions for signed compares
734 static const struct cmp2conditon_t cmp2condition_s[] = {
735 { NULL, pn_Cmp_False }, /* always false */
736 { "e", pn_Cmp_Eq }, /* == */
737 { "l", pn_Cmp_Lt }, /* < */
738 { "le", pn_Cmp_Le }, /* <= */
739 { "g", pn_Cmp_Gt }, /* > */
740 { "ge", pn_Cmp_Ge }, /* >= */
741 { "ne", pn_Cmp_Lg }, /* != */
742 { "ordered", pn_Cmp_Leg }, /* Floating point: ordered */
743 { "unordered", pn_Cmp_Uo }, /* FLoting point: unordered */
744 { "e", pn_Cmp_Ue }, /* Floating point: unordered or == */
745 { "b", pn_Cmp_Ul }, /* Floating point: unordered or < */
746 { "be", pn_Cmp_Ule }, /* Floating point: unordered or <= */
747 { "a", pn_Cmp_Ug }, /* Floating point: unordered or > */
748 { "ae", pn_Cmp_Uge }, /* Floating point: unordered or >= */
749 { "ne", pn_Cmp_Ne }, /* Floating point: unordered or != */
750 { NULL, pn_Cmp_True }, /* always true */
754 * positive conditions for unsigned compares
756 static const struct cmp2conditon_t cmp2condition_u[] = {
757 { NULL, pn_Cmp_False }, /* always false */
758 { "e", pn_Cmp_Eq }, /* == */
759 { "b", pn_Cmp_Lt }, /* < */
760 { "be", pn_Cmp_Le }, /* <= */
761 { "a", pn_Cmp_Gt }, /* > */
762 { "ae", pn_Cmp_Ge }, /* >= */
763 { "ne", pn_Cmp_Lg }, /* != */
764 { "ordered", pn_Cmp_Leg }, /* Floating point: ordered */
765 { "unordered", pn_Cmp_Uo }, /* FLoting point: unordered */
766 { "e", pn_Cmp_Ue }, /* Floating point: unordered or == */
767 { "b", pn_Cmp_Ul }, /* Floating point: unordered or < */
768 { "be", pn_Cmp_Ule }, /* Floating point: unordered or <= */
769 { "a", pn_Cmp_Ug }, /* Floating point: unordered or > */
770 { "ae", pn_Cmp_Uge }, /* Floating point: unordered or >= */
771 { "ne", pn_Cmp_Ne }, /* Floating point: unordered or != */
772 { NULL, pn_Cmp_True }, /* always true */
776 * returns the condition code
778 static const char *get_cmp_suffix(int cmp_code, int unsigned_cmp)
780 assert(cmp2condition_s[cmp_code].num == cmp_code);
781 assert(cmp2condition_u[cmp_code].num == cmp_code);
783 return unsigned_cmp ? cmp2condition_u[cmp_code & 7].name : cmp2condition_s[cmp_code & 7].name;
787 * Returns the target block for a control flow node.
789 static ir_node *get_cfop_target_block(const ir_node *irn) {
790 return get_irn_link(irn);
794 * Returns the target label for a control flow node.
796 static char *get_cfop_target(const ir_node *irn, char *buf) {
797 ir_node *bl = get_cfop_target_block(irn);
799 snprintf(buf, SNPRINTF_BUF_LEN, BLOCK_PREFIX("%ld"), get_irn_node_nr(bl));
803 /** Return the next block in Block schedule */
804 static ir_node *next_blk_sched(const ir_node *block) {
805 return get_irn_link(block);
809 * Returns the Proj with projection number proj and NOT mode_M
811 static ir_node *get_proj(const ir_node *irn, long proj) {
812 const ir_edge_t *edge;
815 assert(get_irn_mode(irn) == mode_T && "expected mode_T node");
817 foreach_out_edge(irn, edge) {
818 src = get_edge_src_irn(edge);
820 assert(is_Proj(src) && "Proj expected");
821 if (get_irn_mode(src) == mode_M)
824 if (get_Proj_proj(src) == proj)
831 * Emits the jump sequence for a conditional jump (cmp + jmp_true + jmp_false)
833 static void finish_CondJmp(FILE *F, const ir_node *irn, ir_mode *mode) {
834 const ir_node *proj_true;
835 const ir_node *proj_false;
836 const ir_node *block;
837 const ir_node *next_block;
838 char buf[SNPRINTF_BUF_LEN];
839 char cmd_buf[SNPRINTF_BUF_LEN];
840 char cmnt_buf[SNPRINTF_BUF_LEN];
845 /* get both Proj's */
846 proj_true = get_proj(irn, pn_Cond_true);
847 assert(proj_true && "CondJmp without true Proj");
849 proj_false = get_proj(irn, pn_Cond_false);
850 assert(proj_false && "CondJmp without false Proj");
852 pnc = get_ia32_pncode(irn);
854 /* for now, the code works for scheduled and non-schedules blocks */
855 block = get_nodes_block(irn);
857 /* we have a block schedule */
858 next_block = next_blk_sched(block);
860 if (get_cfop_target_block(proj_true) == next_block) {
861 /* exchange both proj's so the second one can be omitted */
862 const ir_node *t = proj_true;
863 proj_true = proj_false;
867 pnc = get_negated_pnc(pnc, mode);
870 /* the first Proj must always be created */
871 is_unsigned = mode_is_float(mode) || ! mode_is_signed(mode);
872 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "j%s %s",
873 get_cmp_suffix(pnc, is_unsigned),
874 get_cfop_target(proj_true, buf));
875 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* %s(a, b) %s*/",
876 get_pnc_string(pnc), flipped ? "(was flipped)" : "");
879 /* the second Proj might be a fallthrough */
880 if (get_cfop_target_block(proj_false) != next_block) {
881 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "jmp %s", get_cfop_target(proj_false, buf));
882 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* otherwise */");
886 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* fallthrough %s */", get_cfop_target(proj_false, buf));
892 * Emits code for conditional jump.
894 static void CondJmp_emitter(const ir_node *irn, ia32_emit_env_t *env) {
896 char cmd_buf[SNPRINTF_BUF_LEN];
897 char cmnt_buf[SNPRINTF_BUF_LEN];
899 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "cmp %s", ia32_emit_binop(irn, env));
900 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F */", irn);
902 finish_CondJmp(F, irn, get_ia32_res_mode(irn));
906 * Emits code for conditional jump with two variables.
908 static void emit_ia32_CondJmp(const ir_node *irn, ia32_emit_env_t *env) {
909 CondJmp_emitter(irn, env);
913 * Emits code for conditional test and jump.
915 static void TestJmp_emitter(const ir_node *irn, ia32_emit_env_t *env) {
917 #define IA32_IS_IMMOP (is_ia32_ImmConst(irn) || is_ia32_ImmSymConst(irn))
920 const char *op1 = arch_register_get_name(get_in_reg(irn, 0));
921 const char *op2 = IA32_IS_IMMOP ? get_ia32_cnst(irn) : NULL;
922 char cmd_buf[SNPRINTF_BUF_LEN];
923 char cmnt_buf[SNPRINTF_BUF_LEN];
926 op2 = arch_register_get_name(get_in_reg(irn, 1));
928 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "test %%%s,%s%s ", op1, IA32_IS_IMMOP ? " " : " %", op2);
929 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F */", irn);
932 finish_CondJmp(F, irn, get_ia32_res_mode(irn));
938 * Emits code for conditional test and jump with two variables.
940 static void emit_ia32_TestJmp(const ir_node *irn, ia32_emit_env_t *env) {
941 TestJmp_emitter(irn, env);
944 static void emit_ia32_CJmp(const ir_node *irn, ia32_emit_env_t *env) {
946 char cmd_buf[SNPRINTF_BUF_LEN];
947 char cmnt_buf[SNPRINTF_BUF_LEN];
949 snprintf(cmd_buf, SNPRINTF_BUF_LEN, " ");
950 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F omitted redundant test */", irn);
952 finish_CondJmp(F, irn, get_ia32_res_mode(irn));
955 static void emit_ia32_CJmpAM(const ir_node *irn, ia32_emit_env_t *env) {
957 char cmd_buf[SNPRINTF_BUF_LEN];
958 char cmnt_buf[SNPRINTF_BUF_LEN];
960 snprintf(cmd_buf, SNPRINTF_BUF_LEN, " ");
961 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F omitted redundant test/cmp */", irn);
963 finish_CondJmp(F, irn, get_ia32_res_mode(irn));
967 * Emits code for conditional SSE floating point jump with two variables.
969 static void emit_ia32_xCondJmp(ir_node *irn, ia32_emit_env_t *env) {
971 char cmd_buf[SNPRINTF_BUF_LEN];
972 char cmnt_buf[SNPRINTF_BUF_LEN];
974 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "ucomis%M %s", irn, ia32_emit_binop(irn, env));
975 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F */", irn);
977 finish_CondJmp(F, irn, mode_F);
982 * Emits code for conditional x87 floating point jump with two variables.
984 static void emit_ia32_x87CondJmp(ir_node *irn, ia32_emit_env_t *env) {
986 char cmd_buf[SNPRINTF_BUF_LEN];
987 char cmnt_buf[SNPRINTF_BUF_LEN];
988 ia32_attr_t *attr = get_ia32_attr(irn);
989 const char *reg = attr->x87[1]->name;
990 const char *instr = "fcom";
993 switch (get_ia32_irn_opcode(irn)) {
994 case iro_ia32_fcomrJmp:
996 case iro_ia32_fcomJmp:
1000 case iro_ia32_fcomrpJmp:
1002 case iro_ia32_fcompJmp:
1005 case iro_ia32_fcomrppJmp:
1007 case iro_ia32_fcomppJmp:
1014 set_ia32_pncode(irn, (long)get_inversed_pnc(get_ia32_pncode(irn)));
1016 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "%s %s%s", instr, reg[0] == '\0' ? "" : "%", reg);
1017 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F */", irn);
1019 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "fnstsw %%ax", irn);
1020 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* Store x87 FPU Control Word */");
1022 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "sahf");
1023 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* Store ah into flags */");
1026 /* the compare flags must be evaluated using carry , ie unsigned */
1027 finish_CondJmp(F, irn, mode_Iu);
1030 static void CMov_emitter(ir_node *irn, ia32_emit_env_t *env) {
1032 const lc_arg_env_t *arg_env = ia32_get_arg_env();
1033 ir_mode *mode = get_irn_mode(get_irn_n(irn, 0));
1034 int is_unsigned = mode_is_float(mode) || ! mode_is_signed(mode);
1035 const char *cmp_suffix = get_cmp_suffix(get_ia32_pncode(irn), is_unsigned);
1036 int is_PsiCondCMov = is_ia32_PsiCondCMov(irn);
1037 int idx_left = 2 - is_PsiCondCMov;
1038 int idx_right = 3 - is_PsiCondCMov;
1040 char cmd_buf[SNPRINTF_BUF_LEN];
1041 char cmnt_buf[SNPRINTF_BUF_LEN];
1042 const arch_register_t *in1, *in2, *out;
1044 out = arch_get_irn_register(env->arch_env, irn);
1045 in1 = arch_get_irn_register(env->arch_env, get_irn_n(irn, idx_left));
1046 in2 = arch_get_irn_register(env->arch_env, get_irn_n(irn, idx_right));
1048 /* we have to emit the cmp first, because the destination register */
1049 /* could be one of the compare registers */
1050 if (is_ia32_CmpCMov(irn)) {
1051 lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "cmp %1S, %2S", irn, irn);
1053 else if (is_ia32_xCmpCMov(irn)) {
1054 lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "ucomis%M %1S, %2S", get_irn_n(irn, 0), irn, irn);
1056 else if (is_PsiCondCMov) {
1057 /* omit compare because flags are already set by And/Or */
1058 lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "test %1S, %1S", irn, irn);
1061 assert(0 && "unsupported CMov");
1063 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* Psi condition */" );
1066 if (REGS_ARE_EQUAL(out, in2)) {
1067 /* best case: default in == out -> do nothing */
1069 else if (REGS_ARE_EQUAL(out, in1)) {
1070 /* true in == out -> need complement compare and exchange true and default in */
1071 ir_node *t = get_irn_n(irn, idx_left);
1072 set_irn_n(irn, idx_left, get_irn_n(irn, idx_right));
1073 set_irn_n(irn, idx_right, t);
1075 cmp_suffix = get_cmp_suffix(get_negated_pnc(get_ia32_pncode(irn), get_irn_mode(irn)), is_unsigned);
1079 /* out is different from in: need copy default -> out */
1081 lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "mov %1D, %3S", irn, irn);
1083 lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "mov %1D, %4S", irn, irn);
1085 lc_esnprintf(arg_env, cmnt_buf, SNPRINTF_BUF_LEN, "/* copy default -> out */" );
1090 lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "cmov%s %1D, %2S", cmp_suffix, irn, irn);
1092 lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "cmov%s %1D, %3S", cmp_suffix, irn, irn);
1094 lc_esnprintf(arg_env, cmnt_buf, SNPRINTF_BUF_LEN, "/* condition is true case */" );
1098 static void emit_ia32_CmpCMov(ir_node *irn, ia32_emit_env_t *env) {
1099 CMov_emitter(irn, env);
1102 static void emit_ia32_PsiCondCMov(ir_node *irn, ia32_emit_env_t *env) {
1103 CMov_emitter(irn, env);
1106 static void emit_ia32_xCmpCMov(ir_node *irn, ia32_emit_env_t *env) {
1107 CMov_emitter(irn, env);
1110 static void Set_emitter(ir_node *irn, ir_mode *mode, ia32_emit_env_t *env) {
1112 const lc_arg_env_t *arg_env = ia32_get_arg_env();
1113 int is_unsigned = mode_is_float(mode) || ! mode_is_signed(mode);
1114 const char *cmp_suffix = get_cmp_suffix(get_ia32_pncode(irn), is_unsigned);
1115 const char *reg8bit;
1117 char cmd_buf[SNPRINTF_BUF_LEN];
1118 char cmnt_buf[SNPRINTF_BUF_LEN];
1119 const arch_register_t *out;
1121 out = arch_get_irn_register(env->arch_env, irn);
1122 reg8bit = ia32_get_mapped_reg_name(env->isa->regs_8bit, out);
1124 if (is_ia32_CmpSet(irn)) {
1125 lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "cmp %s", ia32_emit_binop(irn, env));
1127 else if (is_ia32_xCmpSet(irn)) {
1128 lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "ucomis%M %s", get_irn_n(irn, 2), ia32_emit_binop(irn, env));
1130 else if (is_ia32_PsiCondSet(irn)) {
1131 /* omit compare because flags are already set by And/Or */
1132 snprintf(cmd_buf, SNPRINTF_BUF_LEN, " ");
1135 assert(0 && "unsupported Set");
1137 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* calculate Psi condition */" );
1140 /* use mov to clear target because it doesn't affect the eflags */
1141 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "mov %%%s, 0", arch_register_get_name(out));
1142 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* clear target as set modifies only lower 8 bit */");
1145 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "set%s %%%s", cmp_suffix, reg8bit);
1146 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* set 1 iff true, 0 otherweise */" );
1150 static void emit_ia32_CmpSet(ir_node *irn, ia32_emit_env_t *env) {
1151 Set_emitter(irn, get_irn_mode(get_irn_n(irn, 2)), env);
1154 static void emit_ia32_PsiCondSet(ir_node *irn, ia32_emit_env_t *env) {
1155 Set_emitter(irn, get_irn_mode(get_irn_n(irn, 0)), env);
1158 static void emit_ia32_xCmpSet(ir_node *irn, ia32_emit_env_t *env) {
1159 Set_emitter(irn, get_irn_mode(get_irn_n(irn, 2)), env);
1162 static void emit_ia32_xCmp(ir_node *irn, ia32_emit_env_t *env) {
1164 const lc_arg_env_t *arg_env = ia32_get_arg_env();
1166 long pnc = get_ia32_pncode(irn);
1167 long unord = pnc & pn_Cmp_Uo;
1168 char cmd_buf[SNPRINTF_BUF_LEN];
1169 char cmnt_buf[SNPRINTF_BUF_LEN];
1172 case pn_Cmp_Leg: /* odered */
1175 case pn_Cmp_Uo: /* unordered */
1179 case pn_Cmp_Eq: /* == */
1183 case pn_Cmp_Lt: /* < */
1187 case pn_Cmp_Le: /* <= */
1191 case pn_Cmp_Gt: /* > */
1195 case pn_Cmp_Ge: /* >= */
1199 case pn_Cmp_Lg: /* != */
1204 assert(sse_pnc >= 0 && "unsupported compare");
1206 if (unord && sse_pnc != 3) {
1208 We need a separate compare against unordered.
1209 Quick and Dirty solution:
1210 - get some memory on stack
1214 - and result and stored result
1217 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "sub %%esp, 8");
1218 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* reserve some space for unordered compare result */");
1220 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "cmpsd %s, 3", ia32_emit_binop(irn, env));
1221 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* SSE compare: unordered */");
1223 lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "movsd [%%esp], %1D", irn);
1224 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* store compare result */");
1228 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "cmpsd %s, %d", ia32_emit_binop(irn, env), sse_pnc);
1229 lc_esnprintf(arg_env, cmnt_buf, SNPRINTF_BUF_LEN, "/* SSE compare (%+F) with result in %1D */", irn, irn);
1232 if (unord && sse_pnc != 3) {
1233 lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "andpd %1D, [%%esp]", irn);
1234 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* build the final result */");
1236 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "add %%esp, 8");
1237 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* free allocated space */");
1242 /*********************************************************
1245 * ___ _ __ ___ _| |_ _ _ _ _ __ ___ _ __ ___
1246 * / _ \ '_ ` _ \| | __| | | | | | '_ ` _ \| '_ \/ __|
1247 * | __/ | | | | | | |_ | | |_| | | | | | | |_) \__ \
1248 * \___|_| |_| |_|_|\__| | |\__,_|_| |_| |_| .__/|___/
1251 *********************************************************/
1253 /* jump table entry (target and corresponding number) */
1254 typedef struct _branch_t {
1259 /* jump table for switch generation */
1260 typedef struct _jmp_tbl_t {
1261 ir_node *defProj; /**< default target */
1262 int min_value; /**< smallest switch case */
1263 int max_value; /**< largest switch case */
1264 int num_branches; /**< number of jumps */
1265 char *label; /**< label of the jump table */
1266 branch_t *branches; /**< jump array */
1270 * Compare two variables of type branch_t. Used to sort all switch cases
1272 static int ia32_cmp_branch_t(const void *a, const void *b) {
1273 branch_t *b1 = (branch_t *)a;
1274 branch_t *b2 = (branch_t *)b;
1276 if (b1->value <= b2->value)
1283 * Emits code for a SwitchJmp (creates a jump table if
1284 * possible otherwise a cmp-jmp cascade). Port from
1287 static void emit_ia32_SwitchJmp(const ir_node *irn, ia32_emit_env_t *emit_env) {
1288 unsigned long interval;
1289 char buf[SNPRINTF_BUF_LEN];
1290 int last_value, i, pn;
1293 const ir_edge_t *edge;
1294 const lc_arg_env_t *env = ia32_get_arg_env();
1295 FILE *F = emit_env->out;
1296 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1298 /* fill the table structure */
1299 tbl.label = xmalloc(SNPRINTF_BUF_LEN);
1300 tbl.label = get_unique_label(tbl.label, SNPRINTF_BUF_LEN, ".TBL_");
1302 tbl.num_branches = get_irn_n_edges(irn);
1303 tbl.branches = xcalloc(tbl.num_branches, sizeof(tbl.branches[0]));
1304 tbl.min_value = INT_MAX;
1305 tbl.max_value = INT_MIN;
1308 /* go over all proj's and collect them */
1309 foreach_out_edge(irn, edge) {
1310 proj = get_edge_src_irn(edge);
1311 assert(is_Proj(proj) && "Only proj allowed at SwitchJmp");
1313 pn = get_Proj_proj(proj);
1315 /* create branch entry */
1316 tbl.branches[i].target = proj;
1317 tbl.branches[i].value = pn;
1319 tbl.min_value = pn < tbl.min_value ? pn : tbl.min_value;
1320 tbl.max_value = pn > tbl.max_value ? pn : tbl.max_value;
1322 /* check for default proj */
1323 if (pn == get_ia32_pncode(irn)) {
1324 assert(tbl.defProj == NULL && "found two defProjs at SwitchJmp");
1331 /* sort the branches by their number */
1332 qsort(tbl.branches, tbl.num_branches, sizeof(tbl.branches[0]), ia32_cmp_branch_t);
1334 /* two-complement's magic make this work without overflow */
1335 interval = tbl.max_value - tbl.min_value;
1337 /* emit the table */
1338 lc_esnprintf(env, cmd_buf, SNPRINTF_BUF_LEN, "cmp %1S, %u", irn, interval);
1339 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* compare for switch */");
1342 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "ja %s", get_cfop_target(tbl.defProj, buf));
1343 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* default jump if out of range */");
1346 if (tbl.num_branches > 1) {
1349 lc_esnprintf(env, cmd_buf, SNPRINTF_BUF_LEN, "jmp %s[%1S*4]", tbl.label, irn);
1350 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* get jump table entry as target */");
1353 ia32_switch_section(F, SECTION_RODATA);
1354 fprintf(F, "\t.align 4\n");
1356 fprintf(F, "%s:\n", tbl.label);
1358 snprintf(cmd_buf, SNPRINTF_BUF_LEN, ".long %s", get_cfop_target(tbl.branches[0].target, buf));
1359 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* case %d */", tbl.branches[0].value);
1362 last_value = tbl.branches[0].value;
1363 for (i = 1; i < tbl.num_branches; ++i) {
1364 while (++last_value < tbl.branches[i].value) {
1365 snprintf(cmd_buf, SNPRINTF_BUF_LEN, ".long %s", get_cfop_target(tbl.defProj, buf));
1366 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* default case */");
1369 snprintf(cmd_buf, SNPRINTF_BUF_LEN, ".long %s", get_cfop_target(tbl.branches[i].target, buf));
1370 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* case %d */", last_value);
1373 ia32_switch_section(F, SECTION_TEXT);
1376 /* one jump is enough */
1377 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "jmp %s", get_cfop_target(tbl.branches[0].target, buf));
1378 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* only one case given */");
1389 * Emits code for a unconditional jump.
1391 static void emit_Jmp(const ir_node *irn, ia32_emit_env_t *env) {
1392 ir_node *block, *next_bl;
1394 char buf[SNPRINTF_BUF_LEN], cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1396 /* for now, the code works for scheduled and non-schedules blocks */
1397 block = get_nodes_block(irn);
1399 /* we have a block schedule */
1400 next_bl = next_blk_sched(block);
1401 if (get_cfop_target_block(irn) != next_bl) {
1402 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "jmp %s", get_cfop_target(irn, buf));
1403 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F(%+F) */", irn, get_cfop_target_block(irn));
1407 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* fallthrough %s */", get_cfop_target(irn, buf));
1412 /****************************
1415 * _ __ _ __ ___ _ ___
1416 * | '_ \| '__/ _ \| |/ __|
1417 * | |_) | | | (_) | |\__ \
1418 * | .__/|_| \___/| ||___/
1421 ****************************/
1424 * Emits code for a proj -> node
1426 static void emit_Proj(const ir_node *irn, ia32_emit_env_t *env) {
1427 ir_node *pred = get_Proj_pred(irn);
1429 if (get_irn_op(pred) == op_Start) {
1430 switch(get_Proj_proj(irn)) {
1431 case pn_Start_X_initial_exec:
1440 /**********************************
1443 * | | ___ _ __ _ _| |_) |
1444 * | | / _ \| '_ \| | | | _ <
1445 * | |___| (_) | |_) | |_| | |_) |
1446 * \_____\___/| .__/ \__, |____/
1449 **********************************/
1452 * Emit movsb/w instructions to make mov count divideable by 4
1454 static void emit_CopyB_prolog(FILE *F, const ir_node *irn, int rem) {
1455 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1457 ir_fprintf(F, "\t/* memcopy prolog %+F */\n", irn);
1459 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "cld");
1460 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* copy direction forward */");
1465 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "movsb");
1466 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* memcopy remainder 1 */");
1470 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "movsw");
1471 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* memcopy remainder 2 */");
1475 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "movsb");
1476 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* memcopy remainder 3 */");
1478 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "movsw");
1479 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* memcopy remainder 3 */");
1487 * Emit rep movsd instruction for memcopy.
1489 static void emit_ia32_CopyB(const ir_node *irn, ia32_emit_env_t *emit_env) {
1490 FILE *F = emit_env->out;
1491 tarval *tv = get_ia32_Immop_tarval(irn);
1492 int rem = get_tarval_long(tv);
1493 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1495 emit_CopyB_prolog(F, irn, rem);
1497 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "rep movsd");
1498 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* memcopy */");
1503 * Emits unrolled memcopy.
1505 static void emit_ia32_CopyB_i(const ir_node *irn, ia32_emit_env_t *emit_env) {
1506 tarval *tv = get_ia32_Immop_tarval(irn);
1507 int size = get_tarval_long(tv);
1508 FILE *F = emit_env->out;
1509 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1511 emit_CopyB_prolog(F, irn, size & 0x3);
1515 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "movsd");
1516 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* memcopy unrolled */");
1523 /***************************
1527 * | | / _ \| '_ \ \ / /
1528 * | |___| (_) | | | \ V /
1529 * \_____\___/|_| |_|\_/
1531 ***************************/
1534 * Emit code for conversions (I, FP), (FP, I) and (FP, FP).
1536 static void emit_ia32_Conv_with_FP(const ir_node *irn, ia32_emit_env_t *emit_env) {
1537 FILE *F = emit_env->out;
1538 const lc_arg_env_t *env = ia32_get_arg_env();
1539 ir_mode *src_mode = get_ia32_src_mode(irn);
1540 ir_mode *tgt_mode = get_ia32_tgt_mode(irn);
1541 char *from, *to, buf[64];
1542 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1544 from = mode_is_float(src_mode) ? (get_mode_size_bits(src_mode) == 32 ? "ss" : "sd") : "si";
1545 to = mode_is_float(tgt_mode) ? (get_mode_size_bits(tgt_mode) == 32 ? "ss" : "sd") : "si";
1547 switch(get_ia32_op_type(irn)) {
1549 lc_esnprintf(env, buf, sizeof(buf), "%1D, %3S", irn, irn);
1551 case ia32_AddrModeS:
1552 lc_esnprintf(env, buf, sizeof(buf), "%1D, %s", irn, ia32_emit_am(irn, emit_env));
1555 assert(0 && "unsupported op type for Conv");
1558 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "cvt%s2%s %s", from, to, buf);
1559 lc_esnprintf(env, cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F(%+F, %+F) */", irn, src_mode, tgt_mode);
1563 static void emit_ia32_Conv_I2FP(const ir_node *irn, ia32_emit_env_t *emit_env) {
1564 emit_ia32_Conv_with_FP(irn, emit_env);
1567 static void emit_ia32_Conv_FP2I(const ir_node *irn, ia32_emit_env_t *emit_env) {
1568 emit_ia32_Conv_with_FP(irn, emit_env);
1571 static void emit_ia32_Conv_FP2FP(const ir_node *irn, ia32_emit_env_t *emit_env) {
1572 emit_ia32_Conv_with_FP(irn, emit_env);
1576 * Emits code for an Int conversion.
1578 static void emit_ia32_Conv_I2I(const ir_node *irn, ia32_emit_env_t *emit_env) {
1579 FILE *F = emit_env->out;
1580 const lc_arg_env_t *env = ia32_get_arg_env();
1581 char *move_cmd = "movzx";
1582 char *conv_cmd = NULL;
1583 ir_mode *src_mode = get_ia32_src_mode(irn);
1584 ir_mode *tgt_mode = get_ia32_tgt_mode(irn);
1586 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1587 const arch_register_t *in_reg, *out_reg;
1589 n = get_mode_size_bits(src_mode);
1590 m = get_mode_size_bits(tgt_mode);
1592 if (mode_is_signed(n < m ? src_mode : tgt_mode)) {
1594 if (n == 8 || m == 8)
1596 else if (n == 16 || m == 16)
1599 printf("%d -> %d unsupported\n", n, m);
1600 assert(0 && "unsupported Conv_I2I");
1604 switch(get_ia32_op_type(irn)) {
1606 in_reg = get_in_reg(irn, 2);
1607 out_reg = get_out_reg(irn, 0);
1609 if (REGS_ARE_EQUAL(in_reg, &ia32_gp_regs[REG_EAX]) &&
1610 REGS_ARE_EQUAL(out_reg, in_reg) &&
1611 mode_is_signed(n < m ? src_mode : tgt_mode))
1613 /* argument and result are both in EAX and */
1614 /* signedness is ok: -> use converts */
1615 lc_esnprintf(env, cmd_buf, SNPRINTF_BUF_LEN, "%s", conv_cmd);
1617 else if (REGS_ARE_EQUAL(out_reg, in_reg) &&
1618 ! mode_is_signed(n < m ? src_mode : tgt_mode))
1620 /* argument and result are in the same register */
1621 /* and signedness is ok: -> use and with mask */
1622 int mask = (1 << (n < m ? n : m)) - 1;
1623 lc_esnprintf(env, cmd_buf, SNPRINTF_BUF_LEN, "and %1D, 0x%x", irn, mask);
1626 /* use move w/o sign extension */
1627 lc_esnprintf(env, cmd_buf, SNPRINTF_BUF_LEN, "%s %1D, %%%s",
1628 move_cmd, irn, ia32_get_reg_name_for_mode(emit_env, n < m ? src_mode : tgt_mode, in_reg));
1632 case ia32_AddrModeS:
1633 lc_esnprintf(env, cmd_buf, SNPRINTF_BUF_LEN, "%s %1D, %s",
1634 move_cmd, irn, ia32_emit_am(irn, emit_env));
1637 assert(0 && "unsupported op type for Conv");
1640 lc_esnprintf(env, cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F(%d Bit mode_%F -> %d Bit mode_%F) */",
1641 irn, n, src_mode, m, tgt_mode);
1647 * Emits code for an 8Bit Int conversion.
1649 void emit_ia32_Conv_I2I8Bit(const ir_node *irn, ia32_emit_env_t *emit_env) {
1650 emit_ia32_Conv_I2I(irn, emit_env);
1654 /*******************************************
1657 * | |__ ___ _ __ ___ __| | ___ ___
1658 * | '_ \ / _ \ '_ \ / _ \ / _` |/ _ \/ __|
1659 * | |_) | __/ | | | (_) | (_| | __/\__ \
1660 * |_.__/ \___|_| |_|\___/ \__,_|\___||___/
1662 *******************************************/
1665 * Emits a backend call
1667 static void emit_be_Call(const ir_node *irn, ia32_emit_env_t *emit_env) {
1668 FILE *F = emit_env->out;
1669 entity *ent = be_Call_get_entity(irn);
1670 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1673 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "call %s", get_entity_ld_name(ent));
1676 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "call %1D", get_irn_n(irn, be_pos_Call_ptr));
1679 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F (be_Call) */", irn);
1685 * Emits code to increase stack pointer.
1687 static void emit_be_IncSP(const ir_node *irn, ia32_emit_env_t *emit_env) {
1688 FILE *F = emit_env->out;
1689 int offs = be_get_IncSP_offset(irn);
1690 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1694 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "sub %1S, %u", irn, offs);
1696 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "add %1S, %u", irn, -offs);
1697 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F (IncSP) */", irn);
1700 snprintf(cmd_buf, SNPRINTF_BUF_LEN, " ");
1701 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* omitted %+F (IncSP) with 0 */", irn);
1708 * Emits code to set stack pointer.
1710 static void emit_be_SetSP(const ir_node *irn, ia32_emit_env_t *emit_env) {
1711 FILE *F = emit_env->out;
1712 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1714 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "mov %1D, %3S", irn, irn);
1715 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F (restore SP) */", irn);
1720 * Emits code for Copy/CopyKeep.
1722 static void Copy_emitter(const ir_node *irn, ir_node *op, ia32_emit_env_t *emit_env) {
1723 FILE *F = emit_env->out;
1724 const arch_env_t *aenv = emit_env->arch_env;
1725 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1727 if (REGS_ARE_EQUAL(arch_get_irn_register(aenv, irn), arch_get_irn_register(aenv, op)) ||
1728 be_is_unknown_reg(arch_get_irn_register(aenv, op)))
1731 if (mode_is_float(get_irn_mode(irn)))
1732 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "movs%M %1D, %1S", irn, irn, irn);
1734 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "mov %1D, %1S", irn, irn);
1735 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F */", irn);
1739 static void emit_be_Copy(const ir_node *irn, ia32_emit_env_t *emit_env) {
1740 Copy_emitter(irn, be_get_Copy_op(irn), emit_env);
1743 static void emit_be_CopyKeep(const ir_node *irn, ia32_emit_env_t *emit_env) {
1744 Copy_emitter(irn, be_get_CopyKeep_op(irn), emit_env);
1748 * Emits code for exchange.
1750 static void emit_be_Perm(const ir_node *irn, ia32_emit_env_t *emit_env) {
1751 FILE *F = emit_env->out;
1752 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1753 const arch_register_t *in1, *in2;
1754 const arch_register_class_t *cls1, *cls2;
1756 in1 = arch_get_irn_register(emit_env->arch_env, get_irn_n(irn, 0));
1757 in2 = arch_get_irn_register(emit_env->arch_env, get_irn_n(irn, 1));
1759 cls1 = arch_register_get_class(in1);
1760 cls2 = arch_register_get_class(in2);
1762 assert(cls1 == cls2 && "Register class mismatch at Perm");
1764 if (cls1 == &ia32_reg_classes[CLASS_ia32_gp]) {
1765 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "xchg %1S, %2S", irn, irn);
1767 else if (cls1 == &ia32_reg_classes[CLASS_ia32_xmm]) {
1768 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN,
1769 "pxor %1S, %2S\n\tpxor %2S, %1S\n\tpxor %1S, %2S", irn, irn, irn, irn, irn, irn);
1771 else if (cls1 == &ia32_reg_classes[CLASS_ia32_vfp]) {
1775 else if (cls1 == &ia32_reg_classes[CLASS_ia32_st]) {
1780 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F(%1A, %2A) */", irn, irn, irn);
1785 * Emits code for Constant loading.
1787 static void emit_ia32_Const(const ir_node *n, ia32_emit_env_t *env) {
1789 char cmd_buf[256], cmnt_buf[256];
1790 const lc_arg_env_t *arg_env = ia32_get_arg_env();
1792 if (get_ia32_Immop_tarval(n) == get_tarval_null(get_irn_mode(n))) {
1793 const char *instr = "xor";
1794 if (env->isa->opt_arch == arch_pentium_4) {
1795 /* P4 prefers sub r, r, others xor r, r */
1798 lc_esnprintf(arg_env, cmd_buf, 256, "%s %1D, %1D ", instr, n, n);
1799 lc_esnprintf(arg_env, cmnt_buf, 256, "/* optimized mov 0 to register */");
1802 if (get_ia32_op_type(n) == ia32_SymConst) {
1803 lc_esnprintf(arg_env, cmd_buf, 256, "mov %1D, OFFSET FLAT:%C ", n, n);
1804 lc_esnprintf(arg_env, cmnt_buf, 256, "/* Move address of SymConst into register */");
1807 lc_esnprintf(arg_env, cmd_buf, 256, "mov %1D, %C ", n, n);
1808 lc_esnprintf(arg_env, cmnt_buf, 256, "/* Mov Const into register */");
1811 lc_efprintf(arg_env, F, "\t%-35s %-60s /* %+F (%+G) */\n", cmd_buf, cmnt_buf, n, n);
1815 * Emits code to increase stack pointer.
1817 static void emit_ia32_AddSP(const ir_node *irn, ia32_emit_env_t *emit_env) {
1818 FILE *F = emit_env->out;
1819 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1821 if (is_ia32_ImmConst(irn)) {
1822 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "sub %1D, %C", irn, irn);
1824 else if (is_ia32_ImmSymConst(irn)) {
1825 if (get_ia32_op_type(irn) == ia32_Normal)
1826 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "sub %1D, OFFSET_FLAT:%C", irn, irn);
1827 else /* source address mode */
1828 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "sub %1D, [%s%s]", irn, get_id_str(get_ia32_am_sc(irn)), get_ia32_am_offs(irn));
1831 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "sub %1D, %2S", irn, irn);
1833 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* reserve space on stack */");
1839 * Emits code to load the TLS base
1841 static void emit_ia32_LdTls(const ir_node *irn, ia32_emit_env_t *emit_env) {
1842 FILE *F = emit_env->out;
1843 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1845 switch (asm_flavour) {
1847 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "mov %1D, DWORD PTR %%gs:0", irn);
1850 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "mov %1D, DWORD PTR %%gs:0", irn);
1853 assert(0 && "unsupported TLS");
1856 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* get thread local storage base */");
1861 static void emit_be_Return(const ir_node *n, ia32_emit_env_t *env) {
1863 const lc_arg_env_t *arg_env = ia32_get_arg_env();
1865 lc_efprintf(arg_env, F, "\t%-35s %-60s /* %+F (%+G) */\n", "ret", "/* be_Return */", n, n);
1868 static void emit_Nothing(const ir_node *n, ia32_emit_env_t *env) {
1871 ir_fprintf(F, "\t%35s /* %+F (%+G) */\n", " ", n, n);
1875 /***********************************************************************************
1878 * _ __ ___ __ _ _ _ __ | |_ _ __ __ _ _ __ ___ _____ _____ _ __| | __
1879 * | '_ ` _ \ / _` | | '_ \ | _| '__/ _` | '_ ` _ \ / _ \ \ /\ / / _ \| '__| |/ /
1880 * | | | | | | (_| | | | | | | | | | | (_| | | | | | | __/\ V V / (_) | | | <
1881 * |_| |_| |_|\__,_|_|_| |_| |_| |_| \__,_|_| |_| |_|\___| \_/\_/ \___/|_| |_|\_\
1883 ***********************************************************************************/
1886 * Enters the emitter functions for handled nodes into the generic
1887 * pointer of an opcode.
1889 static void ia32_register_emitters(void) {
1891 #define IA32_EMIT2(a,b) op_ia32_##a->ops.generic = (op_func)emit_ia32_##b
1892 #define IA32_EMIT(a) IA32_EMIT2(a,a)
1893 #define EMIT(a) op_##a->ops.generic = (op_func)emit_##a
1894 #define IGN(a) op_##a->ops.generic = (op_func)emit_Nothing
1895 #define BE_EMIT(a) op_be_##a->ops.generic = (op_func)emit_be_##a
1896 #define BE_IGN(a) op_be_##a->ops.generic = (op_func)emit_Nothing
1898 /* first clear the generic function pointer for all ops */
1899 clear_irp_opcodes_generic_func();
1901 /* register all emitter functions defined in spec */
1902 ia32_register_spec_emitters();
1904 /* other ia32 emitter functions */
1910 IA32_EMIT(PsiCondCMov);
1912 IA32_EMIT(PsiCondSet);
1913 IA32_EMIT(SwitchJmp);
1916 IA32_EMIT(Conv_I2FP);
1917 IA32_EMIT(Conv_FP2I);
1918 IA32_EMIT(Conv_FP2FP);
1919 IA32_EMIT(Conv_I2I);
1920 IA32_EMIT(Conv_I2I8Bit);
1926 IA32_EMIT(xCmpCMov);
1927 IA32_EMIT(xCondJmp);
1928 IA32_EMIT2(fcomJmp, x87CondJmp);
1929 IA32_EMIT2(fcompJmp, x87CondJmp);
1930 IA32_EMIT2(fcomppJmp, x87CondJmp);
1931 IA32_EMIT2(fcomrJmp, x87CondJmp);
1932 IA32_EMIT2(fcomrpJmp, x87CondJmp);
1933 IA32_EMIT2(fcomrppJmp, x87CondJmp);
1935 /* benode emitter */
1962 * Emits code for a node.
1964 static void ia32_emit_node(const ir_node *irn, void *env) {
1965 ia32_emit_env_t *emit_env = env;
1966 ir_op *op = get_irn_op(irn);
1967 DEBUG_ONLY(firm_dbg_module_t *mod = emit_env->mod;)
1969 DBG((mod, LEVEL_1, "emitting code for %+F\n", irn));
1971 if (op->ops.generic) {
1972 void (*emit)(const ir_node *, void *) = (void (*)(const ir_node *, void *))op->ops.generic;
1976 emit_Nothing(irn, env);
1977 ir_fprintf(stderr, "Warning: No emit handler for node %+F (%+G)\n", irn, irn);
1982 * Emits gas alignment directives
1984 static void ia32_emit_alignment(FILE *F, unsigned align, unsigned skip) {
1985 fprintf(F, "\t.p2align %u,,%u\n", align, skip);
1989 * Emits gas alignment directives for Functions depended on cpu architecture.
1991 static void ia32_emit_align_func(FILE *F, cpu_support cpu) {
1992 unsigned align; unsigned maximum_skip;
1994 /* gcc doesn't emit alignment for p4 ?*/
1995 if (cpu == arch_pentium_4)
2000 align = 2; maximum_skip = 3;
2003 align = 4; maximum_skip = 15;
2006 align = 5; maximum_skip = 31;
2009 align = 4; maximum_skip = 15;
2011 ia32_emit_alignment(F, align, maximum_skip);
2015 * Emits gas alignment directives for Labels depended on cpu architecture.
2017 static void ia32_emit_align_label(FILE *F, cpu_support cpu) {
2018 unsigned align; unsigned maximum_skip;
2020 /* gcc doesn't emit alignment for p4 ?*/
2021 if (cpu == arch_pentium_4)
2026 align = 2; maximum_skip = 3;
2029 align = 4; maximum_skip = 15;
2032 align = 5; maximum_skip = 7;
2035 align = 4; maximum_skip = 7;
2037 ia32_emit_alignment(F, align, maximum_skip);
2041 * Walks over the nodes in a block connected by scheduling edges
2042 * and emits code for each node.
2044 static void ia32_gen_block(ir_node *block, void *env) {
2045 ia32_emit_env_t *emit_env = env;
2047 int need_label = block != get_irg_start_block(get_irn_irg(block));
2048 FILE *F = emit_env->out;
2050 if (! is_Block(block))
2053 if (need_label && (emit_env->cg->opt & IA32_OPT_EXTBB)) {
2054 /* if the extended block scheduler is used, only leader blocks need
2056 need_label = (block == get_extbb_leader(get_nodes_extbb(block)));
2060 char cmd_buf[SNPRINTF_BUF_LEN];
2063 ia32_emit_align_label(emit_env->out, emit_env->isa->opt_arch);
2065 ir_snprintf(cmd_buf, sizeof(cmd_buf), BLOCK_PREFIX("%d:"),
2066 get_irn_node_nr(block));
2067 fprintf(F, "%-43s ", cmd_buf);
2069 /* emit list of pred blocks in comment */
2070 fprintf(F, "/* preds:");
2072 arity = get_irn_arity(block);
2073 for(i = 0; i < arity; ++i) {
2074 ir_node *predblock = get_Block_cfgpred_block(block, i);
2075 fprintf(F, " %ld", get_irn_node_nr(predblock));
2077 fprintf(F, " */\n");
2080 /* emit the contents of the block */
2081 sched_foreach(block, irn) {
2082 ia32_emit_node(irn, env);
2087 * Emits code for function start.
2089 static void ia32_emit_func_prolog(FILE *F, ir_graph *irg, cpu_support cpu) {
2090 entity *irg_ent = get_irg_entity(irg);
2091 const char *irg_name = get_entity_ld_name(irg_ent);
2094 ia32_switch_section(F, SECTION_TEXT);
2095 ia32_emit_align_func(F, cpu);
2096 if (get_entity_visibility(irg_ent) == visibility_external_visible) {
2097 fprintf(F, ".globl %s\n", irg_name);
2099 ia32_dump_function_object(F, irg_name);
2100 fprintf(F, "%s:\n", irg_name);
2104 * Emits code for function end
2106 static void ia32_emit_func_epilog(FILE *F, ir_graph *irg) {
2107 const char *irg_name = get_entity_ld_name(get_irg_entity(irg));
2109 ia32_dump_function_size(F, irg_name);
2115 * Sets labels for control flow nodes (jump target)
2116 * TODO: Jump optimization
2118 static void ia32_gen_labels(ir_node *block, void *env) {
2120 int n = get_Block_n_cfgpreds(block);
2122 for (n--; n >= 0; n--) {
2123 pred = get_Block_cfgpred(block, n);
2124 set_irn_link(pred, block);
2129 * Main driver. Emits the code for one routine.
2131 void ia32_gen_routine(FILE *F, ir_graph *irg, const ia32_code_gen_t *cg) {
2132 ia32_emit_env_t emit_env;
2136 emit_env.arch_env = cg->arch_env;
2138 emit_env.isa = (ia32_isa_t *)cg->arch_env->isa;
2139 FIRM_DBG_REGISTER(emit_env.mod, "firm.be.ia32.emitter");
2141 /* set the global arch_env (needed by print hooks) */
2142 arch_env = cg->arch_env;
2144 ia32_register_emitters();
2146 ia32_emit_func_prolog(F, irg, emit_env.isa->opt_arch);
2147 irg_block_walk_graph(irg, ia32_gen_labels, NULL, &emit_env);
2149 if ((cg->opt & IA32_OPT_EXTBB) && cg->blk_sched) {
2150 int i, n = ARR_LEN(cg->blk_sched);
2152 for (i = 0; i < n;) {
2155 block = cg->blk_sched[i];
2157 next_bl = i < n ? cg->blk_sched[i] : NULL;
2159 /* set here the link. the emitter expects to find the next block here */
2160 set_irn_link(block, next_bl);
2161 ia32_gen_block(block, &emit_env);
2165 /* "normal" block schedule: Note the get_next_block() returns the NUMBER of the block
2166 in the block schedule. As this number should NEVER be equal the next block,
2167 we does not need a clear block link here. */
2168 irg_walk_blkwise_graph(irg, NULL, ia32_gen_block, &emit_env);
2171 ia32_emit_func_epilog(F, irg);