2 * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This file implements the ia32 node emitter.
23 * @author Christian Wuerdig, Matthias Braun
39 #include "iredges_t.h"
42 #include "raw_bitset.h"
45 #include "../besched_t.h"
46 #include "../benode_t.h"
48 #include "../be_dbgout.h"
49 #include "../beemitter.h"
50 #include "../begnuas.h"
51 #include "../beirg_t.h"
52 #include "../be_dbgout.h"
54 #include "ia32_emitter.h"
55 #include "gen_ia32_emitter.h"
56 #include "gen_ia32_regalloc_if.h"
57 #include "ia32_nodes_attr.h"
58 #include "ia32_new_nodes.h"
59 #include "ia32_map_regs.h"
60 #include "ia32_architecture.h"
61 #include "bearch_ia32_t.h"
63 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
65 #define BLOCK_PREFIX ".L"
67 #define SNPRINTF_BUF_LEN 128
69 static const ia32_isa_t *isa;
70 static ia32_code_gen_t *cg;
72 static char pic_base_label[128];
73 static ir_label_t exc_label_id;
74 static int mark_spill_reload = 0;
76 /** Return the next block in Block schedule */
77 static ir_node *get_prev_block_sched(const ir_node *block)
79 return get_irn_link(block);
82 /** Checks if the current block is a fall-through target. */
83 static int is_fallthrough(const ir_node *cfgpred)
87 if (!is_Proj(cfgpred))
89 pred = get_Proj_pred(cfgpred);
90 if (is_ia32_SwitchJmp(pred))
97 * returns non-zero if the given block needs a label
98 * because of being a jump-target (and not a fall-through)
100 static int block_needs_label(const ir_node *block)
103 int n_cfgpreds = get_Block_n_cfgpreds(block);
105 if (n_cfgpreds == 0) {
107 } else if (n_cfgpreds == 1) {
108 ir_node *cfgpred = get_Block_cfgpred(block, 0);
109 ir_node *cfgpred_block = get_nodes_block(cfgpred);
111 if (get_prev_block_sched(block) == cfgpred_block
112 && is_fallthrough(cfgpred)) {
121 * Returns the register at in position pos.
123 static const arch_register_t *get_in_reg(const ir_node *irn, int pos)
126 const arch_register_t *reg = NULL;
128 assert(get_irn_arity(irn) > pos && "Invalid IN position");
130 /* The out register of the operator at position pos is the
131 in register we need. */
132 op = get_irn_n(irn, pos);
134 reg = arch_get_irn_register(op);
136 assert(reg && "no in register found");
138 if (reg == &ia32_gp_regs[REG_GP_NOREG])
139 panic("trying to emit noreg for %+F input %d", irn, pos);
141 /* in case of unknown register: just return a valid register */
142 if (reg == &ia32_gp_regs[REG_GP_UKNWN]) {
143 const arch_register_req_t *req = arch_get_register_req(irn, pos);
145 if (arch_register_req_is(req, limited)) {
146 /* in case of limited requirements: get the first allowed register */
147 unsigned idx = rbitset_next(req->limited, 0, 1);
148 reg = arch_register_for_index(req->cls, idx);
150 /* otherwise get first register in class */
151 reg = arch_register_for_index(req->cls, 0);
159 * Returns the register at out position pos.
161 static const arch_register_t *get_out_reg(const ir_node *irn, int pos)
164 const arch_register_t *reg = NULL;
166 /* 1st case: irn is not of mode_T, so it has only */
167 /* one OUT register -> good */
168 /* 2nd case: irn is of mode_T -> collect all Projs and ask the */
169 /* Proj with the corresponding projnum for the register */
171 if (get_irn_mode(irn) != mode_T) {
173 reg = arch_get_irn_register(irn);
174 } else if (is_ia32_irn(irn)) {
175 reg = arch_irn_get_register(irn, pos);
177 const ir_edge_t *edge;
179 foreach_out_edge(irn, edge) {
180 proj = get_edge_src_irn(edge);
181 assert(is_Proj(proj) && "non-Proj from mode_T node");
182 if (get_Proj_proj(proj) == pos) {
183 reg = arch_get_irn_register(proj);
189 assert(reg && "no out register found");
194 * Add a number to a prefix. This number will not be used a second time.
196 static char *get_unique_label(char *buf, size_t buflen, const char *prefix)
198 static unsigned long id = 0;
199 snprintf(buf, buflen, "%s%lu", prefix, ++id);
203 /*************************************************************
205 * (_) | | / _| | | | |
206 * _ __ _ __ _ _ __ | |_| |_ | |__ ___| |_ __ ___ _ __
207 * | '_ \| '__| | '_ \| __| _| | '_ \ / _ \ | '_ \ / _ \ '__|
208 * | |_) | | | | | | | |_| | | | | | __/ | |_) | __/ |
209 * | .__/|_| |_|_| |_|\__|_| |_| |_|\___|_| .__/ \___|_|
212 *************************************************************/
215 * Emit the name of the 8bit low register
217 static void emit_8bit_register(const arch_register_t *reg)
219 const char *reg_name = arch_register_get_name(reg);
222 be_emit_char(reg_name[1]);
227 * Emit the name of the 8bit high register
229 static void emit_8bit_register_high(const arch_register_t *reg)
231 const char *reg_name = arch_register_get_name(reg);
234 be_emit_char(reg_name[1]);
238 static void emit_16bit_register(const arch_register_t *reg)
240 const char *reg_name = ia32_get_mapped_reg_name(isa->regs_16bit, reg);
243 be_emit_string(reg_name);
246 static void emit_register(const arch_register_t *reg, const ir_mode *mode)
248 const char *reg_name;
251 int size = get_mode_size_bits(mode);
253 case 8: emit_8bit_register(reg); return;
254 case 16: emit_16bit_register(reg); return;
256 assert(mode_is_float(mode) || size == 32);
259 reg_name = arch_register_get_name(reg);
262 be_emit_string(reg_name);
265 void ia32_emit_source_register(const ir_node *node, int pos)
267 const arch_register_t *reg = get_in_reg(node, pos);
269 emit_register(reg, NULL);
272 static void ia32_emit_entity(ir_entity *entity, int no_pic_adjust)
276 set_entity_backend_marked(entity, 1);
277 id = get_entity_ld_ident(entity);
280 if (get_entity_owner(entity) == get_tls_type()) {
281 if (get_entity_visibility(entity) == visibility_external_allocated) {
282 be_emit_cstring("@INDNTPOFF");
284 be_emit_cstring("@NTPOFF");
288 if (!no_pic_adjust && do_pic) {
289 /* TODO: only do this when necessary */
291 be_emit_string(pic_base_label);
295 static void emit_ia32_Immediate_no_prefix(const ir_node *node)
297 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(node);
299 if (attr->symconst != NULL) {
302 ia32_emit_entity(attr->symconst, 0);
304 if (attr->symconst == NULL || attr->offset != 0) {
305 if (attr->symconst != NULL) {
306 be_emit_irprintf("%+d", attr->offset);
308 be_emit_irprintf("0x%X", attr->offset);
313 static void emit_ia32_Immediate(const ir_node *node)
316 emit_ia32_Immediate_no_prefix(node);
319 void ia32_emit_8bit_source_register_or_immediate(const ir_node *node, int pos)
321 const arch_register_t *reg;
322 const ir_node *in = get_irn_n(node, pos);
323 if (is_ia32_Immediate(in)) {
324 emit_ia32_Immediate(in);
328 reg = get_in_reg(node, pos);
329 emit_8bit_register(reg);
332 void ia32_emit_8bit_high_source_register(const ir_node *node, int pos)
334 const ir_node *in = get_irn_n(node, pos);
335 const arch_register_t *reg = get_in_reg(node, pos);
336 emit_8bit_register_high(reg);
339 void ia32_emit_dest_register(const ir_node *node, int pos)
341 const arch_register_t *reg = get_out_reg(node, pos);
343 emit_register(reg, NULL);
346 void ia32_emit_8bit_dest_register(const ir_node *node, int pos)
348 const arch_register_t *reg = get_out_reg(node, pos);
350 emit_register(reg, mode_Bu);
353 void ia32_emit_x87_register(const ir_node *node, int pos)
355 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
359 be_emit_string(attr->x87[pos]->name);
362 static void ia32_emit_mode_suffix_mode(const ir_mode *mode)
364 assert(mode_is_int(mode) || mode_is_reference(mode));
365 switch (get_mode_size_bits(mode)) {
366 case 8: be_emit_char('b'); return;
367 case 16: be_emit_char('w'); return;
368 case 32: be_emit_char('l'); return;
369 /* gas docu says q is the suffix but gcc, objdump and icc use ll
371 case 64: be_emit_cstring("ll"); return;
373 panic("Can't output mode_suffix for %+F", mode);
376 void ia32_emit_mode_suffix(const ir_node *node)
378 ir_mode *mode = get_ia32_ls_mode(node);
382 ia32_emit_mode_suffix_mode(mode);
385 void ia32_emit_x87_mode_suffix(const ir_node *node)
389 /* we only need to emit the mode on address mode */
390 if (get_ia32_op_type(node) == ia32_Normal)
393 mode = get_ia32_ls_mode(node);
394 assert(mode != NULL);
396 if (mode_is_float(mode)) {
397 switch (get_mode_size_bits(mode)) {
398 case 32: be_emit_char('s'); return;
399 case 64: be_emit_char('l'); return;
401 case 96: be_emit_char('t'); return;
404 assert(mode_is_int(mode));
405 switch (get_mode_size_bits(mode)) {
406 case 16: be_emit_char('s'); return;
407 case 32: be_emit_char('l'); return;
408 /* gas docu says q is the suffix but gcc, objdump and icc use ll
410 case 64: be_emit_cstring("ll"); return;
413 panic("Can't output mode_suffix for %+F", mode);
416 static char get_xmm_mode_suffix(ir_mode *mode)
418 assert(mode_is_float(mode));
419 switch(get_mode_size_bits(mode)) {
422 default: panic("Invalid XMM mode");
426 void ia32_emit_xmm_mode_suffix(const ir_node *node)
428 ir_mode *mode = get_ia32_ls_mode(node);
429 assert(mode != NULL);
431 be_emit_char(get_xmm_mode_suffix(mode));
434 void ia32_emit_xmm_mode_suffix_s(const ir_node *node)
436 ir_mode *mode = get_ia32_ls_mode(node);
437 assert(mode != NULL);
438 be_emit_char(get_xmm_mode_suffix(mode));
441 void ia32_emit_extend_suffix(const ir_node *node)
443 ir_mode *mode = get_ia32_ls_mode(node);
444 if (get_mode_size_bits(mode) == 32)
446 be_emit_char(mode_is_signed(mode) ? 's' : 'z');
447 ia32_emit_mode_suffix_mode(mode);
450 void ia32_emit_source_register_or_immediate(const ir_node *node, int pos)
452 ir_node *in = get_irn_n(node, pos);
453 if (is_ia32_Immediate(in)) {
454 emit_ia32_Immediate(in);
456 const ir_mode *mode = get_ia32_ls_mode(node);
457 const arch_register_t *reg = get_in_reg(node, pos);
458 emit_register(reg, mode);
463 * Returns the target block for a control flow node.
465 static ir_node *get_cfop_target_block(const ir_node *irn)
467 assert(get_irn_mode(irn) == mode_X);
468 return get_irn_link(irn);
472 * Emits a block label for the given block.
474 static void ia32_emit_block_name(const ir_node *block)
476 if (has_Block_label(block)) {
477 be_emit_string(be_gas_block_label_prefix());
478 be_emit_irprintf("%lu", get_Block_label(block));
480 be_emit_cstring(BLOCK_PREFIX);
481 be_emit_irprintf("%ld", get_irn_node_nr(block));
486 * Emits the target label for a control flow node.
488 static void ia32_emit_cfop_target(const ir_node *node)
490 ir_node *block = get_cfop_target_block(node);
491 ia32_emit_block_name(block);
495 * positive conditions for signed compares
497 static const char *const cmp2condition_s[] = {
498 NULL, /* always false */
505 NULL /* always true */
509 * positive conditions for unsigned compares
511 static const char *const cmp2condition_u[] = {
512 NULL, /* always false */
519 NULL /* always true */
522 static void ia32_emit_cmp_suffix(int pnc)
526 if (pnc == ia32_pn_Cmp_parity) {
530 if (pnc & ia32_pn_Cmp_float || pnc & ia32_pn_Cmp_unsigned) {
531 str = cmp2condition_u[pnc & 7];
533 str = cmp2condition_s[pnc & 7];
539 typedef enum ia32_emit_mod_t {
540 EMIT_RESPECT_LS = 1U << 0,
541 EMIT_ALTERNATE_AM = 1U << 1,
546 * fmt parameter output
547 * ---- ---------------------- ---------------------------------------------
549 * %AM <node> address mode of the node
550 * %AR const arch_register_t* address mode of the node or register
551 * %ASx <node> address mode of the node or source register x
552 * %Dx <node> destination register x
553 * %I <node> immediate of the node
554 * %L <node> control flow target of the node
555 * %M <node> mode suffix of the node
556 * %P int condition code
557 * %R const arch_register_t* register
558 * %Sx <node> source register x
559 * %s const char* string
560 * %u unsigned int unsigned int
561 * %d signed int signed int
564 * # modifier for %ASx, %D and %S uses ls mode of node to alter register width
565 * * modifier does not prefix immediates with $, but AM with *
566 * l modifier for %lu and %ld
568 static void ia32_emitf(const ir_node *node, const char *fmt, ...)
574 const char *start = fmt;
575 ia32_emit_mod_t mod = 0;
577 while (*fmt != '%' && *fmt != '\n' && *fmt != '\0')
580 be_emit_string_len(start, fmt - start);
584 be_emit_finish_line_gas(node);
596 mod |= EMIT_ALTERNATE_AM;
601 mod |= EMIT_RESPECT_LS;
618 if (mod & EMIT_ALTERNATE_AM)
624 const arch_register_t *reg = va_arg(ap, const arch_register_t*);
625 if (mod & EMIT_ALTERNATE_AM)
627 if (get_ia32_op_type(node) == ia32_AddrModeS) {
630 emit_register(reg, NULL);
636 if (get_ia32_op_type(node) == ia32_AddrModeS) {
637 if (mod & EMIT_ALTERNATE_AM)
642 assert(get_ia32_op_type(node) == ia32_Normal);
647 default: goto unknown;
654 const arch_register_t *reg;
656 if (*fmt < '0' || '9' <= *fmt)
660 reg = get_out_reg(node, pos);
661 emit_register(reg, mod & EMIT_RESPECT_LS ? get_ia32_ls_mode(node) : NULL);
666 if (!(mod & EMIT_ALTERNATE_AM))
668 emit_ia32_Immediate_no_prefix(node);
672 ia32_emit_cfop_target(node);
676 ia32_emit_mode_suffix_mode(get_ia32_ls_mode(node));
681 int pnc = va_arg(ap, int);
682 ia32_emit_cmp_suffix(pnc);
687 const arch_register_t *reg = va_arg(ap, const arch_register_t*);
688 emit_register(reg, NULL);
697 if (*fmt < '0' || '9' <= *fmt)
701 in = get_irn_n(node, pos);
702 if (is_ia32_Immediate(in)) {
703 if (!(mod & EMIT_ALTERNATE_AM))
705 emit_ia32_Immediate_no_prefix(in);
707 const arch_register_t *reg;
709 if (mod & EMIT_ALTERNATE_AM)
711 reg = get_in_reg(node, pos);
712 emit_register(reg, mod & EMIT_RESPECT_LS ? get_ia32_ls_mode(node) : NULL);
718 const char *str = va_arg(ap, const char*);
724 if (mod & EMIT_LONG) {
725 unsigned long num = va_arg(ap, unsigned long);
726 be_emit_irprintf("%lu", num);
728 unsigned num = va_arg(ap, unsigned);
729 be_emit_irprintf("%u", num);
734 if (mod & EMIT_LONG) {
735 long num = va_arg(ap, long);
736 be_emit_irprintf("%ld", num);
738 int num = va_arg(ap, int);
739 be_emit_irprintf("%d", num);
745 panic("unknown format conversion in ia32_emitf()");
753 * Emits registers and/or address mode of a binary operation.
755 void ia32_emit_binop(const ir_node *node)
757 if (is_ia32_Immediate(get_irn_n(node, n_ia32_binary_right))) {
758 ia32_emitf(node, "%#S4, %#AS3");
760 ia32_emitf(node, "%#AS4, %#S3");
765 * Emits registers and/or address mode of a binary operation.
767 void ia32_emit_x87_binop(const ir_node *node)
769 switch(get_ia32_op_type(node)) {
772 const ia32_x87_attr_t *x87_attr = get_ia32_x87_attr_const(node);
773 const arch_register_t *in1 = x87_attr->x87[0];
774 const arch_register_t *in = x87_attr->x87[1];
775 const arch_register_t *out = x87_attr->x87[2];
779 } else if (out == in) {
784 be_emit_string(arch_register_get_name(in));
785 be_emit_cstring(", %");
786 be_emit_string(arch_register_get_name(out));
794 assert(0 && "unsupported op type");
799 * Emits registers and/or address mode of a unary operation.
801 void ia32_emit_unop(const ir_node *node, int pos)
805 ia32_emitf(node, fmt);
809 * Emits address mode.
811 void ia32_emit_am(const ir_node *node)
813 ir_entity *ent = get_ia32_am_sc(node);
814 int offs = get_ia32_am_offs_int(node);
815 ir_node *base = get_irn_n(node, n_ia32_base);
816 int has_base = !is_ia32_NoReg_GP(base);
817 ir_node *index = get_irn_n(node, n_ia32_index);
818 int has_index = !is_ia32_NoReg_GP(index);
820 /* just to be sure... */
821 assert(!is_ia32_use_frame(node) || get_ia32_frame_ent(node) != NULL);
825 if (is_ia32_am_sc_sign(node))
827 ia32_emit_entity(ent, 0);
830 /* also handle special case if nothing is set */
831 if (offs != 0 || (ent == NULL && !has_base && !has_index)) {
833 be_emit_irprintf("%+d", offs);
835 be_emit_irprintf("%d", offs);
839 if (has_base || has_index) {
844 const arch_register_t *reg = get_in_reg(node, n_ia32_base);
845 emit_register(reg, NULL);
848 /* emit index + scale */
850 const arch_register_t *reg = get_in_reg(node, n_ia32_index);
853 emit_register(reg, NULL);
855 scale = get_ia32_am_scale(node);
857 be_emit_irprintf(",%d", 1 << scale);
864 static void emit_ia32_IMul(const ir_node *node)
866 ir_node *left = get_irn_n(node, n_ia32_IMul_left);
867 const arch_register_t *out_reg = get_out_reg(node, pn_ia32_IMul_res);
869 /* do we need the 3-address form? */
870 if (is_ia32_NoReg_GP(left) ||
871 get_in_reg(node, n_ia32_IMul_left) != out_reg) {
872 ia32_emitf(node, "\timul%M %#S4, %#AS3, %#D0\n");
874 ia32_emitf(node, "\timul%M %#AS4, %#S3\n");
879 * walks up a tree of copies/perms/spills/reloads to find the original value
880 * that is moved around
882 static ir_node *find_original_value(ir_node *node)
884 if (irn_visited(node))
887 mark_irn_visited(node);
888 if (be_is_Copy(node)) {
889 return find_original_value(be_get_Copy_op(node));
890 } else if (be_is_CopyKeep(node)) {
891 return find_original_value(be_get_CopyKeep_op(node));
892 } else if (is_Proj(node)) {
893 ir_node *pred = get_Proj_pred(node);
894 if (be_is_Perm(pred)) {
895 return find_original_value(get_irn_n(pred, get_Proj_proj(node)));
896 } else if (be_is_MemPerm(pred)) {
897 return find_original_value(get_irn_n(pred, get_Proj_proj(node) + 1));
898 } else if (is_ia32_Load(pred)) {
899 return find_original_value(get_irn_n(pred, n_ia32_Load_mem));
903 } else if (is_ia32_Store(node)) {
904 return find_original_value(get_irn_n(node, n_ia32_Store_val));
905 } else if (is_Phi(node)) {
907 arity = get_irn_arity(node);
908 for (i = 0; i < arity; ++i) {
909 ir_node *in = get_irn_n(node, i);
910 ir_node *res = find_original_value(in);
921 static int determine_final_pnc(const ir_node *node, int flags_pos,
924 ir_node *flags = get_irn_n(node, flags_pos);
925 const ia32_attr_t *flags_attr;
926 flags = skip_Proj(flags);
928 if (is_ia32_Sahf(flags)) {
929 ir_node *cmp = get_irn_n(flags, n_ia32_Sahf_val);
930 if (!(is_ia32_FucomFnstsw(cmp) || is_ia32_FucompFnstsw(cmp)
931 || is_ia32_FucomppFnstsw(cmp) || is_ia32_FtstFnstsw(cmp))) {
932 inc_irg_visited(current_ir_graph);
933 cmp = find_original_value(cmp);
935 assert(is_ia32_FucomFnstsw(cmp) || is_ia32_FucompFnstsw(cmp)
936 || is_ia32_FucomppFnstsw(cmp) || is_ia32_FtstFnstsw(cmp));
939 flags_attr = get_ia32_attr_const(cmp);
940 if (flags_attr->data.ins_permuted)
941 pnc = get_mirrored_pnc(pnc);
942 pnc |= ia32_pn_Cmp_float;
943 } else if (is_ia32_Ucomi(flags) || is_ia32_Fucomi(flags)
944 || is_ia32_Fucompi(flags)) {
945 flags_attr = get_ia32_attr_const(flags);
947 if (flags_attr->data.ins_permuted)
948 pnc = get_mirrored_pnc(pnc);
949 pnc |= ia32_pn_Cmp_float;
951 flags_attr = get_ia32_attr_const(flags);
953 if (flags_attr->data.ins_permuted)
954 pnc = get_mirrored_pnc(pnc);
955 if (flags_attr->data.cmp_unsigned)
956 pnc |= ia32_pn_Cmp_unsigned;
962 static pn_Cmp ia32_get_negated_pnc(pn_Cmp pnc)
964 ir_mode *mode = pnc & ia32_pn_Cmp_float ? mode_F : mode_Iu;
965 return get_negated_pnc(pnc, mode);
968 void ia32_emit_cmp_suffix_node(const ir_node *node,
971 const ia32_attr_t *attr = get_ia32_attr_const(node);
973 pn_Cmp pnc = get_ia32_condcode(node);
975 pnc = determine_final_pnc(node, flags_pos, pnc);
976 if (attr->data.ins_permuted)
977 pnc = ia32_get_negated_pnc(pnc);
979 ia32_emit_cmp_suffix(pnc);
983 * Emits an exception label for a given node.
985 static void ia32_emit_exc_label(const ir_node *node)
987 be_emit_string(be_gas_insn_label_prefix());
988 be_emit_irprintf("%lu", get_ia32_exc_label_id(node));
992 * Returns the Proj with projection number proj and NOT mode_M
994 static ir_node *get_proj(const ir_node *node, long proj)
996 const ir_edge_t *edge;
999 assert(get_irn_mode(node) == mode_T && "expected mode_T node");
1001 foreach_out_edge(node, edge) {
1002 src = get_edge_src_irn(edge);
1004 assert(is_Proj(src) && "Proj expected");
1005 if (get_irn_mode(src) == mode_M)
1008 if (get_Proj_proj(src) == proj)
1014 static int can_be_fallthrough(const ir_node *node)
1016 ir_node *target_block = get_cfop_target_block(node);
1017 ir_node *block = get_nodes_block(node);
1018 return get_prev_block_sched(target_block) == block;
1022 * Emits the jump sequence for a conditional jump (cmp + jmp_true + jmp_false)
1024 static void emit_ia32_Jcc(const ir_node *node)
1026 int need_parity_label = 0;
1027 const ir_node *proj_true;
1028 const ir_node *proj_false;
1029 const ir_node *block;
1030 pn_Cmp pnc = get_ia32_condcode(node);
1032 pnc = determine_final_pnc(node, 0, pnc);
1034 /* get both Projs */
1035 proj_true = get_proj(node, pn_ia32_Jcc_true);
1036 assert(proj_true && "Jcc without true Proj");
1038 proj_false = get_proj(node, pn_ia32_Jcc_false);
1039 assert(proj_false && "Jcc without false Proj");
1041 block = get_nodes_block(node);
1043 if (can_be_fallthrough(proj_true)) {
1044 /* exchange both proj's so the second one can be omitted */
1045 const ir_node *t = proj_true;
1047 proj_true = proj_false;
1049 pnc = ia32_get_negated_pnc(pnc);
1052 if (pnc & ia32_pn_Cmp_float) {
1053 /* Some floating point comparisons require a test of the parity flag,
1054 * which indicates that the result is unordered */
1057 ia32_emitf(proj_true, "\tjp %L\n");
1062 ia32_emitf(proj_true, "\tjnp %L\n");
1068 /* we need a local label if the false proj is a fallthrough
1069 * as the falseblock might have no label emitted then */
1070 if (can_be_fallthrough(proj_false)) {
1071 need_parity_label = 1;
1072 ia32_emitf(proj_false, "\tjp 1f\n");
1074 ia32_emitf(proj_false, "\tjp %L\n");
1081 ia32_emitf(proj_true, "\tjp %L\n");
1089 ia32_emitf(proj_true, "\tj%P %L\n", pnc);
1092 if (need_parity_label) {
1093 ia32_emitf(NULL, "1:\n");
1096 /* the second Proj might be a fallthrough */
1097 if (can_be_fallthrough(proj_false)) {
1098 ia32_emitf(proj_false, "\t/* fallthrough to %L */\n");
1100 ia32_emitf(proj_false, "\tjmp %L\n");
1104 static void emit_ia32_CMov(const ir_node *node)
1106 const ia32_attr_t *attr = get_ia32_attr_const(node);
1107 int ins_permuted = attr->data.ins_permuted;
1108 const arch_register_t *out = arch_irn_get_register(node, pn_ia32_res);
1109 pn_Cmp pnc = get_ia32_condcode(node);
1110 const arch_register_t *in_true;
1111 const arch_register_t *in_false;
1113 pnc = determine_final_pnc(node, n_ia32_CMov_eflags, pnc);
1115 in_true = arch_get_irn_register(get_irn_n(node, n_ia32_CMov_val_true));
1116 in_false = arch_get_irn_register(get_irn_n(node, n_ia32_CMov_val_false));
1118 /* should be same constraint fullfilled? */
1119 if (out == in_false) {
1120 /* yes -> nothing to do */
1121 } else if (out == in_true) {
1122 const arch_register_t *tmp;
1124 assert(get_ia32_op_type(node) == ia32_Normal);
1126 ins_permuted = !ins_permuted;
1133 ia32_emitf(node, "\tmovl %R, %R\n", in_false, out);
1137 pnc = ia32_get_negated_pnc(pnc);
1139 /* TODO: handling of Nans isn't correct yet */
1141 ia32_emitf(node, "\tcmov%P %#AR, %#R\n", pnc, in_true, out);
1144 /*********************************************************
1147 * ___ _ __ ___ _| |_ _ _ _ _ __ ___ _ __ ___
1148 * / _ \ '_ ` _ \| | __| | | | | | '_ ` _ \| '_ \/ __|
1149 * | __/ | | | | | | |_ | | |_| | | | | | | |_) \__ \
1150 * \___|_| |_| |_|_|\__| | |\__,_|_| |_| |_| .__/|___/
1153 *********************************************************/
1155 /* jump table entry (target and corresponding number) */
1156 typedef struct _branch_t {
1161 /* jump table for switch generation */
1162 typedef struct _jmp_tbl_t {
1163 ir_node *defProj; /**< default target */
1164 long min_value; /**< smallest switch case */
1165 long max_value; /**< largest switch case */
1166 long num_branches; /**< number of jumps */
1167 char *label; /**< label of the jump table */
1168 branch_t *branches; /**< jump array */
1172 * Compare two variables of type branch_t. Used to sort all switch cases
1174 static int ia32_cmp_branch_t(const void *a, const void *b)
1176 branch_t *b1 = (branch_t *)a;
1177 branch_t *b2 = (branch_t *)b;
1179 if (b1->value <= b2->value)
1186 * Emits code for a SwitchJmp (creates a jump table if
1187 * possible otherwise a cmp-jmp cascade). Port from
1190 static void emit_ia32_SwitchJmp(const ir_node *node)
1192 unsigned long interval;
1198 const ir_edge_t *edge;
1200 /* fill the table structure */
1201 tbl.label = XMALLOCN(char, SNPRINTF_BUF_LEN);
1202 tbl.label = get_unique_label(tbl.label, SNPRINTF_BUF_LEN, ".TBL_");
1204 tbl.num_branches = get_irn_n_edges(node) - 1;
1205 tbl.branches = XMALLOCNZ(branch_t, tbl.num_branches);
1206 tbl.min_value = INT_MAX;
1207 tbl.max_value = INT_MIN;
1209 default_pn = get_ia32_condcode(node);
1211 /* go over all proj's and collect them */
1212 foreach_out_edge(node, edge) {
1213 proj = get_edge_src_irn(edge);
1214 assert(is_Proj(proj) && "Only proj allowed at SwitchJmp");
1216 pnc = get_Proj_proj(proj);
1218 /* check for default proj */
1219 if (pnc == default_pn) {
1220 assert(tbl.defProj == NULL && "found two default Projs at SwitchJmp");
1223 tbl.min_value = pnc < tbl.min_value ? pnc : tbl.min_value;
1224 tbl.max_value = pnc > tbl.max_value ? pnc : tbl.max_value;
1226 /* create branch entry */
1227 tbl.branches[i].target = proj;
1228 tbl.branches[i].value = pnc;
1233 assert(i == tbl.num_branches);
1235 /* sort the branches by their number */
1236 qsort(tbl.branches, tbl.num_branches, sizeof(tbl.branches[0]), ia32_cmp_branch_t);
1238 /* two-complement's magic make this work without overflow */
1239 interval = tbl.max_value - tbl.min_value;
1241 /* emit the table */
1242 ia32_emitf(node, "\tcmpl $%u, %S0\n", interval);
1243 ia32_emitf(tbl.defProj, "\tja %L\n");
1245 if (tbl.num_branches > 1) {
1247 ia32_emitf(node, "\tjmp *%s(,%S0,4)\n", tbl.label);
1249 be_gas_emit_switch_section(GAS_SECTION_RODATA);
1250 ia32_emitf(NULL, "\t.align 4\n");
1251 ia32_emitf(NULL, "%s:\n", tbl.label);
1253 last_value = tbl.branches[0].value;
1254 for (i = 0; i != tbl.num_branches; ++i) {
1255 while (last_value != tbl.branches[i].value) {
1256 ia32_emitf(tbl.defProj, ".long %L\n");
1259 ia32_emitf(tbl.branches[i].target, ".long %L\n");
1262 be_gas_emit_switch_section(GAS_SECTION_TEXT);
1264 /* one jump is enough */
1265 ia32_emitf(tbl.branches[0].target, "\tjmp %L\n");
1275 * Emits code for a unconditional jump.
1277 static void emit_Jmp(const ir_node *node)
1281 /* for now, the code works for scheduled and non-schedules blocks */
1282 block = get_nodes_block(node);
1284 /* we have a block schedule */
1285 if (can_be_fallthrough(node)) {
1286 ia32_emitf(node, "\t/* fallthrough to %L */\n");
1288 ia32_emitf(node, "\tjmp %L\n");
1293 * Emit an inline assembler operand.
1295 * @param node the ia32_ASM node
1296 * @param s points to the operand (a %c)
1298 * @return pointer to the first char in s NOT in the current operand
1300 static const char* emit_asm_operand(const ir_node *node, const char *s)
1302 const ia32_attr_t *ia32_attr = get_ia32_attr_const(node);
1303 const ia32_asm_attr_t *attr = CONST_CAST_IA32_ATTR(ia32_asm_attr_t,
1305 const arch_register_t *reg;
1306 const ia32_asm_reg_t *asm_regs = attr->register_map;
1307 const ia32_asm_reg_t *asm_reg;
1308 const char *reg_name;
1317 /* parse modifiers */
1320 ir_fprintf(stderr, "Warning: asm text (%+F) ends with %%\n", node);
1345 "Warning: asm text (%+F) contains unknown modifier '%c' for asm op\n",
1352 sscanf(s, "%d%n", &num, &p);
1354 ir_fprintf(stderr, "Warning: Couldn't parse assembler operand (%+F)\n",
1361 if (num < 0 || ARR_LEN(asm_regs) <= num) {
1363 "Error: Custom assembler references invalid input/output (%+F)\n",
1367 asm_reg = & asm_regs[num];
1368 assert(asm_reg->valid);
1371 if (asm_reg->use_input == 0) {
1372 reg = get_out_reg(node, asm_reg->inout_pos);
1374 ir_node *pred = get_irn_n(node, asm_reg->inout_pos);
1376 /* might be an immediate value */
1377 if (is_ia32_Immediate(pred)) {
1378 emit_ia32_Immediate(pred);
1381 reg = get_in_reg(node, asm_reg->inout_pos);
1385 "Warning: no register assigned for %d asm op (%+F)\n",
1390 if (asm_reg->memory) {
1395 if (modifier != 0) {
1399 reg_name = ia32_get_mapped_reg_name(isa->regs_8bit, reg);
1402 reg_name = ia32_get_mapped_reg_name(isa->regs_8bit_high, reg);
1405 reg_name = ia32_get_mapped_reg_name(isa->regs_16bit, reg);
1408 panic("Invalid asm op modifier");
1410 be_emit_string(reg_name);
1412 emit_register(reg, asm_reg->mode);
1415 if (asm_reg->memory) {
1423 * Emits code for an ASM pseudo op.
1425 static void emit_ia32_Asm(const ir_node *node)
1427 const void *gen_attr = get_irn_generic_attr_const(node);
1428 const ia32_asm_attr_t *attr
1429 = CONST_CAST_IA32_ATTR(ia32_asm_attr_t, gen_attr);
1430 ident *asm_text = attr->asm_text;
1431 const char *s = get_id_str(asm_text);
1433 ia32_emitf(node, "#APP\t\n");
1440 s = emit_asm_operand(node, s);
1446 ia32_emitf(NULL, "\n#NO_APP\n");
1449 /**********************************
1452 * | | ___ _ __ _ _| |_) |
1453 * | | / _ \| '_ \| | | | _ <
1454 * | |___| (_) | |_) | |_| | |_) |
1455 * \_____\___/| .__/ \__, |____/
1458 **********************************/
1461 * Emit movsb/w instructions to make mov count divideable by 4
1463 static void emit_CopyB_prolog(unsigned size)
1466 ia32_emitf(NULL, "\tmovsb\n");
1468 ia32_emitf(NULL, "\tmovsw\n");
1472 * Emit rep movsd instruction for memcopy.
1474 static void emit_ia32_CopyB(const ir_node *node)
1476 unsigned size = get_ia32_copyb_size(node);
1478 emit_CopyB_prolog(size);
1479 ia32_emitf(node, "\trep movsd\n");
1483 * Emits unrolled memcopy.
1485 static void emit_ia32_CopyB_i(const ir_node *node)
1487 unsigned size = get_ia32_copyb_size(node);
1489 emit_CopyB_prolog(size);
1493 ia32_emitf(NULL, "\tmovsd\n");
1499 /***************************
1503 * | | / _ \| '_ \ \ / /
1504 * | |___| (_) | | | \ V /
1505 * \_____\___/|_| |_|\_/
1507 ***************************/
1510 * Emit code for conversions (I, FP), (FP, I) and (FP, FP).
1512 static void emit_ia32_Conv_with_FP(const ir_node *node, const char* conv_f,
1515 ir_mode *ls_mode = get_ia32_ls_mode(node);
1516 int ls_bits = get_mode_size_bits(ls_mode);
1517 const char *conv = ls_bits == 32 ? conv_f : conv_d;
1519 ia32_emitf(node, "\tcvt%s %AS3, %D0\n", conv);
1522 static void emit_ia32_Conv_I2FP(const ir_node *node)
1524 emit_ia32_Conv_with_FP(node, "si2ss", "si2sd");
1527 static void emit_ia32_Conv_FP2I(const ir_node *node)
1529 emit_ia32_Conv_with_FP(node, "ss2si", "sd2si");
1532 static void emit_ia32_Conv_FP2FP(const ir_node *node)
1534 emit_ia32_Conv_with_FP(node, "sd2ss", "ss2sd");
1538 * Emits code for an Int conversion.
1540 static void emit_ia32_Conv_I2I(const ir_node *node)
1542 ir_mode *smaller_mode = get_ia32_ls_mode(node);
1543 int signed_mode = mode_is_signed(smaller_mode);
1544 const char *sign_suffix;
1546 assert(!mode_is_float(smaller_mode));
1548 sign_suffix = signed_mode ? "s" : "z";
1549 ia32_emitf(node, "\tmov%s%Ml %#AS3, %D0\n", sign_suffix);
1555 static void emit_ia32_Call(const ir_node *node)
1557 /* Special case: Call must not have its immediates prefixed by $, instead
1558 * address mode is prefixed by *. */
1559 ia32_emitf(node, "\tcall %*AS3\n");
1563 /*******************************************
1566 * | |__ ___ _ __ ___ __| | ___ ___
1567 * | '_ \ / _ \ '_ \ / _ \ / _` |/ _ \/ __|
1568 * | |_) | __/ | | | (_) | (_| | __/\__ \
1569 * |_.__/ \___|_| |_|\___/ \__,_|\___||___/
1571 *******************************************/
1574 * Emits code to increase stack pointer.
1576 static void emit_be_IncSP(const ir_node *node)
1578 int offs = be_get_IncSP_offset(node);
1584 ia32_emitf(node, "\tsubl $%u, %D0\n", offs);
1586 ia32_emitf(node, "\taddl $%u, %D0\n", -offs);
1591 * Emits code for Copy/CopyKeep.
1593 static void Copy_emitter(const ir_node *node, const ir_node *op)
1595 const arch_register_t *in = arch_get_irn_register(op);
1596 const arch_register_t *out = arch_get_irn_register(node);
1601 if (is_unknown_reg(in))
1603 /* copies of vf nodes aren't real... */
1604 if (arch_register_get_class(in) == &ia32_reg_classes[CLASS_ia32_vfp])
1607 if (get_irn_mode(node) == mode_E) {
1608 ia32_emitf(node, "\tmovsd %R, %R\n", in, out);
1610 ia32_emitf(node, "\tmovl %R, %R\n", in, out);
1614 static void emit_be_Copy(const ir_node *node)
1616 Copy_emitter(node, be_get_Copy_op(node));
1619 static void emit_be_CopyKeep(const ir_node *node)
1621 Copy_emitter(node, be_get_CopyKeep_op(node));
1625 * Emits code for exchange.
1627 static void emit_be_Perm(const ir_node *node)
1629 const arch_register_t *in0, *in1;
1630 const arch_register_class_t *cls0, *cls1;
1632 in0 = arch_get_irn_register(get_irn_n(node, 0));
1633 in1 = arch_get_irn_register(get_irn_n(node, 1));
1635 cls0 = arch_register_get_class(in0);
1636 cls1 = arch_register_get_class(in1);
1638 assert(cls0 == cls1 && "Register class mismatch at Perm");
1640 if (cls0 == &ia32_reg_classes[CLASS_ia32_gp]) {
1641 ia32_emitf(node, "\txchg %R, %R\n", in1, in0);
1642 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_xmm]) {
1643 ia32_emitf(NULL, "\txorpd %R, %R\n", in1, in0);
1644 ia32_emitf(NULL, "\txorpd %R, %R\n", in0, in1);
1645 ia32_emitf(node, "\txorpd %R, %R\n", in1, in0);
1646 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_vfp]) {
1648 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_st]) {
1651 panic("unexpected register class in be_Perm (%+F)", node);
1656 * Emits code for Constant loading.
1658 static void emit_ia32_Const(const ir_node *node)
1660 ia32_emitf(node, "\tmovl %I, %D0\n");
1664 * Emits code to load the TLS base
1666 static void emit_ia32_LdTls(const ir_node *node)
1668 ia32_emitf(node, "\tmovl %%gs:0, %D0\n");
1671 /* helper function for emit_ia32_Minus64Bit */
1672 static void emit_mov(const ir_node* node, const arch_register_t *src, const arch_register_t *dst)
1674 ia32_emitf(node, "\tmovl %R, %R\n", src, dst);
1677 /* helper function for emit_ia32_Minus64Bit */
1678 static void emit_neg(const ir_node* node, const arch_register_t *reg)
1680 ia32_emitf(node, "\tnegl %R\n", reg);
1683 /* helper function for emit_ia32_Minus64Bit */
1684 static void emit_sbb0(const ir_node* node, const arch_register_t *reg)
1686 ia32_emitf(node, "\tsbbl $0, %R\n", reg);
1689 /* helper function for emit_ia32_Minus64Bit */
1690 static void emit_sbb(const ir_node* node, const arch_register_t *src, const arch_register_t *dst)
1692 ia32_emitf(node, "\tsbbl %R, %R\n", src, dst);
1695 /* helper function for emit_ia32_Minus64Bit */
1696 static void emit_xchg(const ir_node* node, const arch_register_t *src, const arch_register_t *dst)
1698 ia32_emitf(node, "\txchgl %R, %R\n", src, dst);
1701 /* helper function for emit_ia32_Minus64Bit */
1702 static void emit_zero(const ir_node* node, const arch_register_t *reg)
1704 ia32_emitf(node, "\txorl %R, %R\n", reg, reg);
1707 static void emit_ia32_Minus64Bit(const ir_node *node)
1709 const arch_register_t *in_lo = get_in_reg(node, 0);
1710 const arch_register_t *in_hi = get_in_reg(node, 1);
1711 const arch_register_t *out_lo = get_out_reg(node, 0);
1712 const arch_register_t *out_hi = get_out_reg(node, 1);
1714 if (out_lo == in_lo) {
1715 if (out_hi != in_hi) {
1716 /* a -> a, b -> d */
1719 /* a -> a, b -> b */
1722 } else if (out_lo == in_hi) {
1723 if (out_hi == in_lo) {
1724 /* a -> b, b -> a */
1725 emit_xchg(node, in_lo, in_hi);
1728 /* a -> b, b -> d */
1729 emit_mov(node, in_hi, out_hi);
1730 emit_mov(node, in_lo, out_lo);
1734 if (out_hi == in_lo) {
1735 /* a -> c, b -> a */
1736 emit_mov(node, in_lo, out_lo);
1738 } else if (out_hi == in_hi) {
1739 /* a -> c, b -> b */
1740 emit_mov(node, in_lo, out_lo);
1743 /* a -> c, b -> d */
1744 emit_mov(node, in_lo, out_lo);
1750 emit_neg( node, out_hi);
1751 emit_neg( node, out_lo);
1752 emit_sbb0(node, out_hi);
1756 emit_zero(node, out_hi);
1757 emit_neg( node, out_lo);
1758 emit_sbb( node, in_hi, out_hi);
1761 static void emit_ia32_GetEIP(const ir_node *node)
1763 ia32_emitf(node, "\tcall %s\n", pic_base_label);
1764 ia32_emitf(NULL, "%s:\n", pic_base_label);
1765 ia32_emitf(node, "\tpopl %D0\n");
1768 static void emit_ia32_ClimbFrame(const ir_node *node)
1770 const ia32_climbframe_attr_t *attr = get_ia32_climbframe_attr_const(node);
1772 ia32_emitf(node, "\tmovl %S0, %D0\n");
1773 ia32_emitf(node, "\tmovl $%u, %S1\n", attr->count);
1774 ia32_emitf(NULL, BLOCK_PREFIX "%ld:\n", get_irn_node_nr(node));
1775 ia32_emitf(node, "\tmovl (%D0), %D0\n");
1776 ia32_emitf(node, "\tdec %S1\n");
1777 ia32_emitf(node, "\tjnz " BLOCK_PREFIX "%ld\n", get_irn_node_nr(node));
1780 static void emit_be_Return(const ir_node *node)
1782 unsigned pop = be_Return_get_pop(node);
1784 if (pop > 0 || be_Return_get_emit_pop(node)) {
1785 ia32_emitf(node, "\tret $%u\n", pop);
1787 ia32_emitf(node, "\tret\n");
1791 static void emit_Nothing(const ir_node *node)
1797 /***********************************************************************************
1800 * _ __ ___ __ _ _ _ __ | |_ _ __ __ _ _ __ ___ _____ _____ _ __| | __
1801 * | '_ ` _ \ / _` | | '_ \ | _| '__/ _` | '_ ` _ \ / _ \ \ /\ / / _ \| '__| |/ /
1802 * | | | | | | (_| | | | | | | | | | | (_| | | | | | | __/\ V V / (_) | | | <
1803 * |_| |_| |_|\__,_|_|_| |_| |_| |_| \__,_|_| |_| |_|\___| \_/\_/ \___/|_| |_|\_\
1805 ***********************************************************************************/
1808 * Enters the emitter functions for handled nodes into the generic
1809 * pointer of an opcode.
1811 static void ia32_register_emitters(void)
1813 #define IA32_EMIT2(a,b) op_ia32_##a->ops.generic = (op_func)emit_ia32_##b
1814 #define IA32_EMIT(a) IA32_EMIT2(a,a)
1815 #define EMIT(a) op_##a->ops.generic = (op_func)emit_##a
1816 #define IGN(a) op_##a->ops.generic = (op_func)emit_Nothing
1817 #define BE_EMIT(a) op_be_##a->ops.generic = (op_func)emit_be_##a
1818 #define BE_IGN(a) op_be_##a->ops.generic = (op_func)emit_Nothing
1820 /* first clear the generic function pointer for all ops */
1821 clear_irp_opcodes_generic_func();
1823 /* register all emitter functions defined in spec */
1824 ia32_register_spec_emitters();
1826 /* other ia32 emitter functions */
1827 IA32_EMIT2(Conv_I2I8Bit, Conv_I2I);
1832 IA32_EMIT(Conv_FP2FP);
1833 IA32_EMIT(Conv_FP2I);
1834 IA32_EMIT(Conv_I2FP);
1835 IA32_EMIT(Conv_I2I);
1842 IA32_EMIT(Minus64Bit);
1843 IA32_EMIT(SwitchJmp);
1844 IA32_EMIT(ClimbFrame);
1846 /* benode emitter */
1869 typedef void (*emit_func_ptr) (const ir_node *);
1872 * Assign and emit an exception label if the current instruction can fail.
1874 static void ia32_assign_exc_label(ir_node *node)
1876 /* assign a new ID to the instruction */
1877 set_ia32_exc_label_id(node, ++exc_label_id);
1879 ia32_emit_exc_label(node);
1881 be_emit_pad_comment();
1882 be_emit_cstring("/* exception to Block ");
1883 ia32_emit_cfop_target(node);
1884 be_emit_cstring(" */\n");
1885 be_emit_write_line();
1889 * Emits code for a node.
1891 static void ia32_emit_node(ir_node *node)
1893 ir_op *op = get_irn_op(node);
1895 DBG((dbg, LEVEL_1, "emitting code for %+F\n", node));
1897 if (is_ia32_irn(node)) {
1898 if (get_ia32_exc_label(node)) {
1899 /* emit the exception label of this instruction */
1900 ia32_assign_exc_label(node);
1902 if (mark_spill_reload) {
1903 if (is_ia32_is_spill(node)) {
1904 ia32_emitf(NULL, "\txchg %ebx, %ebx /* spill mark */\n");
1906 if (is_ia32_is_reload(node)) {
1907 ia32_emitf(NULL, "\txchg %edx, %edx /* reload mark */\n");
1909 if (is_ia32_is_remat(node)) {
1910 ia32_emitf(NULL, "\txchg %ecx, %ecx /* remat mark */\n");
1914 if (op->ops.generic) {
1915 emit_func_ptr func = (emit_func_ptr) op->ops.generic;
1917 be_dbg_set_dbg_info(get_irn_dbg_info(node));
1922 ir_fprintf(stderr, "Error: No emit handler for node %+F (%+G, graph %+F)\n", node, node, current_ir_graph);
1928 * Emits gas alignment directives
1930 static void ia32_emit_alignment(unsigned align, unsigned skip)
1932 ia32_emitf(NULL, "\t.p2align %u,,%u\n", align, skip);
1936 * Emits gas alignment directives for Labels depended on cpu architecture.
1938 static void ia32_emit_align_label(void)
1940 unsigned align = ia32_cg_config.label_alignment;
1941 unsigned maximum_skip = ia32_cg_config.label_alignment_max_skip;
1942 ia32_emit_alignment(align, maximum_skip);
1946 * Test whether a block should be aligned.
1947 * For cpus in the P4/Athlon class it is useful to align jump labels to
1948 * 16 bytes. However we should only do that if the alignment nops before the
1949 * label aren't executed more often than we have jumps to the label.
1951 static int should_align_block(const ir_node *block)
1953 static const double DELTA = .0001;
1954 ir_exec_freq *exec_freq = cg->birg->exec_freq;
1955 ir_node *prev = get_prev_block_sched(block);
1957 double prev_freq = 0; /**< execfreq of the fallthrough block */
1958 double jmp_freq = 0; /**< execfreq of all non-fallthrough blocks */
1961 if (exec_freq == NULL)
1963 if (ia32_cg_config.label_alignment_factor <= 0)
1966 block_freq = get_block_execfreq(exec_freq, block);
1967 if (block_freq < DELTA)
1970 n_cfgpreds = get_Block_n_cfgpreds(block);
1971 for(i = 0; i < n_cfgpreds; ++i) {
1972 const ir_node *pred = get_Block_cfgpred_block(block, i);
1973 double pred_freq = get_block_execfreq(exec_freq, pred);
1976 prev_freq += pred_freq;
1978 jmp_freq += pred_freq;
1982 if (prev_freq < DELTA && !(jmp_freq < DELTA))
1985 jmp_freq /= prev_freq;
1987 return jmp_freq > ia32_cg_config.label_alignment_factor;
1991 * Emit the block header for a block.
1993 * @param block the block
1994 * @param prev_block the previous block
1996 static void ia32_emit_block_header(ir_node *block)
1998 ir_graph *irg = current_ir_graph;
1999 int need_label = block_needs_label(block);
2001 ir_exec_freq *exec_freq = cg->birg->exec_freq;
2003 if (block == get_irg_end_block(irg))
2006 if (ia32_cg_config.label_alignment > 0) {
2007 /* align the current block if:
2008 * a) if should be aligned due to its execution frequency
2009 * b) there is no fall-through here
2011 if (should_align_block(block)) {
2012 ia32_emit_align_label();
2014 /* if the predecessor block has no fall-through,
2015 we can always align the label. */
2017 int has_fallthrough = 0;
2019 for (i = get_Block_n_cfgpreds(block) - 1; i >= 0; --i) {
2020 ir_node *cfg_pred = get_Block_cfgpred(block, i);
2021 if (can_be_fallthrough(cfg_pred)) {
2022 has_fallthrough = 1;
2027 if (!has_fallthrough)
2028 ia32_emit_align_label();
2032 if (need_label || has_Block_label(block)) {
2033 ia32_emit_block_name(block);
2036 be_emit_pad_comment();
2037 be_emit_cstring(" /* ");
2039 be_emit_cstring("\t/* ");
2040 ia32_emit_block_name(block);
2041 be_emit_cstring(": ");
2044 be_emit_cstring("preds:");
2046 /* emit list of pred blocks in comment */
2047 arity = get_irn_arity(block);
2049 be_emit_cstring(" none");
2051 for (i = 0; i < arity; ++i) {
2052 ir_node *predblock = get_Block_cfgpred_block(block, i);
2053 be_emit_irprintf(" %d", get_irn_node_nr(predblock));
2056 if (exec_freq != NULL) {
2057 be_emit_irprintf(", freq: %f",
2058 get_block_execfreq(exec_freq, block));
2060 be_emit_cstring(" */\n");
2061 be_emit_write_line();
2065 * Walks over the nodes in a block connected by scheduling edges
2066 * and emits code for each node.
2068 static void ia32_gen_block(ir_node *block)
2072 ia32_emit_block_header(block);
2074 /* emit the contents of the block */
2075 be_dbg_set_dbg_info(get_irn_dbg_info(block));
2076 sched_foreach(block, node) {
2077 ia32_emit_node(node);
2081 typedef struct exc_entry {
2082 ir_node *exc_instr; /** The instruction that can issue an exception. */
2083 ir_node *block; /** The block to call then. */
2088 * Sets labels for control flow nodes (jump target).
2089 * Links control predecessors to there destination blocks.
2091 static void ia32_gen_labels(ir_node *block, void *data)
2093 exc_entry **exc_list = data;
2097 for (n = get_Block_n_cfgpreds(block) - 1; n >= 0; --n) {
2098 pred = get_Block_cfgpred(block, n);
2099 set_irn_link(pred, block);
2101 pred = skip_Proj(pred);
2102 if (is_ia32_irn(pred) && get_ia32_exc_label(pred)) {
2107 ARR_APP1(exc_entry, *exc_list, e);
2108 set_irn_link(pred, block);
2114 * Compare two exception_entries.
2116 static int cmp_exc_entry(const void *a, const void *b)
2118 const exc_entry *ea = a;
2119 const exc_entry *eb = b;
2121 if (get_ia32_exc_label_id(ea->exc_instr) < get_ia32_exc_label_id(eb->exc_instr))
2127 * Main driver. Emits the code for one routine.
2129 void ia32_gen_routine(ia32_code_gen_t *ia32_cg, ir_graph *irg)
2131 ir_entity *entity = get_irg_entity(irg);
2132 exc_entry *exc_list = NEW_ARR_F(exc_entry, 0);
2137 do_pic = cg->birg->main_env->options->pic;
2139 ia32_register_emitters();
2141 get_unique_label(pic_base_label, sizeof(pic_base_label), ".PIC_BASE");
2143 be_dbg_method_begin(entity, be_abi_get_stack_layout(cg->birg->abi));
2144 be_gas_emit_function_prolog(entity, ia32_cg_config.function_alignment);
2146 /* we use links to point to target blocks */
2147 ir_reserve_resources(irg, IR_RESOURCE_IRN_LINK);
2148 irg_block_walk_graph(irg, ia32_gen_labels, NULL, &exc_list);
2150 /* initialize next block links */
2151 n = ARR_LEN(cg->blk_sched);
2152 for (i = 0; i < n; ++i) {
2153 ir_node *block = cg->blk_sched[i];
2154 ir_node *prev = i > 0 ? cg->blk_sched[i-1] : NULL;
2156 set_irn_link(block, prev);
2159 for (i = 0; i < n; ++i) {
2160 ir_node *block = cg->blk_sched[i];
2162 ia32_gen_block(block);
2165 be_gas_emit_function_epilog(entity);
2166 be_dbg_method_end();
2168 be_emit_write_line();
2170 ir_free_resources(irg, IR_RESOURCE_IRN_LINK);
2172 /* Sort the exception table using the exception label id's.
2173 Those are ascending with ascending addresses. */
2174 qsort(exc_list, ARR_LEN(exc_list), sizeof(exc_list[0]), cmp_exc_entry);
2178 for (i = 0; i < ARR_LEN(exc_list); ++i) {
2179 be_emit_cstring("\t.long ");
2180 ia32_emit_exc_label(exc_list[i].exc_instr);
2182 be_emit_cstring("\t.long ");
2183 ia32_emit_block_name(exc_list[i].block);
2187 DEL_ARR_F(exc_list);
2190 static const lc_opt_table_entry_t ia32_emitter_options[] = {
2191 LC_OPT_ENT_BOOL("mark_spill_reload", "mark spills and reloads with ud opcodes", &mark_spill_reload),
2195 void ia32_init_emitter(void)
2197 lc_opt_entry_t *be_grp;
2198 lc_opt_entry_t *ia32_grp;
2200 be_grp = lc_opt_get_grp(firm_opt_get_root(), "be");
2201 ia32_grp = lc_opt_get_grp(be_grp, "ia32");
2203 lc_opt_add_table(ia32_grp, ia32_emitter_options);
2205 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.emitter");