2 * Copyright (C) 1995-2011 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This file implements the ia32 node emitter.
23 * @author Christian Wuerdig, Matthias Braun
26 * Summary table for x86 floatingpoint compares:
27 * (remember effect of unordered on x86: ZF=1, PF=1, CF=1)
35 * pnc_Leg => NP (ordered)
57 #include "iredges_t.h"
61 #include "raw_bitset.h"
65 #include "../besched.h"
66 #include "../benode.h"
68 #include "../be_dbgout.h"
69 #include "../beemitter.h"
70 #include "../begnuas.h"
72 #include "../be_dbgout.h"
74 #include "ia32_emitter.h"
75 #include "ia32_common_transform.h"
76 #include "gen_ia32_emitter.h"
77 #include "gen_ia32_regalloc_if.h"
78 #include "ia32_nodes_attr.h"
79 #include "ia32_new_nodes.h"
80 #include "ia32_architecture.h"
81 #include "bearch_ia32_t.h"
83 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
85 #define SNPRINTF_BUF_LEN 128
87 static const ia32_isa_t *isa;
88 static char pic_base_label[128];
89 static ir_label_t exc_label_id;
90 static int mark_spill_reload = 0;
93 /** Return the next block in Block schedule */
94 static ir_node *get_prev_block_sched(const ir_node *block)
96 return (ir_node*)get_irn_link(block);
99 /** Checks if the current block is a fall-through target. */
100 static int is_fallthrough(const ir_node *cfgpred)
104 if (!is_Proj(cfgpred))
106 pred = get_Proj_pred(cfgpred);
107 if (is_ia32_SwitchJmp(pred))
114 * returns non-zero if the given block needs a label
115 * because of being a jump-target (and not a fall-through)
117 static int block_needs_label(const ir_node *block)
120 int n_cfgpreds = get_Block_n_cfgpreds(block);
122 if (has_Block_entity(block))
125 if (n_cfgpreds == 0) {
127 } else if (n_cfgpreds == 1) {
128 ir_node *cfgpred = get_Block_cfgpred(block, 0);
129 ir_node *cfgpred_block = get_nodes_block(cfgpred);
131 if (get_prev_block_sched(block) == cfgpred_block
132 && is_fallthrough(cfgpred)) {
141 * Returns the register at in position pos.
143 static const arch_register_t *get_in_reg(const ir_node *irn, int pos)
146 const arch_register_t *reg = NULL;
148 assert(get_irn_arity(irn) > pos && "Invalid IN position");
150 /* The out register of the operator at position pos is the
151 in register we need. */
152 op = get_irn_n(irn, pos);
154 reg = arch_get_irn_register(op);
156 assert(reg && "no in register found");
158 if (reg == &ia32_registers[REG_GP_NOREG])
159 panic("trying to emit noreg for %+F input %d", irn, pos);
165 * Returns the register at out position pos.
167 static const arch_register_t *get_out_reg(const ir_node *irn, int pos)
170 const arch_register_t *reg = NULL;
172 /* 1st case: irn is not of mode_T, so it has only */
173 /* one OUT register -> good */
174 /* 2nd case: irn is of mode_T -> collect all Projs and ask the */
175 /* Proj with the corresponding projnum for the register */
177 if (get_irn_mode(irn) != mode_T) {
179 reg = arch_get_irn_register(irn);
180 } else if (is_ia32_irn(irn)) {
181 reg = arch_irn_get_register(irn, pos);
183 const ir_edge_t *edge;
185 foreach_out_edge(irn, edge) {
186 proj = get_edge_src_irn(edge);
187 assert(is_Proj(proj) && "non-Proj from mode_T node");
188 if (get_Proj_proj(proj) == pos) {
189 reg = arch_get_irn_register(proj);
195 assert(reg && "no out register found");
200 * Add a number to a prefix. This number will not be used a second time.
202 static char *get_unique_label(char *buf, size_t buflen, const char *prefix)
204 static unsigned long id = 0;
205 snprintf(buf, buflen, "%s%s%lu", be_gas_get_private_prefix(), prefix, ++id);
210 * Emit the name of the 8bit low register
212 static void emit_8bit_register(const arch_register_t *reg)
214 const char *reg_name = arch_register_get_name(reg);
215 assert(reg->index == REG_GP_EAX || reg->index == REG_GP_EBX
216 || reg->index == REG_GP_ECX || reg->index == REG_GP_EDX);
219 be_emit_char(reg_name[1]); /* get the basic name of the register */
224 * Emit the name of the 8bit high register
226 static void emit_8bit_register_high(const arch_register_t *reg)
228 const char *reg_name = arch_register_get_name(reg);
229 assert(reg->index == REG_GP_EAX || reg->index == REG_GP_EBX
230 || reg->index == REG_GP_ECX || reg->index == REG_GP_EDX);
233 be_emit_char(reg_name[1]); /* get the basic name of the register */
237 static void emit_16bit_register(const arch_register_t *reg)
239 const char *reg_name = arch_register_get_name(reg);
242 be_emit_string(reg_name+1); /* skip the 'e' prefix of the 32bit names */
246 * emit a register, possible shortened by a mode
248 * @param reg the register
249 * @param mode the mode of the register or NULL for full register
251 static void emit_register(const arch_register_t *reg, const ir_mode *mode)
253 const char *reg_name;
256 int size = get_mode_size_bits(mode);
258 case 8: emit_8bit_register(reg); return;
259 case 16: emit_16bit_register(reg); return;
261 assert(mode_is_float(mode) || size == 32);
264 reg_name = arch_register_get_name(reg);
267 be_emit_string(reg_name);
270 void ia32_emit_source_register(const ir_node *node, int pos)
272 const arch_register_t *reg = get_in_reg(node, pos);
274 emit_register(reg, NULL);
277 static void ia32_emit_entity(ir_entity *entity, int no_pic_adjust)
279 be_gas_emit_entity(entity);
281 if (get_entity_owner(entity) == get_tls_type()) {
282 if (get_entity_visibility(entity) == ir_visibility_external) {
283 be_emit_cstring("@INDNTPOFF");
285 be_emit_cstring("@NTPOFF");
289 if (do_pic && !no_pic_adjust) {
291 be_emit_string(pic_base_label);
295 static void emit_ia32_Immediate_no_prefix(const ir_node *node)
297 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(node);
299 if (attr->symconst != NULL) {
302 ia32_emit_entity(attr->symconst, attr->no_pic_adjust);
304 if (attr->symconst == NULL || attr->offset != 0) {
305 if (attr->symconst != NULL) {
306 be_emit_irprintf("%+d", attr->offset);
308 be_emit_irprintf("0x%X", attr->offset);
313 static void emit_ia32_Immediate(const ir_node *node)
316 emit_ia32_Immediate_no_prefix(node);
319 void ia32_emit_8bit_source_register_or_immediate(const ir_node *node, int pos)
321 const arch_register_t *reg;
322 const ir_node *in = get_irn_n(node, pos);
323 if (is_ia32_Immediate(in)) {
324 emit_ia32_Immediate(in);
328 reg = get_in_reg(node, pos);
329 emit_8bit_register(reg);
332 void ia32_emit_8bit_high_source_register(const ir_node *node, int pos)
334 const arch_register_t *reg = get_in_reg(node, pos);
335 emit_8bit_register_high(reg);
338 void ia32_emit_16bit_source_register_or_immediate(const ir_node *node, int pos)
340 const arch_register_t *reg;
341 const ir_node *in = get_irn_n(node, pos);
342 if (is_ia32_Immediate(in)) {
343 emit_ia32_Immediate(in);
347 reg = get_in_reg(node, pos);
348 emit_16bit_register(reg);
351 void ia32_emit_dest_register(const ir_node *node, int pos)
353 const arch_register_t *reg = get_out_reg(node, pos);
355 emit_register(reg, NULL);
358 void ia32_emit_dest_register_size(const ir_node *node, int pos)
360 const arch_register_t *reg = get_out_reg(node, pos);
362 emit_register(reg, get_ia32_ls_mode(node));
365 void ia32_emit_8bit_dest_register(const ir_node *node, int pos)
367 const arch_register_t *reg = get_out_reg(node, pos);
369 emit_register(reg, mode_Bu);
372 void ia32_emit_x87_register(const ir_node *node, int pos)
374 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
378 be_emit_string(attr->x87[pos]->name);
381 static void ia32_emit_mode_suffix_mode(const ir_mode *mode)
383 assert(mode_is_int(mode) || mode_is_reference(mode));
384 switch (get_mode_size_bits(mode)) {
385 case 8: be_emit_char('b'); return;
386 case 16: be_emit_char('w'); return;
387 case 32: be_emit_char('l'); return;
388 /* gas docu says q is the suffix but gcc, objdump and icc use ll
390 case 64: be_emit_cstring("ll"); return;
392 panic("Can't output mode_suffix for %+F", mode);
395 void ia32_emit_mode_suffix(const ir_node *node)
397 ir_mode *mode = get_ia32_ls_mode(node);
401 ia32_emit_mode_suffix_mode(mode);
404 void ia32_emit_x87_mode_suffix(const ir_node *node)
408 /* we only need to emit the mode on address mode */
409 if (get_ia32_op_type(node) == ia32_Normal)
412 mode = get_ia32_ls_mode(node);
413 assert(mode != NULL);
415 if (mode_is_float(mode)) {
416 switch (get_mode_size_bits(mode)) {
417 case 32: be_emit_char('s'); return;
418 case 64: be_emit_char('l'); return;
419 /* long doubles have different sizes due to alignment on different
423 case 128: be_emit_char('t'); return;
426 assert(mode_is_int(mode) || mode_is_reference(mode));
427 switch (get_mode_size_bits(mode)) {
428 case 16: be_emit_char('s'); return;
429 case 32: be_emit_char('l'); return;
430 /* gas docu says q is the suffix but gcc, objdump and icc use ll
432 case 64: be_emit_cstring("ll"); return;
435 panic("Can't output mode_suffix for %+F", mode);
438 static char get_xmm_mode_suffix(ir_mode *mode)
440 assert(mode_is_float(mode));
441 switch (get_mode_size_bits(mode)) {
444 default: panic("Invalid XMM mode");
448 void ia32_emit_xmm_mode_suffix(const ir_node *node)
450 ir_mode *mode = get_ia32_ls_mode(node);
451 assert(mode != NULL);
453 be_emit_char(get_xmm_mode_suffix(mode));
456 void ia32_emit_xmm_mode_suffix_s(const ir_node *node)
458 ir_mode *mode = get_ia32_ls_mode(node);
459 assert(mode != NULL);
460 be_emit_char(get_xmm_mode_suffix(mode));
463 void ia32_emit_extend_suffix(const ir_node *node)
465 ir_mode *mode = get_ia32_ls_mode(node);
466 if (get_mode_size_bits(mode) == 32)
468 be_emit_char(mode_is_signed(mode) ? 's' : 'z');
469 ia32_emit_mode_suffix_mode(mode);
472 void ia32_emit_source_register_or_immediate(const ir_node *node, int pos)
474 ir_node *in = get_irn_n(node, pos);
475 if (is_ia32_Immediate(in)) {
476 emit_ia32_Immediate(in);
478 const ir_mode *mode = get_ia32_ls_mode(node);
479 const arch_register_t *reg = get_in_reg(node, pos);
480 emit_register(reg, mode);
485 * Returns the target block for a control flow node.
487 static ir_node *get_cfop_target_block(const ir_node *irn)
489 assert(get_irn_mode(irn) == mode_X);
490 return (ir_node*)get_irn_link(irn);
494 * Emits the target label for a control flow node.
496 static void ia32_emit_cfop_target(const ir_node *node)
498 ir_node *block = get_cfop_target_block(node);
499 be_gas_emit_block_name(block);
503 * Emit the suffix for a compare instruction.
505 static void ia32_emit_condition_code(ia32_condition_code_t cc)
508 case ia32_cc_overflow: be_emit_cstring("o"); return;
509 case ia32_cc_not_overflow: be_emit_cstring("no"); return;
510 case ia32_cc_float_below:
511 case ia32_cc_float_unordered_below:
512 case ia32_cc_below: be_emit_cstring("b"); return;
513 case ia32_cc_float_above_equal:
514 case ia32_cc_float_unordered_above_equal:
515 case ia32_cc_above_equal: be_emit_cstring("ae"); return;
516 case ia32_cc_float_equal:
517 case ia32_cc_equal: be_emit_cstring("e"); return;
518 case ia32_cc_float_not_equal:
519 case ia32_cc_not_equal: be_emit_cstring("ne"); return;
520 case ia32_cc_float_below_equal:
521 case ia32_cc_float_unordered_below_equal:
522 case ia32_cc_below_equal: be_emit_cstring("be"); return;
523 case ia32_cc_float_above:
524 case ia32_cc_float_unordered_above:
525 case ia32_cc_above: be_emit_cstring("a"); return;
526 case ia32_cc_sign: be_emit_cstring("s"); return;
527 case ia32_cc_not_sign: be_emit_cstring("ns"); return;
528 case ia32_cc_parity: be_emit_cstring("p"); return;
529 case ia32_cc_not_parity: be_emit_cstring("np"); return;
530 case ia32_cc_less: be_emit_cstring("l"); return;
531 case ia32_cc_greater_equal: be_emit_cstring("ge"); return;
532 case ia32_cc_less_equal: be_emit_cstring("le"); return;
533 case ia32_cc_greater: be_emit_cstring("g"); return;
534 case ia32_cc_float_parity_cases:
535 case ia32_cc_additional_float_cases:
538 panic("Invalid ia32 condition code");
541 typedef enum ia32_emit_mod_t {
543 EMIT_RESPECT_LS = 1U << 0,
544 EMIT_ALTERNATE_AM = 1U << 1,
546 EMIT_HIGH_REG = 1U << 3,
547 EMIT_LOW_REG = 1U << 4
549 ENUM_BITSET(ia32_emit_mod_t)
552 * Emits address mode.
554 void ia32_emit_am(const ir_node *node)
556 ir_entity *ent = get_ia32_am_sc(node);
557 int offs = get_ia32_am_offs_int(node);
558 ir_node *base = get_irn_n(node, n_ia32_base);
559 int has_base = !is_ia32_NoReg_GP(base);
560 ir_node *idx = get_irn_n(node, n_ia32_index);
561 int has_index = !is_ia32_NoReg_GP(idx);
563 /* just to be sure... */
564 assert(!is_ia32_use_frame(node) || get_ia32_frame_ent(node) != NULL);
566 if (get_ia32_am_tls_segment(node))
567 be_emit_cstring("%gs:");
571 const ia32_attr_t *attr = get_ia32_attr_const(node);
572 if (is_ia32_am_sc_sign(node))
574 ia32_emit_entity(ent, attr->data.am_sc_no_pic_adjust);
577 /* also handle special case if nothing is set */
578 if (offs != 0 || (ent == NULL && !has_base && !has_index)) {
580 be_emit_irprintf("%+d", offs);
582 be_emit_irprintf("%d", offs);
586 if (has_base || has_index) {
591 const arch_register_t *reg = get_in_reg(node, n_ia32_base);
592 emit_register(reg, NULL);
595 /* emit index + scale */
597 const arch_register_t *reg = get_in_reg(node, n_ia32_index);
600 emit_register(reg, NULL);
602 scale = get_ia32_am_scale(node);
604 be_emit_irprintf(",%d", 1 << scale);
612 * fmt parameter output
613 * ---- ---------------------- ---------------------------------------------
615 * %AM <node> address mode of the node
616 * %AR const arch_register_t* address mode of the node or register
617 * %ASx <node> address mode of the node or source register x
618 * %Dx <node> destination register x
619 * %I <node> immediate of the node
620 * %L <node> control flow target of the node
621 * %M <node> mode suffix of the node
622 * %P int condition code
623 * %R const arch_register_t* register
624 * %Sx <node> source register x
625 * %s const char* string
626 * %u unsigned int unsigned int
627 * %d signed int signed int
630 * # modifier for %ASx, %D, %R, and %S uses ls mode of node to alter register width
631 * * modifier does not prefix immediates with $, but AM with *
632 * l modifier for %lu and %ld
633 * > modifier to output high 8bit register (ah, bh)
634 * < modifier to output low 8bit register (al, bl)
636 static void ia32_emitf(const ir_node *node, const char *fmt, ...)
642 const char *start = fmt;
643 ia32_emit_mod_t mod = EMIT_NONE;
645 while (*fmt != '%' && *fmt != '\n' && *fmt != '\0')
648 be_emit_string_len(start, fmt - start);
652 be_emit_finish_line_gas(node);
665 case '*': mod |= EMIT_ALTERNATE_AM; break;
666 case '#': mod |= EMIT_RESPECT_LS; break;
667 case 'l': mod |= EMIT_LONG; break;
668 case '>': mod |= EMIT_HIGH_REG; break;
669 case '<': mod |= EMIT_LOW_REG; break;
678 arch_register_t const *reg;
689 if (mod & EMIT_ALTERNATE_AM)
695 reg = va_arg(ap, const arch_register_t*);
696 if (get_ia32_op_type(node) == ia32_AddrModeS) {
703 if (get_ia32_op_type(node) == ia32_AddrModeS) {
707 assert(get_ia32_op_type(node) == ia32_Normal);
711 default: goto unknown;
717 if (*fmt < '0' || '9' <= *fmt)
719 reg = get_out_reg(node, *fmt++ - '0');
725 if (!(mod & EMIT_ALTERNATE_AM))
727 emit_ia32_Immediate_no_prefix(imm);
731 ia32_emit_cfop_target(node);
735 ia32_emit_mode_suffix_mode(get_ia32_ls_mode(node));
739 ia32_condition_code_t cc = va_arg(ap, ia32_condition_code_t);
740 ia32_emit_condition_code(cc);
745 reg = va_arg(ap, const arch_register_t*);
747 if (mod & EMIT_ALTERNATE_AM)
749 if (mod & EMIT_HIGH_REG) {
750 emit_8bit_register_high(reg);
751 } else if (mod & EMIT_LOW_REG) {
752 emit_8bit_register(reg);
754 emit_register(reg, mod & EMIT_RESPECT_LS ? get_ia32_ls_mode(node) : NULL);
762 if (*fmt < '0' || '9' <= *fmt)
766 imm = get_irn_n(node, pos);
767 if (is_ia32_Immediate(imm)) {
770 reg = get_in_reg(node, pos);
776 const char *str = va_arg(ap, const char*);
782 if (mod & EMIT_LONG) {
783 unsigned long num = va_arg(ap, unsigned long);
784 be_emit_irprintf("%lu", num);
786 unsigned num = va_arg(ap, unsigned);
787 be_emit_irprintf("%u", num);
792 if (mod & EMIT_LONG) {
793 long num = va_arg(ap, long);
794 be_emit_irprintf("%ld", num);
796 int num = va_arg(ap, int);
797 be_emit_irprintf("%d", num);
803 panic("unknown format conversion in ia32_emitf()");
811 * Emits registers and/or address mode of a binary operation.
813 void ia32_emit_binop(const ir_node *node)
815 if (is_ia32_Immediate(get_irn_n(node, n_ia32_binary_right))) {
816 ia32_emitf(node, "%#S4, %#AS3");
818 ia32_emitf(node, "%#AS4, %#S3");
823 * Emits registers and/or address mode of a binary operation.
825 void ia32_emit_x87_binop(const ir_node *node)
827 switch (get_ia32_op_type(node)) {
830 const ia32_x87_attr_t *x87_attr = get_ia32_x87_attr_const(node);
831 const arch_register_t *in1 = x87_attr->x87[0];
832 const arch_register_t *in = x87_attr->x87[1];
833 const arch_register_t *out = x87_attr->x87[2];
837 } else if (out == in) {
842 be_emit_string(arch_register_get_name(in));
843 be_emit_cstring(", %");
844 be_emit_string(arch_register_get_name(out));
852 assert(0 && "unsupported op type");
857 * Emits registers and/or address mode of a unary operation.
859 void ia32_emit_unop(const ir_node *node, int pos)
863 ia32_emitf(node, fmt);
866 static void emit_ia32_IMul(const ir_node *node)
868 ir_node *left = get_irn_n(node, n_ia32_IMul_left);
869 const arch_register_t *out_reg = get_out_reg(node, pn_ia32_IMul_res);
871 /* do we need the 3-address form? */
872 if (is_ia32_NoReg_GP(left) ||
873 get_in_reg(node, n_ia32_IMul_left) != out_reg) {
874 ia32_emitf(node, "\timul%M %#S4, %#AS3, %#D0\n");
876 ia32_emitf(node, "\timul%M %#AS4, %#S3\n");
881 * walks up a tree of copies/perms/spills/reloads to find the original value
882 * that is moved around
884 static ir_node *find_original_value(ir_node *node)
886 if (irn_visited(node))
889 mark_irn_visited(node);
890 if (be_is_Copy(node)) {
891 return find_original_value(be_get_Copy_op(node));
892 } else if (be_is_CopyKeep(node)) {
893 return find_original_value(be_get_CopyKeep_op(node));
894 } else if (is_Proj(node)) {
895 ir_node *pred = get_Proj_pred(node);
896 if (be_is_Perm(pred)) {
897 return find_original_value(get_irn_n(pred, get_Proj_proj(node)));
898 } else if (be_is_MemPerm(pred)) {
899 return find_original_value(get_irn_n(pred, get_Proj_proj(node) + 1));
900 } else if (is_ia32_Load(pred)) {
901 return find_original_value(get_irn_n(pred, n_ia32_Load_mem));
905 } else if (is_ia32_Store(node)) {
906 return find_original_value(get_irn_n(node, n_ia32_Store_val));
907 } else if (is_Phi(node)) {
909 arity = get_irn_arity(node);
910 for (i = 0; i < arity; ++i) {
911 ir_node *in = get_irn_n(node, i);
912 ir_node *res = find_original_value(in);
923 static int determine_final_cc(const ir_node *node, int flags_pos, int cc)
925 ir_node *flags = get_irn_n(node, flags_pos);
926 const ia32_attr_t *flags_attr;
927 flags = skip_Proj(flags);
929 if (is_ia32_Sahf(flags)) {
930 ir_node *cmp = get_irn_n(flags, n_ia32_Sahf_val);
931 if (!(is_ia32_FucomFnstsw(cmp) || is_ia32_FucompFnstsw(cmp)
932 || is_ia32_FucomppFnstsw(cmp) || is_ia32_FtstFnstsw(cmp))) {
933 inc_irg_visited(current_ir_graph);
934 cmp = find_original_value(cmp);
936 assert(is_ia32_FucomFnstsw(cmp) || is_ia32_FucompFnstsw(cmp)
937 || is_ia32_FucomppFnstsw(cmp) || is_ia32_FtstFnstsw(cmp));
940 flags_attr = get_ia32_attr_const(cmp);
942 flags_attr = get_ia32_attr_const(flags);
945 if (flags_attr->data.ins_permuted)
946 cc = ia32_invert_condition_code(cc);
950 void ia32_emit_cmp_suffix_node(const ir_node *node, int flags_pos)
952 ia32_condition_code_t cc = get_ia32_condcode(node);
953 cc = determine_final_cc(node, flags_pos, cc);
955 ia32_emit_condition_code(cc);
959 * Emits an exception label for a given node.
961 static void ia32_emit_exc_label(const ir_node *node)
963 be_emit_string(be_gas_insn_label_prefix());
964 be_emit_irprintf("%lu", get_ia32_exc_label_id(node));
968 * Returns the Proj with projection number proj and NOT mode_M
970 static ir_node *get_proj(const ir_node *node, long proj)
972 const ir_edge_t *edge;
975 assert(get_irn_mode(node) == mode_T && "expected mode_T node");
977 foreach_out_edge(node, edge) {
978 src = get_edge_src_irn(edge);
980 assert(is_Proj(src) && "Proj expected");
981 if (get_irn_mode(src) == mode_M)
984 if (get_Proj_proj(src) == proj)
990 static int can_be_fallthrough(const ir_node *node)
992 ir_node *target_block = get_cfop_target_block(node);
993 ir_node *block = get_nodes_block(node);
994 return get_prev_block_sched(target_block) == block;
998 * Emits the jump sequence for a conditional jump (cmp + jmp_true + jmp_false)
1000 static void emit_ia32_Jcc(const ir_node *node)
1002 int need_parity_label = 0;
1003 ia32_condition_code_t cc = get_ia32_condcode(node);
1004 const ir_node *proj_true;
1005 const ir_node *proj_false;
1007 cc = determine_final_cc(node, 0, cc);
1009 /* get both Projs */
1010 proj_true = get_proj(node, pn_ia32_Jcc_true);
1011 assert(proj_true && "Jcc without true Proj");
1013 proj_false = get_proj(node, pn_ia32_Jcc_false);
1014 assert(proj_false && "Jcc without false Proj");
1016 if (can_be_fallthrough(proj_true)) {
1017 /* exchange both proj's so the second one can be omitted */
1018 const ir_node *t = proj_true;
1020 proj_true = proj_false;
1022 cc = ia32_negate_condition_code(cc);
1025 if (cc & ia32_cc_float_parity_cases) {
1026 /* Some floating point comparisons require a test of the parity flag,
1027 * which indicates that the result is unordered */
1028 if (cc & ia32_cc_negated) {
1029 ia32_emitf(proj_true, "\tjp %L\n");
1031 /* we need a local label if the false proj is a fallthrough
1032 * as the falseblock might have no label emitted then */
1033 if (can_be_fallthrough(proj_false)) {
1034 need_parity_label = 1;
1035 ia32_emitf(proj_false, "\tjp 1f\n");
1037 ia32_emitf(proj_false, "\tjp %L\n");
1041 ia32_emitf(proj_true, "\tj%P %L\n", cc);
1042 if (need_parity_label) {
1043 ia32_emitf(NULL, "1:\n");
1046 /* the second Proj might be a fallthrough */
1047 if (can_be_fallthrough(proj_false)) {
1048 ia32_emitf(proj_false, "\t/* fallthrough to %L */\n");
1050 ia32_emitf(proj_false, "\tjmp %L\n");
1055 * Emits an ia32 Setcc. This is mostly easy but some floating point compares
1058 static void emit_ia32_Setcc(const ir_node *node)
1060 const arch_register_t *dreg = get_out_reg(node, pn_ia32_Setcc_res);
1062 ia32_condition_code_t cc = get_ia32_condcode(node);
1063 cc = determine_final_cc(node, n_ia32_Setcc_eflags, cc);
1064 if (cc & ia32_cc_float_parity_cases) {
1065 if (cc & ia32_cc_negated) {
1066 ia32_emitf(node, "\tset%P %<R\n", cc, dreg);
1067 ia32_emitf(node, "\tsetp %>R\n", dreg);
1068 ia32_emitf(node, "\torb %>R, %<R\n", dreg, dreg);
1070 ia32_emitf(node, "\tset%P %<R\n", cc, dreg);
1071 ia32_emitf(node, "\tsetnp %>R\n", dreg);
1072 ia32_emitf(node, "\tandb %>R, %<R\n", dreg, dreg);
1075 ia32_emitf(node, "\tset%P %#R\n", cc, dreg);
1079 static void emit_ia32_CMovcc(const ir_node *node)
1081 const ia32_attr_t *attr = get_ia32_attr_const(node);
1082 const arch_register_t *out = arch_irn_get_register(node, pn_ia32_res);
1083 ia32_condition_code_t cc = get_ia32_condcode(node);
1084 const arch_register_t *in_true;
1085 const arch_register_t *in_false;
1087 cc = determine_final_cc(node, n_ia32_CMovcc_eflags, cc);
1088 /* although you can't set ins_permuted in the constructor it might still
1089 * be set by memory operand folding
1090 * Permuting inputs of a cmov means the condition is negated!
1092 if (attr->data.ins_permuted)
1093 cc = ia32_negate_condition_code(cc);
1095 in_true = arch_get_irn_register(get_irn_n(node, n_ia32_CMovcc_val_true));
1096 in_false = arch_get_irn_register(get_irn_n(node, n_ia32_CMovcc_val_false));
1098 /* should be same constraint fullfilled? */
1099 if (out == in_false) {
1100 /* yes -> nothing to do */
1101 } else if (out == in_true) {
1102 const arch_register_t *tmp;
1104 assert(get_ia32_op_type(node) == ia32_Normal);
1106 cc = ia32_negate_condition_code(cc);
1113 ia32_emitf(node, "\tmovl %R, %R\n", in_false, out);
1116 if (cc & ia32_cc_float_parity_cases) {
1117 panic("CMov with floatingpoint compare/parity not supported yet");
1120 ia32_emitf(node, "\tcmov%P %#AR, %#R\n", cc, in_true, out);
1124 * Emits code for a SwitchJmp
1126 static void emit_ia32_SwitchJmp(const ir_node *node)
1128 ir_entity *jump_table = get_ia32_am_sc(node);
1129 long default_pn = get_ia32_default_pn(node);
1131 ia32_emitf(node, "\tjmp *%AM\n", node);
1133 emit_jump_table(node, default_pn, jump_table, get_cfop_target_block);
1137 * Emits code for a unconditional jump.
1139 static void emit_ia32_Jmp(const ir_node *node)
1141 /* we have a block schedule */
1142 if (can_be_fallthrough(node)) {
1143 ia32_emitf(node, "\t/* fallthrough to %L */\n");
1145 ia32_emitf(node, "\tjmp %L\n");
1150 * Emit an inline assembler operand.
1152 * @param node the ia32_ASM node
1153 * @param s points to the operand (a %c)
1155 * @return pointer to the first char in s NOT in the current operand
1157 static const char* emit_asm_operand(const ir_node *node, const char *s)
1159 const ia32_attr_t *ia32_attr = get_ia32_attr_const(node);
1160 const ia32_asm_attr_t *attr = CONST_CAST_IA32_ATTR(ia32_asm_attr_t,
1162 const arch_register_t *reg;
1163 const ia32_asm_reg_t *asm_regs = attr->register_map;
1164 const ia32_asm_reg_t *asm_reg;
1173 /* parse modifiers */
1176 ir_fprintf(stderr, "Warning: asm text (%+F) ends with %%\n", node);
1201 "Warning: asm text (%+F) contains unknown modifier '%c' for asm op\n",
1208 if (sscanf(s, "%d%n", &num, &p) != 1) {
1209 ir_fprintf(stderr, "Warning: Couldn't parse assembler operand (%+F)\n",
1216 if (num < 0 || ARR_LEN(asm_regs) <= (size_t)num) {
1218 "Error: Custom assembler references invalid input/output (%+F)\n",
1222 asm_reg = & asm_regs[num];
1223 assert(asm_reg->valid);
1226 if (asm_reg->use_input == 0) {
1227 reg = get_out_reg(node, asm_reg->inout_pos);
1229 ir_node *pred = get_irn_n(node, asm_reg->inout_pos);
1231 /* might be an immediate value */
1232 if (is_ia32_Immediate(pred)) {
1233 emit_ia32_Immediate(pred);
1236 reg = get_in_reg(node, asm_reg->inout_pos);
1240 "Warning: no register assigned for %d asm op (%+F)\n",
1245 if (asm_reg->memory) {
1250 if (modifier != 0) {
1253 emit_8bit_register(reg);
1256 emit_8bit_register_high(reg);
1259 emit_16bit_register(reg);
1262 panic("Invalid asm op modifier");
1265 emit_register(reg, asm_reg->mode);
1268 if (asm_reg->memory) {
1276 * Emits code for an ASM pseudo op.
1278 static void emit_ia32_Asm(const ir_node *node)
1280 const void *gen_attr = get_irn_generic_attr_const(node);
1281 const ia32_asm_attr_t *attr
1282 = CONST_CAST_IA32_ATTR(ia32_asm_attr_t, gen_attr);
1283 ident *asm_text = attr->asm_text;
1284 const char *s = get_id_str(asm_text);
1286 ia32_emitf(node, "#APP\t\n");
1293 s = emit_asm_operand(node, s);
1299 ia32_emitf(NULL, "\n#NO_APP\n");
1304 * Emit movsb/w instructions to make mov count divideable by 4
1306 static void emit_CopyB_prolog(unsigned size)
1309 ia32_emitf(NULL, "\tmovsb\n");
1311 ia32_emitf(NULL, "\tmovsw\n");
1315 * Emit rep movsd instruction for memcopy.
1317 static void emit_ia32_CopyB(const ir_node *node)
1319 unsigned size = get_ia32_copyb_size(node);
1321 emit_CopyB_prolog(size);
1322 ia32_emitf(node, "\trep movsd\n");
1326 * Emits unrolled memcopy.
1328 static void emit_ia32_CopyB_i(const ir_node *node)
1330 unsigned size = get_ia32_copyb_size(node);
1332 emit_CopyB_prolog(size);
1336 ia32_emitf(NULL, "\tmovsd\n");
1342 * Emit code for conversions (I, FP), (FP, I) and (FP, FP).
1344 static void emit_ia32_Conv_with_FP(const ir_node *node, const char* conv_f,
1347 ir_mode *ls_mode = get_ia32_ls_mode(node);
1348 int ls_bits = get_mode_size_bits(ls_mode);
1349 const char *conv = ls_bits == 32 ? conv_f : conv_d;
1351 ia32_emitf(node, "\tcvt%s %AS3, %D0\n", conv);
1354 static void emit_ia32_Conv_I2FP(const ir_node *node)
1356 emit_ia32_Conv_with_FP(node, "si2ss", "si2sd");
1359 static void emit_ia32_Conv_FP2I(const ir_node *node)
1361 emit_ia32_Conv_with_FP(node, "ss2si", "sd2si");
1364 static void emit_ia32_Conv_FP2FP(const ir_node *node)
1366 emit_ia32_Conv_with_FP(node, "sd2ss", "ss2sd");
1370 * Emits code for an Int conversion.
1372 static void emit_ia32_Conv_I2I(const ir_node *node)
1374 ir_mode *smaller_mode = get_ia32_ls_mode(node);
1375 int signed_mode = mode_is_signed(smaller_mode);
1376 const char *sign_suffix;
1378 assert(!mode_is_float(smaller_mode));
1380 sign_suffix = signed_mode ? "s" : "z";
1381 ia32_emitf(node, "\tmov%s%Ml %#AS3, %D0\n", sign_suffix);
1387 static void emit_ia32_Call(const ir_node *node)
1389 /* Special case: Call must not have its immediates prefixed by $, instead
1390 * address mode is prefixed by *. */
1391 ia32_emitf(node, "\tcall %*AS3\n");
1396 * Emits code to increase stack pointer.
1398 static void emit_be_IncSP(const ir_node *node)
1400 int offs = be_get_IncSP_offset(node);
1406 ia32_emitf(node, "\tsubl $%u, %D0\n", offs);
1408 ia32_emitf(node, "\taddl $%u, %D0\n", -offs);
1413 * Emits code for Copy/CopyKeep.
1415 static void Copy_emitter(const ir_node *node, const ir_node *op)
1417 const arch_register_t *in = arch_get_irn_register(op);
1418 const arch_register_t *out = arch_get_irn_register(node);
1423 /* copies of vf nodes aren't real... */
1424 if (arch_register_get_class(in) == &ia32_reg_classes[CLASS_ia32_vfp])
1427 if (get_irn_mode(node) == mode_E) {
1428 ia32_emitf(node, "\tmovsd %R, %R\n", in, out);
1430 ia32_emitf(node, "\tmovl %R, %R\n", in, out);
1434 static void emit_be_Copy(const ir_node *node)
1436 Copy_emitter(node, be_get_Copy_op(node));
1439 static void emit_be_CopyKeep(const ir_node *node)
1441 Copy_emitter(node, be_get_CopyKeep_op(node));
1445 * Emits code for exchange.
1447 static void emit_be_Perm(const ir_node *node)
1449 const arch_register_t *in0, *in1;
1450 const arch_register_class_t *cls0, *cls1;
1452 in0 = arch_get_irn_register(get_irn_n(node, 0));
1453 in1 = arch_get_irn_register(get_irn_n(node, 1));
1455 cls0 = arch_register_get_class(in0);
1456 cls1 = arch_register_get_class(in1);
1458 assert(cls0 == cls1 && "Register class mismatch at Perm");
1460 if (cls0 == &ia32_reg_classes[CLASS_ia32_gp]) {
1461 ia32_emitf(node, "\txchg %R, %R\n", in1, in0);
1462 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_xmm]) {
1463 ia32_emitf(NULL, "\txorpd %R, %R\n", in1, in0);
1464 ia32_emitf(NULL, "\txorpd %R, %R\n", in0, in1);
1465 ia32_emitf(node, "\txorpd %R, %R\n", in1, in0);
1466 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_vfp]) {
1468 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_st]) {
1471 panic("unexpected register class in be_Perm (%+F)", node);
1476 * Emits code for Constant loading.
1478 static void emit_ia32_Const(const ir_node *node)
1480 ia32_emitf(node, "\tmovl %I, %D0\n");
1483 /* helper function for emit_ia32_Minus64Bit */
1484 static void emit_mov(const ir_node* node, const arch_register_t *src, const arch_register_t *dst)
1486 ia32_emitf(node, "\tmovl %R, %R\n", src, dst);
1489 /* helper function for emit_ia32_Minus64Bit */
1490 static void emit_neg(const ir_node* node, const arch_register_t *reg)
1492 ia32_emitf(node, "\tnegl %R\n", reg);
1495 /* helper function for emit_ia32_Minus64Bit */
1496 static void emit_sbb0(const ir_node* node, const arch_register_t *reg)
1498 ia32_emitf(node, "\tsbbl $0, %R\n", reg);
1501 /* helper function for emit_ia32_Minus64Bit */
1502 static void emit_sbb(const ir_node* node, const arch_register_t *src, const arch_register_t *dst)
1504 ia32_emitf(node, "\tsbbl %R, %R\n", src, dst);
1507 /* helper function for emit_ia32_Minus64Bit */
1508 static void emit_xchg(const ir_node* node, const arch_register_t *src, const arch_register_t *dst)
1510 ia32_emitf(node, "\txchgl %R, %R\n", src, dst);
1513 /* helper function for emit_ia32_Minus64Bit */
1514 static void emit_zero(const ir_node* node, const arch_register_t *reg)
1516 ia32_emitf(node, "\txorl %R, %R\n", reg, reg);
1519 static void emit_ia32_Minus64Bit(const ir_node *node)
1521 const arch_register_t *in_lo = get_in_reg(node, 0);
1522 const arch_register_t *in_hi = get_in_reg(node, 1);
1523 const arch_register_t *out_lo = get_out_reg(node, 0);
1524 const arch_register_t *out_hi = get_out_reg(node, 1);
1526 if (out_lo == in_lo) {
1527 if (out_hi != in_hi) {
1528 /* a -> a, b -> d */
1531 /* a -> a, b -> b */
1534 } else if (out_lo == in_hi) {
1535 if (out_hi == in_lo) {
1536 /* a -> b, b -> a */
1537 emit_xchg(node, in_lo, in_hi);
1540 /* a -> b, b -> d */
1541 emit_mov(node, in_hi, out_hi);
1542 emit_mov(node, in_lo, out_lo);
1546 if (out_hi == in_lo) {
1547 /* a -> c, b -> a */
1548 emit_mov(node, in_lo, out_lo);
1550 } else if (out_hi == in_hi) {
1551 /* a -> c, b -> b */
1552 emit_mov(node, in_lo, out_lo);
1555 /* a -> c, b -> d */
1556 emit_mov(node, in_lo, out_lo);
1562 emit_neg( node, out_hi);
1563 emit_neg( node, out_lo);
1564 emit_sbb0(node, out_hi);
1568 emit_zero(node, out_hi);
1569 emit_neg( node, out_lo);
1570 emit_sbb( node, in_hi, out_hi);
1573 static void emit_ia32_GetEIP(const ir_node *node)
1575 ia32_emitf(node, "\tcall %s\n", pic_base_label);
1576 ia32_emitf(NULL, "%s:\n", pic_base_label);
1577 ia32_emitf(node, "\tpopl %D0\n");
1580 static void emit_ia32_ClimbFrame(const ir_node *node)
1582 const ia32_climbframe_attr_t *attr = get_ia32_climbframe_attr_const(node);
1584 ia32_emitf(node, "\tmovl %S0, %D0\n");
1585 ia32_emitf(node, "\tmovl $%u, %S1\n", attr->count);
1586 be_gas_emit_block_name(node);
1587 be_emit_cstring(":\n");
1588 be_emit_write_line();
1589 ia32_emitf(node, "\tmovl (%D0), %D0\n");
1590 ia32_emitf(node, "\tdec %S1\n");
1591 be_emit_cstring("\tjnz ");
1592 be_gas_emit_block_name(node);
1593 be_emit_finish_line_gas(node);
1596 static void emit_be_Return(const ir_node *node)
1598 unsigned pop = be_Return_get_pop(node);
1600 if (pop > 0 || be_Return_get_emit_pop(node)) {
1601 ia32_emitf(node, "\tret $%u\n", pop);
1603 ia32_emitf(node, "\tret\n");
1607 static void emit_Nothing(const ir_node *node)
1614 * Enters the emitter functions for handled nodes into the generic
1615 * pointer of an opcode.
1617 static void ia32_register_emitters(void)
1619 #define IA32_EMIT2(a,b) op_ia32_##a->ops.generic = (op_func)emit_ia32_##b
1620 #define IA32_EMIT(a) IA32_EMIT2(a,a)
1621 #define EMIT(a) op_##a->ops.generic = (op_func)emit_##a
1622 #define IGN(a) op_##a->ops.generic = (op_func)emit_Nothing
1623 #define BE_EMIT(a) op_be_##a->ops.generic = (op_func)emit_be_##a
1624 #define BE_IGN(a) op_be_##a->ops.generic = (op_func)emit_Nothing
1626 /* first clear the generic function pointer for all ops */
1627 clear_irp_opcodes_generic_func();
1629 /* register all emitter functions defined in spec */
1630 ia32_register_spec_emitters();
1632 /* other ia32 emitter functions */
1633 IA32_EMIT2(Conv_I2I8Bit, Conv_I2I);
1638 IA32_EMIT(Conv_FP2FP);
1639 IA32_EMIT(Conv_FP2I);
1640 IA32_EMIT(Conv_I2FP);
1641 IA32_EMIT(Conv_I2I);
1648 IA32_EMIT(Minus64Bit);
1649 IA32_EMIT(SwitchJmp);
1650 IA32_EMIT(ClimbFrame);
1653 /* benode emitter */
1673 typedef void (*emit_func_ptr) (const ir_node *);
1676 * Assign and emit an exception label if the current instruction can fail.
1678 static void ia32_assign_exc_label(ir_node *node)
1680 /* assign a new ID to the instruction */
1681 set_ia32_exc_label_id(node, ++exc_label_id);
1683 ia32_emit_exc_label(node);
1685 be_emit_pad_comment();
1686 be_emit_cstring("/* exception to Block ");
1687 ia32_emit_cfop_target(node);
1688 be_emit_cstring(" */\n");
1689 be_emit_write_line();
1693 * Emits code for a node.
1695 static void ia32_emit_node(ir_node *node)
1697 ir_op *op = get_irn_op(node);
1699 DBG((dbg, LEVEL_1, "emitting code for %+F\n", node));
1701 if (is_ia32_irn(node)) {
1702 if (get_ia32_exc_label(node)) {
1703 /* emit the exception label of this instruction */
1704 ia32_assign_exc_label(node);
1706 if (mark_spill_reload) {
1707 if (is_ia32_is_spill(node)) {
1708 ia32_emitf(NULL, "\txchg %ebx, %ebx /* spill mark */\n");
1710 if (is_ia32_is_reload(node)) {
1711 ia32_emitf(NULL, "\txchg %edx, %edx /* reload mark */\n");
1713 if (is_ia32_is_remat(node)) {
1714 ia32_emitf(NULL, "\txchg %ecx, %ecx /* remat mark */\n");
1718 if (op->ops.generic) {
1719 emit_func_ptr func = (emit_func_ptr) op->ops.generic;
1721 be_dbg_set_dbg_info(get_irn_dbg_info(node));
1726 ir_fprintf(stderr, "Error: No emit handler for node %+F (%+G, graph %+F)\n", node, node, current_ir_graph);
1732 * Emits gas alignment directives
1734 static void ia32_emit_alignment(unsigned align, unsigned skip)
1736 ia32_emitf(NULL, "\t.p2align %u,,%u\n", align, skip);
1740 * Emits gas alignment directives for Labels depended on cpu architecture.
1742 static void ia32_emit_align_label(void)
1744 unsigned align = ia32_cg_config.label_alignment;
1745 unsigned maximum_skip = ia32_cg_config.label_alignment_max_skip;
1746 ia32_emit_alignment(align, maximum_skip);
1750 * Test whether a block should be aligned.
1751 * For cpus in the P4/Athlon class it is useful to align jump labels to
1752 * 16 bytes. However we should only do that if the alignment nops before the
1753 * label aren't executed more often than we have jumps to the label.
1755 static int should_align_block(const ir_node *block)
1757 static const double DELTA = .0001;
1758 ir_graph *irg = get_irn_irg(block);
1759 ir_exec_freq *exec_freq = be_get_irg_exec_freq(irg);
1760 ir_node *prev = get_prev_block_sched(block);
1762 double prev_freq = 0; /**< execfreq of the fallthrough block */
1763 double jmp_freq = 0; /**< execfreq of all non-fallthrough blocks */
1766 if (exec_freq == NULL)
1768 if (ia32_cg_config.label_alignment_factor <= 0)
1771 block_freq = get_block_execfreq(exec_freq, block);
1772 if (block_freq < DELTA)
1775 n_cfgpreds = get_Block_n_cfgpreds(block);
1776 for (i = 0; i < n_cfgpreds; ++i) {
1777 const ir_node *pred = get_Block_cfgpred_block(block, i);
1778 double pred_freq = get_block_execfreq(exec_freq, pred);
1781 prev_freq += pred_freq;
1783 jmp_freq += pred_freq;
1787 if (prev_freq < DELTA && !(jmp_freq < DELTA))
1790 jmp_freq /= prev_freq;
1792 return jmp_freq > ia32_cg_config.label_alignment_factor;
1796 * Emit the block header for a block.
1798 * @param block the block
1799 * @param prev_block the previous block
1801 static void ia32_emit_block_header(ir_node *block)
1803 ir_graph *irg = current_ir_graph;
1804 int need_label = block_needs_label(block);
1805 ir_exec_freq *exec_freq = be_get_irg_exec_freq(irg);
1808 if (block == get_irg_end_block(irg))
1811 if (ia32_cg_config.label_alignment > 0) {
1812 /* align the current block if:
1813 * a) if should be aligned due to its execution frequency
1814 * b) there is no fall-through here
1816 if (should_align_block(block)) {
1817 ia32_emit_align_label();
1819 /* if the predecessor block has no fall-through,
1820 we can always align the label. */
1822 int has_fallthrough = 0;
1824 for (i = get_Block_n_cfgpreds(block) - 1; i >= 0; --i) {
1825 ir_node *cfg_pred = get_Block_cfgpred(block, i);
1826 if (can_be_fallthrough(cfg_pred)) {
1827 has_fallthrough = 1;
1832 if (!has_fallthrough)
1833 ia32_emit_align_label();
1838 be_gas_emit_block_name(block);
1841 be_emit_pad_comment();
1842 be_emit_cstring(" /* ");
1844 be_emit_cstring("\t/* ");
1845 be_gas_emit_block_name(block);
1846 be_emit_cstring(": ");
1849 be_emit_cstring("preds:");
1851 /* emit list of pred blocks in comment */
1852 arity = get_irn_arity(block);
1854 be_emit_cstring(" none");
1857 for (i = 0; i < arity; ++i) {
1858 ir_node *predblock = get_Block_cfgpred_block(block, i);
1859 be_emit_irprintf(" %d", get_irn_node_nr(predblock));
1862 if (exec_freq != NULL) {
1863 be_emit_irprintf(", freq: %f",
1864 get_block_execfreq(exec_freq, block));
1866 be_emit_cstring(" */\n");
1867 be_emit_write_line();
1871 * Walks over the nodes in a block connected by scheduling edges
1872 * and emits code for each node.
1874 static void ia32_gen_block(ir_node *block)
1878 ia32_emit_block_header(block);
1880 /* emit the contents of the block */
1881 be_dbg_set_dbg_info(get_irn_dbg_info(block));
1882 sched_foreach(block, node) {
1883 ia32_emit_node(node);
1887 typedef struct exc_entry {
1888 ir_node *exc_instr; /** The instruction that can issue an exception. */
1889 ir_node *block; /** The block to call then. */
1894 * Sets labels for control flow nodes (jump target).
1895 * Links control predecessors to there destination blocks.
1897 static void ia32_gen_labels(ir_node *block, void *data)
1899 exc_entry **exc_list = (exc_entry**)data;
1903 for (n = get_Block_n_cfgpreds(block) - 1; n >= 0; --n) {
1904 pred = get_Block_cfgpred(block, n);
1905 set_irn_link(pred, block);
1907 pred = skip_Proj(pred);
1908 if (is_ia32_irn(pred) && get_ia32_exc_label(pred)) {
1913 ARR_APP1(exc_entry, *exc_list, e);
1914 set_irn_link(pred, block);
1920 * Compare two exception_entries.
1922 static int cmp_exc_entry(const void *a, const void *b)
1924 const exc_entry *ea = (const exc_entry*)a;
1925 const exc_entry *eb = (const exc_entry*)b;
1927 if (get_ia32_exc_label_id(ea->exc_instr) < get_ia32_exc_label_id(eb->exc_instr))
1933 * Main driver. Emits the code for one routine.
1935 void ia32_gen_routine(ir_graph *irg)
1937 ir_entity *entity = get_irg_entity(irg);
1938 exc_entry *exc_list = NEW_ARR_F(exc_entry, 0);
1939 const arch_env_t *arch_env = be_get_irg_arch_env(irg);
1940 ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
1941 ir_node **blk_sched = irg_data->blk_sched;
1944 isa = (ia32_isa_t*) arch_env;
1945 do_pic = be_get_irg_options(irg)->pic;
1947 be_gas_elf_type_char = '@';
1949 ia32_register_emitters();
1951 get_unique_label(pic_base_label, sizeof(pic_base_label), "PIC_BASE");
1953 be_dbg_method_begin(entity);
1954 be_gas_emit_function_prolog(entity, ia32_cg_config.function_alignment);
1956 /* we use links to point to target blocks */
1957 ir_reserve_resources(irg, IR_RESOURCE_IRN_LINK);
1958 irg_block_walk_graph(irg, ia32_gen_labels, NULL, &exc_list);
1960 /* initialize next block links */
1961 n = ARR_LEN(blk_sched);
1962 for (i = 0; i < n; ++i) {
1963 ir_node *block = blk_sched[i];
1964 ir_node *prev = i > 0 ? blk_sched[i-1] : NULL;
1966 set_irn_link(block, prev);
1969 for (i = 0; i < n; ++i) {
1970 ir_node *block = blk_sched[i];
1972 ia32_gen_block(block);
1975 be_gas_emit_function_epilog(entity);
1976 be_dbg_method_end();
1978 be_emit_write_line();
1980 ir_free_resources(irg, IR_RESOURCE_IRN_LINK);
1982 /* Sort the exception table using the exception label id's.
1983 Those are ascending with ascending addresses. */
1984 qsort(exc_list, ARR_LEN(exc_list), sizeof(exc_list[0]), cmp_exc_entry);
1988 for (e = 0; e < ARR_LEN(exc_list); ++e) {
1989 be_emit_cstring("\t.long ");
1990 ia32_emit_exc_label(exc_list[e].exc_instr);
1992 be_emit_cstring("\t.long ");
1993 be_gas_emit_block_name(exc_list[e].block);
1997 DEL_ARR_F(exc_list);
2000 static const lc_opt_table_entry_t ia32_emitter_options[] = {
2001 LC_OPT_ENT_BOOL("mark_spill_reload", "mark spills and reloads with ud opcodes", &mark_spill_reload),
2005 /* ==== Experimental binary emitter ==== */
2007 static unsigned char reg_gp_map[N_ia32_gp_REGS];
2008 //static unsigned char reg_mmx_map[N_ia32_mmx_REGS];
2009 //static unsigned char reg_sse_map[N_ia32_xmm_REGS];
2011 static void build_reg_map(void)
2013 reg_gp_map[REG_GP_EAX] = 0x0;
2014 reg_gp_map[REG_GP_ECX] = 0x1;
2015 reg_gp_map[REG_GP_EDX] = 0x2;
2016 reg_gp_map[REG_GP_EBX] = 0x3;
2017 reg_gp_map[REG_GP_ESP] = 0x4;
2018 reg_gp_map[REG_GP_EBP] = 0x5;
2019 reg_gp_map[REG_GP_ESI] = 0x6;
2020 reg_gp_map[REG_GP_EDI] = 0x7;
2023 /** Returns the encoding for a pnc field. */
2024 static unsigned char pnc2cc(ia32_condition_code_t cc)
2029 /** Sign extension bit values for binops */
2031 UNSIGNED_IMM = 0, /**< unsigned immediate */
2032 SIGNEXT_IMM = 2, /**< sign extended immediate */
2035 /** The mod encoding of the ModR/M */
2037 MOD_IND = 0x00, /**< [reg1] */
2038 MOD_IND_BYTE_OFS = 0x40, /**< [reg1 + byte ofs] */
2039 MOD_IND_WORD_OFS = 0x80, /**< [reg1 + word ofs] */
2040 MOD_REG = 0xC0 /**< reg1 */
2043 /** create R/M encoding for ModR/M */
2044 #define ENC_RM(x) (x)
2045 /** create REG encoding for ModR/M */
2046 #define ENC_REG(x) ((x) << 3)
2048 /** create encoding for a SIB byte */
2049 #define ENC_SIB(scale, index, base) ((scale) << 6 | (index) << 3 | (base))
2051 /* Node: The following routines are supposed to append bytes, words, dwords
2052 to the output stream.
2053 Currently the implementation is stupid in that it still creates output
2054 for an "assembler" in the form of .byte, .long
2055 We will change this when enough infrastructure is there to create complete
2056 machine code in memory/object files */
2058 static void bemit8(const unsigned char byte)
2060 be_emit_irprintf("\t.byte 0x%x\n", byte);
2061 be_emit_write_line();
2064 static void bemit16(const unsigned short u16)
2066 be_emit_irprintf("\t.word 0x%x\n", u16);
2067 be_emit_write_line();
2070 static void bemit32(const unsigned u32)
2072 be_emit_irprintf("\t.long 0x%x\n", u32);
2073 be_emit_write_line();
2077 * Emit address of an entity. If @p is_relative is true then a relative
2078 * offset from behind the address to the entity is created.
2080 static void bemit_entity(ir_entity *entity, bool entity_sign, int offset,
2083 if (entity == NULL) {
2088 /* the final version should remember the position in the bytestream
2089 and patch it with the correct address at linktime... */
2090 be_emit_cstring("\t.long ");
2093 be_gas_emit_entity(entity);
2095 if (get_entity_owner(entity) == get_tls_type()) {
2096 if (get_entity_visibility(entity) == ir_visibility_external) {
2097 be_emit_cstring("@INDNTPOFF");
2099 be_emit_cstring("@NTPOFF");
2104 be_emit_cstring("-.");
2109 be_emit_irprintf("%+d", offset);
2112 be_emit_write_line();
2115 static void bemit_jmp_destination(const ir_node *dest_block)
2117 be_emit_cstring("\t.long ");
2118 be_gas_emit_block_name(dest_block);
2119 be_emit_cstring(" - . - 4\n");
2120 be_emit_write_line();
2123 /* end emit routines, all emitters following here should only use the functions
2126 typedef enum reg_modifier {
2131 /** Create a ModR/M byte for src1,src2 registers */
2132 static void bemit_modrr(const arch_register_t *src1,
2133 const arch_register_t *src2)
2135 unsigned char modrm = MOD_REG;
2136 modrm |= ENC_RM(reg_gp_map[src1->index]);
2137 modrm |= ENC_REG(reg_gp_map[src2->index]);
2141 /** Create a ModR/M8 byte for src1,src2 registers */
2142 static void bemit_modrr8(reg_modifier_t high_part1, const arch_register_t *src1,
2143 reg_modifier_t high_part2, const arch_register_t *src2)
2145 unsigned char modrm = MOD_REG;
2146 modrm |= ENC_RM(reg_gp_map[src1->index] + (high_part1 == REG_HIGH ? 4 : 0));
2147 modrm |= ENC_REG(reg_gp_map[src2->index] + (high_part2 == REG_HIGH ? 4 : 0));
2151 /** Create a ModR/M byte for one register and extension */
2152 static void bemit_modru(const arch_register_t *reg, unsigned ext)
2154 unsigned char modrm = MOD_REG;
2156 modrm |= ENC_RM(reg_gp_map[reg->index]);
2157 modrm |= ENC_REG(ext);
2161 /** Create a ModR/M8 byte for one register */
2162 static void bemit_modrm8(reg_modifier_t high_part, const arch_register_t *reg)
2164 unsigned char modrm = MOD_REG;
2165 assert(reg_gp_map[reg->index] < 4);
2166 modrm |= ENC_RM(reg_gp_map[reg->index] + (high_part == REG_HIGH ? 4 : 0));
2172 * Calculate the size of an signed immediate in bytes.
2174 * @param offset an offset
2176 static unsigned get_signed_imm_size(int offset)
2178 if (-128 <= offset && offset < 128) {
2180 } else if (-32768 <= offset && offset < 32768) {
2188 * Emit an address mode.
2190 * @param reg content of the reg field: either a register index or an opcode extension
2191 * @param node the node
2193 static void bemit_mod_am(unsigned reg, const ir_node *node)
2195 ir_entity *ent = get_ia32_am_sc(node);
2196 int offs = get_ia32_am_offs_int(node);
2197 ir_node *base = get_irn_n(node, n_ia32_base);
2198 int has_base = !is_ia32_NoReg_GP(base);
2199 ir_node *idx = get_irn_n(node, n_ia32_index);
2200 int has_index = !is_ia32_NoReg_GP(idx);
2203 unsigned emitoffs = 0;
2204 bool emitsib = false;
2207 /* set the mod part depending on displacement */
2209 modrm |= MOD_IND_WORD_OFS;
2211 } else if (offs == 0) {
2214 } else if (-128 <= offs && offs < 128) {
2215 modrm |= MOD_IND_BYTE_OFS;
2218 modrm |= MOD_IND_WORD_OFS;
2223 const arch_register_t *base_reg = arch_get_irn_register(base);
2224 base_enc = reg_gp_map[base_reg->index];
2226 /* Use the EBP encoding + MOD_IND if NO base register. There is
2227 * always a 32bit offset present in this case. */
2233 /* Determine if we need a SIB byte. */
2235 const arch_register_t *reg_index = arch_get_irn_register(idx);
2236 int scale = get_ia32_am_scale(node);
2238 /* R/M set to ESP means SIB in 32bit mode. */
2239 modrm |= ENC_RM(0x04);
2240 sib = ENC_SIB(scale, reg_gp_map[reg_index->index], base_enc);
2242 } else if (base_enc == 0x04) {
2243 /* for the above reason we are forced to emit a SIB when base is ESP.
2244 * Only the base is used, index must be ESP too, which means no index.
2246 modrm |= ENC_RM(0x04);
2247 sib = ENC_SIB(0, 0x04, 0x04);
2250 modrm |= ENC_RM(base_enc);
2253 /* We are forced to emit an 8bit offset as EBP base without offset is a
2254 * special case for SIB without base register. */
2255 if (base_enc == 0x05 && emitoffs == 0) {
2256 modrm |= MOD_IND_BYTE_OFS;
2260 modrm |= ENC_REG(reg);
2266 /* emit displacement */
2267 if (emitoffs == 8) {
2268 bemit8((unsigned) offs);
2269 } else if (emitoffs == 32) {
2270 bemit_entity(ent, is_ia32_am_sc_sign(node), offs, false);
2275 * Emit a binop with a immediate operand.
2277 * @param node the node to emit
2278 * @param opcode_eax the opcode for the op eax, imm variant
2279 * @param opcode the opcode for the reg, imm variant
2280 * @param ruval the opcode extension for opcode
2282 static void bemit_binop_with_imm(
2283 const ir_node *node,
2284 unsigned char opcode_ax,
2285 unsigned char opcode, unsigned char ruval)
2287 /* Use in-reg, because some instructions (cmp, test) have no out-reg. */
2288 const ir_node *op = get_irn_n(node, n_ia32_binary_right);
2289 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(op);
2292 /* Some instructions (test) have no short form with 32bit value + 8bit
2294 if (attr->symconst != NULL || opcode & SIGNEXT_IMM) {
2297 /* check for sign extension */
2298 size = get_signed_imm_size(attr->offset);
2303 bemit8(opcode | SIGNEXT_IMM);
2304 /* cmp has this special mode */
2305 if (get_ia32_op_type(node) == ia32_AddrModeS) {
2306 bemit_mod_am(ruval, node);
2308 const arch_register_t *reg = get_in_reg(node, n_ia32_binary_left);
2309 bemit_modru(reg, ruval);
2311 bemit8((unsigned char)attr->offset);
2315 /* check for eax variant: this variant is shorter for 32bit immediates only */
2316 if (get_ia32_op_type(node) == ia32_AddrModeS) {
2318 bemit_mod_am(ruval, node);
2320 const arch_register_t *reg = get_in_reg(node, n_ia32_binary_left);
2321 if (reg->index == REG_GP_EAX) {
2325 bemit_modru(reg, ruval);
2328 bemit_entity(attr->symconst, attr->sc_sign, attr->offset, false);
2331 panic("invalid imm size?!?");
2337 static void bemit_binop_2(const ir_node *node, unsigned code)
2339 const arch_register_t *out = get_in_reg(node, n_ia32_binary_left);
2341 if (get_ia32_op_type(node) == ia32_Normal) {
2342 const arch_register_t *op2 = get_in_reg(node, n_ia32_binary_right);
2343 bemit_modrr(op2, out);
2345 bemit_mod_am(reg_gp_map[out->index], node);
2352 static void bemit_binop(const ir_node *node, const unsigned char opcodes[4])
2354 ir_node *right = get_irn_n(node, n_ia32_binary_right);
2355 if (is_ia32_Immediate(right)) {
2356 bemit_binop_with_imm(node, opcodes[1], opcodes[2], opcodes[3]);
2358 bemit_binop_2(node, opcodes[0]);
2365 static void bemit_unop(const ir_node *node, unsigned char code, unsigned char ext, int input)
2368 if (get_ia32_op_type(node) == ia32_Normal) {
2369 const arch_register_t *in = get_in_reg(node, input);
2370 bemit_modru(in, ext);
2372 bemit_mod_am(ext, node);
2376 static void bemit_unop_reg(const ir_node *node, unsigned char code, int input)
2378 const arch_register_t *out = get_out_reg(node, 0);
2379 bemit_unop(node, code, reg_gp_map[out->index], input);
2382 static void bemit_unop_mem(const ir_node *node, unsigned char code, unsigned char ext)
2384 unsigned size = get_mode_size_bits(get_ia32_ls_mode(node));
2387 bemit8(size == 8 ? code : code + 1);
2388 bemit_mod_am(ext, node);
2391 static void bemit_immediate(const ir_node *node, bool relative)
2393 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(node);
2394 bemit_entity(attr->symconst, attr->sc_sign, attr->offset, relative);
2397 static void bemit_copy(const ir_node *copy)
2399 const arch_register_t *in = get_in_reg(copy, 0);
2400 const arch_register_t *out = get_out_reg(copy, 0);
2404 /* copies of vf nodes aren't real... */
2405 if (arch_register_get_class(in) == &ia32_reg_classes[CLASS_ia32_vfp])
2408 if (get_irn_mode(copy) == mode_E) {
2411 assert(arch_register_get_class(in) == &ia32_reg_classes[CLASS_ia32_gp]);
2413 bemit_modrr(in, out);
2417 static void bemit_perm(const ir_node *node)
2419 const arch_register_t *in0 = arch_get_irn_register(get_irn_n(node, 0));
2420 const arch_register_t *in1 = arch_get_irn_register(get_irn_n(node, 1));
2421 const arch_register_class_t *cls0 = arch_register_get_class(in0);
2423 assert(cls0 == arch_register_get_class(in1) && "Register class mismatch at Perm");
2425 if (cls0 == &ia32_reg_classes[CLASS_ia32_gp]) {
2426 if (in0->index == REG_GP_EAX) {
2427 bemit8(0x90 + reg_gp_map[in1->index]);
2428 } else if (in1->index == REG_GP_EAX) {
2429 bemit8(0x90 + reg_gp_map[in0->index]);
2432 bemit_modrr(in0, in1);
2434 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_xmm]) {
2435 panic("unimplemented"); // TODO implement
2436 //ia32_emitf(NULL, "\txorpd %R, %R\n", in1, in0);
2437 //ia32_emitf(NULL, "\txorpd %R, %R\n", in0, in1);
2438 //ia32_emitf(node, "\txorpd %R, %R\n", in1, in0);
2439 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_vfp]) {
2441 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_st]) {
2444 panic("unexpected register class in be_Perm (%+F)", node);
2448 static void bemit_xor0(const ir_node *node)
2450 const arch_register_t *out = get_out_reg(node, 0);
2452 bemit_modrr(out, out);
2455 static void bemit_mov_const(const ir_node *node)
2457 const arch_register_t *out = get_out_reg(node, 0);
2458 bemit8(0xB8 + reg_gp_map[out->index]);
2459 bemit_immediate(node, false);
2463 * Creates a function for a Binop with 3 possible encodings.
2465 #define BINOP(op, op0, op1, op2, op2_ext) \
2466 static void bemit_ ## op(const ir_node *node) { \
2467 static const unsigned char op ## _codes[] = {op0, op1, op2, op2_ext}; \
2468 bemit_binop(node, op ## _codes); \
2471 /* insn def eax,imm imm */
2472 BINOP(add, 0x03, 0x05, 0x81, 0)
2473 BINOP(or, 0x0B, 0x0D, 0x81, 1)
2474 BINOP(adc, 0x13, 0x15, 0x81, 2)
2475 BINOP(sbb, 0x1B, 0x1D, 0x81, 3)
2476 BINOP(and, 0x23, 0x25, 0x81, 4)
2477 BINOP(sub, 0x2B, 0x2D, 0x81, 5)
2478 BINOP(xor, 0x33, 0x35, 0x81, 6)
2479 BINOP(test, 0x85, 0xA9, 0xF7, 0)
2481 #define BINOPMEM(op, ext) \
2482 static void bemit_##op(const ir_node *node) \
2485 unsigned size = get_mode_size_bits(get_ia32_ls_mode(node)); \
2488 val = get_irn_n(node, n_ia32_unary_op); \
2489 if (is_ia32_Immediate(val)) { \
2490 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(val); \
2491 int offset = attr->offset; \
2492 if (attr->symconst == NULL && get_signed_imm_size(offset) == 1) { \
2494 bemit_mod_am(ext, node); \
2498 bemit_mod_am(ext, node); \
2502 bemit_entity(attr->symconst, attr->sc_sign, offset, false); \
2506 bemit8(ext << 3 | 1); \
2507 bemit_mod_am(reg_gp_map[get_out_reg(val, 0)->index], node); \
2511 static void bemit_##op##8bit(const ir_node *node) \
2513 ir_node *val = get_irn_n(node, n_ia32_unary_op); \
2514 if (is_ia32_Immediate(val)) { \
2516 bemit_mod_am(ext, node); \
2517 bemit8(get_ia32_immediate_attr_const(val)->offset); \
2520 bemit_mod_am(reg_gp_map[get_out_reg(val, 0)->index], node); \
2532 * Creates a function for an Unop with code /ext encoding.
2534 #define UNOP(op, code, ext, input) \
2535 static void bemit_ ## op(const ir_node *node) { \
2536 bemit_unop(node, code, ext, input); \
2539 UNOP(not, 0xF7, 2, n_ia32_Not_val)
2540 UNOP(neg, 0xF7, 3, n_ia32_Neg_val)
2541 UNOP(mul, 0xF7, 4, n_ia32_Mul_right)
2542 UNOP(imul1op, 0xF7, 5, n_ia32_IMul1OP_right)
2543 UNOP(div, 0xF7, 6, n_ia32_Div_divisor)
2544 UNOP(idiv, 0xF7, 7, n_ia32_IDiv_divisor)
2546 /* TODO: am support for IJmp */
2547 UNOP(ijmp, 0xFF, 4, n_ia32_IJmp_target)
2549 #define SHIFT(op, ext) \
2550 static void bemit_##op(const ir_node *node) \
2552 const arch_register_t *out = get_out_reg(node, 0); \
2553 ir_node *count = get_irn_n(node, 1); \
2554 if (is_ia32_Immediate(count)) { \
2555 int offset = get_ia32_immediate_attr_const(count)->offset; \
2556 if (offset == 1) { \
2558 bemit_modru(out, ext); \
2561 bemit_modru(out, ext); \
2566 bemit_modru(out, ext); \
2570 static void bemit_##op##mem(const ir_node *node) \
2573 unsigned size = get_mode_size_bits(get_ia32_ls_mode(node)); \
2576 count = get_irn_n(node, 1); \
2577 if (is_ia32_Immediate(count)) { \
2578 int offset = get_ia32_immediate_attr_const(count)->offset; \
2579 if (offset == 1) { \
2580 bemit8(size == 8 ? 0xD0 : 0xD1); \
2581 bemit_mod_am(ext, node); \
2583 bemit8(size == 8 ? 0xC0 : 0xC1); \
2584 bemit_mod_am(ext, node); \
2588 bemit8(size == 8 ? 0xD2 : 0xD3); \
2589 bemit_mod_am(ext, node); \
2599 static void bemit_shld(const ir_node *node)
2601 const arch_register_t *in = get_in_reg(node, n_ia32_ShlD_val_low);
2602 const arch_register_t *out = get_out_reg(node, pn_ia32_ShlD_res);
2603 ir_node *count = get_irn_n(node, n_ia32_ShlD_count);
2605 if (is_ia32_Immediate(count)) {
2607 bemit_modrr(out, in);
2608 bemit8(get_ia32_immediate_attr_const(count)->offset);
2611 bemit_modrr(out, in);
2615 static void bemit_shrd(const ir_node *node)
2617 const arch_register_t *in = get_in_reg(node, n_ia32_ShrD_val_low);
2618 const arch_register_t *out = get_out_reg(node, pn_ia32_ShrD_res);
2619 ir_node *count = get_irn_n(node, n_ia32_ShrD_count);
2621 if (is_ia32_Immediate(count)) {
2623 bemit_modrr(out, in);
2624 bemit8(get_ia32_immediate_attr_const(count)->offset);
2627 bemit_modrr(out, in);
2632 * binary emitter for setcc.
2634 static void bemit_setcc(const ir_node *node)
2636 const arch_register_t *dreg = get_out_reg(node, pn_ia32_Setcc_res);
2638 ia32_condition_code_t cc = get_ia32_condcode(node);
2639 cc = determine_final_cc(node, n_ia32_Setcc_eflags, cc);
2640 if (cc & ia32_cc_float_parity_cases) {
2641 if (cc & ia32_cc_negated) {
2644 bemit8(0x90 | pnc2cc(cc));
2645 bemit_modrm8(REG_LOW, dreg);
2650 bemit_modrm8(REG_HIGH, dreg);
2652 /* orb %>dreg, %<dreg */
2654 bemit_modrr8(REG_LOW, dreg, REG_HIGH, dreg);
2658 bemit8(0x90 | pnc2cc(cc));
2659 bemit_modrm8(REG_LOW, dreg);
2664 bemit_modrm8(REG_HIGH, dreg);
2666 /* andb %>dreg, %<dreg */
2668 bemit_modrr8(REG_LOW, dreg, REG_HIGH, dreg);
2673 bemit8(0x90 | pnc2cc(cc));
2674 bemit_modrm8(REG_LOW, dreg);
2678 static void bemit_cmovcc(const ir_node *node)
2680 const ia32_attr_t *attr = get_ia32_attr_const(node);
2681 int ins_permuted = attr->data.ins_permuted;
2682 const arch_register_t *out = arch_irn_get_register(node, pn_ia32_res);
2683 ia32_condition_code_t cc = get_ia32_condcode(node);
2684 const arch_register_t *in_true;
2685 const arch_register_t *in_false;
2687 cc = determine_final_cc(node, n_ia32_CMovcc_eflags, cc);
2689 in_true = arch_get_irn_register(get_irn_n(node, n_ia32_CMovcc_val_true));
2690 in_false = arch_get_irn_register(get_irn_n(node, n_ia32_CMovcc_val_false));
2692 /* should be same constraint fullfilled? */
2693 if (out == in_false) {
2694 /* yes -> nothing to do */
2695 } else if (out == in_true) {
2696 assert(get_ia32_op_type(node) == ia32_Normal);
2697 ins_permuted = !ins_permuted;
2701 bemit8(0x8B); // mov %in_false, %out
2702 bemit_modrr(in_false, out);
2706 cc = ia32_negate_condition_code(cc);
2708 if (cc & ia32_cc_float_parity_cases)
2709 panic("cmov can't handle parity float cases");
2712 bemit8(0x40 | pnc2cc(cc));
2713 if (get_ia32_op_type(node) == ia32_Normal) {
2714 bemit_modrr(in_true, out);
2716 bemit_mod_am(reg_gp_map[out->index], node);
2720 static void bemit_cmp(const ir_node *node)
2722 unsigned ls_size = get_mode_size_bits(get_ia32_ls_mode(node));
2728 right = get_irn_n(node, n_ia32_binary_right);
2729 if (is_ia32_Immediate(right)) {
2730 /* Use in-reg, because some instructions (cmp, test) have no out-reg. */
2731 const ir_node *op = get_irn_n(node, n_ia32_binary_right);
2732 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(op);
2735 if (attr->symconst != NULL) {
2738 /* check for sign extension */
2739 size = get_signed_imm_size(attr->offset);
2744 bemit8(0x81 | SIGNEXT_IMM);
2745 /* cmp has this special mode */
2746 if (get_ia32_op_type(node) == ia32_AddrModeS) {
2747 bemit_mod_am(7, node);
2749 const arch_register_t *reg = get_in_reg(node, n_ia32_binary_left);
2750 bemit_modru(reg, 7);
2752 bemit8((unsigned char)attr->offset);
2756 /* check for eax variant: this variant is shorter for 32bit immediates only */
2757 if (get_ia32_op_type(node) == ia32_AddrModeS) {
2759 bemit_mod_am(7, node);
2761 const arch_register_t *reg = get_in_reg(node, n_ia32_binary_left);
2762 if (reg->index == REG_GP_EAX) {
2766 bemit_modru(reg, 7);
2769 if (ls_size == 16) {
2770 bemit16(attr->offset);
2772 bemit_entity(attr->symconst, attr->sc_sign, attr->offset, false);
2776 panic("invalid imm size?!?");
2778 const arch_register_t *out = get_in_reg(node, n_ia32_binary_left);
2780 if (get_ia32_op_type(node) == ia32_Normal) {
2781 const arch_register_t *op2 = get_in_reg(node, n_ia32_binary_right);
2782 bemit_modrr(op2, out);
2784 bemit_mod_am(reg_gp_map[out->index], node);
2789 static void bemit_cmp8bit(const ir_node *node)
2791 ir_node *right = get_irn_n(node, n_ia32_binary_right);
2792 if (is_ia32_Immediate(right)) {
2793 if (get_ia32_op_type(node) == ia32_Normal) {
2794 const arch_register_t *out = get_in_reg(node, n_ia32_Cmp_left);
2795 if (out->index == REG_GP_EAX) {
2799 bemit_modru(out, 7);
2803 bemit_mod_am(7, node);
2805 bemit8(get_ia32_immediate_attr_const(right)->offset);
2807 const arch_register_t *out = get_in_reg(node, n_ia32_Cmp_left);
2809 if (get_ia32_op_type(node) == ia32_Normal) {
2810 const arch_register_t *in = get_in_reg(node, n_ia32_Cmp_right);
2811 bemit_modrr(out, in);
2813 bemit_mod_am(reg_gp_map[out->index], node);
2818 static void bemit_test8bit(const ir_node *node)
2820 ir_node *right = get_irn_n(node, n_ia32_Test8Bit_right);
2821 if (is_ia32_Immediate(right)) {
2822 if (get_ia32_op_type(node) == ia32_Normal) {
2823 const arch_register_t *out = get_in_reg(node, n_ia32_Test8Bit_left);
2824 if (out->index == REG_GP_EAX) {
2828 bemit_modru(out, 0);
2832 bemit_mod_am(0, node);
2834 bemit8(get_ia32_immediate_attr_const(right)->offset);
2836 const arch_register_t *out = get_in_reg(node, n_ia32_Test8Bit_left);
2838 if (get_ia32_op_type(node) == ia32_Normal) {
2839 const arch_register_t *in = get_in_reg(node, n_ia32_Test8Bit_right);
2840 bemit_modrr(out, in);
2842 bemit_mod_am(reg_gp_map[out->index], node);
2847 static void bemit_imul(const ir_node *node)
2849 ir_node *right = get_irn_n(node, n_ia32_IMul_right);
2850 /* Do we need the immediate form? */
2851 if (is_ia32_Immediate(right)) {
2852 int imm = get_ia32_immediate_attr_const(right)->offset;
2853 if (get_signed_imm_size(imm) == 1) {
2854 bemit_unop_reg(node, 0x6B, n_ia32_IMul_left);
2857 bemit_unop_reg(node, 0x69, n_ia32_IMul_left);
2862 bemit_unop_reg(node, 0xAF, n_ia32_IMul_right);
2866 static void bemit_dec(const ir_node *node)
2868 const arch_register_t *out = get_out_reg(node, pn_ia32_Dec_res);
2869 bemit8(0x48 + reg_gp_map[out->index]);
2872 static void bemit_inc(const ir_node *node)
2874 const arch_register_t *out = get_out_reg(node, pn_ia32_Inc_res);
2875 bemit8(0x40 + reg_gp_map[out->index]);
2878 #define UNOPMEM(op, code, ext) \
2879 static void bemit_##op(const ir_node *node) \
2881 bemit_unop_mem(node, code, ext); \
2884 UNOPMEM(notmem, 0xF6, 2)
2885 UNOPMEM(negmem, 0xF6, 3)
2886 UNOPMEM(incmem, 0xFE, 0)
2887 UNOPMEM(decmem, 0xFE, 1)
2889 static void bemit_ldtls(const ir_node *node)
2891 const arch_register_t *out = get_out_reg(node, 0);
2893 bemit8(0x65); // gs:
2894 if (out->index == REG_GP_EAX) {
2895 bemit8(0xA1); // movl 0, %eax
2897 bemit8(0x8B); // movl 0, %reg
2898 bemit8(MOD_IND | ENC_REG(reg_gp_map[out->index]) | ENC_RM(0x05));
2906 static void bemit_lea(const ir_node *node)
2908 const arch_register_t *out = get_out_reg(node, 0);
2910 bemit_mod_am(reg_gp_map[out->index], node);
2913 /* helper function for bemit_minus64bit */
2914 static void bemit_helper_mov(const arch_register_t *src, const arch_register_t *dst)
2916 bemit8(0x8B); // movl %src, %dst
2917 bemit_modrr(src, dst);
2920 /* helper function for bemit_minus64bit */
2921 static void bemit_helper_neg(const arch_register_t *reg)
2923 bemit8(0xF7); // negl %reg
2924 bemit_modru(reg, 3);
2927 /* helper function for bemit_minus64bit */
2928 static void bemit_helper_sbb0(const arch_register_t *reg)
2930 bemit8(0x83); // sbbl $0, %reg
2931 bemit_modru(reg, 3);
2935 /* helper function for bemit_minus64bit */
2936 static void bemit_helper_sbb(const arch_register_t *src, const arch_register_t *dst)
2938 bemit8(0x1B); // sbbl %src, %dst
2939 bemit_modrr(src, dst);
2942 /* helper function for bemit_minus64bit */
2943 static void bemit_helper_xchg(const arch_register_t *src, const arch_register_t *dst)
2945 if (src->index == REG_GP_EAX) {
2946 bemit8(0x90 + reg_gp_map[dst->index]); // xchgl %eax, %dst
2947 } else if (dst->index == REG_GP_EAX) {
2948 bemit8(0x90 + reg_gp_map[src->index]); // xchgl %src, %eax
2950 bemit8(0x87); // xchgl %src, %dst
2951 bemit_modrr(src, dst);
2955 /* helper function for bemit_minus64bit */
2956 static void bemit_helper_zero(const arch_register_t *reg)
2958 bemit8(0x33); // xorl %reg, %reg
2959 bemit_modrr(reg, reg);
2962 static void bemit_minus64bit(const ir_node *node)
2964 const arch_register_t *in_lo = get_in_reg(node, 0);
2965 const arch_register_t *in_hi = get_in_reg(node, 1);
2966 const arch_register_t *out_lo = get_out_reg(node, 0);
2967 const arch_register_t *out_hi = get_out_reg(node, 1);
2969 if (out_lo == in_lo) {
2970 if (out_hi != in_hi) {
2971 /* a -> a, b -> d */
2974 /* a -> a, b -> b */
2977 } else if (out_lo == in_hi) {
2978 if (out_hi == in_lo) {
2979 /* a -> b, b -> a */
2980 bemit_helper_xchg(in_lo, in_hi);
2983 /* a -> b, b -> d */
2984 bemit_helper_mov(in_hi, out_hi);
2985 bemit_helper_mov(in_lo, out_lo);
2989 if (out_hi == in_lo) {
2990 /* a -> c, b -> a */
2991 bemit_helper_mov(in_lo, out_lo);
2993 } else if (out_hi == in_hi) {
2994 /* a -> c, b -> b */
2995 bemit_helper_mov(in_lo, out_lo);
2998 /* a -> c, b -> d */
2999 bemit_helper_mov(in_lo, out_lo);
3005 bemit_helper_neg( out_hi);
3006 bemit_helper_neg( out_lo);
3007 bemit_helper_sbb0(out_hi);
3011 bemit_helper_zero(out_hi);
3012 bemit_helper_neg( out_lo);
3013 bemit_helper_sbb( in_hi, out_hi);
3017 * Emit a single opcode.
3019 #define EMIT_SINGLEOP(op, code) \
3020 static void bemit_ ## op(const ir_node *node) { \
3025 //EMIT_SINGLEOP(daa, 0x27)
3026 //EMIT_SINGLEOP(das, 0x2F)
3027 //EMIT_SINGLEOP(aaa, 0x37)
3028 //EMIT_SINGLEOP(aas, 0x3F)
3029 //EMIT_SINGLEOP(nop, 0x90)
3030 EMIT_SINGLEOP(cwtl, 0x98)
3031 EMIT_SINGLEOP(cltd, 0x99)
3032 //EMIT_SINGLEOP(fwait, 0x9B)
3033 EMIT_SINGLEOP(sahf, 0x9E)
3034 //EMIT_SINGLEOP(popf, 0x9D)
3035 EMIT_SINGLEOP(leave, 0xC9)
3036 EMIT_SINGLEOP(int3, 0xCC)
3037 //EMIT_SINGLEOP(iret, 0xCF)
3038 //EMIT_SINGLEOP(xlat, 0xD7)
3039 //EMIT_SINGLEOP(lock, 0xF0)
3040 EMIT_SINGLEOP(rep, 0xF3)
3041 //EMIT_SINGLEOP(halt, 0xF4)
3042 EMIT_SINGLEOP(cmc, 0xF5)
3043 EMIT_SINGLEOP(stc, 0xF9)
3044 //EMIT_SINGLEOP(cli, 0xFA)
3045 //EMIT_SINGLEOP(sti, 0xFB)
3046 //EMIT_SINGLEOP(std, 0xFD)
3049 * Emits a MOV out, [MEM].
3051 static void bemit_load(const ir_node *node)
3053 const arch_register_t *out = get_out_reg(node, 0);
3055 if (out->index == REG_GP_EAX) {
3056 ir_node *base = get_irn_n(node, n_ia32_base);
3057 int has_base = !is_ia32_NoReg_GP(base);
3058 ir_node *idx = get_irn_n(node, n_ia32_index);
3059 int has_index = !is_ia32_NoReg_GP(idx);
3060 if (!has_base && !has_index) {
3061 ir_entity *ent = get_ia32_am_sc(node);
3062 int offs = get_ia32_am_offs_int(node);
3063 /* load from constant address to EAX can be encoded
3066 bemit_entity(ent, 0, offs, false);
3071 bemit_mod_am(reg_gp_map[out->index], node);
3075 * Emits a MOV [mem], in.
3077 static void bemit_store(const ir_node *node)
3079 const ir_node *value = get_irn_n(node, n_ia32_Store_val);
3080 unsigned size = get_mode_size_bits(get_ia32_ls_mode(node));
3082 if (is_ia32_Immediate(value)) {
3085 bemit_mod_am(0, node);
3086 bemit8(get_ia32_immediate_attr_const(value)->offset);
3087 } else if (size == 16) {
3090 bemit_mod_am(0, node);
3091 bemit16(get_ia32_immediate_attr_const(value)->offset);
3094 bemit_mod_am(0, node);
3095 bemit_immediate(value, false);
3098 const arch_register_t *in = get_in_reg(node, n_ia32_Store_val);
3100 if (in->index == REG_GP_EAX) {
3101 ir_node *base = get_irn_n(node, n_ia32_base);
3102 int has_base = !is_ia32_NoReg_GP(base);
3103 ir_node *idx = get_irn_n(node, n_ia32_index);
3104 int has_index = !is_ia32_NoReg_GP(idx);
3105 if (!has_base && !has_index) {
3106 ir_entity *ent = get_ia32_am_sc(node);
3107 int offs = get_ia32_am_offs_int(node);
3108 /* store to constant address from EAX can be encoded as
3109 * 0xA2/0xA3 [offset]*/
3117 bemit_entity(ent, 0, offs, false);
3129 bemit_mod_am(reg_gp_map[in->index], node);
3133 static void bemit_conv_i2i(const ir_node *node)
3135 ir_mode *smaller_mode = get_ia32_ls_mode(node);
3144 if (mode_is_signed(smaller_mode)) opcode |= 0x08;
3145 if (get_mode_size_bits(smaller_mode) == 16) opcode |= 0x01;
3146 bemit_unop_reg(node, opcode, n_ia32_Conv_I2I_val);
3152 static void bemit_push(const ir_node *node)
3154 const ir_node *value = get_irn_n(node, n_ia32_Push_val);
3156 if (is_ia32_Immediate(value)) {
3157 const ia32_immediate_attr_t *attr
3158 = get_ia32_immediate_attr_const(value);
3159 unsigned size = get_signed_imm_size(attr->offset);
3165 bemit8((unsigned char)attr->offset);
3170 bemit_immediate(value, false);
3173 } else if (is_ia32_NoReg_GP(value)) {
3175 bemit_mod_am(6, node);
3177 const arch_register_t *reg = get_in_reg(node, n_ia32_Push_val);
3178 bemit8(0x50 + reg_gp_map[reg->index]);
3185 static void bemit_pop(const ir_node *node)
3187 const arch_register_t *reg = get_out_reg(node, pn_ia32_Pop_res);
3188 bemit8(0x58 + reg_gp_map[reg->index]);
3191 static void bemit_popmem(const ir_node *node)
3194 bemit_mod_am(0, node);
3197 static void bemit_call(const ir_node *node)
3199 ir_node *proc = get_irn_n(node, n_ia32_Call_addr);
3201 if (is_ia32_Immediate(proc)) {
3203 bemit_immediate(proc, true);
3205 bemit_unop(node, 0xFF, 2, n_ia32_Call_addr);
3209 static void bemit_jmp(const ir_node *dest_block)
3212 bemit_jmp_destination(dest_block);
3215 static void bemit_jump(const ir_node *node)
3217 if (can_be_fallthrough(node))
3220 bemit_jmp(get_cfop_target_block(node));
3223 static void bemit_jcc(int pnc, const ir_node *dest_block)
3225 unsigned char cc = pnc2cc(pnc);
3228 bemit_jmp_destination(dest_block);
3231 static void bemit_jp(bool odd, const ir_node *dest_block)
3235 bemit_jmp_destination(dest_block);
3238 static void bemit_ia32_jcc(const ir_node *node)
3240 ia32_condition_code_t cc = get_ia32_condcode(node);
3241 const ir_node *proj_true;
3242 const ir_node *proj_false;
3243 const ir_node *dest_true;
3244 const ir_node *dest_false;
3246 cc = determine_final_cc(node, 0, cc);
3248 /* get both Projs */
3249 proj_true = get_proj(node, pn_ia32_Jcc_true);
3250 assert(proj_true && "Jcc without true Proj");
3252 proj_false = get_proj(node, pn_ia32_Jcc_false);
3253 assert(proj_false && "Jcc without false Proj");
3255 if (can_be_fallthrough(proj_true)) {
3256 /* exchange both proj's so the second one can be omitted */
3257 const ir_node *t = proj_true;
3259 proj_true = proj_false;
3261 cc = ia32_negate_condition_code(cc);
3264 dest_true = get_cfop_target_block(proj_true);
3265 dest_false = get_cfop_target_block(proj_false);
3267 if (cc & ia32_cc_float_parity_cases) {
3268 /* Some floating point comparisons require a test of the parity flag,
3269 * which indicates that the result is unordered */
3270 if (cc & ia32_cc_negated) {
3271 bemit_jp(false, dest_true);
3273 /* we need a local label if the false proj is a fallthrough
3274 * as the falseblock might have no label emitted then */
3275 if (can_be_fallthrough(proj_false)) {
3277 bemit8(0x06); // jp + 6
3279 bemit_jp(false, dest_false);
3283 bemit_jcc(cc, dest_true);
3285 /* the second Proj might be a fallthrough */
3286 if (can_be_fallthrough(proj_false)) {
3287 /* it's a fallthrough */
3289 bemit_jmp(dest_false);
3293 static void bemit_switchjmp(const ir_node *node)
3295 ir_entity *jump_table = get_ia32_am_sc(node);
3296 long default_pn = get_ia32_default_pn(node);
3298 bemit8(0xFF); // jmp *tbl.label(,%in,4)
3299 bemit_mod_am(0x05, node);
3301 emit_jump_table(node, default_pn, jump_table, get_cfop_target_block);
3307 static void bemit_return(const ir_node *node)
3309 unsigned pop = be_Return_get_pop(node);
3310 if (pop > 0 || be_Return_get_emit_pop(node)) {
3312 assert(pop <= 0xffff);
3319 static void bemit_subsp(const ir_node *node)
3321 const arch_register_t *out;
3324 /* mov %esp, %out */
3326 out = get_out_reg(node, 1);
3327 bemit8(MOD_REG | ENC_REG(reg_gp_map[out->index]) | ENC_RM(0x04));
3330 static void bemit_incsp(const ir_node *node)
3333 const arch_register_t *reg;
3337 offs = be_get_IncSP_offset(node);
3348 size = get_signed_imm_size(offs);
3349 bemit8(size == 1 ? 0x83 : 0x81);
3351 reg = get_out_reg(node, 0);
3352 bemit_modru(reg, ext);
3361 static void bemit_copybi(const ir_node *node)
3363 unsigned size = get_ia32_copyb_size(node);
3365 bemit8(0xA4); // movsb
3368 bemit8(0xA5); // movsw
3372 bemit8(0xA5); // movsl
3376 static void bemit_fbinop(const ir_node *node, unsigned code, unsigned code_to)
3378 if (get_ia32_op_type(node) == ia32_Normal) {
3379 const ia32_x87_attr_t *x87_attr = get_ia32_x87_attr_const(node);
3380 const arch_register_t *in1 = x87_attr->x87[0];
3381 const arch_register_t *in = x87_attr->x87[1];
3382 const arch_register_t *out = x87_attr->x87[2];
3386 } else if (out == in) {
3390 if (out->index == 0) {
3392 bemit8(MOD_REG | ENC_REG(code) | ENC_RM(in->index));
3395 bemit8(MOD_REG | ENC_REG(code_to) | ENC_RM(out->index));
3398 if (get_mode_size_bits(get_ia32_ls_mode(node)) == 32) {
3403 bemit_mod_am(code, node);
3407 static void bemit_fbinopp(const ir_node *node, unsigned const code)
3409 const ia32_x87_attr_t *x87_attr = get_ia32_x87_attr_const(node);
3410 const arch_register_t *out = x87_attr->x87[2];
3412 bemit8(code + out->index);
3415 static void bemit_fabs(const ir_node *node)
3423 static void bemit_fadd(const ir_node *node)
3425 bemit_fbinop(node, 0, 0);
3428 static void bemit_faddp(const ir_node *node)
3430 bemit_fbinopp(node, 0xC0);
3433 static void bemit_fchs(const ir_node *node)
3441 static void bemit_fdiv(const ir_node *node)
3443 bemit_fbinop(node, 6, 7);
3446 static void bemit_fdivp(const ir_node *node)
3448 bemit_fbinopp(node, 0xF8);
3451 static void bemit_fdivr(const ir_node *node)
3453 bemit_fbinop(node, 7, 6);
3456 static void bemit_fdivrp(const ir_node *node)
3458 bemit_fbinopp(node, 0xF0);
3461 static void bemit_fild(const ir_node *node)
3463 switch (get_mode_size_bits(get_ia32_ls_mode(node))) {
3465 bemit8(0xDF); // filds
3466 bemit_mod_am(0, node);
3470 bemit8(0xDB); // fildl
3471 bemit_mod_am(0, node);
3475 bemit8(0xDF); // fildll
3476 bemit_mod_am(5, node);
3480 panic("invalid mode size");
3484 static void bemit_fist(const ir_node *node)
3486 switch (get_mode_size_bits(get_ia32_ls_mode(node))) {
3488 bemit8(0xDF); // fists
3492 bemit8(0xDB); // fistl
3496 panic("invalid mode size");
3498 bemit_mod_am(2, node);
3501 static void bemit_fistp(const ir_node *node)
3503 switch (get_mode_size_bits(get_ia32_ls_mode(node))) {
3505 bemit8(0xDF); // fistps
3506 bemit_mod_am(3, node);
3510 bemit8(0xDB); // fistpl
3511 bemit_mod_am(3, node);
3515 bemit8(0xDF); // fistpll
3516 bemit_mod_am(7, node);
3520 panic("invalid mode size");
3524 static void bemit_fld(const ir_node *node)
3526 switch (get_mode_size_bits(get_ia32_ls_mode(node))) {
3528 bemit8(0xD9); // flds
3529 bemit_mod_am(0, node);
3533 bemit8(0xDD); // fldl
3534 bemit_mod_am(0, node);
3539 bemit8(0xDB); // fldt
3540 bemit_mod_am(5, node);
3544 panic("invalid mode size");
3548 static void bemit_fld1(const ir_node *node)
3552 bemit8(0xE8); // fld1
3555 static void bemit_fldcw(const ir_node *node)
3557 bemit8(0xD9); // fldcw
3558 bemit_mod_am(5, node);
3561 static void bemit_fldz(const ir_node *node)
3565 bemit8(0xEE); // fldz
3568 static void bemit_fmul(const ir_node *node)
3570 bemit_fbinop(node, 1, 1);
3573 static void bemit_fmulp(const ir_node *node)
3575 bemit_fbinopp(node, 0xC8);
3578 static void bemit_fpop(const ir_node *node)
3580 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
3582 bemit8(0xD8 + attr->x87[0]->index);
3585 static void bemit_fpush(const ir_node *node)
3587 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
3589 bemit8(0xC0 + attr->x87[0]->index);
3592 static void bemit_fpushcopy(const ir_node *node)
3594 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
3596 bemit8(0xC0 + attr->x87[0]->index);
3599 static void bemit_fst(const ir_node *node)
3601 switch (get_mode_size_bits(get_ia32_ls_mode(node))) {
3603 bemit8(0xD9); // fsts
3607 bemit8(0xDD); // fstl
3611 panic("invalid mode size");
3613 bemit_mod_am(2, node);
3616 static void bemit_fstp(const ir_node *node)
3618 switch (get_mode_size_bits(get_ia32_ls_mode(node))) {
3620 bemit8(0xD9); // fstps
3621 bemit_mod_am(3, node);
3625 bemit8(0xDD); // fstpl
3626 bemit_mod_am(3, node);
3631 bemit8(0xDB); // fstpt
3632 bemit_mod_am(7, node);
3636 panic("invalid mode size");
3640 static void bemit_fsub(const ir_node *node)
3642 bemit_fbinop(node, 4, 5);
3645 static void bemit_fsubp(const ir_node *node)
3647 bemit_fbinopp(node, 0xE8);
3650 static void bemit_fsubr(const ir_node *node)
3652 bemit_fbinop(node, 5, 4);
3655 static void bemit_fsubrp(const ir_node *node)
3657 bemit_fbinopp(node, 0xE0);
3660 static void bemit_fnstcw(const ir_node *node)
3662 bemit8(0xD9); // fnstcw
3663 bemit_mod_am(7, node);
3666 static void bemit_fnstsw(void)
3668 bemit8(0xDF); // fnstsw %ax
3672 static void bemit_ftstfnstsw(const ir_node *node)
3676 bemit8(0xD9); // ftst
3681 static void bemit_fucomi(const ir_node *node)
3683 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
3684 bemit8(0xDB); // fucomi
3685 bemit8(0xE8 + attr->x87[1]->index);
3688 static void bemit_fucomip(const ir_node *node)
3690 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
3691 bemit8(0xDF); // fucomip
3692 bemit8(0xE8 + attr->x87[1]->index);
3695 static void bemit_fucomfnstsw(const ir_node *node)
3697 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
3698 bemit8(0xDD); // fucom
3699 bemit8(0xE0 + attr->x87[1]->index);
3703 static void bemit_fucompfnstsw(const ir_node *node)
3705 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
3706 bemit8(0xDD); // fucomp
3707 bemit8(0xE8 + attr->x87[1]->index);
3711 static void bemit_fucomppfnstsw(const ir_node *node)
3715 bemit8(0xDA); // fucompp
3720 static void bemit_fxch(const ir_node *node)
3722 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
3724 bemit8(0xC8 + attr->x87[0]->index);
3728 * The type of a emitter function.
3730 typedef void (*emit_func) (const ir_node *);
3733 * Set a node emitter. Make it a bit more type safe.
3735 static void register_emitter(ir_op *op, emit_func func)
3737 op->ops.generic = (op_func) func;
3740 static void ia32_register_binary_emitters(void)
3742 /* first clear the generic function pointer for all ops */
3743 clear_irp_opcodes_generic_func();
3745 /* benode emitter */
3746 register_emitter(op_be_Copy, bemit_copy);
3747 register_emitter(op_be_CopyKeep, bemit_copy);
3748 register_emitter(op_be_IncSP, bemit_incsp);
3749 register_emitter(op_be_Perm, bemit_perm);
3750 register_emitter(op_be_Return, bemit_return);
3751 register_emitter(op_ia32_Adc, bemit_adc);
3752 register_emitter(op_ia32_Add, bemit_add);
3753 register_emitter(op_ia32_AddMem, bemit_addmem);
3754 register_emitter(op_ia32_AddMem8Bit, bemit_addmem8bit);
3755 register_emitter(op_ia32_And, bemit_and);
3756 register_emitter(op_ia32_AndMem, bemit_andmem);
3757 register_emitter(op_ia32_AndMem8Bit, bemit_andmem8bit);
3758 register_emitter(op_ia32_Breakpoint, bemit_int3);
3759 register_emitter(op_ia32_CMovcc, bemit_cmovcc);
3760 register_emitter(op_ia32_Call, bemit_call);
3761 register_emitter(op_ia32_Cltd, bemit_cltd);
3762 register_emitter(op_ia32_Cmc, bemit_cmc);
3763 register_emitter(op_ia32_Cmp, bemit_cmp);
3764 register_emitter(op_ia32_Cmp8Bit, bemit_cmp8bit);
3765 register_emitter(op_ia32_Const, bemit_mov_const);
3766 register_emitter(op_ia32_Conv_I2I, bemit_conv_i2i);
3767 register_emitter(op_ia32_Conv_I2I8Bit, bemit_conv_i2i);
3768 register_emitter(op_ia32_CopyB_i, bemit_copybi);
3769 register_emitter(op_ia32_Cwtl, bemit_cwtl);
3770 register_emitter(op_ia32_Dec, bemit_dec);
3771 register_emitter(op_ia32_DecMem, bemit_decmem);
3772 register_emitter(op_ia32_Div, bemit_div);
3773 register_emitter(op_ia32_FldCW, bemit_fldcw);
3774 register_emitter(op_ia32_FnstCW, bemit_fnstcw);
3775 register_emitter(op_ia32_FtstFnstsw, bemit_ftstfnstsw);
3776 register_emitter(op_ia32_FucomFnstsw, bemit_fucomfnstsw);
3777 register_emitter(op_ia32_Fucomi, bemit_fucomi);
3778 register_emitter(op_ia32_FucompFnstsw, bemit_fucompfnstsw);
3779 register_emitter(op_ia32_Fucompi, bemit_fucomip);
3780 register_emitter(op_ia32_FucomppFnstsw, bemit_fucomppfnstsw);
3781 register_emitter(op_ia32_IDiv, bemit_idiv);
3782 register_emitter(op_ia32_IJmp, bemit_ijmp);
3783 register_emitter(op_ia32_IMul, bemit_imul);
3784 register_emitter(op_ia32_IMul1OP, bemit_imul1op);
3785 register_emitter(op_ia32_Inc, bemit_inc);
3786 register_emitter(op_ia32_IncMem, bemit_incmem);
3787 register_emitter(op_ia32_Jcc, bemit_ia32_jcc);
3788 register_emitter(op_ia32_Jmp, bemit_jump);
3789 register_emitter(op_ia32_LdTls, bemit_ldtls);
3790 register_emitter(op_ia32_Lea, bemit_lea);
3791 register_emitter(op_ia32_Leave, bemit_leave);
3792 register_emitter(op_ia32_Load, bemit_load);
3793 register_emitter(op_ia32_Minus64Bit, bemit_minus64bit);
3794 register_emitter(op_ia32_Mul, bemit_mul);
3795 register_emitter(op_ia32_Neg, bemit_neg);
3796 register_emitter(op_ia32_NegMem, bemit_negmem);
3797 register_emitter(op_ia32_Not, bemit_not);
3798 register_emitter(op_ia32_NotMem, bemit_notmem);
3799 register_emitter(op_ia32_Or, bemit_or);
3800 register_emitter(op_ia32_OrMem, bemit_ormem);
3801 register_emitter(op_ia32_OrMem8Bit, bemit_ormem8bit);
3802 register_emitter(op_ia32_Pop, bemit_pop);
3803 register_emitter(op_ia32_PopEbp, bemit_pop);
3804 register_emitter(op_ia32_PopMem, bemit_popmem);
3805 register_emitter(op_ia32_Push, bemit_push);
3806 register_emitter(op_ia32_RepPrefix, bemit_rep);
3807 register_emitter(op_ia32_Rol, bemit_rol);
3808 register_emitter(op_ia32_RolMem, bemit_rolmem);
3809 register_emitter(op_ia32_Ror, bemit_ror);
3810 register_emitter(op_ia32_RorMem, bemit_rormem);
3811 register_emitter(op_ia32_Sahf, bemit_sahf);
3812 register_emitter(op_ia32_Sar, bemit_sar);
3813 register_emitter(op_ia32_SarMem, bemit_sarmem);
3814 register_emitter(op_ia32_Sbb, bemit_sbb);
3815 register_emitter(op_ia32_Setcc, bemit_setcc);
3816 register_emitter(op_ia32_Shl, bemit_shl);
3817 register_emitter(op_ia32_ShlD, bemit_shld);
3818 register_emitter(op_ia32_ShlMem, bemit_shlmem);
3819 register_emitter(op_ia32_Shr, bemit_shr);
3820 register_emitter(op_ia32_ShrD, bemit_shrd);
3821 register_emitter(op_ia32_ShrMem, bemit_shrmem);
3822 register_emitter(op_ia32_Stc, bemit_stc);
3823 register_emitter(op_ia32_Store, bemit_store);
3824 register_emitter(op_ia32_Store8Bit, bemit_store);
3825 register_emitter(op_ia32_Sub, bemit_sub);
3826 register_emitter(op_ia32_SubMem, bemit_submem);
3827 register_emitter(op_ia32_SubMem8Bit, bemit_submem8bit);
3828 register_emitter(op_ia32_SubSP, bemit_subsp);
3829 register_emitter(op_ia32_SwitchJmp, bemit_switchjmp);
3830 register_emitter(op_ia32_Test, bemit_test);
3831 register_emitter(op_ia32_Test8Bit, bemit_test8bit);
3832 register_emitter(op_ia32_Xor, bemit_xor);
3833 register_emitter(op_ia32_Xor0, bemit_xor0);
3834 register_emitter(op_ia32_XorMem, bemit_xormem);
3835 register_emitter(op_ia32_XorMem8Bit, bemit_xormem8bit);
3836 register_emitter(op_ia32_fabs, bemit_fabs);
3837 register_emitter(op_ia32_fadd, bemit_fadd);
3838 register_emitter(op_ia32_faddp, bemit_faddp);
3839 register_emitter(op_ia32_fchs, bemit_fchs);
3840 register_emitter(op_ia32_fdiv, bemit_fdiv);
3841 register_emitter(op_ia32_fdivp, bemit_fdivp);
3842 register_emitter(op_ia32_fdivr, bemit_fdivr);
3843 register_emitter(op_ia32_fdivrp, bemit_fdivrp);
3844 register_emitter(op_ia32_fild, bemit_fild);
3845 register_emitter(op_ia32_fist, bemit_fist);
3846 register_emitter(op_ia32_fistp, bemit_fistp);
3847 register_emitter(op_ia32_fld, bemit_fld);
3848 register_emitter(op_ia32_fld1, bemit_fld1);
3849 register_emitter(op_ia32_fldz, bemit_fldz);
3850 register_emitter(op_ia32_fmul, bemit_fmul);
3851 register_emitter(op_ia32_fmulp, bemit_fmulp);
3852 register_emitter(op_ia32_fpop, bemit_fpop);
3853 register_emitter(op_ia32_fpush, bemit_fpush);
3854 register_emitter(op_ia32_fpushCopy, bemit_fpushcopy);
3855 register_emitter(op_ia32_fst, bemit_fst);
3856 register_emitter(op_ia32_fstp, bemit_fstp);
3857 register_emitter(op_ia32_fsub, bemit_fsub);
3858 register_emitter(op_ia32_fsubp, bemit_fsubp);
3859 register_emitter(op_ia32_fsubr, bemit_fsubr);
3860 register_emitter(op_ia32_fsubrp, bemit_fsubrp);
3861 register_emitter(op_ia32_fxch, bemit_fxch);
3863 /* ignore the following nodes */
3864 register_emitter(op_ia32_ProduceVal, emit_Nothing);
3865 register_emitter(op_be_Keep, emit_Nothing);
3866 register_emitter(op_be_Start, emit_Nothing);
3867 register_emitter(op_Phi, emit_Nothing);
3868 register_emitter(op_Start, emit_Nothing);
3871 static void gen_binary_block(ir_node *block)
3875 ia32_emit_block_header(block);
3877 /* emit the contents of the block */
3878 sched_foreach(block, node) {
3879 ia32_emit_node(node);
3883 void ia32_gen_binary_routine(ir_graph *irg)
3885 ir_entity *entity = get_irg_entity(irg);
3886 const arch_env_t *arch_env = be_get_irg_arch_env(irg);
3887 ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
3888 ir_node **blk_sched = irg_data->blk_sched;
3891 isa = (ia32_isa_t*) arch_env;
3893 ia32_register_binary_emitters();
3895 be_gas_emit_function_prolog(entity, ia32_cg_config.function_alignment);
3897 /* we use links to point to target blocks */
3898 ir_reserve_resources(irg, IR_RESOURCE_IRN_LINK);
3899 irg_block_walk_graph(irg, ia32_gen_labels, NULL, NULL);
3901 /* initialize next block links */
3902 n = ARR_LEN(blk_sched);
3903 for (i = 0; i < n; ++i) {
3904 ir_node *block = blk_sched[i];
3905 ir_node *prev = i > 0 ? blk_sched[i-1] : NULL;
3907 set_irn_link(block, prev);
3910 for (i = 0; i < n; ++i) {
3911 ir_node *block = blk_sched[i];
3912 gen_binary_block(block);
3915 be_gas_emit_function_epilog(entity);
3916 be_dbg_method_end();
3918 be_emit_write_line();
3920 ir_free_resources(irg, IR_RESOURCE_IRN_LINK);
3924 void ia32_init_emitter(void)
3926 lc_opt_entry_t *be_grp;
3927 lc_opt_entry_t *ia32_grp;
3929 be_grp = lc_opt_get_grp(firm_opt_get_root(), "be");
3930 ia32_grp = lc_opt_get_grp(be_grp, "ia32");
3932 lc_opt_add_table(ia32_grp, ia32_emitter_options);
3936 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.emitter");