2 * Copyright (C) 1995-2007 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This file implements the ia32 node emitter.
23 * @author Christian Wuerdig, Matthias Braun
41 #include "iredges_t.h"
44 #include "raw_bitset.h"
46 #include "../besched_t.h"
47 #include "../benode_t.h"
49 #include "../be_dbgout.h"
50 #include "../beemitter.h"
51 #include "../begnuas.h"
52 #include "../beirg_t.h"
54 #include "ia32_emitter.h"
55 #include "gen_ia32_emitter.h"
56 #include "gen_ia32_regalloc_if.h"
57 #include "ia32_nodes_attr.h"
58 #include "ia32_new_nodes.h"
59 #include "ia32_map_regs.h"
60 #include "bearch_ia32_t.h"
62 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
64 #define BLOCK_PREFIX ".L"
66 #define SNPRINTF_BUF_LEN 128
69 * Returns the register at in position pos.
72 const arch_register_t *get_in_reg(ia32_emit_env_t *env, const ir_node *irn,
75 const arch_env_t *arch_env = env->arch_env;
77 const arch_register_t *reg = NULL;
79 assert(get_irn_arity(irn) > pos && "Invalid IN position");
81 /* The out register of the operator at position pos is the
82 in register we need. */
83 op = get_irn_n(irn, pos);
85 reg = arch_get_irn_register(arch_env, op);
87 assert(reg && "no in register found");
89 /* in case of a joker register: just return a valid register */
90 if (arch_register_type_is(reg, joker)) {
91 const arch_register_req_t *req;
93 /* ask for the requirements */
94 req = arch_get_register_req(arch_env, irn, pos);
96 if (arch_register_req_is(req, limited)) {
97 /* in case of limited requirements: get the first allowed register */
98 unsigned idx = rbitset_next(req->limited, 0, 1);
99 reg = arch_register_for_index(req->cls, idx);
101 /* otherwise get first register in class */
102 reg = arch_register_for_index(req->cls, 0);
110 * Returns the register at out position pos.
113 const arch_register_t *get_out_reg(ia32_emit_env_t *env, const ir_node *irn,
116 const arch_env_t *arch_env = env->arch_env;
118 const arch_register_t *reg = NULL;
120 /* 1st case: irn is not of mode_T, so it has only */
121 /* one OUT register -> good */
122 /* 2nd case: irn is of mode_T -> collect all Projs and ask the */
123 /* Proj with the corresponding projnum for the register */
125 if (get_irn_mode(irn) != mode_T) {
126 reg = arch_get_irn_register(arch_env, irn);
127 } else if (is_ia32_irn(irn)) {
128 reg = get_ia32_out_reg(irn, pos);
130 const ir_edge_t *edge;
132 foreach_out_edge(irn, edge) {
133 proj = get_edge_src_irn(edge);
134 assert(is_Proj(proj) && "non-Proj from mode_T node");
135 if (get_Proj_proj(proj) == pos) {
136 reg = arch_get_irn_register(arch_env, proj);
142 assert(reg && "no out register found");
147 * Determine the gnu assembler suffix that indicates a mode
150 char get_mode_suffix(const ir_mode *mode) {
151 if(mode_is_float(mode)) {
152 switch(get_mode_size_bits(mode)) {
161 assert(mode_is_int(mode) || mode_is_reference(mode) || mode_is_character(mode));
162 switch(get_mode_size_bits(mode)) {
173 panic("Can't output mode_suffix for %+F\n", mode);
177 int produces_result(const ir_node *node) {
178 return !(is_ia32_St(node) ||
179 is_ia32_CondJmp(node) ||
180 is_ia32_xCondJmp(node) ||
181 is_ia32_CmpSet(node) ||
182 is_ia32_xCmpSet(node) ||
183 is_ia32_SwitchJmp(node));
187 const char *ia32_get_reg_name_for_mode(ia32_emit_env_t *env, ir_mode *mode,
188 const arch_register_t *reg) {
189 switch(get_mode_size_bits(mode)) {
191 return ia32_get_mapped_reg_name(env->isa->regs_8bit, reg);
193 return ia32_get_mapped_reg_name(env->isa->regs_16bit, reg);
195 return (char *)arch_register_get_name(reg);
200 * Add a number to a prefix. This number will not be used a second time.
203 char *get_unique_label(char *buf, size_t buflen, const char *prefix) {
204 static unsigned long id = 0;
205 snprintf(buf, buflen, "%s%lu", prefix, ++id);
209 /*************************************************************
211 * (_) | | / _| | | | |
212 * _ __ _ __ _ _ __ | |_| |_ | |__ ___| |_ __ ___ _ __
213 * | '_ \| '__| | '_ \| __| _| | '_ \ / _ \ | '_ \ / _ \ '__|
214 * | |_) | | | | | | | |_| | | | | | __/ | |_) | __/ |
215 * | .__/|_| |_|_| |_|\__|_| |_| |_|\___|_| .__/ \___|_|
218 *************************************************************/
220 // we have no C++ and can't define an implicit ia32_emit_env_t* cast to
221 // be_emit_env_t* so we cheat a bit...
222 #define be_emit_char(env,c) be_emit_char(env->emit,c)
223 #define be_emit_string(env,s) be_emit_string(env->emit,s)
224 #undef be_emit_cstring
225 #define be_emit_cstring(env,x) { be_emit_string_len(env->emit, x, sizeof(x)-1); }
226 #define be_emit_ident(env,i) be_emit_ident(env->emit,i)
227 #define be_emit_write_line(env) be_emit_write_line(env->emit)
228 #define be_emit_finish_line_gas(env,n) be_emit_finish_line_gas(env->emit,n)
229 #define be_emit_pad_comment(env) be_emit_pad_comment(env->emit)
231 void ia32_emit_source_register(ia32_emit_env_t *env, const ir_node *node, int pos)
233 const arch_register_t *reg = get_in_reg(env, node, pos);
234 const char *reg_name = arch_register_get_name(reg);
236 assert(pos < get_irn_arity(node));
238 be_emit_char(env, '%');
239 be_emit_string(env, reg_name);
242 void ia32_emit_dest_register(ia32_emit_env_t *env, const ir_node *node, int pos) {
243 const arch_register_t *reg = get_out_reg(env, node, pos);
244 const char *reg_name = arch_register_get_name(reg);
246 be_emit_char(env, '%');
247 be_emit_string(env, reg_name);
250 void ia32_emit_x87_name(ia32_emit_env_t *env, const ir_node *node, int pos)
252 ia32_attr_t *attr = get_ia32_attr(node);
255 be_emit_char(env, '%');
256 be_emit_string(env, attr->x87[pos]->name);
259 void ia32_emit_immediate(ia32_emit_env_t *env, const ir_node *node)
265 be_emit_char(env, '$');
267 switch(get_ia32_immop_type(node)) {
269 tv = get_ia32_Immop_tarval(node);
270 be_emit_tarval(env->emit, tv);
272 case ia32_ImmSymConst:
273 ent = get_ia32_Immop_symconst(node);
274 mark_entity_visited(ent);
275 id = get_entity_ld_ident(ent);
276 be_emit_ident(env, id);
283 be_emit_string(env, "BAD");
288 void ia32_emit_mode_suffix_mode(ia32_emit_env_t *env, const ir_mode *mode)
290 be_emit_char(env, get_mode_suffix(mode));
293 void ia32_emit_mode_suffix(ia32_emit_env_t *env, const ir_node *node)
295 ir_mode *mode = get_ia32_ls_mode(node);
299 ia32_emit_mode_suffix_mode(env, mode);
302 void ia32_emit_x87_mode_suffix(ia32_emit_env_t *env, const ir_node *node)
304 ir_mode *mode = get_ia32_ls_mode(node);
306 ia32_emit_mode_suffix_mode(env, mode);
310 char get_xmm_mode_suffix(ir_mode *mode)
312 assert(mode_is_float(mode));
313 switch(get_mode_size_bits(mode)) {
324 void ia32_emit_xmm_mode_suffix(ia32_emit_env_t *env, const ir_node *node)
326 ir_mode *mode = get_ia32_ls_mode(node);
327 assert(mode != NULL);
328 be_emit_char(env, 's');
329 be_emit_char(env, get_xmm_mode_suffix(mode));
332 void ia32_emit_xmm_mode_suffix_s(ia32_emit_env_t *env, const ir_node *node)
334 ir_mode *mode = get_ia32_ls_mode(node);
335 assert(mode != NULL);
336 be_emit_char(env, get_xmm_mode_suffix(mode));
339 void ia32_emit_extend_suffix(ia32_emit_env_t *env, const ir_mode *mode)
341 if(get_mode_size_bits(mode) == 32)
343 if(mode_is_signed(mode)) {
344 be_emit_char(env, 's');
346 be_emit_char(env, 'z');
351 void ia32_emit_function_object(ia32_emit_env_t *env, const char *name)
353 switch (be_gas_flavour) {
354 case GAS_FLAVOUR_NORMAL:
355 be_emit_cstring(env, "\t.type\t");
356 be_emit_string(env, name);
357 be_emit_cstring(env, ", @function\n");
358 be_emit_write_line(env);
360 case GAS_FLAVOUR_MINGW:
361 be_emit_cstring(env, "\t.def\t");
362 be_emit_string(env, name);
363 be_emit_cstring(env, ";\t.scl\t2;\t.type\t32;\t.endef\n");
364 be_emit_write_line(env);
372 void ia32_emit_function_size(ia32_emit_env_t *env, const char *name)
374 switch (be_gas_flavour) {
375 case GAS_FLAVOUR_NORMAL:
376 be_emit_cstring(env, "\t.size\t");
377 be_emit_string(env, name);
378 be_emit_cstring(env, ", .-");
379 be_emit_string(env, name);
380 be_emit_char(env, '\n');
381 be_emit_write_line(env);
391 * Emits registers and/or address mode of a binary operation.
393 void ia32_emit_binop(ia32_emit_env_t *env, const ir_node *node) {
394 switch(get_ia32_op_type(node)) {
396 if (is_ia32_ImmConst(node) || is_ia32_ImmSymConst(node)) {
397 ia32_emit_immediate(env, node);
398 be_emit_cstring(env, ", ");
399 ia32_emit_source_register(env, node, 2);
401 const arch_register_t *in1 = get_in_reg(env, node, 2);
402 const arch_register_t *in2 = get_in_reg(env, node, 3);
403 const arch_register_t *out = produces_result(node) ? get_out_reg(env, node, 0) : NULL;
404 const arch_register_t *in;
407 in = out ? (REGS_ARE_EQUAL(out, in2) ? in1 : in2) : in2;
408 out = out ? out : in1;
409 in_name = arch_register_get_name(in);
411 if (is_ia32_emit_cl(node)) {
412 assert(REGS_ARE_EQUAL(&ia32_gp_regs[REG_ECX], in) && "shift operation needs ecx");
416 be_emit_char(env, '%');
417 be_emit_string(env, in_name);
418 be_emit_cstring(env, ", %");
419 be_emit_string(env, arch_register_get_name(out));
423 ia32_emit_am(env, node);
424 be_emit_cstring(env, ", ");
425 if (is_ia32_ImmConst(node) || is_ia32_ImmSymConst(node)) {
426 assert(!produces_result(node) && "Source AM with Const must not produce result");
427 ia32_emit_immediate(env, node);
428 } else if (produces_result(node)) {
429 ia32_emit_dest_register(env, node, 0);
431 ia32_emit_source_register(env, node, 2);
435 if (is_ia32_ImmConst(node) || is_ia32_ImmSymConst(node)) {
436 ia32_emit_immediate(env, node);
437 be_emit_cstring(env, ", ");
438 ia32_emit_am(env, node);
440 const arch_register_t *in1 = get_in_reg(env, node,
441 get_irn_arity(node) == 5 ? 3 : 2);
442 ir_mode *mode = get_ia32_ls_mode(node);
445 in_name = ia32_get_reg_name_for_mode(env, mode, in1);
447 if (is_ia32_emit_cl(node)) {
448 assert(REGS_ARE_EQUAL(&ia32_gp_regs[REG_ECX], in1) && "shift operation needs ecx");
452 be_emit_char(env, '%');
453 be_emit_string(env, in_name);
454 be_emit_cstring(env, ", ");
455 ia32_emit_am(env, node);
459 assert(0 && "unsupported op type");
464 * Emits registers and/or address mode of a binary operation.
466 void ia32_emit_x87_binop(ia32_emit_env_t *env, const ir_node *node) {
467 switch(get_ia32_op_type(node)) {
469 if (is_ia32_ImmConst(node) || is_ia32_ImmSymConst(node)) {
470 // should not happen...
473 ia32_attr_t *attr = get_ia32_attr(node);
474 const arch_register_t *in1 = attr->x87[0];
475 const arch_register_t *in2 = attr->x87[1];
476 const arch_register_t *out = attr->x87[2];
477 const arch_register_t *in;
479 in = out ? (REGS_ARE_EQUAL(out, in2) ? in1 : in2) : in2;
480 out = out ? out : in1;
482 be_emit_char(env, '%');
483 be_emit_string(env, arch_register_get_name(in));
484 be_emit_cstring(env, ", %");
485 be_emit_string(env, arch_register_get_name(out));
490 ia32_emit_am(env, node);
493 assert(0 && "unsupported op type");
498 * Emits registers and/or address mode of a unary operation.
500 void ia32_emit_unop(ia32_emit_env_t *env, const ir_node *node) {
501 switch(get_ia32_op_type(node)) {
503 if (is_ia32_ImmConst(node) || is_ia32_ImmSymConst(node)) {
504 ia32_emit_immediate(env, node);
506 if (is_ia32_Mul(node) || is_ia32_IMul1OP(node)) {
507 ia32_emit_source_register(env, node, 3);
508 } else if(is_ia32_IDiv(node) || is_ia32_Div(node)) {
509 ia32_emit_source_register(env, node, 4);
510 } else if(is_ia32_Push(node)) {
511 ia32_emit_source_register(env, node, 2);
512 } else if(is_ia32_Pop(node)) {
513 ia32_emit_dest_register(env, node, 1);
515 ia32_emit_dest_register(env, node, 0);
521 ia32_emit_am(env, node);
524 assert(0 && "unsupported op type");
529 * Emits address mode.
531 void ia32_emit_am(ia32_emit_env_t *env, const ir_node *node) {
532 ir_entity *ent = get_ia32_am_sc(node);
533 int offs = get_ia32_am_offs_int(node);
534 ir_node *base = get_irn_n(node, 0);
535 int has_base = !is_ia32_NoReg_GP(base);
536 ir_node *index = get_irn_n(node, 1);
537 int has_index = !is_ia32_NoReg_GP(index);
539 /* just to be sure... */
540 assert(!is_ia32_use_frame(node) || get_ia32_frame_ent(node) != NULL);
546 mark_entity_visited(ent);
547 id = get_entity_ld_ident(ent);
548 if (is_ia32_am_sc_sign(node))
549 be_emit_char(env, '-');
550 be_emit_ident(env, id);
552 if(get_entity_owner(ent) == get_tls_type()) {
553 if (get_entity_visibility(ent) == visibility_external_allocated) {
554 be_emit_cstring(env, "@INDNTPOFF");
556 be_emit_cstring(env, "@NTPOFF");
563 be_emit_irprintf(env->emit, "%+d", offs);
565 be_emit_irprintf(env->emit, "%d", offs);
569 if (has_base || has_index) {
570 be_emit_char(env, '(');
574 ia32_emit_source_register(env, node, 0);
577 /* emit index + scale */
580 be_emit_char(env, ',');
581 ia32_emit_source_register(env, node, 1);
583 scale = get_ia32_am_scale(node);
585 be_emit_irprintf(env->emit, ",%d", 1 << get_ia32_am_scale(node));
588 be_emit_char(env, ')');
592 /*************************************************
595 * ___ _ __ ___ _| |_ ___ ___ _ __ __| |
596 * / _ \ '_ ` _ \| | __| / __/ _ \| '_ \ / _` |
597 * | __/ | | | | | | |_ | (_| (_) | | | | (_| |
598 * \___|_| |_| |_|_|\__| \___\___/|_| |_|\__,_|
600 *************************************************/
603 #define IA32_DO_EMIT(irn) ia32_fprintf_format(F, irn, cmd_buf, cmnt_buf)
606 * coding of conditions
608 struct cmp2conditon_t {
614 * positive conditions for signed compares
617 const struct cmp2conditon_t cmp2condition_s[] = {
618 { NULL, pn_Cmp_False }, /* always false */
619 { "e", pn_Cmp_Eq }, /* == */
620 { "l", pn_Cmp_Lt }, /* < */
621 { "le", pn_Cmp_Le }, /* <= */
622 { "g", pn_Cmp_Gt }, /* > */
623 { "ge", pn_Cmp_Ge }, /* >= */
624 { "ne", pn_Cmp_Lg }, /* != */
625 { NULL, pn_Cmp_Leg}, /* Floating point: ordered */
626 { NULL, pn_Cmp_Uo }, /* Floating point: unordered */
627 { "e", pn_Cmp_Ue }, /* Floating point: unordered or == */
628 { "b", pn_Cmp_Ul }, /* Floating point: unordered or < */
629 { "be", pn_Cmp_Ule }, /* Floating point: unordered or <= */
630 { "a", pn_Cmp_Ug }, /* Floating point: unordered or > */
631 { "ae", pn_Cmp_Uge }, /* Floating point: unordered or >= */
632 { "ne", pn_Cmp_Ne }, /* Floating point: unordered or != */
633 { NULL, pn_Cmp_True }, /* always true */
637 * positive conditions for unsigned compares
640 const struct cmp2conditon_t cmp2condition_u[] = {
641 { NULL, pn_Cmp_False }, /* always false */
642 { "e", pn_Cmp_Eq }, /* == */
643 { "b", pn_Cmp_Lt }, /* < */
644 { "be", pn_Cmp_Le }, /* <= */
645 { "a", pn_Cmp_Gt }, /* > */
646 { "ae", pn_Cmp_Ge }, /* >= */
647 { "ne", pn_Cmp_Lg }, /* != */
648 { NULL, pn_Cmp_True }, /* always true */
652 * returns the condition code
655 const char *get_cmp_suffix(int cmp_code)
657 assert( (cmp2condition_s[cmp_code & 15].num) == (cmp_code & 15));
658 assert( (cmp2condition_u[cmp_code & 7].num) == (cmp_code & 7));
660 if((cmp_code & ia32_pn_Cmp_Unsigned)) {
661 return cmp2condition_u[cmp_code & 7].name;
663 return cmp2condition_s[cmp_code & 15].name;
667 void ia32_emit_cmp_suffix(ia32_emit_env_t *env, long pnc)
669 be_emit_string(env, get_cmp_suffix(pnc));
674 * Returns the target block for a control flow node.
677 ir_node *get_cfop_target_block(const ir_node *irn) {
678 return get_irn_link(irn);
682 void ia32_emit_block_name(ia32_emit_env_t *env, const ir_node *block)
684 be_emit_cstring(env, BLOCK_PREFIX);
685 be_emit_irprintf(env->emit, "%d", get_irn_node_nr(block));
689 * Returns the target label for a control flow node.
692 void ia32_emit_cfop_target(ia32_emit_env_t * env, const ir_node *node) {
693 ir_node *block = get_cfop_target_block(node);
695 ia32_emit_block_name(env, block);
698 /** Return the next block in Block schedule */
699 static ir_node *next_blk_sched(const ir_node *block) {
700 return get_irn_link(block);
704 * Returns the Proj with projection number proj and NOT mode_M
707 ir_node *get_proj(const ir_node *node, long proj) {
708 const ir_edge_t *edge;
711 assert(get_irn_mode(node) == mode_T && "expected mode_T node");
713 foreach_out_edge(node, edge) {
714 src = get_edge_src_irn(edge);
716 assert(is_Proj(src) && "Proj expected");
717 if (get_irn_mode(src) == mode_M)
720 if (get_Proj_proj(src) == proj)
727 * Emits the jump sequence for a conditional jump (cmp + jmp_true + jmp_false)
730 void finish_CondJmp(ia32_emit_env_t *env, const ir_node *node, ir_mode *mode,
732 const ir_node *proj_true;
733 const ir_node *proj_false;
734 const ir_node *block;
735 const ir_node *next_block;
738 /* get both Proj's */
739 proj_true = get_proj(node, pn_Cond_true);
740 assert(proj_true && "CondJmp without true Proj");
742 proj_false = get_proj(node, pn_Cond_false);
743 assert(proj_false && "CondJmp without false Proj");
745 /* for now, the code works for scheduled and non-schedules blocks */
746 block = get_nodes_block(node);
748 /* we have a block schedule */
749 next_block = next_blk_sched(block);
751 if (get_cfop_target_block(proj_true) == next_block) {
752 /* exchange both proj's so the second one can be omitted */
753 const ir_node *t = proj_true;
755 proj_true = proj_false;
758 pnc = get_negated_pnc(pnc, mode);
761 /* in case of unordered compare, check for parity */
762 if (pnc & pn_Cmp_Uo) {
763 be_emit_cstring(env, "\tjp ");
764 ia32_emit_cfop_target(env, proj_true);
765 be_emit_finish_line_gas(env, proj_true);
768 be_emit_cstring(env, "\tj");
769 ia32_emit_cmp_suffix(env, pnc);
770 be_emit_char(env, ' ');
771 ia32_emit_cfop_target(env, proj_true);
772 be_emit_finish_line_gas(env, proj_true);
774 /* the second Proj might be a fallthrough */
775 if (get_cfop_target_block(proj_false) != next_block) {
776 be_emit_cstring(env, "\tjmp ");
777 ia32_emit_cfop_target(env, proj_false);
778 be_emit_finish_line_gas(env, proj_false);
780 be_emit_cstring(env, "\t/* fallthrough to ");
781 ia32_emit_cfop_target(env, proj_false);
782 be_emit_cstring(env, " */");
783 be_emit_finish_line_gas(env, proj_false);
788 * Emits code for conditional jump.
791 void CondJmp_emitter(ia32_emit_env_t *env, const ir_node *node) {
792 be_emit_cstring(env, "\tcmp ");
793 ia32_emit_binop(env, node);
794 be_emit_finish_line_gas(env, node);
796 finish_CondJmp(env, node, mode_Iu, get_ia32_pncode(node));
800 * Emits code for conditional jump with two variables.
803 void emit_ia32_CondJmp(ia32_emit_env_t *env, const ir_node *node) {
804 CondJmp_emitter(env, node);
808 * Emits code for conditional test and jump.
811 void TestJmp_emitter(ia32_emit_env_t *env, const ir_node *node) {
812 if(is_ia32_ImmSymConst(node) || is_ia32_ImmConst(node)) {
813 be_emit_cstring(env, "\ttest ");
814 ia32_emit_immediate(env, node);
815 be_emit_cstring(env, ", ");
816 ia32_emit_source_register(env, node, 0);
817 be_emit_finish_line_gas(env, node);
819 be_emit_cstring(env, "\ttest ");
820 ia32_emit_source_register(env, node, 1);
821 be_emit_cstring(env, ", ");
822 ia32_emit_source_register(env, node, 0);
823 be_emit_finish_line_gas(env, node);
825 finish_CondJmp(env, node, mode_Iu, get_ia32_pncode(node));
829 * Emits code for conditional test and jump with two variables.
832 void emit_ia32_TestJmp(ia32_emit_env_t *env, const ir_node *node) {
833 TestJmp_emitter(env, node);
837 void emit_ia32_CJmp(ia32_emit_env_t *env, const ir_node *node) {
838 be_emit_cstring(env, "/* omitted redundant test */");
839 be_emit_finish_line_gas(env, node);
841 finish_CondJmp(env, node, mode_Is, get_ia32_pncode(node));
845 void emit_ia32_CJmpAM(ia32_emit_env_t *env, const ir_node *node) {
846 be_emit_cstring(env, "/* omitted redundant test/cmp */");
847 be_emit_finish_line_gas(env, node);
849 finish_CondJmp(env, node, mode_Is, get_ia32_pncode(node));
853 * Emits code for conditional SSE floating point jump with two variables.
856 void emit_ia32_xCondJmp(ia32_emit_env_t *env, const ir_node *node) {
857 be_emit_cstring(env, "\tucomi");
858 ia32_emit_xmm_mode_suffix(env, node);
859 be_emit_char(env, ' ');
860 ia32_emit_binop(env, node);
861 be_emit_finish_line_gas(env, node);
863 finish_CondJmp(env, node, mode_F, get_ia32_pncode(node));
867 * Emits code for conditional x87 floating point jump with two variables.
870 void emit_ia32_x87CondJmp(ia32_emit_env_t *env, const ir_node *node) {
871 ia32_attr_t *attr = get_ia32_attr(node);
872 const char *reg = attr->x87[1]->name;
873 long pnc = get_ia32_pncode(node);
875 switch (get_ia32_irn_opcode(node)) {
876 case iro_ia32_fcomrJmp:
877 pnc = get_inversed_pnc(pnc);
878 reg = attr->x87[0]->name;
879 case iro_ia32_fcomJmp:
881 be_emit_cstring(env, "\tfucom ");
883 case iro_ia32_fcomrpJmp:
884 pnc = get_inversed_pnc(pnc);
885 reg = attr->x87[0]->name;
886 case iro_ia32_fcompJmp:
887 be_emit_cstring(env, "\tfucomp ");
889 case iro_ia32_fcomrppJmp:
890 pnc = get_inversed_pnc(pnc);
891 case iro_ia32_fcomppJmp:
892 be_emit_cstring(env, "\tfucompp ");
898 be_emit_char(env, '%');
899 be_emit_string(env, reg);
901 be_emit_finish_line_gas(env, node);
903 be_emit_cstring(env, "\tfnstsw %ax");
904 be_emit_finish_line_gas(env, node);
905 be_emit_cstring(env, "\tsahf");
906 be_emit_finish_line_gas(env, node);
908 finish_CondJmp(env, node, mode_E, pnc);
912 void CMov_emitter(ia32_emit_env_t *env, const ir_node *node) {
913 long pnc = get_ia32_pncode(node);
914 int is_PsiCondCMov = is_ia32_PsiCondCMov(node);
915 int idx_left = 2 - is_PsiCondCMov;
916 int idx_right = 3 - is_PsiCondCMov;
917 const arch_register_t *in1, *in2, *out;
919 out = arch_get_irn_register(env->arch_env, node);
920 in1 = arch_get_irn_register(env->arch_env, get_irn_n(node, idx_left));
921 in2 = arch_get_irn_register(env->arch_env, get_irn_n(node, idx_right));
923 /* we have to emit the cmp first, because the destination register */
924 /* could be one of the compare registers */
925 if (is_ia32_CmpCMov(node)) {
926 be_emit_cstring(env, "\tcmp ");
927 ia32_emit_source_register(env, node, 1);
928 be_emit_cstring(env, ", ");
929 ia32_emit_source_register(env, node, 0);
930 } else if (is_ia32_xCmpCMov(node)) {
931 be_emit_cstring(env, "\tucomis");
932 ia32_emit_mode_suffix_mode(env, get_irn_mode(node));
933 be_emit_char(env, ' ');
934 ia32_emit_source_register(env, node, 1);
935 be_emit_cstring(env, ", ");
936 ia32_emit_source_register(env, node, 0);
937 } else if (is_PsiCondCMov) {
938 /* omit compare because flags are already set by And/Or */
939 be_emit_cstring(env, "\ttest ");
940 ia32_emit_source_register(env, node, 0);
941 be_emit_cstring(env, ", ");
942 ia32_emit_source_register(env, node, 0);
944 assert(0 && "unsupported CMov");
946 be_emit_finish_line_gas(env, node);
948 if (REGS_ARE_EQUAL(out, in2)) {
949 /* best case: default in == out -> do nothing */
950 } else if (REGS_ARE_EQUAL(out, in1)) {
951 ir_node *n = (ir_node*) node;
952 /* true in == out -> need complement compare and exchange true and default in */
953 ir_node *t = get_irn_n(n, idx_left);
954 set_irn_n(n, idx_left, get_irn_n(n, idx_right));
955 set_irn_n(n, idx_right, t);
957 pnc = get_negated_pnc(pnc, get_irn_mode(node));
959 /* out is different from in: need copy default -> out */
960 if (is_PsiCondCMov) {
961 be_emit_cstring(env, "\tmovl ");
962 ia32_emit_dest_register(env, node, 2);
963 be_emit_cstring(env, ", ");
964 ia32_emit_dest_register(env, node, 0);
966 be_emit_cstring(env, "\tmovl ");
967 ia32_emit_source_register(env, node, 3);
968 be_emit_cstring(env, ", ");
969 ia32_emit_dest_register(env, node, 0);
971 be_emit_finish_line_gas(env, node);
974 if (is_PsiCondCMov) {
975 be_emit_cstring(env, "\tcmov");
976 ia32_emit_cmp_suffix(env, pnc);
977 be_emit_cstring(env, "l ");
978 ia32_emit_source_register(env, node, 1);
979 be_emit_cstring(env, ", ");
980 ia32_emit_dest_register(env, node, 0);
982 be_emit_cstring(env, "\tcmov");
983 ia32_emit_cmp_suffix(env, pnc);
984 be_emit_cstring(env, "l ");
985 ia32_emit_source_register(env, node, 2);
986 be_emit_cstring(env, ", ");
987 ia32_emit_dest_register(env, node, 0);
989 be_emit_finish_line_gas(env, node);
993 void emit_ia32_CmpCMov(ia32_emit_env_t *env, const ir_node *node) {
994 CMov_emitter(env, node);
998 void emit_ia32_PsiCondCMov(ia32_emit_env_t *env, const ir_node *node) {
999 CMov_emitter(env, node);
1003 void emit_ia32_xCmpCMov(ia32_emit_env_t *env, const ir_node *node) {
1004 CMov_emitter(env, node);
1008 void Set_emitter(ia32_emit_env_t *env, const ir_node *node, ir_mode *mode) {
1009 int pnc = get_ia32_pncode(node);
1010 const char *reg8bit;
1011 const arch_register_t *out;
1013 out = arch_get_irn_register(env->arch_env, node);
1014 reg8bit = ia32_get_mapped_reg_name(env->isa->regs_8bit, out);
1016 if (is_ia32_CmpSet(node)) {
1017 be_emit_cstring(env, "\tcmp ");
1018 ia32_emit_binop(env, node);
1019 } else if (is_ia32_xCmpSet(node)) {
1020 be_emit_cstring(env, "\tucomis");
1021 ia32_emit_mode_suffix_mode(env, get_irn_mode(get_irn_n(node, 2)));
1022 be_emit_char(env, ' ');
1023 ia32_emit_binop(env, node);
1024 } else if (is_ia32_PsiCondSet(node)) {
1025 be_emit_cstring(env, "\tcmp $0, ");
1026 ia32_emit_source_register(env, node, 0);
1028 assert(0 && "unsupported Set");
1030 be_emit_finish_line_gas(env, node);
1032 /* use mov to clear target because it doesn't affect the eflags */
1033 be_emit_cstring(env, "\tmovl $0, %");
1034 be_emit_string(env, arch_register_get_name(out));
1035 be_emit_finish_line_gas(env, node);
1037 be_emit_cstring(env, "\tset");
1038 ia32_emit_cmp_suffix(env, pnc);
1039 be_emit_cstring(env, " %");
1040 be_emit_string(env, reg8bit);
1041 be_emit_finish_line_gas(env, node);
1045 void emit_ia32_CmpSet(ia32_emit_env_t *env, const ir_node *node) {
1046 Set_emitter(env, node, get_irn_mode(get_irn_n(node, 2)));
1050 void emit_ia32_PsiCondSet(ia32_emit_env_t *env, const ir_node *node) {
1051 Set_emitter(env, node, get_irn_mode(get_irn_n(node, 0)));
1055 void emit_ia32_xCmpSet(ia32_emit_env_t *env, const ir_node *node) {
1056 Set_emitter(env, node, get_irn_mode(get_irn_n(node, 2)));
1060 void emit_ia32_xCmp(ia32_emit_env_t *env, const ir_node *node) {
1062 long pnc = get_ia32_pncode(node);
1063 long unord = pnc & pn_Cmp_Uo;
1065 assert( (pnc & ia32_pn_Cmp_Unsigned) == 0);
1068 case pn_Cmp_Leg: /* odered */
1071 case pn_Cmp_Uo: /* unordered */
1075 case pn_Cmp_Eq: /* == */
1079 case pn_Cmp_Lt: /* < */
1083 case pn_Cmp_Le: /* <= */
1087 case pn_Cmp_Gt: /* > */
1091 case pn_Cmp_Ge: /* >= */
1095 case pn_Cmp_Lg: /* != */
1100 assert(sse_pnc >= 0 && "unsupported compare");
1102 if (unord && sse_pnc != 3) {
1104 We need a separate compare against unordered.
1105 Quick and Dirty solution:
1106 - get some memory on stack
1110 - and result and stored result
1113 be_emit_cstring(env, "\tsubl $8, %esp");
1114 be_emit_finish_line_gas(env, node);
1116 be_emit_cstring(env, "\tcmpsd $3, ");
1117 ia32_emit_binop(env, node);
1118 be_emit_finish_line_gas(env, node);
1120 be_emit_cstring(env, "\tmovsd ");
1121 ia32_emit_dest_register(env, node, 0);
1122 be_emit_cstring(env, ", (%esp)");
1123 be_emit_finish_line_gas(env, node);
1126 be_emit_cstring(env, "\tcmpsd ");
1127 be_emit_irprintf(env->emit, "%d, ", sse_pnc);
1128 ia32_emit_binop(env, node);
1129 be_emit_finish_line_gas(env, node);
1131 if (unord && sse_pnc != 3) {
1132 be_emit_cstring(env, "\tandpd (%esp), ");
1133 ia32_emit_dest_register(env, node, 0);
1134 be_emit_finish_line_gas(env, node);
1136 be_emit_cstring(env, "\taddl $8, %esp");
1137 be_emit_finish_line_gas(env, node);
1141 /*********************************************************
1144 * ___ _ __ ___ _| |_ _ _ _ _ __ ___ _ __ ___
1145 * / _ \ '_ ` _ \| | __| | | | | | '_ ` _ \| '_ \/ __|
1146 * | __/ | | | | | | |_ | | |_| | | | | | | |_) \__ \
1147 * \___|_| |_| |_|_|\__| | |\__,_|_| |_| |_| .__/|___/
1150 *********************************************************/
1152 /* jump table entry (target and corresponding number) */
1153 typedef struct _branch_t {
1158 /* jump table for switch generation */
1159 typedef struct _jmp_tbl_t {
1160 ir_node *defProj; /**< default target */
1161 int min_value; /**< smallest switch case */
1162 int max_value; /**< largest switch case */
1163 int num_branches; /**< number of jumps */
1164 char *label; /**< label of the jump table */
1165 branch_t *branches; /**< jump array */
1169 * Compare two variables of type branch_t. Used to sort all switch cases
1172 int ia32_cmp_branch_t(const void *a, const void *b) {
1173 branch_t *b1 = (branch_t *)a;
1174 branch_t *b2 = (branch_t *)b;
1176 if (b1->value <= b2->value)
1183 * Emits code for a SwitchJmp (creates a jump table if
1184 * possible otherwise a cmp-jmp cascade). Port from
1188 void emit_ia32_SwitchJmp(ia32_emit_env_t *env, const ir_node *node) {
1189 unsigned long interval;
1194 const ir_edge_t *edge;
1196 /* fill the table structure */
1197 tbl.label = xmalloc(SNPRINTF_BUF_LEN);
1198 tbl.label = get_unique_label(tbl.label, SNPRINTF_BUF_LEN, ".TBL_");
1200 tbl.num_branches = get_irn_n_edges(node);
1201 tbl.branches = xcalloc(tbl.num_branches, sizeof(tbl.branches[0]));
1202 tbl.min_value = INT_MAX;
1203 tbl.max_value = INT_MIN;
1206 /* go over all proj's and collect them */
1207 foreach_out_edge(node, edge) {
1208 proj = get_edge_src_irn(edge);
1209 assert(is_Proj(proj) && "Only proj allowed at SwitchJmp");
1211 pnc = get_Proj_proj(proj);
1213 /* create branch entry */
1214 tbl.branches[i].target = proj;
1215 tbl.branches[i].value = pnc;
1217 tbl.min_value = pnc < tbl.min_value ? pnc : tbl.min_value;
1218 tbl.max_value = pnc > tbl.max_value ? pnc : tbl.max_value;
1220 /* check for default proj */
1221 if (pnc == get_ia32_pncode(node)) {
1222 assert(tbl.defProj == NULL && "found two defProjs at SwitchJmp");
1229 /* sort the branches by their number */
1230 qsort(tbl.branches, tbl.num_branches, sizeof(tbl.branches[0]), ia32_cmp_branch_t);
1232 /* two-complement's magic make this work without overflow */
1233 interval = tbl.max_value - tbl.min_value;
1235 /* emit the table */
1236 be_emit_cstring(env, "\tcmpl $");
1237 be_emit_irprintf(env->emit, "%u, ", interval);
1238 ia32_emit_source_register(env, node, 0);
1239 be_emit_finish_line_gas(env, node);
1241 be_emit_cstring(env, "\tja ");
1242 ia32_emit_cfop_target(env, tbl.defProj);
1243 be_emit_finish_line_gas(env, node);
1245 if (tbl.num_branches > 1) {
1247 be_emit_cstring(env, "\tjmp *");
1248 be_emit_string(env, tbl.label);
1249 be_emit_cstring(env, "(,");
1250 ia32_emit_source_register(env, node, 0);
1251 be_emit_cstring(env, ",4)");
1252 be_emit_finish_line_gas(env, node);
1254 be_gas_emit_switch_section(env->emit, GAS_SECTION_RODATA);
1255 be_emit_cstring(env, "\t.align 4\n");
1256 be_emit_write_line(env);
1258 be_emit_string(env, tbl.label);
1259 be_emit_cstring(env, ":\n");
1260 be_emit_write_line(env);
1262 be_emit_cstring(env, ".long ");
1263 ia32_emit_cfop_target(env, tbl.branches[0].target);
1264 be_emit_finish_line_gas(env, NULL);
1266 last_value = tbl.branches[0].value;
1267 for (i = 1; i < tbl.num_branches; ++i) {
1268 while (++last_value < tbl.branches[i].value) {
1269 be_emit_cstring(env, ".long ");
1270 ia32_emit_cfop_target(env, tbl.defProj);
1271 be_emit_finish_line_gas(env, NULL);
1273 be_emit_cstring(env, ".long ");
1274 ia32_emit_cfop_target(env, tbl.branches[i].target);
1275 be_emit_finish_line_gas(env, NULL);
1277 be_gas_emit_switch_section(env->emit, GAS_SECTION_TEXT);
1279 /* one jump is enough */
1280 be_emit_cstring(env, "\tjmp ");
1281 ia32_emit_cfop_target(env, tbl.branches[0].target);
1282 be_emit_finish_line_gas(env, node);
1292 * Emits code for a unconditional jump.
1295 void emit_Jmp(ia32_emit_env_t *env, const ir_node *node) {
1296 ir_node *block, *next_block;
1298 /* for now, the code works for scheduled and non-schedules blocks */
1299 block = get_nodes_block(node);
1301 /* we have a block schedule */
1302 next_block = next_blk_sched(block);
1303 if (get_cfop_target_block(node) != next_block) {
1304 be_emit_cstring(env, "\tjmp ");
1305 ia32_emit_cfop_target(env, node);
1307 be_emit_cstring(env, "\t/* fallthrough to ");
1308 ia32_emit_cfop_target(env, node);
1309 be_emit_cstring(env, " */");
1311 be_emit_finish_line_gas(env, node);
1315 const char* emit_asm_operand(ia32_emit_env_t *env, const ir_node *node,
1318 const arch_register_t *reg;
1319 const char *reg_name;
1330 /* parse modifiers */
1333 ir_fprintf(stderr, "Warning: asm text (%+F) ends with %\n", node);
1334 be_emit_char(env, '%');
1337 be_emit_char(env, '%');
1356 ir_fprintf(stderr, "Warning: asm text (%+F) contains unknown modifier "
1357 "'%c' for asm op\n", node, c);
1363 sscanf(s, "%d%n", &num, &p);
1365 ir_fprintf(stderr, "Warning: Couldn't parse assembler operand (%+F)\n",
1373 attr = get_ia32_attr(node);
1374 n_outs = attr->data.n_res;
1376 reg = get_out_reg(env, node, num);
1378 int in = num - n_outs;
1379 if(in >= get_irn_arity(node)) {
1380 ir_fprintf(stderr, "Warning: Invalid input %d specified in asm "
1381 "op (%+F)\n", num, node);
1384 reg = get_in_reg(env, node, in);
1387 ir_fprintf(stderr, "Warning: no register assigned for %d asm op "
1388 "(%+F)\n", num, node);
1393 be_emit_char(env, '%');
1396 reg_name = arch_register_get_name(reg);
1399 reg_name = ia32_get_mapped_reg_name(env->isa->regs_8bit, reg);
1402 reg_name = ia32_get_mapped_reg_name(env->isa->regs_16bit, reg);
1405 panic("Invalid asm op modifier");
1407 be_emit_string(env, reg_name);
1413 * Emits code for an ASM pseudo op.
1416 void emit_ia32_Asm(ia32_emit_env_t *env, const ir_node *node)
1418 ia32_attr_t *attr = get_ia32_attr(node);
1419 ident *asm_text = attr->cnst_val.asm_text;
1420 const char *s = get_id_str(asm_text);
1422 be_emit_cstring(env, "# Begin ASM \t");
1423 be_emit_finish_line_gas(env, node);
1426 be_emit_char(env, '\t');
1430 s = emit_asm_operand(env, node, s);
1433 be_emit_char(env, *s);
1438 be_emit_char(env, '\n');
1439 be_emit_write_line(env);
1441 be_emit_cstring(env, "# End ASM\n");
1442 be_emit_write_line(env);
1445 /**********************************
1448 * | | ___ _ __ _ _| |_) |
1449 * | | / _ \| '_ \| | | | _ <
1450 * | |___| (_) | |_) | |_| | |_) |
1451 * \_____\___/| .__/ \__, |____/
1454 **********************************/
1457 * Emit movsb/w instructions to make mov count divideable by 4
1460 void emit_CopyB_prolog(ia32_emit_env_t *env, int rem) {
1461 be_emit_cstring(env, "\tcld");
1462 be_emit_finish_line_gas(env, NULL);
1466 be_emit_cstring(env, "\tmovsb");
1467 be_emit_finish_line_gas(env, NULL);
1470 be_emit_cstring(env, "\tmovsw");
1471 be_emit_finish_line_gas(env, NULL);
1474 be_emit_cstring(env, "\tmovsb");
1475 be_emit_finish_line_gas(env, NULL);
1476 be_emit_cstring(env, "\tmovsw");
1477 be_emit_finish_line_gas(env, NULL);
1483 * Emit rep movsd instruction for memcopy.
1486 void emit_ia32_CopyB(ia32_emit_env_t *env, const ir_node *node) {
1487 tarval *tv = get_ia32_Immop_tarval(node);
1488 int rem = get_tarval_long(tv);
1490 emit_CopyB_prolog(env, rem);
1492 be_emit_cstring(env, "\trep movsd");
1493 be_emit_finish_line_gas(env, node);
1497 * Emits unrolled memcopy.
1500 void emit_ia32_CopyB_i(ia32_emit_env_t *env, const ir_node *node) {
1501 tarval *tv = get_ia32_Immop_tarval(node);
1502 int size = get_tarval_long(tv);
1504 emit_CopyB_prolog(env, size & 0x3);
1508 be_emit_cstring(env, "\tmovsd");
1509 be_emit_finish_line_gas(env, NULL);
1515 /***************************
1519 * | | / _ \| '_ \ \ / /
1520 * | |___| (_) | | | \ V /
1521 * \_____\___/|_| |_|\_/
1523 ***************************/
1526 * Emit code for conversions (I, FP), (FP, I) and (FP, FP).
1529 void emit_ia32_Conv_with_FP(ia32_emit_env_t *env, const ir_node *node) {
1530 ir_mode *ls_mode = get_ia32_ls_mode(node);
1531 int ls_bits = get_mode_size_bits(ls_mode);
1533 be_emit_cstring(env, "\tcvt");
1535 if(is_ia32_Conv_I2FP(node)) {
1537 be_emit_cstring(env, "si2ss");
1539 be_emit_cstring(env, "si2sd");
1541 } else if(is_ia32_Conv_FP2I(node)) {
1543 be_emit_cstring(env, "ss2si");
1545 be_emit_cstring(env, "sd2si");
1548 assert(is_ia32_Conv_FP2FP(node));
1550 be_emit_cstring(env, "sd2ss");
1552 be_emit_cstring(env, "ss2sd");
1555 be_emit_char(env, ' ');
1557 switch(get_ia32_op_type(node)) {
1559 ia32_emit_source_register(env, node, 2);
1560 be_emit_cstring(env, ", ");
1561 ia32_emit_dest_register(env, node, 0);
1563 case ia32_AddrModeS:
1564 ia32_emit_dest_register(env, node, 0);
1565 be_emit_cstring(env, ", ");
1566 ia32_emit_am(env, node);
1569 assert(0 && "unsupported op type for Conv");
1571 be_emit_finish_line_gas(env, node);
1575 void emit_ia32_Conv_I2FP(ia32_emit_env_t *env, const ir_node *node) {
1576 emit_ia32_Conv_with_FP(env, node);
1580 void emit_ia32_Conv_FP2I(ia32_emit_env_t *env, const ir_node *node) {
1581 emit_ia32_Conv_with_FP(env, node);
1585 void emit_ia32_Conv_FP2FP(ia32_emit_env_t *env, const ir_node *node) {
1586 emit_ia32_Conv_with_FP(env, node);
1590 * Emits code for an Int conversion.
1593 void emit_ia32_Conv_I2I(ia32_emit_env_t *env, const ir_node *node) {
1594 const char *sign_suffix;
1595 ir_mode *smaller_mode = get_ia32_ls_mode(node);
1596 int smaller_bits = get_mode_size_bits(smaller_mode);
1598 const arch_register_t *in_reg, *out_reg;
1600 assert(!mode_is_float(smaller_mode));
1601 assert(smaller_bits == 8 || smaller_bits == 16 || smaller_bits == 32);
1603 signed_mode = mode_is_signed(smaller_mode);
1604 if(smaller_bits == 32) {
1605 // this should not happen as it's no convert
1609 sign_suffix = signed_mode ? "s" : "z";
1612 switch(get_ia32_op_type(node)) {
1614 in_reg = get_in_reg(env, node, 2);
1615 out_reg = get_out_reg(env, node, 0);
1617 if (REGS_ARE_EQUAL(in_reg, &ia32_gp_regs[REG_EAX]) &&
1618 REGS_ARE_EQUAL(out_reg, in_reg) &&
1621 /* argument and result are both in EAX and */
1622 /* signedness is ok: -> use converts */
1623 if (smaller_bits == 8) {
1624 be_emit_cstring(env, "\tcbtw");
1625 } else if (smaller_bits == 16) {
1626 be_emit_cstring(env, "\tcwtl");
1630 } else if (REGS_ARE_EQUAL(out_reg, in_reg) && !signed_mode) {
1631 /* argument and result are in the same register */
1632 /* and signedness is ok: -> use and with mask */
1633 int mask = (1 << smaller_bits) - 1;
1634 be_emit_cstring(env, "\tandl $0x");
1635 be_emit_irprintf(env->emit, "%x, ", mask);
1636 ia32_emit_dest_register(env, node, 0);
1638 const char *sreg = ia32_get_reg_name_for_mode(env, smaller_mode, in_reg);
1640 be_emit_cstring(env, "\tmov");
1641 be_emit_string(env, sign_suffix);
1642 ia32_emit_mode_suffix_mode(env, smaller_mode);
1643 be_emit_cstring(env, "l %");
1644 be_emit_string(env, sreg);
1645 be_emit_cstring(env, ", ");
1646 ia32_emit_dest_register(env, node, 0);
1649 case ia32_AddrModeS: {
1650 be_emit_cstring(env, "\tmov");
1651 be_emit_string(env, sign_suffix);
1652 ia32_emit_mode_suffix_mode(env, smaller_mode);
1653 be_emit_cstring(env, "l %");
1654 ia32_emit_am(env, node);
1655 be_emit_cstring(env, ", ");
1656 ia32_emit_dest_register(env, node, 0);
1660 assert(0 && "unsupported op type for Conv");
1662 be_emit_finish_line_gas(env, node);
1666 * Emits code for an 8Bit Int conversion.
1668 void emit_ia32_Conv_I2I8Bit(ia32_emit_env_t *env, const ir_node *node) {
1669 emit_ia32_Conv_I2I(env, node);
1673 /*******************************************
1676 * | |__ ___ _ __ ___ __| | ___ ___
1677 * | '_ \ / _ \ '_ \ / _ \ / _` |/ _ \/ __|
1678 * | |_) | __/ | | | (_) | (_| | __/\__ \
1679 * |_.__/ \___|_| |_|\___/ \__,_|\___||___/
1681 *******************************************/
1684 * Emits a backend call
1687 void emit_be_Call(ia32_emit_env_t *env, const ir_node *node) {
1688 ir_entity *ent = be_Call_get_entity(node);
1690 be_emit_cstring(env, "\tcall ");
1692 mark_entity_visited(ent);
1693 be_emit_string(env, get_entity_ld_name(ent));
1695 be_emit_char(env, '*');
1696 ia32_emit_dest_register(env, get_irn_n(node, be_pos_Call_ptr), 0);
1698 be_emit_finish_line_gas(env, node);
1702 * Emits code to increase stack pointer.
1705 void emit_be_IncSP(ia32_emit_env_t *env, const ir_node *node) {
1706 int offs = be_get_IncSP_offset(node);
1712 be_emit_cstring(env, "\tsubl $");
1713 be_emit_irprintf(env->emit, "%u, ", offs);
1714 ia32_emit_source_register(env, node, 0);
1716 be_emit_cstring(env, "\taddl $");
1717 be_emit_irprintf(env->emit, "%u, ", -offs);
1718 ia32_emit_source_register(env, node, 0);
1720 be_emit_finish_line_gas(env, node);
1724 * Emits code to set stack pointer.
1727 void emit_be_SetSP(ia32_emit_env_t *env, const ir_node *node) {
1728 be_emit_cstring(env, "\tmovl ");
1729 ia32_emit_source_register(env, node, 2);
1730 be_emit_cstring(env, ", ");
1731 ia32_emit_dest_register(env, node, 0);
1732 be_emit_finish_line_gas(env, node);
1736 * Emits code for Copy/CopyKeep.
1739 void Copy_emitter(ia32_emit_env_t *env, const ir_node *node, const ir_node *op)
1741 const arch_env_t *aenv = env->arch_env;
1744 if (REGS_ARE_EQUAL(arch_get_irn_register(aenv, node), arch_get_irn_register(aenv, op)) ||
1745 arch_register_type_is(arch_get_irn_register(aenv, op), virtual))
1748 mode = get_irn_mode(node);
1749 if (mode == mode_E) {
1750 be_emit_cstring(env, "\tmovsd ");
1751 ia32_emit_source_register(env, node, 0);
1752 be_emit_cstring(env, ", ");
1753 ia32_emit_dest_register(env, node, 0);
1755 be_emit_cstring(env, "\tmovl ");
1756 ia32_emit_source_register(env, node, 0);
1757 be_emit_cstring(env, ", ");
1758 ia32_emit_dest_register(env, node, 0);
1760 be_emit_finish_line_gas(env, node);
1764 void emit_be_Copy(ia32_emit_env_t *env, const ir_node *node) {
1765 Copy_emitter(env, node, be_get_Copy_op(node));
1769 void emit_be_CopyKeep(ia32_emit_env_t *env, const ir_node *node) {
1770 Copy_emitter(env, node, be_get_CopyKeep_op(node));
1774 * Emits code for exchange.
1777 void emit_be_Perm(ia32_emit_env_t *env, const ir_node *node) {
1778 const arch_register_t *in1, *in2;
1779 const arch_register_class_t *cls1, *cls2;
1781 in1 = arch_get_irn_register(env->arch_env, get_irn_n(node, 0));
1782 in2 = arch_get_irn_register(env->arch_env, get_irn_n(node, 1));
1784 cls1 = arch_register_get_class(in1);
1785 cls2 = arch_register_get_class(in2);
1787 assert(cls1 == cls2 && "Register class mismatch at Perm");
1789 if (cls1 == &ia32_reg_classes[CLASS_ia32_gp]) {
1790 be_emit_cstring(env, "\txchg ");
1791 ia32_emit_source_register(env, node, 1);
1792 be_emit_cstring(env, ", ");
1793 ia32_emit_source_register(env, node, 0);
1794 be_emit_finish_line_gas(env, node);
1795 } else if (cls1 == &ia32_reg_classes[CLASS_ia32_xmm]) {
1796 be_emit_cstring(env, "\txorpd ");
1797 ia32_emit_source_register(env, node, 1);
1798 be_emit_cstring(env, ", ");
1799 ia32_emit_source_register(env, node, 0);
1800 be_emit_finish_line_gas(env, NULL);
1802 be_emit_cstring(env, "\txorpd ");
1803 ia32_emit_source_register(env, node, 0);
1804 be_emit_cstring(env, ", ");
1805 ia32_emit_source_register(env, node, 1);
1806 be_emit_finish_line_gas(env, NULL);
1808 be_emit_cstring(env, "\txorpd ");
1809 ia32_emit_source_register(env, node, 1);
1810 be_emit_cstring(env, ", ");
1811 ia32_emit_source_register(env, node, 0);
1812 be_emit_finish_line_gas(env, node);
1813 } else if (cls1 == &ia32_reg_classes[CLASS_ia32_vfp]) {
1815 } else if (cls1 == &ia32_reg_classes[CLASS_ia32_st]) {
1821 * Emits code for Constant loading.
1824 void emit_ia32_Const(ia32_emit_env_t *env, const ir_node *node) {
1825 ia32_immop_type_t imm_tp = get_ia32_immop_type(node);
1827 if (imm_tp == ia32_ImmSymConst) {
1828 be_emit_cstring(env, "\tmovl ");
1829 ia32_emit_immediate(env, node);
1830 be_emit_cstring(env, ", ");
1831 ia32_emit_dest_register(env, node, 0);
1833 tarval *tv = get_ia32_Immop_tarval(node);
1834 assert(get_irn_mode(node) == mode_Iu);
1835 /* beware: in some rare cases mode is mode_b which has no tarval_null() */
1836 if (tarval_is_null(tv)) {
1837 if (env->isa->opt_arch == arch_pentium_4) {
1838 /* P4 prefers sub r, r, others xor r, r */
1839 be_emit_cstring(env, "\tsubl ");
1841 be_emit_cstring(env, "\txorl ");
1843 ia32_emit_dest_register(env, node, 0);
1844 be_emit_cstring(env, ", ");
1845 ia32_emit_dest_register(env, node, 0);
1847 be_emit_cstring(env, "\tmovl ");
1848 ia32_emit_immediate(env, node);
1849 be_emit_cstring(env, ", ");
1850 ia32_emit_dest_register(env, node, 0);
1853 be_emit_finish_line_gas(env, node);
1857 * Emits code to load the TLS base
1860 void emit_ia32_LdTls(ia32_emit_env_t *env, const ir_node *node) {
1861 be_emit_cstring(env, "\tmovl %gs:0, ");
1862 ia32_emit_dest_register(env, node, 0);
1863 be_emit_finish_line_gas(env, node);
1867 void emit_be_Return(ia32_emit_env_t *env, const ir_node *node) {
1868 be_emit_cstring(env, "\tret");
1869 be_emit_finish_line_gas(env, node);
1873 void emit_Nothing(ia32_emit_env_t *env, const ir_node *node) {
1877 /***********************************************************************************
1880 * _ __ ___ __ _ _ _ __ | |_ _ __ __ _ _ __ ___ _____ _____ _ __| | __
1881 * | '_ ` _ \ / _` | | '_ \ | _| '__/ _` | '_ ` _ \ / _ \ \ /\ / / _ \| '__| |/ /
1882 * | | | | | | (_| | | | | | | | | | | (_| | | | | | | __/\ V V / (_) | | | <
1883 * |_| |_| |_|\__,_|_|_| |_| |_| |_| \__,_|_| |_| |_|\___| \_/\_/ \___/|_| |_|\_\
1885 ***********************************************************************************/
1888 * Enters the emitter functions for handled nodes into the generic
1889 * pointer of an opcode.
1892 void ia32_register_emitters(void) {
1894 #define IA32_EMIT2(a,b) op_ia32_##a->ops.generic = (op_func)emit_ia32_##b
1895 #define IA32_EMIT(a) IA32_EMIT2(a,a)
1896 #define EMIT(a) op_##a->ops.generic = (op_func)emit_##a
1897 #define IGN(a) op_##a->ops.generic = (op_func)emit_Nothing
1898 #define BE_EMIT(a) op_be_##a->ops.generic = (op_func)emit_be_##a
1899 #define BE_IGN(a) op_be_##a->ops.generic = (op_func)emit_Nothing
1901 /* first clear the generic function pointer for all ops */
1902 clear_irp_opcodes_generic_func();
1904 /* register all emitter functions defined in spec */
1905 ia32_register_spec_emitters();
1907 /* other ia32 emitter functions */
1914 IA32_EMIT(PsiCondCMov);
1916 IA32_EMIT(PsiCondSet);
1917 IA32_EMIT(SwitchJmp);
1920 IA32_EMIT(Conv_I2FP);
1921 IA32_EMIT(Conv_FP2I);
1922 IA32_EMIT(Conv_FP2FP);
1923 IA32_EMIT(Conv_I2I);
1924 IA32_EMIT(Conv_I2I8Bit);
1929 IA32_EMIT(xCmpCMov);
1930 IA32_EMIT(xCondJmp);
1931 IA32_EMIT2(fcomJmp, x87CondJmp);
1932 IA32_EMIT2(fcompJmp, x87CondJmp);
1933 IA32_EMIT2(fcomppJmp, x87CondJmp);
1934 IA32_EMIT2(fcomrJmp, x87CondJmp);
1935 IA32_EMIT2(fcomrpJmp, x87CondJmp);
1936 IA32_EMIT2(fcomrppJmp, x87CondJmp);
1938 /* benode emitter */
1964 static const char *last_name = NULL;
1965 static unsigned last_line = -1;
1966 static unsigned num = -1;
1969 * Emit the debug support for node node.
1972 void ia32_emit_dbg(ia32_emit_env_t *env, const ir_node *node) {
1973 dbg_info *db = get_irn_dbg_info(node);
1975 const char *fname = be_retrieve_dbg_info(db, &lineno);
1977 if (! env->cg->birg->main_env->options->stabs_debug_support)
1981 if (last_name != fname) {
1983 be_dbg_include_begin(env->cg->birg->main_env->db_handle, fname);
1986 if (last_line != lineno) {
1989 snprintf(name, sizeof(name), ".LM%u", ++num);
1991 be_dbg_line(env->cg->birg->main_env->db_handle, lineno, name);
1992 be_emit_string(env, name);
1993 be_emit_cstring(env, ":\n");
1994 be_emit_write_line(env);
1999 typedef void (*emit_func_ptr) (ia32_emit_env_t *, const ir_node *);
2002 * Emits code for a node.
2005 void ia32_emit_node(ia32_emit_env_t *env, const ir_node *node) {
2006 ir_op *op = get_irn_op(node);
2008 DBG((dbg, LEVEL_1, "emitting code for %+F\n", node));
2010 if (op->ops.generic) {
2011 emit_func_ptr func = (emit_func_ptr) op->ops.generic;
2012 ia32_emit_dbg(env, node);
2013 (*func) (env, node);
2015 emit_Nothing(env, node);
2016 ir_fprintf(stderr, "Warning: No emit handler for node %+F (%+G)\n", node, node);
2021 * Emits gas alignment directives
2024 void ia32_emit_alignment(ia32_emit_env_t *env, unsigned align, unsigned skip) {
2025 be_emit_cstring(env, "\t.p2align ");
2026 be_emit_irprintf(env->emit, "%u,,%u\n", align, skip);
2027 be_emit_write_line(env);
2031 * Emits gas alignment directives for Functions depended on cpu architecture.
2034 void ia32_emit_align_func(ia32_emit_env_t *env, cpu_support cpu) {
2036 unsigned maximum_skip;
2051 maximum_skip = (1 << align) - 1;
2052 ia32_emit_alignment(env, align, maximum_skip);
2056 * Emits gas alignment directives for Labels depended on cpu architecture.
2059 void ia32_emit_align_label(ia32_emit_env_t *env, cpu_support cpu) {
2060 unsigned align; unsigned maximum_skip;
2075 maximum_skip = (1 << align) - 1;
2076 ia32_emit_alignment(env, align, maximum_skip);
2080 * Test wether a block should be aligned.
2081 * For cpus in the P4/Athlon class it is usefull to align jump labels to
2082 * 16 bytes. However we should only do that if the alignment nops before the
2083 * label aren't executed more often than we have jumps to the label.
2086 int should_align_block(ia32_emit_env_t *env, ir_node *block, ir_node *prev) {
2087 static const double DELTA = .0001;
2088 ir_exec_freq *exec_freq = env->cg->birg->exec_freq;
2090 double prev_freq = 0; /**< execfreq of the fallthrough block */
2091 double jmp_freq = 0; /**< execfreq of all non-fallthrough blocks */
2092 cpu_support cpu = env->isa->opt_arch;
2095 if(exec_freq == NULL)
2097 if(cpu == arch_i386 || cpu == arch_i486)
2100 block_freq = get_block_execfreq(exec_freq, block);
2101 if(block_freq < DELTA)
2104 n_cfgpreds = get_Block_n_cfgpreds(block);
2105 for(i = 0; i < n_cfgpreds; ++i) {
2106 ir_node *pred = get_Block_cfgpred_block(block, i);
2107 double pred_freq = get_block_execfreq(exec_freq, pred);
2110 prev_freq += pred_freq;
2112 jmp_freq += pred_freq;
2116 if(prev_freq < DELTA && !(jmp_freq < DELTA))
2119 jmp_freq /= prev_freq;
2123 case arch_athlon_64:
2125 return jmp_freq > 3;
2127 return jmp_freq > 2;
2132 void ia32_emit_block_header(ia32_emit_env_t *env, ir_node *block, ir_node *prev)
2137 ir_exec_freq *exec_freq = env->cg->birg->exec_freq;
2140 n_cfgpreds = get_Block_n_cfgpreds(block);
2141 if (n_cfgpreds == 0) {
2143 } else if (n_cfgpreds == 1) {
2144 ir_node *pred = get_Block_cfgpred(block, 0);
2145 ir_node *pred_block = get_nodes_block(pred);
2147 /* we don't need labels for fallthrough blocks, however switch-jmps
2148 * are no fallthoughs */
2149 if(pred_block == prev &&
2150 !(is_Proj(pred) && is_ia32_SwitchJmp(get_Proj_pred(pred)))) {
2159 if (should_align_block(env, block, prev)) {
2161 ia32_emit_align_label(env, env->isa->opt_arch);
2165 ia32_emit_block_name(env, block);
2166 be_emit_char(env, ':');
2168 be_emit_pad_comment(env);
2169 be_emit_cstring(env, " /* preds:");
2171 /* emit list of pred blocks in comment */
2172 arity = get_irn_arity(block);
2173 for (i = 0; i < arity; ++i) {
2174 ir_node *predblock = get_Block_cfgpred_block(block, i);
2175 be_emit_irprintf(env->emit, " %d", get_irn_node_nr(predblock));
2178 be_emit_cstring(env, "\t/* ");
2179 ia32_emit_block_name(env, block);
2180 be_emit_cstring(env, ": ");
2182 if (exec_freq != NULL) {
2183 be_emit_irprintf(env->emit, " freq: %f",
2184 get_block_execfreq(exec_freq, block));
2186 be_emit_cstring(env, " */\n");
2187 be_emit_write_line(env);
2191 * Walks over the nodes in a block connected by scheduling edges
2192 * and emits code for each node.
2195 void ia32_gen_block(ia32_emit_env_t *env, ir_node *block, ir_node *last_block)
2197 const ir_node *node;
2199 ia32_emit_block_header(env, block, last_block);
2201 /* emit the contents of the block */
2202 ia32_emit_dbg(env, block);
2203 sched_foreach(block, node) {
2204 ia32_emit_node(env, node);
2209 * Emits code for function start.
2212 void ia32_emit_func_prolog(ia32_emit_env_t *env, ir_graph *irg) {
2213 ir_entity *irg_ent = get_irg_entity(irg);
2214 const char *irg_name = get_entity_ld_name(irg_ent);
2215 cpu_support cpu = env->isa->opt_arch;
2216 const be_irg_t *birg = env->cg->birg;
2218 be_emit_write_line(env);
2219 be_gas_emit_switch_section(env->emit, GAS_SECTION_TEXT);
2220 be_dbg_method_begin(birg->main_env->db_handle, irg_ent, be_abi_get_stack_layout(birg->abi));
2221 ia32_emit_align_func(env, cpu);
2222 if (get_entity_visibility(irg_ent) == visibility_external_visible) {
2223 be_emit_cstring(env, ".global ");
2224 be_emit_string(env, irg_name);
2225 be_emit_char(env, '\n');
2226 be_emit_write_line(env);
2228 ia32_emit_function_object(env, irg_name);
2229 be_emit_string(env, irg_name);
2230 be_emit_cstring(env, ":\n");
2231 be_emit_write_line(env);
2235 * Emits code for function end
2238 void ia32_emit_func_epilog(ia32_emit_env_t *env, ir_graph *irg) {
2239 const char *irg_name = get_entity_ld_name(get_irg_entity(irg));
2240 const be_irg_t *birg = env->cg->birg;
2242 ia32_emit_function_size(env, irg_name);
2243 be_dbg_method_end(birg->main_env->db_handle);
2244 be_emit_char(env, '\n');
2245 be_emit_write_line(env);
2250 * Sets labels for control flow nodes (jump target)
2253 void ia32_gen_labels(ir_node *block, void *data) {
2255 int n = get_Block_n_cfgpreds(block);
2257 for (n--; n >= 0; n--) {
2258 pred = get_Block_cfgpred(block, n);
2259 set_irn_link(pred, block);
2264 * Emit an exception label if the current instruction can fail.
2266 void ia32_emit_exc_label(ia32_emit_env_t *env, const ir_node *node) {
2267 if (get_ia32_exc_label(node)) {
2268 be_emit_irprintf(env->emit, ".EXL%u\n", 0);
2269 be_emit_write_line(env);
2274 * Main driver. Emits the code for one routine.
2276 void ia32_gen_routine(ia32_code_gen_t *cg, ir_graph *irg) {
2277 ia32_emit_env_t env;
2279 ir_node *last_block = NULL;
2282 env.isa = (ia32_isa_t *)cg->arch_env->isa;
2283 env.emit = &env.isa->emit;
2284 env.arch_env = cg->arch_env;
2287 ia32_register_emitters();
2289 ia32_emit_func_prolog(&env, irg);
2290 irg_block_walk_graph(irg, ia32_gen_labels, NULL, &env);
2292 n = ARR_LEN(cg->blk_sched);
2293 for (i = 0; i < n;) {
2296 block = cg->blk_sched[i];
2298 next_bl = i < n ? cg->blk_sched[i] : NULL;
2300 /* set here the link. the emitter expects to find the next block here */
2301 set_irn_link(block, next_bl);
2302 ia32_gen_block(&env, block, last_block);
2306 ia32_emit_func_epilog(&env, irg);
2309 void ia32_init_emitter(void)
2311 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.emitter");