2 * This file implements the node emitter.
3 * @author Christian Wuerdig
22 #include "iredges_t.h"
25 #include "../besched_t.h"
26 #include "../benode_t.h"
28 #include "../be_dbgout.h"
30 #include "ia32_emitter.h"
31 #include "gen_ia32_emitter.h"
32 #include "gen_ia32_regalloc_if.h"
33 #include "ia32_nodes_attr.h"
34 #include "ia32_new_nodes.h"
35 #include "ia32_map_regs.h"
36 #include "bearch_ia32_t.h"
38 #define BLOCK_PREFIX(x) ".L" x
40 #define SNPRINTF_BUF_LEN 128
42 /* global arch_env for lc_printf functions */
43 static const arch_env_t *arch_env = NULL;
45 /** by default, we generate assembler code for the Linux gas */
46 asm_flavour_t asm_flavour = ASM_LINUX_GAS;
49 * Switch to a new section
51 void ia32_switch_section(FILE *F, section_t sec) {
52 static section_t curr_sec = NO_SECTION;
53 static const char *text[ASM_MAX][SECTION_MAX] = {
59 ".section\t.tbss,\"awT\",@nobits",
60 ".section\t.ctors,\"aw\",@progbits"
65 ".section .rdata,\"dr\"",
67 ".section\t.tbss,\"awT\",@nobits",
68 ".section\t.ctors,\"aw\",@progbits"
87 fprintf(F, "\t%s\n", text[asm_flavour][sec]);
95 static void ia32_dump_function_object(FILE *F, const char *name)
97 switch (asm_flavour) {
99 fprintf(F, "\t.type\t%s, @function\n", name);
102 fprintf(F, "\t.def\t%s;\t.scl\t2;\t.type\t32;\t.endef\n", name);
109 static void ia32_dump_function_size(FILE *F, const char *name)
111 switch (asm_flavour) {
113 fprintf(F, "\t.size\t%s, .-%s\n", name, name);
120 /*************************************************************
122 * (_) | | / _| | | | |
123 * _ __ _ __ _ _ __ | |_| |_ | |__ ___| |_ __ ___ _ __
124 * | '_ \| '__| | '_ \| __| _| | '_ \ / _ \ | '_ \ / _ \ '__|
125 * | |_) | | | | | | | |_| | | | | | __/ | |_) | __/ |
126 * | .__/|_| |_|_| |_|\__|_| |_| |_|\___|_| .__/ \___|_|
129 *************************************************************/
131 /* We always pass the ir_node which is a pointer. */
132 static int ia32_get_arg_type(const lc_arg_occ_t *occ) {
133 return lc_arg_type_ptr;
138 * Returns the register at in position pos.
140 static const arch_register_t *get_in_reg(const ir_node *irn, int pos) {
142 const arch_register_t *reg = NULL;
144 assert(get_irn_arity(irn) > pos && "Invalid IN position");
146 /* The out register of the operator at position pos is the
147 in register we need. */
148 op = get_irn_n(irn, pos);
150 reg = arch_get_irn_register(arch_env, op);
152 assert(reg && "no in register found");
154 /* in case of a joker register: just return a valid register */
155 if (arch_register_type_is(reg, joker)) {
156 arch_register_req_t req;
157 const arch_register_req_t *p_req;
159 /* ask for the requirements */
160 p_req = arch_get_register_req(arch_env, &req, irn, pos);
162 if (arch_register_req_is(p_req, limited)) {
163 /* in case of limited requirements: get the first allowed register */
165 bitset_t *bs = bitset_alloca(arch_register_class_n_regs(p_req->cls));
168 p_req->limited(p_req->limited_env, bs);
169 idx = bitset_next_set(bs, 0);
170 reg = arch_register_for_index(p_req->cls, idx);
173 /* otherwise get first register in class */
174 reg = arch_register_for_index(p_req->cls, 0);
182 * Returns the register at out position pos.
184 static const arch_register_t *get_out_reg(const ir_node *irn, int pos) {
186 const arch_register_t *reg = NULL;
188 /* 1st case: irn is not of mode_T, so it has only */
189 /* one OUT register -> good */
190 /* 2nd case: irn is of mode_T -> collect all Projs and ask the */
191 /* Proj with the corresponding projnum for the register */
193 if (get_irn_mode(irn) != mode_T) {
194 reg = arch_get_irn_register(arch_env, irn);
196 else if (is_ia32_irn(irn)) {
197 reg = get_ia32_out_reg(irn, pos);
200 const ir_edge_t *edge;
202 foreach_out_edge(irn, edge) {
203 proj = get_edge_src_irn(edge);
204 assert(is_Proj(proj) && "non-Proj from mode_T node");
205 if (get_Proj_proj(proj) == pos) {
206 reg = arch_get_irn_register(arch_env, proj);
212 assert(reg && "no out register found");
222 * Returns the name of the in register at position pos.
224 static const char *get_ia32_reg_name(ir_node *irn, int pos, enum io_direction in_out) {
225 const arch_register_t *reg;
227 if (in_out == IN_REG) {
228 reg = get_in_reg(irn, pos);
230 if (reg->reg_class == &ia32_reg_classes[CLASS_ia32_vfp]) {
231 /* FIXME: works for binop only */
232 assert(2 <= pos && pos <= 3);
233 reg = get_ia32_attr(irn)->x87[pos - 2];
237 /* destination address mode nodes don't have outputs */
238 if (is_ia32_irn(irn) && get_ia32_op_type(irn) == ia32_AddrModeD) {
242 reg = get_out_reg(irn, pos);
243 if (reg->reg_class == &ia32_reg_classes[CLASS_ia32_vfp])
244 reg = get_ia32_attr(irn)->x87[pos + 2];
246 return arch_register_get_name(reg);
250 * Get the register name for a node.
252 static int ia32_get_reg_name(lc_appendable_t *app,
253 const lc_arg_occ_t *occ, const lc_arg_value_t *arg)
256 ir_node *irn = arg->v_ptr;
257 int nr = occ->width - 1;
260 return lc_appendable_snadd(app, "(null)", 6);
262 buf = get_ia32_reg_name(irn, nr, occ->conversion == 'S' ? IN_REG : OUT_REG);
264 /* append the stupid % to register names */
265 lc_appendable_chadd(app, '%');
266 return lc_appendable_snadd(app, buf, strlen(buf));
270 * Get the x87 register name for a node.
272 static int ia32_get_x87_name(lc_appendable_t *app,
273 const lc_arg_occ_t *occ, const lc_arg_value_t *arg)
276 ir_node *irn = arg->v_ptr;
277 int nr = occ->width - 1;
282 return lc_appendable_snadd(app, "(null)", 6);
284 attr = get_ia32_attr(irn);
285 buf = attr->x87[nr]->name;
287 res += lc_appendable_chadd(app, '%');
288 res += lc_appendable_snadd(app, buf, strlen(buf));
294 * Returns the tarval, offset or scale of an ia32 as a string.
296 static int ia32_const_to_str(lc_appendable_t *app,
297 const lc_arg_occ_t *occ, const lc_arg_value_t *arg)
300 ir_node *irn = arg->v_ptr;
303 return lc_arg_append(app, occ, "(null)", 6);
305 if (occ->conversion == 'C') {
306 buf = get_ia32_cnst(irn);
309 buf = get_ia32_am_offs(irn);
312 return buf ? lc_appendable_snadd(app, buf, strlen(buf)) : 0;
316 * Determines the SSE suffix depending on the mode.
318 static int ia32_get_mode_suffix(lc_appendable_t *app,
319 const lc_arg_occ_t *occ, const lc_arg_value_t *arg)
321 ir_node *irn = arg->v_ptr;
322 ir_mode *mode = get_irn_mode(irn);
324 if (mode == mode_T) {
325 mode = get_ia32_res_mode(irn);
327 mode = get_ia32_ls_mode(irn);
331 return lc_arg_append(app, occ, "(null)", 6);
333 if (mode_is_float(mode)) {
334 return lc_appendable_chadd(app, get_mode_size_bits(mode) == 32 ? 's' : 'd');
337 return lc_appendable_chadd(app, mode_is_signed(mode) ? 's' : 'z');
342 * Return the ia32 printf arg environment.
343 * We use the firm environment with some additional handlers.
345 const lc_arg_env_t *ia32_get_arg_env(void) {
346 static lc_arg_env_t *env = NULL;
348 static const lc_arg_handler_t ia32_reg_handler = { ia32_get_arg_type, ia32_get_reg_name };
349 static const lc_arg_handler_t ia32_const_handler = { ia32_get_arg_type, ia32_const_to_str };
350 static const lc_arg_handler_t ia32_mode_handler = { ia32_get_arg_type, ia32_get_mode_suffix };
351 static const lc_arg_handler_t ia32_x87_handler = { ia32_get_arg_type, ia32_get_x87_name };
354 /* extend the firm printer */
355 env = firm_get_arg_env();
357 lc_arg_register(env, "ia32:sreg", 'S', &ia32_reg_handler);
358 lc_arg_register(env, "ia32:dreg", 'D', &ia32_reg_handler);
359 lc_arg_register(env, "ia32:cnst", 'C', &ia32_const_handler);
360 lc_arg_register(env, "ia32:offs", 'O', &ia32_const_handler);
361 lc_arg_register(env, "ia32:mode", 'M', &ia32_mode_handler);
362 lc_arg_register(env, "ia32:x87", 'X', &ia32_x87_handler);
368 static const char *ia32_get_reg_name_for_mode(ia32_emit_env_t *env, ir_mode *mode, const arch_register_t *reg) {
369 switch(get_mode_size_bits(mode)) {
371 return ia32_get_mapped_reg_name(env->isa->regs_8bit, reg);
373 return ia32_get_mapped_reg_name(env->isa->regs_16bit, reg);
375 return (char *)arch_register_get_name(reg);
380 * Emits registers and/or address mode of a binary operation.
382 const char *ia32_emit_binop(const ir_node *n, ia32_emit_env_t *env) {
383 static char *buf = NULL;
385 /* verify that this function is never called on non-AM supporting operations */
386 //assert(get_ia32_am_support(n) != ia32_am_None && "emit binop expects addressmode support");
388 #define PRODUCES_RESULT(n) \
389 (!(is_ia32_St(n) || \
390 is_ia32_Store8Bit(n) || \
391 is_ia32_CondJmp(n) || \
392 is_ia32_xCondJmp(n) || \
393 is_ia32_CmpSet(n) || \
394 is_ia32_xCmpSet(n) || \
395 is_ia32_SwitchJmp(n)))
398 buf = xcalloc(1, SNPRINTF_BUF_LEN);
401 memset(buf, 0, SNPRINTF_BUF_LEN);
404 switch(get_ia32_op_type(n)) {
406 if (is_ia32_ImmConst(n)) {
407 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%3S, %s", n, get_ia32_cnst(n));
409 else if (is_ia32_ImmSymConst(n)) {
410 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%3S, OFFSET FLAT:%s", n, get_ia32_cnst(n));
413 const arch_register_t *in1 = get_in_reg(n, 2);
414 const arch_register_t *in2 = get_in_reg(n, 3);
415 const arch_register_t *out = PRODUCES_RESULT(n) ? get_out_reg(n, 0) : NULL;
416 const arch_register_t *in;
419 in = out ? (REGS_ARE_EQUAL(out, in2) ? in1 : in2) : in2;
420 out = out ? out : in1;
421 in_name = arch_register_get_name(in);
423 if (is_ia32_emit_cl(n)) {
424 assert(REGS_ARE_EQUAL(&ia32_gp_regs[REG_ECX], in) && "shift operation needs ecx");
428 snprintf(buf, SNPRINTF_BUF_LEN, "%%%s, %%%s", arch_register_get_name(out), in_name);
432 if (is_ia32_ImmConst(n) || is_ia32_ImmSymConst(n)) {
433 assert(! PRODUCES_RESULT(n) && "Source AM with Const must not produce result");
434 snprintf(buf, SNPRINTF_BUF_LEN, "%s, %s", get_ia32_cnst(n), ia32_emit_am(n, env));
437 if (PRODUCES_RESULT(n)) {
438 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%1D, %s", n, ia32_emit_am(n, env));
441 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%3S, %s", n, ia32_emit_am(n, env));
446 if (is_ia32_ImmConst(n) || is_ia32_ImmSymConst(n)) {
447 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%s,%s%s",
448 ia32_emit_am(n, env),
449 is_ia32_ImmSymConst(n) ? " OFFSET FLAT:" : " ", /* In case of a symconst we must add OFFSET to */
450 get_ia32_cnst(n)); /* tell the assembler to store it's address. */
453 const arch_register_t *in1 = get_in_reg(n, get_irn_arity(n) == 5 ? 3 : 2);
454 ir_mode *mode = get_ia32_res_mode(n);
457 mode = mode ? mode : get_ia32_ls_mode(n);
458 in_name = ia32_get_reg_name_for_mode(env, mode, in1);
460 if (is_ia32_emit_cl(n)) {
461 assert(REGS_ARE_EQUAL(&ia32_gp_regs[REG_ECX], in1) && "shift operation needs ecx");
465 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%s, %%%s", ia32_emit_am(n, env), in_name);
469 assert(0 && "unsupported op type");
472 #undef PRODUCES_RESULT
478 * Returns the xxx PTR string for a given mode
480 * @param mode the mode
481 * @param x87_insn if non-zero returns the string for a x87 instruction
482 * else for a SSE instruction
484 static const char *pointer_size(ir_mode *mode, int x87_insn)
487 switch (get_mode_size_bits(mode)) {
488 case 8: return "BYTE PTR";
489 case 16: return "WORD PTR";
490 case 32: return "DWORD PTR";
496 case 96: return "XWORD PTR";
497 default: return NULL;
504 * Translate the stx names into %st(x).
506 static char *get_x87_reg_name(const arch_register_t *reg, char *buf) {
507 const char *name = arch_register_get_name(reg);
526 * Emits registers and/or address mode of a binary operation.
528 const char *ia32_emit_x87_binop(const ir_node *n, ia32_emit_env_t *env) {
529 static char *buf = NULL;
531 /* verify that this function is never called on non-AM supporting operations */
532 //assert(get_ia32_am_support(n) != ia32_am_None && "emit binop expects addressmode support");
535 buf = xcalloc(1, SNPRINTF_BUF_LEN);
538 memset(buf, 0, SNPRINTF_BUF_LEN);
541 switch(get_ia32_op_type(n)) {
543 if (is_ia32_ImmConst(n) || is_ia32_ImmSymConst(n)) {
544 ir_mode *mode = get_ia32_ls_mode(n);
545 const char *p = pointer_size(mode, 1);
546 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%s %s", p, get_ia32_cnst(n));
549 ia32_attr_t *attr = get_ia32_attr(n);
550 const arch_register_t *in1 = attr->x87[0];
551 const arch_register_t *in2 = attr->x87[1];
552 const arch_register_t *out = attr->x87[2];
553 const arch_register_t *in;
554 char buf1[7], buf2[7];
556 in = out ? (REGS_ARE_EQUAL(out, in2) ? in1 : in2) : in2;
557 out = out ? out : in1;
559 snprintf(buf, SNPRINTF_BUF_LEN, "%%%s, %%%s",
560 arch_register_get_name(out), arch_register_get_name(in));
565 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%s", ia32_emit_am(n, env));
568 assert(0 && "unsupported op type");
575 * Emits registers and/or address mode of a unary operation.
577 const char *ia32_emit_unop(const ir_node *n, ia32_emit_env_t *env) {
578 static char *buf = NULL;
581 buf = xcalloc(1, SNPRINTF_BUF_LEN);
584 memset(buf, 0, SNPRINTF_BUF_LEN);
587 switch(get_ia32_op_type(n)) {
589 if (is_ia32_ImmConst(n)) {
590 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%C", n);
592 else if (is_ia32_ImmSymConst(n)) {
593 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "OFFSET FLAT:%C", n);
596 if (is_ia32_MulS(n) || is_ia32_Mulh(n)) {
597 /* MulS and Mulh implicitly multiply by EAX */
598 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%4S", n);
599 } else if(is_ia32_Push(n)) {
600 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%3S", n);
602 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%1D", n);
607 assert(!is_ia32_Push(n));
608 snprintf(buf, SNPRINTF_BUF_LEN, "%s", ia32_emit_am(n, env));
612 Mulh is emitted via emit_unop
613 imul [MEM] means EDX:EAX <- EAX * [MEM]
615 assert((is_ia32_Mulh(n) || is_ia32_MulS(n) || is_ia32_Push(n)) && "Only MulS and Mulh can have AM source as unop");
616 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%s", ia32_emit_am(n, env));
619 assert(0 && "unsupported op type");
626 * Emits address mode.
628 const char *ia32_emit_am(const ir_node *n, ia32_emit_env_t *env) {
629 ia32_am_flavour_t am_flav = get_ia32_am_flavour(n);
633 static struct obstack *obst = NULL;
634 ir_mode *mode = get_ia32_ls_mode(n);
636 if (! is_ia32_Lea(n))
637 assert(mode && "AM node must have ls_mode attribute set.");
640 obst = xcalloc(1, sizeof(*obst));
643 obstack_free(obst, NULL);
646 /* obstack_free with NULL results in an uninitialized obstack */
649 p = pointer_size(mode, ia32_has_x87_register(n) || is_ia32_GetST0(n) || is_ia32_SetST0(n));
651 obstack_printf(obst, "%s ", p);
653 /* emit address mode symconst */
654 if (get_ia32_am_sc(n)) {
655 if (is_ia32_am_sc_sign(n))
656 obstack_printf(obst, "-");
657 obstack_printf(obst, "%s", get_id_str(get_ia32_am_sc(n)));
660 if (am_flav & ia32_B) {
661 obstack_printf(obst, "[");
662 lc_eoprintf(ia32_get_arg_env(), obst, "%1S", n);
666 if (am_flav & ia32_I) {
668 obstack_printf(obst, "+");
671 obstack_printf(obst, "[");
674 lc_eoprintf(ia32_get_arg_env(), obst, "%2S", n);
676 if (am_flav & ia32_S) {
677 obstack_printf(obst, "*%d", 1 << get_ia32_am_scale(n));
683 if (am_flav & ia32_O) {
684 int offs = get_ia32_am_offs_int(n);
687 /* omit explicit + if there was no base or index */
689 obstack_printf(obst, "[%d", offs);
691 obstack_printf(obst, "%+d", offs);
699 obstack_printf(obst, "] ");
701 obstack_1grow(obst, '\0');
702 s = obstack_finish(obst);
710 const char *ia32_emit_adr(const ir_node *irn, ia32_emit_env_t *env)
712 static char buf[SNPRINTF_BUF_LEN];
713 ir_mode *mode = get_ia32_ls_mode(irn);
714 const char *adr = get_ia32_cnst(irn);
715 const char *pref = pointer_size(mode, ia32_has_x87_register(irn));
717 snprintf(buf, SNPRINTF_BUF_LEN, "%s %s", pref ? pref : "", adr);
722 * Formated print of commands and comments.
724 static void ia32_fprintf_format(FILE *F, const ir_node *irn, char *cmd_buf, char *cmnt_buf) {
726 const char *name = irn ? be_retrieve_dbg_info(get_irn_dbg_info((ir_node *)irn), &lineno) : NULL;
729 fprintf(F, "\t%-35s %-60s /* %s:%u */\n", cmd_buf, cmnt_buf, name, lineno);
731 fprintf(F, "\t%-35s %-60s\n", cmd_buf, cmnt_buf);
737 * Add a number to a prefix. This number will not be used a second time.
739 static char *get_unique_label(char *buf, size_t buflen, const char *prefix) {
740 static unsigned long id = 0;
741 snprintf(buf, buflen, "%s%lu", prefix, ++id);
747 /*************************************************
750 * ___ _ __ ___ _| |_ ___ ___ _ __ __| |
751 * / _ \ '_ ` _ \| | __| / __/ _ \| '_ \ / _` |
752 * | __/ | | | | | | |_ | (_| (_) | | | | (_| |
753 * \___|_| |_| |_|_|\__| \___\___/|_| |_|\__,_|
755 *************************************************/
758 #define IA32_DO_EMIT(irn) ia32_fprintf_format(F, irn, cmd_buf, cmnt_buf)
761 * coding of conditions
763 struct cmp2conditon_t {
769 * positive conditions for signed compares
771 static const struct cmp2conditon_t cmp2condition_s[] = {
772 { NULL, pn_Cmp_False }, /* always false */
773 { "e", pn_Cmp_Eq }, /* == */
774 { "l", pn_Cmp_Lt }, /* < */
775 { "le", pn_Cmp_Le }, /* <= */
776 { "g", pn_Cmp_Gt }, /* > */
777 { "ge", pn_Cmp_Ge }, /* >= */
778 { "ne", pn_Cmp_Lg }, /* != */
779 { "ordered", pn_Cmp_Leg }, /* Floating point: ordered */
780 { "unordered", pn_Cmp_Uo }, /* FLoting point: unordered */
781 { "e", pn_Cmp_Ue }, /* Floating point: unordered or == */
782 { "b", pn_Cmp_Ul }, /* Floating point: unordered or < */
783 { "be", pn_Cmp_Ule }, /* Floating point: unordered or <= */
784 { "a", pn_Cmp_Ug }, /* Floating point: unordered or > */
785 { "ae", pn_Cmp_Uge }, /* Floating point: unordered or >= */
786 { "ne", pn_Cmp_Ne }, /* Floating point: unordered or != */
787 { NULL, pn_Cmp_True }, /* always true */
791 * positive conditions for unsigned compares
793 static const struct cmp2conditon_t cmp2condition_u[] = {
794 { NULL, pn_Cmp_False }, /* always false */
795 { "e", pn_Cmp_Eq }, /* == */
796 { "b", pn_Cmp_Lt }, /* < */
797 { "be", pn_Cmp_Le }, /* <= */
798 { "a", pn_Cmp_Gt }, /* > */
799 { "ae", pn_Cmp_Ge }, /* >= */
800 { "ne", pn_Cmp_Lg }, /* != */
801 { "ordered", pn_Cmp_Leg }, /* Floating point: ordered */
802 { "unordered", pn_Cmp_Uo }, /* FLoting point: unordered */
803 { "e", pn_Cmp_Ue }, /* Floating point: unordered or == */
804 { "b", pn_Cmp_Ul }, /* Floating point: unordered or < */
805 { "be", pn_Cmp_Ule }, /* Floating point: unordered or <= */
806 { "a", pn_Cmp_Ug }, /* Floating point: unordered or > */
807 { "ae", pn_Cmp_Uge }, /* Floating point: unordered or >= */
808 { "ne", pn_Cmp_Ne }, /* Floating point: unordered or != */
809 { NULL, pn_Cmp_True }, /* always true */
813 * returns the condition code
815 static const char *get_cmp_suffix(int cmp_code, int unsigned_cmp)
817 assert(cmp2condition_s[cmp_code].num == cmp_code);
818 assert(cmp2condition_u[cmp_code].num == cmp_code);
820 return unsigned_cmp ? cmp2condition_u[cmp_code & 7].name : cmp2condition_s[cmp_code & 7].name;
824 * Returns the target block for a control flow node.
826 static ir_node *get_cfop_target_block(const ir_node *irn) {
827 return get_irn_link(irn);
831 * Returns the target label for a control flow node.
833 static char *get_cfop_target(const ir_node *irn, char *buf) {
834 ir_node *bl = get_cfop_target_block(irn);
836 snprintf(buf, SNPRINTF_BUF_LEN, BLOCK_PREFIX("%ld"), get_irn_node_nr(bl));
840 /** Return the next block in Block schedule */
841 static ir_node *next_blk_sched(const ir_node *block) {
842 return get_irn_link(block);
846 * Returns the Proj with projection number proj and NOT mode_M
848 static ir_node *get_proj(const ir_node *irn, long proj) {
849 const ir_edge_t *edge;
852 assert(get_irn_mode(irn) == mode_T && "expected mode_T node");
854 foreach_out_edge(irn, edge) {
855 src = get_edge_src_irn(edge);
857 assert(is_Proj(src) && "Proj expected");
858 if (get_irn_mode(src) == mode_M)
861 if (get_Proj_proj(src) == proj)
868 * Emits the jump sequence for a conditional jump (cmp + jmp_true + jmp_false)
870 static void finish_CondJmp(FILE *F, const ir_node *irn, ir_mode *mode) {
871 const ir_node *proj_true;
872 const ir_node *proj_false;
873 const ir_node *block;
874 const ir_node *next_block;
875 char buf[SNPRINTF_BUF_LEN];
876 char cmd_buf[SNPRINTF_BUF_LEN];
877 char cmnt_buf[SNPRINTF_BUF_LEN];
882 /* get both Proj's */
883 proj_true = get_proj(irn, pn_Cond_true);
884 assert(proj_true && "CondJmp without true Proj");
886 proj_false = get_proj(irn, pn_Cond_false);
887 assert(proj_false && "CondJmp without false Proj");
889 pnc = get_ia32_pncode(irn);
891 /* for now, the code works for scheduled and non-schedules blocks */
892 block = get_nodes_block(irn);
894 /* we have a block schedule */
895 next_block = next_blk_sched(block);
897 if (get_cfop_target_block(proj_true) == next_block) {
898 /* exchange both proj's so the second one can be omitted */
899 const ir_node *t = proj_true;
901 proj_true = proj_false;
904 pnc = get_negated_pnc(pnc, mode);
907 /* the first Proj must always be created */
908 is_unsigned = mode_is_float(mode) || ! mode_is_signed(mode);
910 /* in case of unordered compare, check for parity */
911 if (pnc & pn_Cmp_Uo) {
912 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "jp %s", get_cfop_target(proj_true, buf));
913 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* jump to false if result is unordered */");
917 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "j%s %s",
918 get_cmp_suffix(pnc, is_unsigned),
919 get_cfop_target(proj_true, buf));
920 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* %s(a, b) %s*/",
921 get_pnc_string(pnc), flipped ? "(was flipped)" : "");
924 /* the second Proj might be a fallthrough */
925 if (get_cfop_target_block(proj_false) != next_block) {
926 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "jmp %s", get_cfop_target(proj_false, buf));
927 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* otherwise */");
931 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* fallthrough %s */", get_cfop_target(proj_false, buf));
937 * Emits code for conditional jump.
939 static void CondJmp_emitter(const ir_node *irn, ia32_emit_env_t *env) {
941 char cmd_buf[SNPRINTF_BUF_LEN];
942 char cmnt_buf[SNPRINTF_BUF_LEN];
944 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "cmp %s", ia32_emit_binop(irn, env));
945 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F */", irn);
947 finish_CondJmp(F, irn, get_ia32_res_mode(irn));
951 * Emits code for conditional jump with two variables.
953 static void emit_ia32_CondJmp(const ir_node *irn, ia32_emit_env_t *env) {
954 CondJmp_emitter(irn, env);
958 * Emits code for conditional test and jump.
960 static void TestJmp_emitter(const ir_node *irn, ia32_emit_env_t *env) {
962 #define IA32_IS_IMMOP (is_ia32_ImmConst(irn) || is_ia32_ImmSymConst(irn))
965 const char *op1 = arch_register_get_name(get_in_reg(irn, 0));
966 const char *op2 = IA32_IS_IMMOP ? get_ia32_cnst(irn) : NULL;
967 char cmd_buf[SNPRINTF_BUF_LEN];
968 char cmnt_buf[SNPRINTF_BUF_LEN];
971 op2 = arch_register_get_name(get_in_reg(irn, 1));
973 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "test %%%s,%s%s ", op1, IA32_IS_IMMOP ? " " : " %", op2);
974 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F */", irn);
977 finish_CondJmp(F, irn, get_ia32_res_mode(irn));
983 * Emits code for conditional test and jump with two variables.
985 static void emit_ia32_TestJmp(const ir_node *irn, ia32_emit_env_t *env) {
986 TestJmp_emitter(irn, env);
989 static void emit_ia32_CJmp(const ir_node *irn, ia32_emit_env_t *env) {
991 char cmd_buf[SNPRINTF_BUF_LEN];
992 char cmnt_buf[SNPRINTF_BUF_LEN];
994 snprintf(cmd_buf, SNPRINTF_BUF_LEN, " ");
995 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F omitted redundant test */", irn);
997 finish_CondJmp(F, irn, get_ia32_res_mode(irn));
1000 static void emit_ia32_CJmpAM(const ir_node *irn, ia32_emit_env_t *env) {
1002 char cmd_buf[SNPRINTF_BUF_LEN];
1003 char cmnt_buf[SNPRINTF_BUF_LEN];
1005 snprintf(cmd_buf, SNPRINTF_BUF_LEN, " ");
1006 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F omitted redundant test/cmp */", irn);
1008 finish_CondJmp(F, irn, get_ia32_res_mode(irn));
1012 * Emits code for conditional SSE floating point jump with two variables.
1014 static void emit_ia32_xCondJmp(ir_node *irn, ia32_emit_env_t *env) {
1016 char cmd_buf[SNPRINTF_BUF_LEN];
1017 char cmnt_buf[SNPRINTF_BUF_LEN];
1018 const lc_arg_env_t *arg_env = ia32_get_arg_env();
1020 lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "ucomis%M %s", irn, ia32_emit_binop(irn, env));
1021 lc_esnprintf(arg_env, cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F */", irn);
1024 finish_CondJmp(F, irn, mode_F);
1028 * Emits code for conditional x87 floating point jump with two variables.
1030 static void emit_ia32_x87CondJmp(ir_node *irn, ia32_emit_env_t *env) {
1032 char cmd_buf[SNPRINTF_BUF_LEN];
1033 char cmnt_buf[SNPRINTF_BUF_LEN];
1034 ia32_attr_t *attr = get_ia32_attr(irn);
1035 const char *reg = attr->x87[1]->name;
1036 const char *instr = "fcom";
1039 switch (get_ia32_irn_opcode(irn)) {
1040 case iro_ia32_fcomrJmp:
1042 case iro_ia32_fcomJmp:
1046 case iro_ia32_fcomrpJmp:
1048 case iro_ia32_fcompJmp:
1051 case iro_ia32_fcomrppJmp:
1053 case iro_ia32_fcomppJmp:
1060 set_ia32_pncode(irn, (long)get_inversed_pnc(get_ia32_pncode(irn)));
1062 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "%s %s%s", instr, reg[0] == '\0' ? "" : "%", reg);
1063 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F */", irn);
1065 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "fnstsw %%ax", irn);
1066 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* Store x87 FPU Control Word */");
1068 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "sahf");
1069 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* Store ah into flags */");
1072 /* the compare flags must be evaluated using carry , ie unsigned */
1073 finish_CondJmp(F, irn, mode_Iu);
1076 static void CMov_emitter(ir_node *irn, ia32_emit_env_t *env) {
1078 const lc_arg_env_t *arg_env = ia32_get_arg_env();
1079 ir_mode *mode = get_irn_mode(get_irn_n(irn, 0));
1080 int is_unsigned = mode_is_float(mode) || ! mode_is_signed(mode);
1081 const char *cmp_suffix = get_cmp_suffix(get_ia32_pncode(irn), is_unsigned);
1082 int is_PsiCondCMov = is_ia32_PsiCondCMov(irn);
1083 int idx_left = 2 - is_PsiCondCMov;
1084 int idx_right = 3 - is_PsiCondCMov;
1086 char cmd_buf[SNPRINTF_BUF_LEN];
1087 char cmnt_buf[SNPRINTF_BUF_LEN];
1088 const arch_register_t *in1, *in2, *out;
1090 out = arch_get_irn_register(env->arch_env, irn);
1091 in1 = arch_get_irn_register(env->arch_env, get_irn_n(irn, idx_left));
1092 in2 = arch_get_irn_register(env->arch_env, get_irn_n(irn, idx_right));
1094 /* we have to emit the cmp first, because the destination register */
1095 /* could be one of the compare registers */
1096 if (is_ia32_CmpCMov(irn)) {
1097 lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "cmp %1S, %2S", irn, irn);
1099 else if (is_ia32_xCmpCMov(irn)) {
1100 lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "ucomis%M %1S, %2S", get_irn_n(irn, 0), irn, irn);
1102 else if (is_PsiCondCMov) {
1103 /* omit compare because flags are already set by And/Or */
1104 lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "test %1S, %1S", irn, irn);
1107 assert(0 && "unsupported CMov");
1109 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* Psi condition */" );
1112 if (REGS_ARE_EQUAL(out, in2)) {
1113 /* best case: default in == out -> do nothing */
1115 else if (REGS_ARE_EQUAL(out, in1)) {
1116 /* true in == out -> need complement compare and exchange true and default in */
1117 ir_node *t = get_irn_n(irn, idx_left);
1118 set_irn_n(irn, idx_left, get_irn_n(irn, idx_right));
1119 set_irn_n(irn, idx_right, t);
1121 cmp_suffix = get_cmp_suffix(get_negated_pnc(get_ia32_pncode(irn), get_irn_mode(irn)), is_unsigned);
1125 /* out is different from in: need copy default -> out */
1127 lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "mov %1D, %3S", irn, irn);
1129 lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "mov %1D, %4S", irn, irn);
1131 lc_esnprintf(arg_env, cmnt_buf, SNPRINTF_BUF_LEN, "/* copy default -> out */" );
1136 lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "cmov%s %1D, %2S", cmp_suffix, irn, irn);
1138 lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "cmov%s %1D, %3S", cmp_suffix, irn, irn);
1140 lc_esnprintf(arg_env, cmnt_buf, SNPRINTF_BUF_LEN, "/* condition is true case */" );
1144 static void emit_ia32_CmpCMov(ir_node *irn, ia32_emit_env_t *env) {
1145 CMov_emitter(irn, env);
1148 static void emit_ia32_PsiCondCMov(ir_node *irn, ia32_emit_env_t *env) {
1149 CMov_emitter(irn, env);
1152 static void emit_ia32_xCmpCMov(ir_node *irn, ia32_emit_env_t *env) {
1153 CMov_emitter(irn, env);
1156 static void Set_emitter(ir_node *irn, ir_mode *mode, ia32_emit_env_t *env) {
1158 const lc_arg_env_t *arg_env = ia32_get_arg_env();
1159 int is_unsigned = mode_is_float(mode) || ! mode_is_signed(mode);
1160 const char *cmp_suffix = get_cmp_suffix(get_ia32_pncode(irn), is_unsigned);
1161 const char *reg8bit;
1163 char cmd_buf[SNPRINTF_BUF_LEN];
1164 char cmnt_buf[SNPRINTF_BUF_LEN];
1165 const arch_register_t *out;
1167 out = arch_get_irn_register(env->arch_env, irn);
1168 reg8bit = ia32_get_mapped_reg_name(env->isa->regs_8bit, out);
1170 if (is_ia32_CmpSet(irn)) {
1171 lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "cmp %s", ia32_emit_binop(irn, env));
1173 else if (is_ia32_xCmpSet(irn)) {
1174 lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "ucomis%M %s", get_irn_n(irn, 2), ia32_emit_binop(irn, env));
1176 else if (is_ia32_PsiCondSet(irn)) {
1177 /* omit compare because flags are already set by And/Or */
1178 snprintf(cmd_buf, SNPRINTF_BUF_LEN, " ");
1181 assert(0 && "unsupported Set");
1183 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* calculate Psi condition */" );
1186 /* use mov to clear target because it doesn't affect the eflags */
1187 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "mov %%%s, 0", arch_register_get_name(out));
1188 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* clear target as set modifies only lower 8 bit */");
1191 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "set%s %%%s", cmp_suffix, reg8bit);
1192 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* set 1 iff true, 0 otherweise */" );
1196 static void emit_ia32_CmpSet(ir_node *irn, ia32_emit_env_t *env) {
1197 Set_emitter(irn, get_irn_mode(get_irn_n(irn, 2)), env);
1200 static void emit_ia32_PsiCondSet(ir_node *irn, ia32_emit_env_t *env) {
1201 Set_emitter(irn, get_irn_mode(get_irn_n(irn, 0)), env);
1204 static void emit_ia32_xCmpSet(ir_node *irn, ia32_emit_env_t *env) {
1205 Set_emitter(irn, get_irn_mode(get_irn_n(irn, 2)), env);
1208 static void emit_ia32_xCmp(ir_node *irn, ia32_emit_env_t *env) {
1210 const lc_arg_env_t *arg_env = ia32_get_arg_env();
1212 long pnc = get_ia32_pncode(irn);
1213 long unord = pnc & pn_Cmp_Uo;
1214 char cmd_buf[SNPRINTF_BUF_LEN];
1215 char cmnt_buf[SNPRINTF_BUF_LEN];
1218 case pn_Cmp_Leg: /* odered */
1221 case pn_Cmp_Uo: /* unordered */
1225 case pn_Cmp_Eq: /* == */
1229 case pn_Cmp_Lt: /* < */
1233 case pn_Cmp_Le: /* <= */
1237 case pn_Cmp_Gt: /* > */
1241 case pn_Cmp_Ge: /* >= */
1245 case pn_Cmp_Lg: /* != */
1250 assert(sse_pnc >= 0 && "unsupported compare");
1252 if (unord && sse_pnc != 3) {
1254 We need a separate compare against unordered.
1255 Quick and Dirty solution:
1256 - get some memory on stack
1260 - and result and stored result
1263 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "sub %%esp, 8");
1264 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* reserve some space for unordered compare result */");
1266 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "cmpsd %s, 3", ia32_emit_binop(irn, env));
1267 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* SSE compare: unordered */");
1269 lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "movsd [%%esp], %1D", irn);
1270 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* store compare result */");
1274 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "cmpsd %s, %d", ia32_emit_binop(irn, env), sse_pnc);
1275 lc_esnprintf(arg_env, cmnt_buf, SNPRINTF_BUF_LEN, "/* SSE compare (%+F) with result in %1D */", irn, irn);
1278 if (unord && sse_pnc != 3) {
1279 lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "andpd %1D, [%%esp]", irn);
1280 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* build the final result */");
1282 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "add %%esp, 8");
1283 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* free allocated space */");
1288 /*********************************************************
1291 * ___ _ __ ___ _| |_ _ _ _ _ __ ___ _ __ ___
1292 * / _ \ '_ ` _ \| | __| | | | | | '_ ` _ \| '_ \/ __|
1293 * | __/ | | | | | | |_ | | |_| | | | | | | |_) \__ \
1294 * \___|_| |_| |_|_|\__| | |\__,_|_| |_| |_| .__/|___/
1297 *********************************************************/
1299 /* jump table entry (target and corresponding number) */
1300 typedef struct _branch_t {
1305 /* jump table for switch generation */
1306 typedef struct _jmp_tbl_t {
1307 ir_node *defProj; /**< default target */
1308 int min_value; /**< smallest switch case */
1309 int max_value; /**< largest switch case */
1310 int num_branches; /**< number of jumps */
1311 char *label; /**< label of the jump table */
1312 branch_t *branches; /**< jump array */
1316 * Compare two variables of type branch_t. Used to sort all switch cases
1318 static int ia32_cmp_branch_t(const void *a, const void *b) {
1319 branch_t *b1 = (branch_t *)a;
1320 branch_t *b2 = (branch_t *)b;
1322 if (b1->value <= b2->value)
1329 * Emits code for a SwitchJmp (creates a jump table if
1330 * possible otherwise a cmp-jmp cascade). Port from
1333 static void emit_ia32_SwitchJmp(const ir_node *irn, ia32_emit_env_t *emit_env) {
1334 unsigned long interval;
1335 char buf[SNPRINTF_BUF_LEN];
1336 int last_value, i, pn;
1339 const ir_edge_t *edge;
1340 const lc_arg_env_t *env = ia32_get_arg_env();
1341 FILE *F = emit_env->out;
1342 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1344 /* fill the table structure */
1345 tbl.label = xmalloc(SNPRINTF_BUF_LEN);
1346 tbl.label = get_unique_label(tbl.label, SNPRINTF_BUF_LEN, ".TBL_");
1348 tbl.num_branches = get_irn_n_edges(irn);
1349 tbl.branches = xcalloc(tbl.num_branches, sizeof(tbl.branches[0]));
1350 tbl.min_value = INT_MAX;
1351 tbl.max_value = INT_MIN;
1354 /* go over all proj's and collect them */
1355 foreach_out_edge(irn, edge) {
1356 proj = get_edge_src_irn(edge);
1357 assert(is_Proj(proj) && "Only proj allowed at SwitchJmp");
1359 pn = get_Proj_proj(proj);
1361 /* create branch entry */
1362 tbl.branches[i].target = proj;
1363 tbl.branches[i].value = pn;
1365 tbl.min_value = pn < tbl.min_value ? pn : tbl.min_value;
1366 tbl.max_value = pn > tbl.max_value ? pn : tbl.max_value;
1368 /* check for default proj */
1369 if (pn == get_ia32_pncode(irn)) {
1370 assert(tbl.defProj == NULL && "found two defProjs at SwitchJmp");
1377 /* sort the branches by their number */
1378 qsort(tbl.branches, tbl.num_branches, sizeof(tbl.branches[0]), ia32_cmp_branch_t);
1380 /* two-complement's magic make this work without overflow */
1381 interval = tbl.max_value - tbl.min_value;
1383 /* emit the table */
1384 lc_esnprintf(env, cmd_buf, SNPRINTF_BUF_LEN, "cmp %1S, %u", irn, interval);
1385 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* compare for switch */");
1388 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "ja %s", get_cfop_target(tbl.defProj, buf));
1389 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* default jump if out of range */");
1392 if (tbl.num_branches > 1) {
1395 lc_esnprintf(env, cmd_buf, SNPRINTF_BUF_LEN, "jmp %s[%1S*4]", tbl.label, irn);
1396 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* get jump table entry as target */");
1399 ia32_switch_section(F, SECTION_RODATA);
1400 fprintf(F, "\t.align 4\n");
1402 fprintf(F, "%s:\n", tbl.label);
1404 snprintf(cmd_buf, SNPRINTF_BUF_LEN, ".long %s", get_cfop_target(tbl.branches[0].target, buf));
1405 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* case %d */", tbl.branches[0].value);
1408 last_value = tbl.branches[0].value;
1409 for (i = 1; i < tbl.num_branches; ++i) {
1410 while (++last_value < tbl.branches[i].value) {
1411 snprintf(cmd_buf, SNPRINTF_BUF_LEN, ".long %s", get_cfop_target(tbl.defProj, buf));
1412 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* default case */");
1415 snprintf(cmd_buf, SNPRINTF_BUF_LEN, ".long %s", get_cfop_target(tbl.branches[i].target, buf));
1416 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* case %d */", last_value);
1419 ia32_switch_section(F, SECTION_TEXT);
1422 /* one jump is enough */
1423 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "jmp %s", get_cfop_target(tbl.branches[0].target, buf));
1424 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* only one case given */");
1435 * Emits code for a unconditional jump.
1437 static void emit_Jmp(const ir_node *irn, ia32_emit_env_t *env) {
1438 ir_node *block, *next_bl;
1440 char buf[SNPRINTF_BUF_LEN], cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1442 /* for now, the code works for scheduled and non-schedules blocks */
1443 block = get_nodes_block(irn);
1445 /* we have a block schedule */
1446 next_bl = next_blk_sched(block);
1447 if (get_cfop_target_block(irn) != next_bl) {
1448 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "jmp %s", get_cfop_target(irn, buf));
1449 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F(%+F) */", irn, get_cfop_target_block(irn));
1453 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* fallthrough %s */", get_cfop_target(irn, buf));
1458 /****************************
1461 * _ __ _ __ ___ _ ___
1462 * | '_ \| '__/ _ \| |/ __|
1463 * | |_) | | | (_) | |\__ \
1464 * | .__/|_| \___/| ||___/
1467 ****************************/
1470 * Emits code for a proj -> node
1472 static void emit_Proj(const ir_node *irn, ia32_emit_env_t *env) {
1473 ir_node *pred = get_Proj_pred(irn);
1475 if (get_irn_op(pred) == op_Start) {
1476 switch(get_Proj_proj(irn)) {
1477 case pn_Start_X_initial_exec:
1486 /**********************************
1489 * | | ___ _ __ _ _| |_) |
1490 * | | / _ \| '_ \| | | | _ <
1491 * | |___| (_) | |_) | |_| | |_) |
1492 * \_____\___/| .__/ \__, |____/
1495 **********************************/
1498 * Emit movsb/w instructions to make mov count divideable by 4
1500 static void emit_CopyB_prolog(FILE *F, const ir_node *irn, int rem) {
1501 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1503 ir_fprintf(F, "\t/* memcopy prolog %+F */\n", irn);
1505 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "cld");
1506 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* copy direction forward */");
1511 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "movsb");
1512 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* memcopy remainder 1 */");
1516 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "movsw");
1517 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* memcopy remainder 2 */");
1521 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "movsb");
1522 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* memcopy remainder 3 */");
1524 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "movsw");
1525 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* memcopy remainder 3 */");
1533 * Emit rep movsd instruction for memcopy.
1535 static void emit_ia32_CopyB(const ir_node *irn, ia32_emit_env_t *emit_env) {
1536 FILE *F = emit_env->out;
1537 tarval *tv = get_ia32_Immop_tarval(irn);
1538 int rem = get_tarval_long(tv);
1539 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1541 emit_CopyB_prolog(F, irn, rem);
1543 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "rep movsd");
1544 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* memcopy */");
1549 * Emits unrolled memcopy.
1551 static void emit_ia32_CopyB_i(const ir_node *irn, ia32_emit_env_t *emit_env) {
1552 tarval *tv = get_ia32_Immop_tarval(irn);
1553 int size = get_tarval_long(tv);
1554 FILE *F = emit_env->out;
1555 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1557 emit_CopyB_prolog(F, irn, size & 0x3);
1561 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "movsd");
1562 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* memcopy unrolled */");
1569 /***************************
1573 * | | / _ \| '_ \ \ / /
1574 * | |___| (_) | | | \ V /
1575 * \_____\___/|_| |_|\_/
1577 ***************************/
1580 * Emit code for conversions (I, FP), (FP, I) and (FP, FP).
1582 static void emit_ia32_Conv_with_FP(const ir_node *irn, ia32_emit_env_t *emit_env) {
1583 FILE *F = emit_env->out;
1584 const lc_arg_env_t *env = ia32_get_arg_env();
1585 ir_mode *src_mode = get_ia32_src_mode(irn);
1586 ir_mode *tgt_mode = get_ia32_tgt_mode(irn);
1587 char *from, *to, buf[64];
1588 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1590 from = mode_is_float(src_mode) ? (get_mode_size_bits(src_mode) == 32 ? "ss" : "sd") : "si";
1591 to = mode_is_float(tgt_mode) ? (get_mode_size_bits(tgt_mode) == 32 ? "ss" : "sd") : "si";
1593 switch(get_ia32_op_type(irn)) {
1595 lc_esnprintf(env, buf, sizeof(buf), "%1D, %3S", irn, irn);
1597 case ia32_AddrModeS:
1598 lc_esnprintf(env, buf, sizeof(buf), "%1D, %s", irn, ia32_emit_am(irn, emit_env));
1601 assert(0 && "unsupported op type for Conv");
1604 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "cvt%s2%s %s", from, to, buf);
1605 lc_esnprintf(env, cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F(%+F, %+F) */", irn, src_mode, tgt_mode);
1609 static void emit_ia32_Conv_I2FP(const ir_node *irn, ia32_emit_env_t *emit_env) {
1610 emit_ia32_Conv_with_FP(irn, emit_env);
1613 static void emit_ia32_Conv_FP2I(const ir_node *irn, ia32_emit_env_t *emit_env) {
1614 emit_ia32_Conv_with_FP(irn, emit_env);
1617 static void emit_ia32_Conv_FP2FP(const ir_node *irn, ia32_emit_env_t *emit_env) {
1618 emit_ia32_Conv_with_FP(irn, emit_env);
1622 * Emits code for an Int conversion.
1624 static void emit_ia32_Conv_I2I(const ir_node *irn, ia32_emit_env_t *emit_env) {
1625 FILE *F = emit_env->out;
1626 const lc_arg_env_t *env = ia32_get_arg_env();
1627 char *move_cmd = "movzx";
1628 char *conv_cmd = NULL;
1629 ir_mode *src_mode = get_ia32_src_mode(irn);
1630 ir_mode *tgt_mode = get_ia32_tgt_mode(irn);
1633 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1634 const arch_register_t *in_reg, *out_reg;
1636 n = get_mode_size_bits(src_mode);
1637 m = get_mode_size_bits(tgt_mode);
1639 assert(n == 8 || n == 16 || n == 32);
1640 assert(m == 8 || m == 16 || m == 32);
1643 signed_mode = mode_is_signed(n < m ? src_mode : tgt_mode);
1648 switch(get_ia32_op_type(irn)) {
1650 in_reg = get_in_reg(irn, 2);
1651 out_reg = get_out_reg(irn, 0);
1653 if (REGS_ARE_EQUAL(in_reg, &ia32_gp_regs[REG_EAX]) &&
1654 REGS_ARE_EQUAL(out_reg, in_reg) &&
1657 if (n == 8 || m == 8)
1659 else if (n == 16 || m == 16)
1662 /* argument and result are both in EAX and */
1663 /* signedness is ok: -> use converts */
1664 lc_esnprintf(env, cmd_buf, SNPRINTF_BUF_LEN, "%s", conv_cmd);
1666 else if (REGS_ARE_EQUAL(out_reg, in_reg) && ! signed_mode)
1668 /* argument and result are in the same register */
1669 /* and signedness is ok: -> use and with mask */
1670 int mask = (1 << (n < m ? n : m)) - 1;
1671 lc_esnprintf(env, cmd_buf, SNPRINTF_BUF_LEN, "and %1D, 0x%x", irn, mask);
1674 /* use move w/o sign extension */
1675 lc_esnprintf(env, cmd_buf, SNPRINTF_BUF_LEN, "%s %1D, %%%s",
1676 move_cmd, irn, ia32_get_reg_name_for_mode(emit_env, n < m ? src_mode : tgt_mode, in_reg));
1680 case ia32_AddrModeS:
1681 lc_esnprintf(env, cmd_buf, SNPRINTF_BUF_LEN, "%s %1D, %s",
1682 move_cmd, irn, ia32_emit_am(irn, emit_env));
1685 assert(0 && "unsupported op type for Conv");
1688 lc_esnprintf(env, cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F(%d Bit mode_%F -> %d Bit mode_%F) */",
1689 irn, n, src_mode, m, tgt_mode);
1695 * Emits code for an 8Bit Int conversion.
1697 void emit_ia32_Conv_I2I8Bit(const ir_node *irn, ia32_emit_env_t *emit_env) {
1698 emit_ia32_Conv_I2I(irn, emit_env);
1702 /*******************************************
1705 * | |__ ___ _ __ ___ __| | ___ ___
1706 * | '_ \ / _ \ '_ \ / _ \ / _` |/ _ \/ __|
1707 * | |_) | __/ | | | (_) | (_| | __/\__ \
1708 * |_.__/ \___|_| |_|\___/ \__,_|\___||___/
1710 *******************************************/
1713 * Emits a backend call
1715 static void emit_be_Call(const ir_node *irn, ia32_emit_env_t *emit_env) {
1716 FILE *F = emit_env->out;
1717 entity *ent = be_Call_get_entity(irn);
1718 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1721 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "call %s", get_entity_ld_name(ent));
1724 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "call %1D", get_irn_n(irn, be_pos_Call_ptr));
1727 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F (be_Call) */", irn);
1733 * Emits code to increase stack pointer.
1735 static void emit_be_IncSP(const ir_node *irn, ia32_emit_env_t *emit_env) {
1736 FILE *F = emit_env->out;
1737 int offs = be_get_IncSP_offset(irn);
1738 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1742 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "sub %1S, %u", irn, offs);
1744 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "add %1S, %u", irn, -offs);
1745 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F (IncSP) */", irn);
1748 snprintf(cmd_buf, SNPRINTF_BUF_LEN, " ");
1749 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* omitted %+F (IncSP) with 0 */", irn);
1756 * Emits code to set stack pointer.
1758 static void emit_be_SetSP(const ir_node *irn, ia32_emit_env_t *emit_env) {
1759 FILE *F = emit_env->out;
1760 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1762 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "mov %1D, %3S", irn, irn);
1763 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F (restore SP) */", irn);
1768 * Emits code for Copy/CopyKeep.
1770 static void Copy_emitter(const ir_node *irn, ir_node *op, ia32_emit_env_t *emit_env) {
1771 FILE *F = emit_env->out;
1772 const arch_env_t *aenv = emit_env->arch_env;
1773 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1775 if (REGS_ARE_EQUAL(arch_get_irn_register(aenv, irn), arch_get_irn_register(aenv, op)) ||
1776 arch_register_type_is(arch_get_irn_register(aenv, op), virtual))
1779 if (mode_is_float(get_irn_mode(irn)))
1780 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "movs%M %1D, %1S", irn, irn, irn);
1782 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "mov %1D, %1S", irn, irn);
1783 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F */", irn);
1787 static void emit_be_Copy(const ir_node *irn, ia32_emit_env_t *emit_env) {
1788 Copy_emitter(irn, be_get_Copy_op(irn), emit_env);
1791 static void emit_be_CopyKeep(const ir_node *irn, ia32_emit_env_t *emit_env) {
1792 Copy_emitter(irn, be_get_CopyKeep_op(irn), emit_env);
1796 * Emits code for exchange.
1798 static void emit_be_Perm(const ir_node *irn, ia32_emit_env_t *emit_env) {
1799 FILE *F = emit_env->out;
1800 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1801 const arch_register_t *in1, *in2;
1802 const arch_register_class_t *cls1, *cls2;
1804 in1 = arch_get_irn_register(emit_env->arch_env, get_irn_n(irn, 0));
1805 in2 = arch_get_irn_register(emit_env->arch_env, get_irn_n(irn, 1));
1807 cls1 = arch_register_get_class(in1);
1808 cls2 = arch_register_get_class(in2);
1810 assert(cls1 == cls2 && "Register class mismatch at Perm");
1812 if (cls1 == &ia32_reg_classes[CLASS_ia32_gp]) {
1813 if(emit_env->isa->opt_arch == arch_athlon) {
1814 // xchg commands are Vector path on athlons and therefore stall the DirectPath pipeline
1815 // it is nearly always beneficial to use the 3 xor trick instead of an xchg
1817 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "xor %1S, %2S", irn, irn);
1819 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "xor %2S, %1S", irn, irn);
1821 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "xor %1S, %2S", irn, irn);
1823 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "xchg %1S, %2S", irn, irn);
1826 else if (cls1 == &ia32_reg_classes[CLASS_ia32_xmm]) {
1827 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN,
1828 "pxor %1S, %2S\n\tpxor %2S, %1S\n\tpxor %1S, %2S", irn, irn, irn, irn, irn, irn);
1830 else if (cls1 == &ia32_reg_classes[CLASS_ia32_vfp]) {
1834 else if (cls1 == &ia32_reg_classes[CLASS_ia32_st]) {
1839 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F(%1A, %2A) */", irn, irn, irn);
1844 * Emits code for Constant loading.
1846 static void emit_ia32_Const(const ir_node *n, ia32_emit_env_t *env) {
1848 char cmd_buf[256], cmnt_buf[256];
1849 const lc_arg_env_t *arg_env = ia32_get_arg_env();
1850 ir_mode *mode = get_irn_mode(n);
1851 tarval *tv = get_ia32_Immop_tarval(n);
1853 if (get_ia32_op_type(n) == ia32_SymConst) {
1854 lc_esnprintf(arg_env, cmd_buf, 256, "mov %1D, OFFSET FLAT:%C ", n, n);
1855 lc_esnprintf(arg_env, cmnt_buf, 256, "/* Move address of SymConst into register */");
1857 assert(mode == get_tarval_mode(tv) || (mode_is_reference(get_tarval_mode(tv)) && mode == mode_Iu));
1858 /* beware: in some rare cases mode is mode_b which has no tarval_null() */
1859 if (tv == get_tarval_b_false() || tv == get_tarval_null(mode)) {
1860 const char *instr = "xor";
1861 if (env->isa->opt_arch == arch_pentium_4) {
1862 /* P4 prefers sub r, r, others xor r, r */
1865 lc_esnprintf(arg_env, cmd_buf, 256, "%s %1D, %1D ", instr, n, n);
1866 lc_esnprintf(arg_env, cmnt_buf, 256, "/* optimized mov 0 to register */");
1868 lc_esnprintf(arg_env, cmd_buf, 256, "mov %1D, %C ", n, n);
1869 lc_esnprintf(arg_env, cmnt_buf, 256, "/* Mov Const into register */");
1872 lc_efprintf(arg_env, F, "\t%-35s %-60s /* %+F (%+G) */\n", cmd_buf, cmnt_buf, n, n);
1876 * Emits code to increase stack pointer.
1878 static void emit_ia32_AddSP(const ir_node *irn, ia32_emit_env_t *emit_env) {
1879 FILE *F = emit_env->out;
1880 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1882 if (is_ia32_ImmConst(irn)) {
1883 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "sub %1D, %C", irn, irn);
1885 else if (is_ia32_ImmSymConst(irn)) {
1886 if (get_ia32_op_type(irn) == ia32_Normal)
1887 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "sub %1D, OFFSET_FLAT:%C", irn, irn);
1888 else /* source address mode */
1889 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "sub %1D, [%s%s]", irn, get_id_str(get_ia32_am_sc(irn)), get_ia32_am_offs(irn));
1892 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "sub %1D, %2S", irn, irn);
1894 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* reserve space on stack */");
1900 * Emits code to increase stack pointer.
1902 static void emit_ia32_SubSP(const ir_node *irn, ia32_emit_env_t *emit_env) {
1903 FILE *F = emit_env->out;
1904 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1906 if (is_ia32_ImmConst(irn)) {
1907 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "add %1D, %C", irn, irn);
1909 else if (is_ia32_ImmSymConst(irn)) {
1910 if (get_ia32_op_type(irn) == ia32_Normal)
1911 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "add %1D, OFFSET_FLAT:%C", irn, irn);
1912 else /* source address mode */
1913 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "add %1D, [%s%s]", irn, get_id_str(get_ia32_am_sc(irn)), get_ia32_am_offs(irn));
1916 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "add %1D, %2S", irn, irn);
1918 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* free space on stack */");
1924 * Emits code to load the TLS base
1926 static void emit_ia32_LdTls(const ir_node *irn, ia32_emit_env_t *emit_env) {
1927 FILE *F = emit_env->out;
1928 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1930 switch (asm_flavour) {
1932 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "mov %1D, DWORD PTR %%gs:0", irn);
1935 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "mov %1D, DWORD PTR %%gs:0", irn);
1938 assert(0 && "unsupported TLS");
1941 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* get thread local storage base */");
1946 static void emit_be_Return(const ir_node *n, ia32_emit_env_t *env) {
1948 const lc_arg_env_t *arg_env = ia32_get_arg_env();
1950 lc_efprintf(arg_env, F, "\t%-35s %-60s /* %+F (%+G) */\n", "ret", "/* be_Return */", n, n);
1953 static void emit_Nothing(const ir_node *n, ia32_emit_env_t *env) {
1956 ir_fprintf(F, "\t%35s /* %+F (%+G) */\n", " ", n, n);
1960 /***********************************************************************************
1963 * _ __ ___ __ _ _ _ __ | |_ _ __ __ _ _ __ ___ _____ _____ _ __| | __
1964 * | '_ ` _ \ / _` | | '_ \ | _| '__/ _` | '_ ` _ \ / _ \ \ /\ / / _ \| '__| |/ /
1965 * | | | | | | (_| | | | | | | | | | | (_| | | | | | | __/\ V V / (_) | | | <
1966 * |_| |_| |_|\__,_|_|_| |_| |_| |_| \__,_|_| |_| |_|\___| \_/\_/ \___/|_| |_|\_\
1968 ***********************************************************************************/
1971 * Enters the emitter functions for handled nodes into the generic
1972 * pointer of an opcode.
1974 static void ia32_register_emitters(void) {
1976 #define IA32_EMIT2(a,b) op_ia32_##a->ops.generic = (op_func)emit_ia32_##b
1977 #define IA32_EMIT(a) IA32_EMIT2(a,a)
1978 #define EMIT(a) op_##a->ops.generic = (op_func)emit_##a
1979 #define IGN(a) op_##a->ops.generic = (op_func)emit_Nothing
1980 #define BE_EMIT(a) op_be_##a->ops.generic = (op_func)emit_be_##a
1981 #define BE_IGN(a) op_be_##a->ops.generic = (op_func)emit_Nothing
1983 /* first clear the generic function pointer for all ops */
1984 clear_irp_opcodes_generic_func();
1986 /* register all emitter functions defined in spec */
1987 ia32_register_spec_emitters();
1989 /* other ia32 emitter functions */
1995 IA32_EMIT(PsiCondCMov);
1997 IA32_EMIT(PsiCondSet);
1998 IA32_EMIT(SwitchJmp);
2001 IA32_EMIT(Conv_I2FP);
2002 IA32_EMIT(Conv_FP2I);
2003 IA32_EMIT(Conv_FP2FP);
2004 IA32_EMIT(Conv_I2I);
2005 IA32_EMIT(Conv_I2I8Bit);
2012 IA32_EMIT(xCmpCMov);
2013 IA32_EMIT(xCondJmp);
2014 IA32_EMIT2(fcomJmp, x87CondJmp);
2015 IA32_EMIT2(fcompJmp, x87CondJmp);
2016 IA32_EMIT2(fcomppJmp, x87CondJmp);
2017 IA32_EMIT2(fcomrJmp, x87CondJmp);
2018 IA32_EMIT2(fcomrpJmp, x87CondJmp);
2019 IA32_EMIT2(fcomrppJmp, x87CondJmp);
2021 /* benode emitter */
2047 static const char *last_name = NULL;
2048 static unsigned last_line = -1;
2049 static unsigned num = -1;
2052 * Emit the debug support for node irn.
2054 static void ia32_emit_dbg(const ir_node *irn, ia32_emit_env_t *env) {
2055 dbg_info *db = get_irn_dbg_info(irn);
2057 const char *fname = be_retrieve_dbg_info(db, &lineno);
2059 if (! env->cg->birg->main_env->options->stabs_debug_support)
2063 if (last_name != fname) {
2065 be_dbg_include_begin(env->cg->birg->main_env->db_handle, fname);
2068 if (last_line != lineno) {
2072 snprintf(name, sizeof(name), ".LM%u", ++num);
2074 be_dbg_line(env->cg->birg->main_env->db_handle, lineno, name);
2075 fprintf(F, "%s:\n", name);
2081 * Emits code for a node.
2083 static void ia32_emit_node(const ir_node *irn, void *env) {
2084 ia32_emit_env_t *emit_env = env;
2085 ir_op *op = get_irn_op(irn);
2086 DEBUG_ONLY(firm_dbg_module_t *mod = emit_env->mod;)
2088 DBG((mod, LEVEL_1, "emitting code for %+F\n", irn));
2090 if (op->ops.generic) {
2091 void (*emit)(const ir_node *, void *) = (void (*)(const ir_node *, void *))op->ops.generic;
2092 ia32_emit_dbg(irn, emit_env);
2096 emit_Nothing(irn, env);
2097 ir_fprintf(stderr, "Warning: No emit handler for node %+F (%+G)\n", irn, irn);
2102 * Emits gas alignment directives
2104 static void ia32_emit_alignment(FILE *F, unsigned align, unsigned skip) {
2105 fprintf(F, "\t.p2align %u,,%u\n", align, skip);
2109 * Emits gas alignment directives for Functions depended on cpu architecture.
2111 static void ia32_emit_align_func(FILE *F, cpu_support cpu) {
2113 unsigned maximum_skip;
2128 maximum_skip = (1 << align) - 1;
2129 ia32_emit_alignment(F, align, maximum_skip);
2133 * Emits gas alignment directives for Labels depended on cpu architecture.
2135 static void ia32_emit_align_label(FILE *F, cpu_support cpu) {
2136 unsigned align; unsigned maximum_skip;
2151 maximum_skip = (1 << align) - 1;
2152 ia32_emit_alignment(F, align, maximum_skip);
2155 static int is_first_loop_block(ir_node *block, ir_node *prev_block, ia32_emit_env_t *env) {
2156 ir_exec_freq *execfreqs = env->cg->birg->execfreqs;
2157 double block_freq, prev_freq;
2158 static const double DELTA = .0001;
2159 cpu_support cpu = env->isa->opt_arch;
2161 if(execfreqs == NULL)
2163 if(cpu == arch_i386 || cpu == arch_i486)
2166 block_freq = get_block_execfreq(execfreqs, block);
2167 prev_freq = get_block_execfreq(execfreqs, prev_block);
2169 if(block_freq < DELTA || prev_freq < DELTA)
2172 block_freq /= prev_freq;
2176 case arch_athlon_64:
2178 return block_freq > 3;
2183 return block_freq > 2;
2187 * Walks over the nodes in a block connected by scheduling edges
2188 * and emits code for each node.
2190 static void ia32_gen_block(ir_node *block, ir_node *last_block, ia32_emit_env_t *env) {
2191 ir_graph *irg = get_irn_irg(block);
2192 ir_node *start_block = get_irg_start_block(irg);
2198 assert(is_Block(block));
2200 if (block == start_block)
2203 if (need_label && get_irn_arity(block) == 1) {
2204 ir_node *pred_block = get_Block_cfgpred_block(block, 0);
2206 if (pred_block == last_block && get_irn_n_edges_kind(pred_block, EDGE_KIND_BLOCK) <= 2)
2210 /* special case: if one of our cfg preds is a switch-jmp we need a label, */
2211 /* otherwise there might be jump table entries jumping to */
2212 /* non-existent (omitted) labels */
2213 for (i = get_Block_n_cfgpreds(block) - 1; i >= 0; --i) {
2214 ir_node *pred = get_Block_cfgpred(block, i);
2216 if (is_Proj(pred)) {
2217 assert(get_irn_mode(pred) == mode_X);
2218 if (is_ia32_SwitchJmp(get_Proj_pred(pred))) {
2225 /* special case because the start block contains no jump instruction */
2226 if (last_block == start_block) {
2227 const ir_edge_t *edge;
2228 ir_node *startsucc = NULL;
2230 foreach_block_succ(start_block, edge) {
2231 startsucc = get_edge_src_irn(edge);
2232 if (startsucc != start_block)
2235 assert(startsucc != NULL);
2237 /* if the last block was the start block and we are not inside the */
2238 /* start successor, emit a jump to the start successor */
2239 if (startsucc != block) {
2240 char buf[SNPRINTF_BUF_LEN];
2241 ir_snprintf(buf, sizeof(buf), BLOCK_PREFIX("%d"),
2242 get_irn_node_nr(startsucc));
2243 ir_fprintf(F, "\tjmp %s\n", buf);
2248 char cmd_buf[SNPRINTF_BUF_LEN];
2251 ir_exec_freq *execfreqs = env->cg->birg->execfreqs;
2253 /* align the loop headers */
2254 if (! is_first_loop_block(block, last_block, env)) {
2255 /* align blocks where the previous block has no fallthrough */
2256 arity = get_irn_arity(block);
2258 for (i = 0; i < arity; ++i) {
2259 ir_node *predblock = get_Block_cfgpred_block(block, i);
2261 if (predblock == last_block) {
2269 ia32_emit_align_label(env->out, env->isa->opt_arch);
2271 ir_snprintf(cmd_buf, sizeof(cmd_buf), BLOCK_PREFIX("%d:"),
2272 get_irn_node_nr(block));
2273 fprintf(F, "%-43s ", cmd_buf);
2275 /* emit list of pred blocks in comment */
2276 fprintf(F, "/* preds:");
2278 arity = get_irn_arity(block);
2279 for (i = 0; i < arity; ++i) {
2280 ir_node *predblock = get_Block_cfgpred_block(block, i);
2281 fprintf(F, " %ld", get_irn_node_nr(predblock));
2284 if (execfreqs != NULL) {
2285 fprintf(F, " freq: %f", get_block_execfreq(execfreqs, block));
2288 fprintf(F, " */\n");
2291 /* emit the contents of the block */
2292 ia32_emit_dbg(block, env);
2293 sched_foreach(block, irn) {
2294 ia32_emit_node(irn, env);
2299 * Emits code for function start.
2301 static void ia32_emit_func_prolog(FILE *F, ir_graph *irg, ia32_emit_env_t *emit_env) {
2302 entity *irg_ent = get_irg_entity(irg);
2303 const char *irg_name = get_entity_ld_name(irg_ent);
2304 cpu_support cpu = emit_env->isa->opt_arch;
2305 const be_irg_t *birg = emit_env->cg->birg;
2308 ia32_switch_section(F, SECTION_TEXT);
2309 be_dbg_method_begin(birg->main_env->db_handle, irg_ent, be_abi_get_stack_layout(birg->abi));
2310 ia32_emit_align_func(F, cpu);
2311 if (get_entity_visibility(irg_ent) == visibility_external_visible) {
2312 fprintf(F, ".globl %s\n", irg_name);
2314 ia32_dump_function_object(F, irg_name);
2315 fprintf(F, "%s:\n", irg_name);
2319 * Emits code for function end
2321 static void ia32_emit_func_epilog(FILE *F, ir_graph *irg, ia32_emit_env_t *emit_env) {
2322 const char *irg_name = get_entity_ld_name(get_irg_entity(irg));
2323 const be_irg_t *birg = emit_env->cg->birg;
2325 ia32_dump_function_size(F, irg_name);
2326 be_dbg_method_end(birg->main_env->db_handle);
2332 * Sets labels for control flow nodes (jump target)
2333 * TODO: Jump optimization
2335 static void ia32_gen_labels(ir_node *block, void *env) {
2337 int n = get_Block_n_cfgpreds(block);
2339 for (n--; n >= 0; n--) {
2340 pred = get_Block_cfgpred(block, n);
2341 set_irn_link(pred, block);
2346 * Main driver. Emits the code for one routine.
2348 void ia32_gen_routine(FILE *F, ir_graph *irg, const ia32_code_gen_t *cg) {
2349 ia32_emit_env_t emit_env;
2351 ir_node *last_block = NULL;
2354 emit_env.arch_env = cg->arch_env;
2356 emit_env.isa = (ia32_isa_t *)cg->arch_env->isa;
2357 FIRM_DBG_REGISTER(emit_env.mod, "firm.be.ia32.emitter");
2359 /* set the global arch_env (needed by print hooks) */
2360 arch_env = cg->arch_env;
2362 ia32_register_emitters();
2364 ia32_emit_func_prolog(F, irg, &emit_env);
2365 irg_block_walk_graph(irg, ia32_gen_labels, NULL, &emit_env);
2367 if ((cg->opt & IA32_OPT_EXTBB) && cg->blk_sched) {
2368 int i, n = ARR_LEN(cg->blk_sched);
2370 for (i = 0; i < n;) {
2373 block = cg->blk_sched[i];
2375 next_bl = i < n ? cg->blk_sched[i] : NULL;
2377 /* set here the link. the emitter expects to find the next block here */
2378 set_irn_link(block, next_bl);
2379 ia32_gen_block(block, last_block, &emit_env);
2384 /* "normal" block schedule: Note the get_next_block() returns the NUMBER of the block
2385 in the block schedule. As this number should NEVER be equal the next block,
2386 we does not need a clear block link here. */
2388 //irg_walk_blkwise_graph(irg, NULL, ia32_gen_block, &emit_env);
2392 ia32_emit_func_epilog(F, irg, &emit_env);