2 * This file implements the node emitter.
3 * @author Christian Wuerdig
22 #include "iredges_t.h"
25 #include "../besched_t.h"
26 #include "../benode_t.h"
28 #include "../be_dbgout.h"
30 #include "ia32_emitter.h"
31 #include "gen_ia32_emitter.h"
32 #include "gen_ia32_regalloc_if.h"
33 #include "ia32_nodes_attr.h"
34 #include "ia32_new_nodes.h"
35 #include "ia32_map_regs.h"
36 #include "bearch_ia32_t.h"
38 #define BLOCK_PREFIX(x) ".L" x
40 #define SNPRINTF_BUF_LEN 128
42 /* global arch_env for lc_printf functions */
43 static const arch_env_t *arch_env = NULL;
45 /** by default, we generate assembler code for the Linux gas */
46 asm_flavour_t asm_flavour = ASM_LINUX_GAS;
49 * Switch to a new section
51 void ia32_switch_section(FILE *F, section_t sec) {
52 static section_t curr_sec = NO_SECTION;
53 static const char *text[ASM_MAX][SECTION_MAX] = {
59 ".section\t.tbss,\"awT\",@nobits",
60 ".section\t.ctors,\"aw\",@progbits"
65 ".section .rdata,\"dr\"",
67 ".section\t.tbss,\"awT\",@nobits",
68 ".section\t.ctors,\"aw\",@progbits"
87 fprintf(F, "\t%s\n", text[asm_flavour][sec]);
95 static void ia32_dump_function_object(FILE *F, const char *name)
97 switch (asm_flavour) {
99 fprintf(F, "\t.type\t%s, @function\n", name);
102 fprintf(F, "\t.def\t%s;\t.scl\t2;\t.type\t32;\t.endef\n", name);
109 static void ia32_dump_function_size(FILE *F, const char *name)
111 switch (asm_flavour) {
113 fprintf(F, "\t.size\t%s, .-%s\n", name, name);
120 /*************************************************************
122 * (_) | | / _| | | | |
123 * _ __ _ __ _ _ __ | |_| |_ | |__ ___| |_ __ ___ _ __
124 * | '_ \| '__| | '_ \| __| _| | '_ \ / _ \ | '_ \ / _ \ '__|
125 * | |_) | | | | | | | |_| | | | | | __/ | |_) | __/ |
126 * | .__/|_| |_|_| |_|\__|_| |_| |_|\___|_| .__/ \___|_|
129 *************************************************************/
131 static INLINE int be_is_unknown_reg(const arch_register_t *reg) {
133 REGS_ARE_EQUAL(reg, &ia32_gp_regs[REG_GP_UKNWN]) || \
134 REGS_ARE_EQUAL(reg, &ia32_xmm_regs[REG_XMM_UKNWN]) || \
135 REGS_ARE_EQUAL(reg, &ia32_vfp_regs[REG_VFP_UKNWN]);
139 * returns true if a node has x87 registers
141 static INLINE int has_x87_register(const ir_node *n) {
142 return is_irn_machine_user(n, 0);
145 /* We always pass the ir_node which is a pointer. */
146 static int ia32_get_arg_type(const lc_arg_occ_t *occ) {
147 return lc_arg_type_ptr;
152 * Returns the register at in position pos.
154 static const arch_register_t *get_in_reg(const ir_node *irn, int pos) {
156 const arch_register_t *reg = NULL;
158 assert(get_irn_arity(irn) > pos && "Invalid IN position");
160 /* The out register of the operator at position pos is the
161 in register we need. */
162 op = get_irn_n(irn, pos);
164 reg = arch_get_irn_register(arch_env, op);
166 assert(reg && "no in register found");
168 /* in case of unknown: just return a register */
169 if (REGS_ARE_EQUAL(reg, &ia32_gp_regs[REG_GP_UKNWN]))
170 reg = &ia32_gp_regs[REG_EAX];
171 else if (REGS_ARE_EQUAL(reg, &ia32_xmm_regs[REG_XMM_UKNWN]))
172 reg = &ia32_xmm_regs[REG_XMM0];
173 else if (REGS_ARE_EQUAL(reg, &ia32_vfp_regs[REG_VFP_UKNWN]))
174 reg = &ia32_vfp_regs[REG_VF0];
180 * Returns the register at out position pos.
182 static const arch_register_t *get_out_reg(const ir_node *irn, int pos) {
184 const arch_register_t *reg = NULL;
186 /* 1st case: irn is not of mode_T, so it has only */
187 /* one OUT register -> good */
188 /* 2nd case: irn is of mode_T -> collect all Projs and ask the */
189 /* Proj with the corresponding projnum for the register */
191 if (get_irn_mode(irn) != mode_T) {
192 reg = arch_get_irn_register(arch_env, irn);
194 else if (is_ia32_irn(irn)) {
195 reg = get_ia32_out_reg(irn, pos);
198 const ir_edge_t *edge;
200 foreach_out_edge(irn, edge) {
201 proj = get_edge_src_irn(edge);
202 assert(is_Proj(proj) && "non-Proj from mode_T node");
203 if (get_Proj_proj(proj) == pos) {
204 reg = arch_get_irn_register(arch_env, proj);
210 assert(reg && "no out register found");
220 * Returns the name of the in register at position pos.
222 static const char *get_ia32_reg_name(ir_node *irn, int pos, enum io_direction in_out) {
223 const arch_register_t *reg;
225 if (in_out == IN_REG) {
226 reg = get_in_reg(irn, pos);
228 if (reg->reg_class == &ia32_reg_classes[CLASS_ia32_vfp]) {
229 /* FIXME: works for binop only */
230 assert(2 <= pos && pos <= 3);
231 reg = get_ia32_attr(irn)->x87[pos - 2];
235 /* destination address mode nodes don't have outputs */
236 if (is_ia32_irn(irn) && get_ia32_op_type(irn) == ia32_AddrModeD) {
240 reg = get_out_reg(irn, pos);
241 if (reg->reg_class == &ia32_reg_classes[CLASS_ia32_vfp])
242 reg = get_ia32_attr(irn)->x87[pos + 2];
244 return arch_register_get_name(reg);
248 * Get the register name for a node.
250 static int ia32_get_reg_name(lc_appendable_t *app,
251 const lc_arg_occ_t *occ, const lc_arg_value_t *arg)
254 ir_node *irn = arg->v_ptr;
255 int nr = occ->width - 1;
258 return lc_appendable_snadd(app, "(null)", 6);
260 buf = get_ia32_reg_name(irn, nr, occ->conversion == 'S' ? IN_REG : OUT_REG);
262 /* append the stupid % to register names */
263 lc_appendable_chadd(app, '%');
264 return lc_appendable_snadd(app, buf, strlen(buf));
268 * Get the x87 register name for a node.
270 static int ia32_get_x87_name(lc_appendable_t *app,
271 const lc_arg_occ_t *occ, const lc_arg_value_t *arg)
274 ir_node *irn = arg->v_ptr;
275 int nr = occ->width - 1;
279 return lc_appendable_snadd(app, "(null)", 6);
281 attr = get_ia32_attr(irn);
282 buf = attr->x87[nr]->name;
283 lc_appendable_chadd(app, '%');
284 return lc_appendable_snadd(app, buf, strlen(buf));
288 * Returns the tarval, offset or scale of an ia32 as a string.
290 static int ia32_const_to_str(lc_appendable_t *app,
291 const lc_arg_occ_t *occ, const lc_arg_value_t *arg)
294 ir_node *irn = arg->v_ptr;
297 return lc_arg_append(app, occ, "(null)", 6);
299 if (occ->conversion == 'C') {
300 buf = get_ia32_cnst(irn);
303 buf = get_ia32_am_offs(irn);
306 return buf ? lc_appendable_snadd(app, buf, strlen(buf)) : 0;
310 * Determines the SSE suffix depending on the mode.
312 static int ia32_get_mode_suffix(lc_appendable_t *app,
313 const lc_arg_occ_t *occ, const lc_arg_value_t *arg)
315 ir_node *irn = arg->v_ptr;
316 ir_mode *mode = get_irn_mode(irn);
318 if (mode == mode_T) {
319 mode = get_ia32_res_mode(irn);
321 mode = get_ia32_ls_mode(irn);
325 return lc_arg_append(app, occ, "(null)", 6);
327 if (mode_is_float(mode)) {
328 return lc_appendable_chadd(app, get_mode_size_bits(mode) == 32 ? 's' : 'd');
331 return lc_appendable_chadd(app, mode_is_signed(mode) ? 's' : 'z');
336 * Return the ia32 printf arg environment.
337 * We use the firm environment with some additional handlers.
339 const lc_arg_env_t *ia32_get_arg_env(void) {
340 static lc_arg_env_t *env = NULL;
342 static const lc_arg_handler_t ia32_reg_handler = { ia32_get_arg_type, ia32_get_reg_name };
343 static const lc_arg_handler_t ia32_const_handler = { ia32_get_arg_type, ia32_const_to_str };
344 static const lc_arg_handler_t ia32_mode_handler = { ia32_get_arg_type, ia32_get_mode_suffix };
345 static const lc_arg_handler_t ia32_x87_handler = { ia32_get_arg_type, ia32_get_x87_name };
348 /* extend the firm printer */
349 env = firm_get_arg_env();
351 lc_arg_register(env, "ia32:sreg", 'S', &ia32_reg_handler);
352 lc_arg_register(env, "ia32:dreg", 'D', &ia32_reg_handler);
353 lc_arg_register(env, "ia32:cnst", 'C', &ia32_const_handler);
354 lc_arg_register(env, "ia32:offs", 'O', &ia32_const_handler);
355 lc_arg_register(env, "ia32:mode", 'M', &ia32_mode_handler);
356 lc_arg_register(env, "ia32:x87", 'X', &ia32_x87_handler);
362 static const char *ia32_get_reg_name_for_mode(ia32_emit_env_t *env, ir_mode *mode, const arch_register_t *reg) {
363 switch(get_mode_size_bits(mode)) {
365 return ia32_get_mapped_reg_name(env->isa->regs_8bit, reg);
367 return ia32_get_mapped_reg_name(env->isa->regs_16bit, reg);
369 return (char *)arch_register_get_name(reg);
374 * Emits registers and/or address mode of a binary operation.
376 const char *ia32_emit_binop(const ir_node *n, ia32_emit_env_t *env) {
377 static char *buf = NULL;
379 /* verify that this function is never called on non-AM supporting operations */
380 //assert(get_ia32_am_support(n) != ia32_am_None && "emit binop expects addressmode support");
382 #define PRODUCES_RESULT(n) \
383 (!(is_ia32_St(n) || \
384 is_ia32_Store8Bit(n) || \
385 is_ia32_CondJmp(n) || \
386 is_ia32_xCondJmp(n) || \
387 is_ia32_CmpSet(n) || \
388 is_ia32_xCmpSet(n) || \
389 is_ia32_SwitchJmp(n)))
392 buf = xcalloc(1, SNPRINTF_BUF_LEN);
395 memset(buf, 0, SNPRINTF_BUF_LEN);
398 switch(get_ia32_op_type(n)) {
400 if (is_ia32_ImmConst(n)) {
401 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%3S, %s", n, get_ia32_cnst(n));
403 else if (is_ia32_ImmSymConst(n)) {
404 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%3S, OFFSET FLAT:%s", n, get_ia32_cnst(n));
407 const arch_register_t *in1 = get_in_reg(n, 2);
408 const arch_register_t *in2 = get_in_reg(n, 3);
409 const arch_register_t *out = PRODUCES_RESULT(n) ? get_out_reg(n, 0) : NULL;
410 const arch_register_t *in;
413 in = out ? (REGS_ARE_EQUAL(out, in2) ? in1 : in2) : in2;
414 out = out ? out : in1;
415 in_name = arch_register_get_name(in);
417 if (is_ia32_emit_cl(n)) {
418 assert(REGS_ARE_EQUAL(&ia32_gp_regs[REG_ECX], in) && "shift operation needs ecx");
422 snprintf(buf, SNPRINTF_BUF_LEN, "%%%s, %%%s", arch_register_get_name(out), in_name);
426 if (is_ia32_ImmConst(n) || is_ia32_ImmSymConst(n)) {
427 assert(! PRODUCES_RESULT(n) && "Source AM with Const must not produce result");
428 snprintf(buf, SNPRINTF_BUF_LEN, "%s, %s", get_ia32_cnst(n), ia32_emit_am(n, env));
431 if (PRODUCES_RESULT(n)) {
432 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%1D, %s", n, ia32_emit_am(n, env));
435 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%3S, %s", n, ia32_emit_am(n, env));
440 if (is_ia32_ImmConst(n) || is_ia32_ImmSymConst(n)) {
441 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%s,%s%s",
442 ia32_emit_am(n, env),
443 is_ia32_ImmSymConst(n) ? " OFFSET FLAT:" : " ", /* In case of a symconst we must add OFFSET to */
444 get_ia32_cnst(n)); /* tell the assembler to store it's address. */
447 const arch_register_t *in1 = get_in_reg(n, get_irn_arity(n) == 5 ? 3 : 2);
448 ir_mode *mode = get_ia32_res_mode(n);
451 mode = mode ? mode : get_ia32_ls_mode(n);
452 in_name = ia32_get_reg_name_for_mode(env, mode, in1);
454 if (is_ia32_emit_cl(n)) {
455 assert(REGS_ARE_EQUAL(&ia32_gp_regs[REG_ECX], in1) && "shift operation needs ecx");
459 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%s, %%%s", ia32_emit_am(n, env), in_name);
463 assert(0 && "unsupported op type");
466 #undef PRODUCES_RESULT
472 * Returns the xxx PTR string for a given mode
474 * @param mode the mode
475 * @param x87_insn if non-zero returns the string for a x87 instruction
476 * else for a SSE instruction
478 static const char *pointer_size(ir_mode *mode, int x87_insn)
481 switch (get_mode_size_bits(mode)) {
482 case 8: return "BYTE PTR";
483 case 16: return "WORD PTR";
484 case 32: return "DWORD PTR";
490 case 96: return "XWORD PTR";
491 default: return NULL;
498 * Emits registers and/or address mode of a binary operation.
500 const char *ia32_emit_x87_binop(const ir_node *n, ia32_emit_env_t *env) {
501 static char *buf = NULL;
503 /* verify that this function is never called on non-AM supporting operations */
504 //assert(get_ia32_am_support(n) != ia32_am_None && "emit binop expects addressmode support");
507 buf = xcalloc(1, SNPRINTF_BUF_LEN);
510 memset(buf, 0, SNPRINTF_BUF_LEN);
513 switch(get_ia32_op_type(n)) {
515 if (is_ia32_ImmConst(n) || is_ia32_ImmSymConst(n)) {
516 ir_mode *mode = get_ia32_ls_mode(n);
517 const char *p = pointer_size(mode, 1);
518 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%s %s", p, get_ia32_cnst(n));
521 ia32_attr_t *attr = get_ia32_attr(n);
522 const arch_register_t *in1 = attr->x87[0];
523 const arch_register_t *in2 = attr->x87[1];
524 const arch_register_t *out = attr->x87[2];
525 const arch_register_t *in;
528 in = out ? (REGS_ARE_EQUAL(out, in2) ? in1 : in2) : in2;
529 out = out ? out : in1;
530 in_name = arch_register_get_name(in);
532 snprintf(buf, SNPRINTF_BUF_LEN, "%%%s, %%%s", arch_register_get_name(out), in_name);
537 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%s", ia32_emit_am(n, env));
540 assert(0 && "unsupported op type");
547 * Emits registers and/or address mode of a unary operation.
549 const char *ia32_emit_unop(const ir_node *n, ia32_emit_env_t *env) {
550 static char *buf = NULL;
553 buf = xcalloc(1, SNPRINTF_BUF_LEN);
556 memset(buf, 0, SNPRINTF_BUF_LEN);
559 switch(get_ia32_op_type(n)) {
561 if (is_ia32_ImmConst(n)) {
562 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%C", n);
564 else if (is_ia32_ImmSymConst(n)) {
565 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "OFFSET FLAT:%C", n);
568 if (is_ia32_MulS(n) || is_ia32_Mulh(n)) {
569 /* MulS and Mulh implicitly multiply by EAX */
570 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%4S", n);
571 } else if(is_ia32_Push(n)) {
572 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%3S", n);
574 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%1D", n);
579 assert(!is_ia32_Push(n));
580 snprintf(buf, SNPRINTF_BUF_LEN, "%s", ia32_emit_am(n, env));
584 Mulh is emitted via emit_unop
585 imul [MEM] means EDX:EAX <- EAX * [MEM]
587 assert((is_ia32_Mulh(n) || is_ia32_MulS(n) || is_ia32_Push(n)) && "Only MulS and Mulh can have AM source as unop");
588 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%s", ia32_emit_am(n, env));
591 assert(0 && "unsupported op type");
598 * Emits address mode.
600 const char *ia32_emit_am(const ir_node *n, ia32_emit_env_t *env) {
601 ia32_am_flavour_t am_flav = get_ia32_am_flavour(n);
605 static struct obstack *obst = NULL;
606 ir_mode *mode = get_ia32_ls_mode(n);
608 if (! is_ia32_Lea(n))
609 assert(mode && "AM node must have ls_mode attribute set.");
612 obst = xcalloc(1, sizeof(*obst));
615 obstack_free(obst, NULL);
618 /* obstack_free with NULL results in an uninitialized obstack */
621 p = pointer_size(mode, has_x87_register(n) || is_ia32_GetST0(n) || is_ia32_SetST0(n));
623 obstack_printf(obst, "%s ", p);
625 /* emit address mode symconst */
626 if (get_ia32_am_sc(n)) {
627 if (is_ia32_am_sc_sign(n))
628 obstack_printf(obst, "-");
629 obstack_printf(obst, "%s", get_id_str(get_ia32_am_sc(n)));
632 if (am_flav & ia32_B) {
633 obstack_printf(obst, "[");
634 lc_eoprintf(ia32_get_arg_env(), obst, "%1S", n);
638 if (am_flav & ia32_I) {
640 obstack_printf(obst, "+");
643 obstack_printf(obst, "[");
646 lc_eoprintf(ia32_get_arg_env(), obst, "%2S", n);
648 if (am_flav & ia32_S) {
649 obstack_printf(obst, "*%d", 1 << get_ia32_am_scale(n));
655 if (am_flav & ia32_O) {
656 int offs = get_ia32_am_offs_int(n);
659 /* omit explicit + if there was no base or index */
661 obstack_printf(obst, "[%d", offs);
663 obstack_printf(obst, "%+d", offs);
671 obstack_printf(obst, "] ");
673 obstack_1grow(obst, '\0');
674 s = obstack_finish(obst);
682 const char *ia32_emit_adr(const ir_node *irn, ia32_emit_env_t *env)
684 static char buf[SNPRINTF_BUF_LEN];
685 ir_mode *mode = get_ia32_ls_mode(irn);
686 const char *adr = get_ia32_cnst(irn);
687 const char *pref = pointer_size(mode, has_x87_register(irn));
689 snprintf(buf, SNPRINTF_BUF_LEN, "%s %s", pref ? pref : "", adr);
694 * Formated print of commands and comments.
696 static void ia32_fprintf_format(FILE *F, const ir_node *irn, char *cmd_buf, char *cmnt_buf) {
698 const char *name = irn ? be_retrieve_dbg_info(get_irn_dbg_info((ir_node *)irn), &lineno) : NULL;
701 fprintf(F, "\t%-35s %-60s /* %s:%u */\n", cmd_buf, cmnt_buf, name, lineno);
703 fprintf(F, "\t%-35s %-60s\n", cmd_buf, cmnt_buf);
709 * Add a number to a prefix. This number will not be used a second time.
711 static char *get_unique_label(char *buf, size_t buflen, const char *prefix) {
712 static unsigned long id = 0;
713 snprintf(buf, buflen, "%s%lu", prefix, ++id);
719 /*************************************************
722 * ___ _ __ ___ _| |_ ___ ___ _ __ __| |
723 * / _ \ '_ ` _ \| | __| / __/ _ \| '_ \ / _` |
724 * | __/ | | | | | | |_ | (_| (_) | | | | (_| |
725 * \___|_| |_| |_|_|\__| \___\___/|_| |_|\__,_|
727 *************************************************/
730 #define IA32_DO_EMIT(irn) ia32_fprintf_format(F, irn, cmd_buf, cmnt_buf)
733 * coding of conditions
735 struct cmp2conditon_t {
741 * positive conditions for signed compares
743 static const struct cmp2conditon_t cmp2condition_s[] = {
744 { NULL, pn_Cmp_False }, /* always false */
745 { "e", pn_Cmp_Eq }, /* == */
746 { "l", pn_Cmp_Lt }, /* < */
747 { "le", pn_Cmp_Le }, /* <= */
748 { "g", pn_Cmp_Gt }, /* > */
749 { "ge", pn_Cmp_Ge }, /* >= */
750 { "ne", pn_Cmp_Lg }, /* != */
751 { "ordered", pn_Cmp_Leg }, /* Floating point: ordered */
752 { "unordered", pn_Cmp_Uo }, /* FLoting point: unordered */
753 { "e", pn_Cmp_Ue }, /* Floating point: unordered or == */
754 { "b", pn_Cmp_Ul }, /* Floating point: unordered or < */
755 { "be", pn_Cmp_Ule }, /* Floating point: unordered or <= */
756 { "a", pn_Cmp_Ug }, /* Floating point: unordered or > */
757 { "ae", pn_Cmp_Uge }, /* Floating point: unordered or >= */
758 { "ne", pn_Cmp_Ne }, /* Floating point: unordered or != */
759 { NULL, pn_Cmp_True }, /* always true */
763 * positive conditions for unsigned compares
765 static const struct cmp2conditon_t cmp2condition_u[] = {
766 { NULL, pn_Cmp_False }, /* always false */
767 { "e", pn_Cmp_Eq }, /* == */
768 { "b", pn_Cmp_Lt }, /* < */
769 { "be", pn_Cmp_Le }, /* <= */
770 { "a", pn_Cmp_Gt }, /* > */
771 { "ae", pn_Cmp_Ge }, /* >= */
772 { "ne", pn_Cmp_Lg }, /* != */
773 { "ordered", pn_Cmp_Leg }, /* Floating point: ordered */
774 { "unordered", pn_Cmp_Uo }, /* FLoting point: unordered */
775 { "e", pn_Cmp_Ue }, /* Floating point: unordered or == */
776 { "b", pn_Cmp_Ul }, /* Floating point: unordered or < */
777 { "be", pn_Cmp_Ule }, /* Floating point: unordered or <= */
778 { "a", pn_Cmp_Ug }, /* Floating point: unordered or > */
779 { "ae", pn_Cmp_Uge }, /* Floating point: unordered or >= */
780 { "ne", pn_Cmp_Ne }, /* Floating point: unordered or != */
781 { NULL, pn_Cmp_True }, /* always true */
785 * returns the condition code
787 static const char *get_cmp_suffix(int cmp_code, int unsigned_cmp)
789 assert(cmp2condition_s[cmp_code].num == cmp_code);
790 assert(cmp2condition_u[cmp_code].num == cmp_code);
792 return unsigned_cmp ? cmp2condition_u[cmp_code & 7].name : cmp2condition_s[cmp_code & 7].name;
796 * Returns the target block for a control flow node.
798 static ir_node *get_cfop_target_block(const ir_node *irn) {
799 return get_irn_link(irn);
803 * Returns the target label for a control flow node.
805 static char *get_cfop_target(const ir_node *irn, char *buf) {
806 ir_node *bl = get_cfop_target_block(irn);
808 snprintf(buf, SNPRINTF_BUF_LEN, BLOCK_PREFIX("%ld"), get_irn_node_nr(bl));
812 /** Return the next block in Block schedule */
813 static ir_node *next_blk_sched(const ir_node *block) {
814 return get_irn_link(block);
818 * Returns the Proj with projection number proj and NOT mode_M
820 static ir_node *get_proj(const ir_node *irn, long proj) {
821 const ir_edge_t *edge;
824 assert(get_irn_mode(irn) == mode_T && "expected mode_T node");
826 foreach_out_edge(irn, edge) {
827 src = get_edge_src_irn(edge);
829 assert(is_Proj(src) && "Proj expected");
830 if (get_irn_mode(src) == mode_M)
833 if (get_Proj_proj(src) == proj)
840 * Emits the jump sequence for a conditional jump (cmp + jmp_true + jmp_false)
842 static void finish_CondJmp(FILE *F, const ir_node *irn, ir_mode *mode) {
843 const ir_node *proj_true;
844 const ir_node *proj_false;
845 const ir_node *block;
846 const ir_node *next_block;
847 char buf[SNPRINTF_BUF_LEN];
848 char cmd_buf[SNPRINTF_BUF_LEN];
849 char cmnt_buf[SNPRINTF_BUF_LEN];
854 /* get both Proj's */
855 proj_true = get_proj(irn, pn_Cond_true);
856 assert(proj_true && "CondJmp without true Proj");
858 proj_false = get_proj(irn, pn_Cond_false);
859 assert(proj_false && "CondJmp without false Proj");
861 pnc = get_ia32_pncode(irn);
863 /* for now, the code works for scheduled and non-schedules blocks */
864 block = get_nodes_block(irn);
866 /* we have a block schedule */
867 next_block = next_blk_sched(block);
869 if (get_cfop_target_block(proj_true) == next_block) {
870 /* exchange both proj's so the second one can be omitted */
871 const ir_node *t = proj_true;
872 proj_true = proj_false;
876 pnc = get_negated_pnc(pnc, mode);
879 /* the first Proj must always be created */
880 is_unsigned = mode_is_float(mode) || ! mode_is_signed(mode);
881 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "j%s %s",
882 get_cmp_suffix(pnc, is_unsigned),
883 get_cfop_target(proj_true, buf));
884 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* %s(a, b) %s*/",
885 get_pnc_string(pnc), flipped ? "(was flipped)" : "");
888 /* the second Proj might be a fallthrough */
889 if (get_cfop_target_block(proj_false) != next_block) {
890 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "jmp %s", get_cfop_target(proj_false, buf));
891 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* otherwise */");
895 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* fallthrough %s */", get_cfop_target(proj_false, buf));
901 * Emits code for conditional jump.
903 static void CondJmp_emitter(const ir_node *irn, ia32_emit_env_t *env) {
905 char cmd_buf[SNPRINTF_BUF_LEN];
906 char cmnt_buf[SNPRINTF_BUF_LEN];
908 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "cmp %s", ia32_emit_binop(irn, env));
909 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F */", irn);
911 finish_CondJmp(F, irn, get_ia32_res_mode(irn));
915 * Emits code for conditional jump with two variables.
917 static void emit_ia32_CondJmp(const ir_node *irn, ia32_emit_env_t *env) {
918 CondJmp_emitter(irn, env);
922 * Emits code for conditional test and jump.
924 static void TestJmp_emitter(const ir_node *irn, ia32_emit_env_t *env) {
926 #define IA32_IS_IMMOP (is_ia32_ImmConst(irn) || is_ia32_ImmSymConst(irn))
929 const char *op1 = arch_register_get_name(get_in_reg(irn, 0));
930 const char *op2 = IA32_IS_IMMOP ? get_ia32_cnst(irn) : NULL;
931 char cmd_buf[SNPRINTF_BUF_LEN];
932 char cmnt_buf[SNPRINTF_BUF_LEN];
935 op2 = arch_register_get_name(get_in_reg(irn, 1));
937 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "test %%%s,%s%s ", op1, IA32_IS_IMMOP ? " " : " %", op2);
938 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F */", irn);
941 finish_CondJmp(F, irn, get_ia32_res_mode(irn));
947 * Emits code for conditional test and jump with two variables.
949 static void emit_ia32_TestJmp(const ir_node *irn, ia32_emit_env_t *env) {
950 TestJmp_emitter(irn, env);
953 static void emit_ia32_CJmp(const ir_node *irn, ia32_emit_env_t *env) {
955 char cmd_buf[SNPRINTF_BUF_LEN];
956 char cmnt_buf[SNPRINTF_BUF_LEN];
958 snprintf(cmd_buf, SNPRINTF_BUF_LEN, " ");
959 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F omitted redundant test */", irn);
961 finish_CondJmp(F, irn, get_ia32_res_mode(irn));
964 static void emit_ia32_CJmpAM(const ir_node *irn, ia32_emit_env_t *env) {
966 char cmd_buf[SNPRINTF_BUF_LEN];
967 char cmnt_buf[SNPRINTF_BUF_LEN];
969 snprintf(cmd_buf, SNPRINTF_BUF_LEN, " ");
970 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F omitted redundant test/cmp */", irn);
972 finish_CondJmp(F, irn, get_ia32_res_mode(irn));
976 * Emits code for conditional SSE floating point jump with two variables.
978 static void emit_ia32_xCondJmp(ir_node *irn, ia32_emit_env_t *env) {
980 char cmd_buf[SNPRINTF_BUF_LEN];
981 char cmnt_buf[SNPRINTF_BUF_LEN];
983 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "ucomis%M %s", irn, ia32_emit_binop(irn, env));
984 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F */", irn);
986 finish_CondJmp(F, irn, mode_F);
991 * Emits code for conditional x87 floating point jump with two variables.
993 static void emit_ia32_x87CondJmp(ir_node *irn, ia32_emit_env_t *env) {
995 char cmd_buf[SNPRINTF_BUF_LEN];
996 char cmnt_buf[SNPRINTF_BUF_LEN];
997 ia32_attr_t *attr = get_ia32_attr(irn);
998 const char *reg = attr->x87[1]->name;
999 const char *instr = "fcom";
1002 switch (get_ia32_irn_opcode(irn)) {
1003 case iro_ia32_fcomrJmp:
1005 case iro_ia32_fcomJmp:
1009 case iro_ia32_fcomrpJmp:
1011 case iro_ia32_fcompJmp:
1014 case iro_ia32_fcomrppJmp:
1016 case iro_ia32_fcomppJmp:
1023 set_ia32_pncode(irn, (long)get_inversed_pnc(get_ia32_pncode(irn)));
1025 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "%s %s%s", instr, reg[0] == '\0' ? "" : "%", reg);
1026 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F */", irn);
1028 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "fnstsw %%ax", irn);
1029 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* Store x87 FPU Control Word */");
1031 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "sahf");
1032 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* Store ah into flags */");
1035 /* the compare flags must be evaluated using carry , ie unsigned */
1036 finish_CondJmp(F, irn, mode_Iu);
1039 static void CMov_emitter(ir_node *irn, ia32_emit_env_t *env) {
1041 const lc_arg_env_t *arg_env = ia32_get_arg_env();
1042 ir_mode *mode = get_irn_mode(get_irn_n(irn, 0));
1043 int is_unsigned = mode_is_float(mode) || ! mode_is_signed(mode);
1044 const char *cmp_suffix = get_cmp_suffix(get_ia32_pncode(irn), is_unsigned);
1045 int is_PsiCondCMov = is_ia32_PsiCondCMov(irn);
1046 int idx_left = 2 - is_PsiCondCMov;
1047 int idx_right = 3 - is_PsiCondCMov;
1049 char cmd_buf[SNPRINTF_BUF_LEN];
1050 char cmnt_buf[SNPRINTF_BUF_LEN];
1051 const arch_register_t *in1, *in2, *out;
1053 out = arch_get_irn_register(env->arch_env, irn);
1054 in1 = arch_get_irn_register(env->arch_env, get_irn_n(irn, idx_left));
1055 in2 = arch_get_irn_register(env->arch_env, get_irn_n(irn, idx_right));
1057 /* we have to emit the cmp first, because the destination register */
1058 /* could be one of the compare registers */
1059 if (is_ia32_CmpCMov(irn)) {
1060 lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "cmp %1S, %2S", irn, irn);
1062 else if (is_ia32_xCmpCMov(irn)) {
1063 lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "ucomis%M %1S, %2S", get_irn_n(irn, 0), irn, irn);
1065 else if (is_PsiCondCMov) {
1066 /* omit compare because flags are already set by And/Or */
1067 lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "test %1S, %1S", irn, irn);
1070 assert(0 && "unsupported CMov");
1072 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* Psi condition */" );
1075 if (REGS_ARE_EQUAL(out, in2)) {
1076 /* best case: default in == out -> do nothing */
1078 else if (REGS_ARE_EQUAL(out, in1)) {
1079 /* true in == out -> need complement compare and exchange true and default in */
1080 ir_node *t = get_irn_n(irn, idx_left);
1081 set_irn_n(irn, idx_left, get_irn_n(irn, idx_right));
1082 set_irn_n(irn, idx_right, t);
1084 cmp_suffix = get_cmp_suffix(get_negated_pnc(get_ia32_pncode(irn), get_irn_mode(irn)), is_unsigned);
1088 /* out is different from in: need copy default -> out */
1090 lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "mov %1D, %3S", irn, irn);
1092 lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "mov %1D, %4S", irn, irn);
1094 lc_esnprintf(arg_env, cmnt_buf, SNPRINTF_BUF_LEN, "/* copy default -> out */" );
1099 lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "cmov%s %1D, %2S", cmp_suffix, irn, irn);
1101 lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "cmov%s %1D, %3S", cmp_suffix, irn, irn);
1103 lc_esnprintf(arg_env, cmnt_buf, SNPRINTF_BUF_LEN, "/* condition is true case */" );
1107 static void emit_ia32_CmpCMov(ir_node *irn, ia32_emit_env_t *env) {
1108 CMov_emitter(irn, env);
1111 static void emit_ia32_PsiCondCMov(ir_node *irn, ia32_emit_env_t *env) {
1112 CMov_emitter(irn, env);
1115 static void emit_ia32_xCmpCMov(ir_node *irn, ia32_emit_env_t *env) {
1116 CMov_emitter(irn, env);
1119 static void Set_emitter(ir_node *irn, ir_mode *mode, ia32_emit_env_t *env) {
1121 const lc_arg_env_t *arg_env = ia32_get_arg_env();
1122 int is_unsigned = mode_is_float(mode) || ! mode_is_signed(mode);
1123 const char *cmp_suffix = get_cmp_suffix(get_ia32_pncode(irn), is_unsigned);
1124 const char *reg8bit;
1126 char cmd_buf[SNPRINTF_BUF_LEN];
1127 char cmnt_buf[SNPRINTF_BUF_LEN];
1128 const arch_register_t *out;
1130 out = arch_get_irn_register(env->arch_env, irn);
1131 reg8bit = ia32_get_mapped_reg_name(env->isa->regs_8bit, out);
1133 if (is_ia32_CmpSet(irn)) {
1134 lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "cmp %s", ia32_emit_binop(irn, env));
1136 else if (is_ia32_xCmpSet(irn)) {
1137 lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "ucomis%M %s", get_irn_n(irn, 2), ia32_emit_binop(irn, env));
1139 else if (is_ia32_PsiCondSet(irn)) {
1140 /* omit compare because flags are already set by And/Or */
1141 snprintf(cmd_buf, SNPRINTF_BUF_LEN, " ");
1144 assert(0 && "unsupported Set");
1146 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* calculate Psi condition */" );
1149 /* use mov to clear target because it doesn't affect the eflags */
1150 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "mov %%%s, 0", arch_register_get_name(out));
1151 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* clear target as set modifies only lower 8 bit */");
1154 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "set%s %%%s", cmp_suffix, reg8bit);
1155 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* set 1 iff true, 0 otherweise */" );
1159 static void emit_ia32_CmpSet(ir_node *irn, ia32_emit_env_t *env) {
1160 Set_emitter(irn, get_irn_mode(get_irn_n(irn, 2)), env);
1163 static void emit_ia32_PsiCondSet(ir_node *irn, ia32_emit_env_t *env) {
1164 Set_emitter(irn, get_irn_mode(get_irn_n(irn, 0)), env);
1167 static void emit_ia32_xCmpSet(ir_node *irn, ia32_emit_env_t *env) {
1168 Set_emitter(irn, get_irn_mode(get_irn_n(irn, 2)), env);
1171 static void emit_ia32_xCmp(ir_node *irn, ia32_emit_env_t *env) {
1173 const lc_arg_env_t *arg_env = ia32_get_arg_env();
1175 long pnc = get_ia32_pncode(irn);
1176 long unord = pnc & pn_Cmp_Uo;
1177 char cmd_buf[SNPRINTF_BUF_LEN];
1178 char cmnt_buf[SNPRINTF_BUF_LEN];
1181 case pn_Cmp_Leg: /* odered */
1184 case pn_Cmp_Uo: /* unordered */
1188 case pn_Cmp_Eq: /* == */
1192 case pn_Cmp_Lt: /* < */
1196 case pn_Cmp_Le: /* <= */
1200 case pn_Cmp_Gt: /* > */
1204 case pn_Cmp_Ge: /* >= */
1208 case pn_Cmp_Lg: /* != */
1213 assert(sse_pnc >= 0 && "unsupported compare");
1215 if (unord && sse_pnc != 3) {
1217 We need a separate compare against unordered.
1218 Quick and Dirty solution:
1219 - get some memory on stack
1223 - and result and stored result
1226 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "sub %%esp, 8");
1227 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* reserve some space for unordered compare result */");
1229 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "cmpsd %s, 3", ia32_emit_binop(irn, env));
1230 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* SSE compare: unordered */");
1232 lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "movsd [%%esp], %1D", irn);
1233 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* store compare result */");
1237 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "cmpsd %s, %d", ia32_emit_binop(irn, env), sse_pnc);
1238 lc_esnprintf(arg_env, cmnt_buf, SNPRINTF_BUF_LEN, "/* SSE compare (%+F) with result in %1D */", irn, irn);
1241 if (unord && sse_pnc != 3) {
1242 lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "andpd %1D, [%%esp]", irn);
1243 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* build the final result */");
1245 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "add %%esp, 8");
1246 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* free allocated space */");
1251 /*********************************************************
1254 * ___ _ __ ___ _| |_ _ _ _ _ __ ___ _ __ ___
1255 * / _ \ '_ ` _ \| | __| | | | | | '_ ` _ \| '_ \/ __|
1256 * | __/ | | | | | | |_ | | |_| | | | | | | |_) \__ \
1257 * \___|_| |_| |_|_|\__| | |\__,_|_| |_| |_| .__/|___/
1260 *********************************************************/
1262 /* jump table entry (target and corresponding number) */
1263 typedef struct _branch_t {
1268 /* jump table for switch generation */
1269 typedef struct _jmp_tbl_t {
1270 ir_node *defProj; /**< default target */
1271 int min_value; /**< smallest switch case */
1272 int max_value; /**< largest switch case */
1273 int num_branches; /**< number of jumps */
1274 char *label; /**< label of the jump table */
1275 branch_t *branches; /**< jump array */
1279 * Compare two variables of type branch_t. Used to sort all switch cases
1281 static int ia32_cmp_branch_t(const void *a, const void *b) {
1282 branch_t *b1 = (branch_t *)a;
1283 branch_t *b2 = (branch_t *)b;
1285 if (b1->value <= b2->value)
1292 * Emits code for a SwitchJmp (creates a jump table if
1293 * possible otherwise a cmp-jmp cascade). Port from
1296 static void emit_ia32_SwitchJmp(const ir_node *irn, ia32_emit_env_t *emit_env) {
1297 unsigned long interval;
1298 char buf[SNPRINTF_BUF_LEN];
1299 int last_value, i, pn;
1302 const ir_edge_t *edge;
1303 const lc_arg_env_t *env = ia32_get_arg_env();
1304 FILE *F = emit_env->out;
1305 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1307 /* fill the table structure */
1308 tbl.label = xmalloc(SNPRINTF_BUF_LEN);
1309 tbl.label = get_unique_label(tbl.label, SNPRINTF_BUF_LEN, ".TBL_");
1311 tbl.num_branches = get_irn_n_edges(irn);
1312 tbl.branches = xcalloc(tbl.num_branches, sizeof(tbl.branches[0]));
1313 tbl.min_value = INT_MAX;
1314 tbl.max_value = INT_MIN;
1317 /* go over all proj's and collect them */
1318 foreach_out_edge(irn, edge) {
1319 proj = get_edge_src_irn(edge);
1320 assert(is_Proj(proj) && "Only proj allowed at SwitchJmp");
1322 pn = get_Proj_proj(proj);
1324 /* create branch entry */
1325 tbl.branches[i].target = proj;
1326 tbl.branches[i].value = pn;
1328 tbl.min_value = pn < tbl.min_value ? pn : tbl.min_value;
1329 tbl.max_value = pn > tbl.max_value ? pn : tbl.max_value;
1331 /* check for default proj */
1332 if (pn == get_ia32_pncode(irn)) {
1333 assert(tbl.defProj == NULL && "found two defProjs at SwitchJmp");
1340 /* sort the branches by their number */
1341 qsort(tbl.branches, tbl.num_branches, sizeof(tbl.branches[0]), ia32_cmp_branch_t);
1343 /* two-complement's magic make this work without overflow */
1344 interval = tbl.max_value - tbl.min_value;
1346 /* emit the table */
1347 lc_esnprintf(env, cmd_buf, SNPRINTF_BUF_LEN, "cmp %1S, %u", irn, interval);
1348 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* compare for switch */");
1351 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "ja %s", get_cfop_target(tbl.defProj, buf));
1352 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* default jump if out of range */");
1355 if (tbl.num_branches > 1) {
1358 lc_esnprintf(env, cmd_buf, SNPRINTF_BUF_LEN, "jmp %s[%1S*4]", tbl.label, irn);
1359 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* get jump table entry as target */");
1362 ia32_switch_section(F, SECTION_RODATA);
1363 fprintf(F, "\t.align 4\n");
1365 fprintf(F, "%s:\n", tbl.label);
1367 snprintf(cmd_buf, SNPRINTF_BUF_LEN, ".long %s", get_cfop_target(tbl.branches[0].target, buf));
1368 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* case %d */", tbl.branches[0].value);
1371 last_value = tbl.branches[0].value;
1372 for (i = 1; i < tbl.num_branches; ++i) {
1373 while (++last_value < tbl.branches[i].value) {
1374 snprintf(cmd_buf, SNPRINTF_BUF_LEN, ".long %s", get_cfop_target(tbl.defProj, buf));
1375 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* default case */");
1378 snprintf(cmd_buf, SNPRINTF_BUF_LEN, ".long %s", get_cfop_target(tbl.branches[i].target, buf));
1379 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* case %d */", last_value);
1382 ia32_switch_section(F, SECTION_TEXT);
1385 /* one jump is enough */
1386 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "jmp %s", get_cfop_target(tbl.branches[0].target, buf));
1387 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* only one case given */");
1398 * Emits code for a unconditional jump.
1400 static void emit_Jmp(const ir_node *irn, ia32_emit_env_t *env) {
1401 ir_node *block, *next_bl;
1403 char buf[SNPRINTF_BUF_LEN], cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1405 /* for now, the code works for scheduled and non-schedules blocks */
1406 block = get_nodes_block(irn);
1408 /* we have a block schedule */
1409 next_bl = next_blk_sched(block);
1410 if (get_cfop_target_block(irn) != next_bl) {
1411 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "jmp %s", get_cfop_target(irn, buf));
1412 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F(%+F) */", irn, get_cfop_target_block(irn));
1416 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* fallthrough %s */", get_cfop_target(irn, buf));
1421 /****************************
1424 * _ __ _ __ ___ _ ___
1425 * | '_ \| '__/ _ \| |/ __|
1426 * | |_) | | | (_) | |\__ \
1427 * | .__/|_| \___/| ||___/
1430 ****************************/
1433 * Emits code for a proj -> node
1435 static void emit_Proj(const ir_node *irn, ia32_emit_env_t *env) {
1436 ir_node *pred = get_Proj_pred(irn);
1438 if (get_irn_op(pred) == op_Start) {
1439 switch(get_Proj_proj(irn)) {
1440 case pn_Start_X_initial_exec:
1449 /**********************************
1452 * | | ___ _ __ _ _| |_) |
1453 * | | / _ \| '_ \| | | | _ <
1454 * | |___| (_) | |_) | |_| | |_) |
1455 * \_____\___/| .__/ \__, |____/
1458 **********************************/
1461 * Emit movsb/w instructions to make mov count divideable by 4
1463 static void emit_CopyB_prolog(FILE *F, const ir_node *irn, int rem) {
1464 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1466 ir_fprintf(F, "\t/* memcopy prolog %+F */\n", irn);
1468 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "cld");
1469 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* copy direction forward */");
1474 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "movsb");
1475 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* memcopy remainder 1 */");
1479 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "movsw");
1480 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* memcopy remainder 2 */");
1484 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "movsb");
1485 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* memcopy remainder 3 */");
1487 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "movsw");
1488 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* memcopy remainder 3 */");
1496 * Emit rep movsd instruction for memcopy.
1498 static void emit_ia32_CopyB(const ir_node *irn, ia32_emit_env_t *emit_env) {
1499 FILE *F = emit_env->out;
1500 tarval *tv = get_ia32_Immop_tarval(irn);
1501 int rem = get_tarval_long(tv);
1502 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1504 emit_CopyB_prolog(F, irn, rem);
1506 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "rep movsd");
1507 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* memcopy */");
1512 * Emits unrolled memcopy.
1514 static void emit_ia32_CopyB_i(const ir_node *irn, ia32_emit_env_t *emit_env) {
1515 tarval *tv = get_ia32_Immop_tarval(irn);
1516 int size = get_tarval_long(tv);
1517 FILE *F = emit_env->out;
1518 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1520 emit_CopyB_prolog(F, irn, size & 0x3);
1524 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "movsd");
1525 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* memcopy unrolled */");
1532 /***************************
1536 * | | / _ \| '_ \ \ / /
1537 * | |___| (_) | | | \ V /
1538 * \_____\___/|_| |_|\_/
1540 ***************************/
1543 * Emit code for conversions (I, FP), (FP, I) and (FP, FP).
1545 static void emit_ia32_Conv_with_FP(const ir_node *irn, ia32_emit_env_t *emit_env) {
1546 FILE *F = emit_env->out;
1547 const lc_arg_env_t *env = ia32_get_arg_env();
1548 ir_mode *src_mode = get_ia32_src_mode(irn);
1549 ir_mode *tgt_mode = get_ia32_tgt_mode(irn);
1550 char *from, *to, buf[64];
1551 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1553 from = mode_is_float(src_mode) ? (get_mode_size_bits(src_mode) == 32 ? "ss" : "sd") : "si";
1554 to = mode_is_float(tgt_mode) ? (get_mode_size_bits(tgt_mode) == 32 ? "ss" : "sd") : "si";
1556 switch(get_ia32_op_type(irn)) {
1558 lc_esnprintf(env, buf, sizeof(buf), "%1D, %3S", irn, irn);
1560 case ia32_AddrModeS:
1561 lc_esnprintf(env, buf, sizeof(buf), "%1D, %s", irn, ia32_emit_am(irn, emit_env));
1564 assert(0 && "unsupported op type for Conv");
1567 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "cvt%s2%s %s", from, to, buf);
1568 lc_esnprintf(env, cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F(%+F, %+F) */", irn, src_mode, tgt_mode);
1572 static void emit_ia32_Conv_I2FP(const ir_node *irn, ia32_emit_env_t *emit_env) {
1573 emit_ia32_Conv_with_FP(irn, emit_env);
1576 static void emit_ia32_Conv_FP2I(const ir_node *irn, ia32_emit_env_t *emit_env) {
1577 emit_ia32_Conv_with_FP(irn, emit_env);
1580 static void emit_ia32_Conv_FP2FP(const ir_node *irn, ia32_emit_env_t *emit_env) {
1581 emit_ia32_Conv_with_FP(irn, emit_env);
1585 * Emits code for an Int conversion.
1587 static void emit_ia32_Conv_I2I(const ir_node *irn, ia32_emit_env_t *emit_env) {
1588 FILE *F = emit_env->out;
1589 const lc_arg_env_t *env = ia32_get_arg_env();
1590 char *move_cmd = "movzx";
1591 char *conv_cmd = NULL;
1592 ir_mode *src_mode = get_ia32_src_mode(irn);
1593 ir_mode *tgt_mode = get_ia32_tgt_mode(irn);
1595 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1596 const arch_register_t *in_reg, *out_reg;
1598 n = get_mode_size_bits(src_mode);
1599 m = get_mode_size_bits(tgt_mode);
1601 if (mode_is_signed(n < m ? src_mode : tgt_mode)) {
1603 if (n == 8 || m == 8)
1605 else if (n == 16 || m == 16)
1608 printf("%d -> %d unsupported\n", n, m);
1609 assert(0 && "unsupported Conv_I2I");
1613 switch(get_ia32_op_type(irn)) {
1615 in_reg = get_in_reg(irn, 2);
1616 out_reg = get_out_reg(irn, 0);
1618 if (REGS_ARE_EQUAL(in_reg, &ia32_gp_regs[REG_EAX]) &&
1619 REGS_ARE_EQUAL(out_reg, in_reg) &&
1620 mode_is_signed(n < m ? src_mode : tgt_mode))
1622 /* argument and result are both in EAX and */
1623 /* signedness is ok: -> use converts */
1624 lc_esnprintf(env, cmd_buf, SNPRINTF_BUF_LEN, "%s", conv_cmd);
1626 else if (REGS_ARE_EQUAL(out_reg, in_reg) &&
1627 ! mode_is_signed(n < m ? src_mode : tgt_mode))
1629 /* argument and result are in the same register */
1630 /* and signedness is ok: -> use and with mask */
1631 int mask = (1 << (n < m ? n : m)) - 1;
1632 lc_esnprintf(env, cmd_buf, SNPRINTF_BUF_LEN, "and %1D, 0x%x", irn, mask);
1635 /* use move w/o sign extension */
1636 lc_esnprintf(env, cmd_buf, SNPRINTF_BUF_LEN, "%s %1D, %%%s",
1637 move_cmd, irn, ia32_get_reg_name_for_mode(emit_env, n < m ? src_mode : tgt_mode, in_reg));
1641 case ia32_AddrModeS:
1642 lc_esnprintf(env, cmd_buf, SNPRINTF_BUF_LEN, "%s %1D, %s",
1643 move_cmd, irn, ia32_emit_am(irn, emit_env));
1646 assert(0 && "unsupported op type for Conv");
1649 lc_esnprintf(env, cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F(%d Bit mode_%F -> %d Bit mode_%F) */",
1650 irn, n, src_mode, m, tgt_mode);
1656 * Emits code for an 8Bit Int conversion.
1658 void emit_ia32_Conv_I2I8Bit(const ir_node *irn, ia32_emit_env_t *emit_env) {
1659 emit_ia32_Conv_I2I(irn, emit_env);
1663 /*******************************************
1666 * | |__ ___ _ __ ___ __| | ___ ___
1667 * | '_ \ / _ \ '_ \ / _ \ / _` |/ _ \/ __|
1668 * | |_) | __/ | | | (_) | (_| | __/\__ \
1669 * |_.__/ \___|_| |_|\___/ \__,_|\___||___/
1671 *******************************************/
1674 * Emits a backend call
1676 static void emit_be_Call(const ir_node *irn, ia32_emit_env_t *emit_env) {
1677 FILE *F = emit_env->out;
1678 entity *ent = be_Call_get_entity(irn);
1679 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1682 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "call %s", get_entity_ld_name(ent));
1685 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "call %1D", get_irn_n(irn, be_pos_Call_ptr));
1688 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F (be_Call) */", irn);
1694 * Emits code to increase stack pointer.
1696 static void emit_be_IncSP(const ir_node *irn, ia32_emit_env_t *emit_env) {
1697 FILE *F = emit_env->out;
1698 int offs = be_get_IncSP_offset(irn);
1699 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1703 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "sub %1S, %u", irn, offs);
1705 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "add %1S, %u", irn, -offs);
1706 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F (IncSP) */", irn);
1709 snprintf(cmd_buf, SNPRINTF_BUF_LEN, " ");
1710 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* omitted %+F (IncSP) with 0 */", irn);
1717 * Emits code to set stack pointer.
1719 static void emit_be_SetSP(const ir_node *irn, ia32_emit_env_t *emit_env) {
1720 FILE *F = emit_env->out;
1721 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1723 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "mov %1D, %3S", irn, irn);
1724 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F (restore SP) */", irn);
1729 * Emits code for Copy/CopyKeep.
1731 static void Copy_emitter(const ir_node *irn, ir_node *op, ia32_emit_env_t *emit_env) {
1732 FILE *F = emit_env->out;
1733 const arch_env_t *aenv = emit_env->arch_env;
1734 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1736 if (REGS_ARE_EQUAL(arch_get_irn_register(aenv, irn), arch_get_irn_register(aenv, op)) ||
1737 be_is_unknown_reg(arch_get_irn_register(aenv, op)))
1740 if (mode_is_float(get_irn_mode(irn)))
1741 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "movs%M %1D, %1S", irn, irn, irn);
1743 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "mov %1D, %1S", irn, irn);
1744 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F */", irn);
1748 static void emit_be_Copy(const ir_node *irn, ia32_emit_env_t *emit_env) {
1749 Copy_emitter(irn, be_get_Copy_op(irn), emit_env);
1752 static void emit_be_CopyKeep(const ir_node *irn, ia32_emit_env_t *emit_env) {
1753 Copy_emitter(irn, be_get_CopyKeep_op(irn), emit_env);
1757 * Emits code for exchange.
1759 static void emit_be_Perm(const ir_node *irn, ia32_emit_env_t *emit_env) {
1760 FILE *F = emit_env->out;
1761 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1762 const arch_register_t *in1, *in2;
1763 const arch_register_class_t *cls1, *cls2;
1765 in1 = arch_get_irn_register(emit_env->arch_env, get_irn_n(irn, 0));
1766 in2 = arch_get_irn_register(emit_env->arch_env, get_irn_n(irn, 1));
1768 cls1 = arch_register_get_class(in1);
1769 cls2 = arch_register_get_class(in2);
1771 assert(cls1 == cls2 && "Register class mismatch at Perm");
1773 if (cls1 == &ia32_reg_classes[CLASS_ia32_gp]) {
1774 if(emit_env->isa->opt_arch == arch_athlon) {
1775 // xchg commands are Vector path on athlons and therefore stall the DirectPath pipeline
1776 // it is nearly always beneficial to use the 3 xor trick instead of an xchg
1778 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "xor %1S, %2S", irn, irn);
1780 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "xor %2S, %1S", irn, irn);
1782 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "xor %1S, %2S", irn, irn);
1784 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "xchg %1S, %2S", irn, irn);
1787 else if (cls1 == &ia32_reg_classes[CLASS_ia32_xmm]) {
1788 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN,
1789 "pxor %1S, %2S\n\tpxor %2S, %1S\n\tpxor %1S, %2S", irn, irn, irn, irn, irn, irn);
1791 else if (cls1 == &ia32_reg_classes[CLASS_ia32_vfp]) {
1795 else if (cls1 == &ia32_reg_classes[CLASS_ia32_st]) {
1800 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F(%1A, %2A) */", irn, irn, irn);
1805 * Emits code for Constant loading.
1807 static void emit_ia32_Const(const ir_node *n, ia32_emit_env_t *env) {
1809 char cmd_buf[256], cmnt_buf[256];
1810 const lc_arg_env_t *arg_env = ia32_get_arg_env();
1811 ir_mode *mode = get_irn_mode(n);
1812 tarval *tv = get_ia32_Immop_tarval(n);
1814 if (get_ia32_op_type(n) == ia32_SymConst) {
1815 lc_esnprintf(arg_env, cmd_buf, 256, "mov %1D, OFFSET FLAT:%C ", n, n);
1816 lc_esnprintf(arg_env, cmnt_buf, 256, "/* Move address of SymConst into register */");
1818 assert(mode == get_tarval_mode(tv));
1819 /* beware: in some rare cases mode is mode_b which has no tarval_null() */
1820 if (tv == get_tarval_b_false() || tv == get_tarval_null(mode)) {
1821 const char *instr = "xor";
1822 if (env->isa->opt_arch == arch_pentium_4) {
1823 /* P4 prefers sub r, r, others xor r, r */
1826 lc_esnprintf(arg_env, cmd_buf, 256, "%s %1D, %1D ", instr, n, n);
1827 lc_esnprintf(arg_env, cmnt_buf, 256, "/* optimized mov 0 to register */");
1829 lc_esnprintf(arg_env, cmd_buf, 256, "mov %1D, %C ", n, n);
1830 lc_esnprintf(arg_env, cmnt_buf, 256, "/* Mov Const into register */");
1833 lc_efprintf(arg_env, F, "\t%-35s %-60s /* %+F (%+G) */\n", cmd_buf, cmnt_buf, n, n);
1837 * Emits code to increase stack pointer.
1839 static void emit_ia32_AddSP(const ir_node *irn, ia32_emit_env_t *emit_env) {
1840 FILE *F = emit_env->out;
1841 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1843 if (is_ia32_ImmConst(irn)) {
1844 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "sub %1D, %C", irn, irn);
1846 else if (is_ia32_ImmSymConst(irn)) {
1847 if (get_ia32_op_type(irn) == ia32_Normal)
1848 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "sub %1D, OFFSET_FLAT:%C", irn, irn);
1849 else /* source address mode */
1850 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "sub %1D, [%s%s]", irn, get_id_str(get_ia32_am_sc(irn)), get_ia32_am_offs(irn));
1853 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "sub %1D, %2S", irn, irn);
1855 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* reserve space on stack */");
1861 * Emits code to increase stack pointer.
1863 static void emit_ia32_SubSP(const ir_node *irn, ia32_emit_env_t *emit_env) {
1864 FILE *F = emit_env->out;
1865 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1867 if (is_ia32_ImmConst(irn)) {
1868 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "add %1D, %C", irn, irn);
1870 else if (is_ia32_ImmSymConst(irn)) {
1871 if (get_ia32_op_type(irn) == ia32_Normal)
1872 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "add %1D, OFFSET_FLAT:%C", irn, irn);
1873 else /* source address mode */
1874 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "add %1D, [%s%s]", irn, get_id_str(get_ia32_am_sc(irn)), get_ia32_am_offs(irn));
1877 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "add %1D, %2S", irn, irn);
1879 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* free space on stack */");
1885 * Emits code to load the TLS base
1887 static void emit_ia32_LdTls(const ir_node *irn, ia32_emit_env_t *emit_env) {
1888 FILE *F = emit_env->out;
1889 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1891 switch (asm_flavour) {
1893 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "mov %1D, DWORD PTR %%gs:0", irn);
1896 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "mov %1D, DWORD PTR %%gs:0", irn);
1899 assert(0 && "unsupported TLS");
1902 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* get thread local storage base */");
1907 static void emit_be_Return(const ir_node *n, ia32_emit_env_t *env) {
1909 const lc_arg_env_t *arg_env = ia32_get_arg_env();
1911 lc_efprintf(arg_env, F, "\t%-35s %-60s /* %+F (%+G) */\n", "ret", "/* be_Return */", n, n);
1914 static void emit_Nothing(const ir_node *n, ia32_emit_env_t *env) {
1917 ir_fprintf(F, "\t%35s /* %+F (%+G) */\n", " ", n, n);
1921 /***********************************************************************************
1924 * _ __ ___ __ _ _ _ __ | |_ _ __ __ _ _ __ ___ _____ _____ _ __| | __
1925 * | '_ ` _ \ / _` | | '_ \ | _| '__/ _` | '_ ` _ \ / _ \ \ /\ / / _ \| '__| |/ /
1926 * | | | | | | (_| | | | | | | | | | | (_| | | | | | | __/\ V V / (_) | | | <
1927 * |_| |_| |_|\__,_|_|_| |_| |_| |_| \__,_|_| |_| |_|\___| \_/\_/ \___/|_| |_|\_\
1929 ***********************************************************************************/
1932 * Enters the emitter functions for handled nodes into the generic
1933 * pointer of an opcode.
1935 static void ia32_register_emitters(void) {
1937 #define IA32_EMIT2(a,b) op_ia32_##a->ops.generic = (op_func)emit_ia32_##b
1938 #define IA32_EMIT(a) IA32_EMIT2(a,a)
1939 #define EMIT(a) op_##a->ops.generic = (op_func)emit_##a
1940 #define IGN(a) op_##a->ops.generic = (op_func)emit_Nothing
1941 #define BE_EMIT(a) op_be_##a->ops.generic = (op_func)emit_be_##a
1942 #define BE_IGN(a) op_be_##a->ops.generic = (op_func)emit_Nothing
1944 /* first clear the generic function pointer for all ops */
1945 clear_irp_opcodes_generic_func();
1947 /* register all emitter functions defined in spec */
1948 ia32_register_spec_emitters();
1950 /* other ia32 emitter functions */
1956 IA32_EMIT(PsiCondCMov);
1958 IA32_EMIT(PsiCondSet);
1959 IA32_EMIT(SwitchJmp);
1962 IA32_EMIT(Conv_I2FP);
1963 IA32_EMIT(Conv_FP2I);
1964 IA32_EMIT(Conv_FP2FP);
1965 IA32_EMIT(Conv_I2I);
1966 IA32_EMIT(Conv_I2I8Bit);
1973 IA32_EMIT(xCmpCMov);
1974 IA32_EMIT(xCondJmp);
1975 IA32_EMIT2(fcomJmp, x87CondJmp);
1976 IA32_EMIT2(fcompJmp, x87CondJmp);
1977 IA32_EMIT2(fcomppJmp, x87CondJmp);
1978 IA32_EMIT2(fcomrJmp, x87CondJmp);
1979 IA32_EMIT2(fcomrpJmp, x87CondJmp);
1980 IA32_EMIT2(fcomrppJmp, x87CondJmp);
1982 /* benode emitter */
2008 static const char *last_name = NULL;
2009 static unsigned last_line = -1;
2010 static unsigned num = -1;
2013 * Emit the debug support for node irn.
2015 static void ia32_emit_dbg(const ir_node *irn, ia32_emit_env_t *env) {
2016 dbg_info *db = get_irn_dbg_info(irn);
2018 const char *fname = be_retrieve_dbg_info(db, &lineno);
2021 if (last_name != fname) {
2023 be_dbg_include_begin(env->cg->birg->main_env->db_handle, fname);
2026 if (last_line != lineno) {
2030 snprintf(name, sizeof(name), ".LM%u", ++num);
2032 be_dbg_line(env->cg->birg->main_env->db_handle, lineno, name);
2033 fprintf(F, "%s:\n", name);
2039 * Emits code for a node.
2041 static void ia32_emit_node(const ir_node *irn, void *env) {
2042 ia32_emit_env_t *emit_env = env;
2043 ir_op *op = get_irn_op(irn);
2044 DEBUG_ONLY(firm_dbg_module_t *mod = emit_env->mod;)
2046 DBG((mod, LEVEL_1, "emitting code for %+F\n", irn));
2048 if (op->ops.generic) {
2049 void (*emit)(const ir_node *, void *) = (void (*)(const ir_node *, void *))op->ops.generic;
2050 ia32_emit_dbg(irn, emit_env);
2054 emit_Nothing(irn, env);
2055 ir_fprintf(stderr, "Warning: No emit handler for node %+F (%+G)\n", irn, irn);
2060 * Emits gas alignment directives
2062 static void ia32_emit_alignment(FILE *F, unsigned align, unsigned skip) {
2063 fprintf(F, "\t.p2align %u,,%u\n", align, skip);
2067 * Emits gas alignment directives for Functions depended on cpu architecture.
2069 static void ia32_emit_align_func(FILE *F, cpu_support cpu) {
2071 unsigned maximum_skip;
2086 maximum_skip = (1 << align) - 1;
2087 ia32_emit_alignment(F, align, maximum_skip);
2091 * Emits gas alignment directives for Labels depended on cpu architecture.
2093 static void ia32_emit_align_label(FILE *F, cpu_support cpu) {
2094 unsigned align; unsigned maximum_skip;
2109 maximum_skip = (1 << align) - 1;
2110 ia32_emit_alignment(F, align, maximum_skip);
2113 static int is_first_loop_block(ir_node *block, ir_node *prev_block, ia32_emit_env_t *env) {
2114 exec_freq_t *execfreqs = env->cg->birg->execfreqs;
2115 double block_freq, prev_freq;
2116 static const double DELTA = .0001;
2117 cpu_support cpu = env->isa->opt_arch;
2119 if(execfreqs == NULL)
2121 if(cpu == arch_i386 || cpu == arch_i486)
2124 block_freq = get_block_execfreq(execfreqs, block);
2125 prev_freq = get_block_execfreq(execfreqs, prev_block);
2127 if(block_freq < DELTA || prev_freq < DELTA)
2130 block_freq /= prev_freq;
2134 case arch_athlon_64:
2136 return block_freq > 3;
2141 return block_freq > 2;
2145 * Walks over the nodes in a block connected by scheduling edges
2146 * and emits code for each node.
2148 static void ia32_gen_block(ir_node *block, ir_node *last_block, void *env) {
2149 ia32_emit_env_t *emit_env = env;
2151 int need_label = block != get_irg_start_block(get_irn_irg(block));
2152 FILE *F = emit_env->out;
2154 if (! is_Block(block))
2157 if (need_label && (emit_env->cg->opt & IA32_OPT_EXTBB)) {
2158 /* if the extended block scheduler is used, only leader blocks need
2160 need_label = (block == get_extbb_leader(get_nodes_extbb(block)));
2164 char cmd_buf[SNPRINTF_BUF_LEN];
2168 // align the loop headers
2169 if(!is_first_loop_block(block, last_block, emit_env)) {
2171 // align blocks where the previous block has no fallthrough
2172 arity = get_irn_arity(block);
2173 for(i = 0; i < arity; ++i) {
2174 ir_node *predblock = get_Block_cfgpred_block(block, i);
2175 if(predblock == last_block) {
2183 ia32_emit_align_label(emit_env->out, emit_env->isa->opt_arch);
2185 ir_snprintf(cmd_buf, sizeof(cmd_buf), BLOCK_PREFIX("%d:"),
2186 get_irn_node_nr(block));
2187 fprintf(F, "%-43s ", cmd_buf);
2189 /* emit list of pred blocks in comment */
2190 fprintf(F, "/* preds:");
2192 arity = get_irn_arity(block);
2193 for(i = 0; i < arity; ++i) {
2194 ir_node *predblock = get_Block_cfgpred_block(block, i);
2195 fprintf(F, " %ld", get_irn_node_nr(predblock));
2197 fprintf(F, " */\n");
2200 /* emit the contents of the block */
2201 ia32_emit_dbg(block, env);
2202 sched_foreach(block, irn) {
2203 ia32_emit_node(irn, env);
2208 * Emits code for function start.
2210 static void ia32_emit_func_prolog(FILE *F, ir_graph *irg, ia32_emit_env_t *emit_env) {
2211 entity *irg_ent = get_irg_entity(irg);
2212 const char *irg_name = get_entity_ld_name(irg_ent);
2213 cpu_support cpu = emit_env->isa->opt_arch;
2214 const be_irg_t *birg = emit_env->cg->birg;
2217 ia32_switch_section(F, SECTION_TEXT);
2218 be_dbg_method_begin(birg->main_env->db_handle, irg_ent, be_abi_get_stack_layout(birg->abi));
2219 ia32_emit_align_func(F, cpu);
2220 if (get_entity_visibility(irg_ent) == visibility_external_visible) {
2221 fprintf(F, ".globl %s\n", irg_name);
2223 ia32_dump_function_object(F, irg_name);
2224 fprintf(F, "%s:\n", irg_name);
2228 * Emits code for function end
2230 static void ia32_emit_func_epilog(FILE *F, ir_graph *irg, ia32_emit_env_t *emit_env) {
2231 const char *irg_name = get_entity_ld_name(get_irg_entity(irg));
2232 const be_irg_t *birg = emit_env->cg->birg;
2234 ia32_dump_function_size(F, irg_name);
2235 be_dbg_method_end(birg->main_env->db_handle);
2241 * Sets labels for control flow nodes (jump target)
2242 * TODO: Jump optimization
2244 static void ia32_gen_labels(ir_node *block, void *env) {
2246 int n = get_Block_n_cfgpreds(block);
2248 for (n--; n >= 0; n--) {
2249 pred = get_Block_cfgpred(block, n);
2250 set_irn_link(pred, block);
2255 * Main driver. Emits the code for one routine.
2257 void ia32_gen_routine(FILE *F, ir_graph *irg, const ia32_code_gen_t *cg) {
2258 ia32_emit_env_t emit_env;
2260 ir_node *last_block = NULL;
2263 emit_env.arch_env = cg->arch_env;
2265 emit_env.isa = (ia32_isa_t *)cg->arch_env->isa;
2266 FIRM_DBG_REGISTER(emit_env.mod, "firm.be.ia32.emitter");
2268 /* set the global arch_env (needed by print hooks) */
2269 arch_env = cg->arch_env;
2271 ia32_register_emitters();
2273 ia32_emit_func_prolog(F, irg, &emit_env);
2274 irg_block_walk_graph(irg, ia32_gen_labels, NULL, &emit_env);
2276 if ((cg->opt & IA32_OPT_EXTBB) && cg->blk_sched) {
2277 int i, n = ARR_LEN(cg->blk_sched);
2279 for (i = 0; i < n;) {
2282 block = cg->blk_sched[i];
2284 next_bl = i < n ? cg->blk_sched[i] : NULL;
2286 /* set here the link. the emitter expects to find the next block here */
2287 set_irn_link(block, next_bl);
2288 ia32_gen_block(block, last_block, &emit_env);
2293 /* "normal" block schedule: Note the get_next_block() returns the NUMBER of the block
2294 in the block schedule. As this number should NEVER be equal the next block,
2295 we does not need a clear block link here. */
2297 //irg_walk_blkwise_graph(irg, NULL, ia32_gen_block, &emit_env);
2301 ia32_emit_func_epilog(F, irg, &emit_env);