2 * This file implements the node emitter.
3 * @author Christian Wuerdig
22 #include "iredges_t.h"
24 #include "../besched_t.h"
25 #include "../benode_t.h"
27 #include "ia32_emitter.h"
28 #include "gen_ia32_emitter.h"
29 #include "gen_ia32_regalloc_if.h"
30 #include "ia32_nodes_attr.h"
31 #include "ia32_new_nodes.h"
32 #include "ia32_map_regs.h"
33 #include "bearch_ia32_t.h"
35 #define BLOCK_PREFIX(x) ".L" x
37 #define SNPRINTF_BUF_LEN 128
39 /* global arch_env for lc_printf functions */
40 static const arch_env_t *arch_env = NULL;
42 /** by default, we generate assembler code for the Linux gas */
43 asm_flavour_t asm_flavour = ASM_LINUX_GAS;
46 * Switch to a new section
48 void ia32_switch_section(FILE *F, section_t sec) {
49 static section_t curr_sec = NO_SECTION;
50 static const char *text[ASM_MAX][SECTION_MAX] = {
56 ".section\t.tbss,\"awT\",@nobits"
61 ".section .rdata,\"dr\"",
63 ".section\t.tbss,\"awT\",@nobits"
81 fprintf(F, "\t%s\n", text[asm_flavour][sec]);
89 static void ia32_dump_function_object(FILE *F, const char *name)
91 switch (asm_flavour) {
93 fprintf(F, "\t.type\t%s, @function\n", name);
96 fprintf(F, "\t.def\t%s;\t.scl\t2;\t.type\t32;\t.endef\n", name);
103 static void ia32_dump_function_size(FILE *F, const char *name)
105 switch (asm_flavour) {
107 fprintf(F, "\t.size\t%s, .-%s\n", name, name);
114 /*************************************************************
116 * (_) | | / _| | | | |
117 * _ __ _ __ _ _ __ | |_| |_ | |__ ___| |_ __ ___ _ __
118 * | '_ \| '__| | '_ \| __| _| | '_ \ / _ \ | '_ \ / _ \ '__|
119 * | |_) | | | | | | | |_| | | | | | __/ | |_) | __/ |
120 * | .__/|_| |_|_| |_|\__|_| |_| |_|\___|_| .__/ \___|_|
123 *************************************************************/
125 static INLINE int be_is_unknown_reg(const arch_register_t *reg) {
127 REGS_ARE_EQUAL(reg, &ia32_gp_regs[REG_GP_UKNWN]) || \
128 REGS_ARE_EQUAL(reg, &ia32_xmm_regs[REG_XMM_UKNWN]) || \
129 REGS_ARE_EQUAL(reg, &ia32_vfp_regs[REG_VFP_UKNWN]);
133 * returns true if a node has x87 registers
135 static INLINE int has_x87_register(const ir_node *n) {
136 return is_irn_machine_user(n, 0);
139 /* We always pass the ir_node which is a pointer. */
140 static int ia32_get_arg_type(const lc_arg_occ_t *occ) {
141 return lc_arg_type_ptr;
146 * Returns the register at in position pos.
148 static const arch_register_t *get_in_reg(const ir_node *irn, int pos) {
150 const arch_register_t *reg = NULL;
152 assert(get_irn_arity(irn) > pos && "Invalid IN position");
154 /* The out register of the operator at position pos is the
155 in register we need. */
156 op = get_irn_n(irn, pos);
158 reg = arch_get_irn_register(arch_env, op);
160 assert(reg && "no in register found");
162 /* in case of unknown: just return a register */
163 if (REGS_ARE_EQUAL(reg, &ia32_gp_regs[REG_GP_UKNWN]))
164 reg = &ia32_gp_regs[REG_EAX];
165 else if (REGS_ARE_EQUAL(reg, &ia32_xmm_regs[REG_XMM_UKNWN]))
166 reg = &ia32_xmm_regs[REG_XMM0];
167 else if (REGS_ARE_EQUAL(reg, &ia32_vfp_regs[REG_VFP_UKNWN]))
168 reg = &ia32_vfp_regs[REG_VF0];
174 * Returns the register at out position pos.
176 static const arch_register_t *get_out_reg(const ir_node *irn, int pos) {
178 const arch_register_t *reg = NULL;
180 /* 1st case: irn is not of mode_T, so it has only */
181 /* one OUT register -> good */
182 /* 2nd case: irn is of mode_T -> collect all Projs and ask the */
183 /* Proj with the corresponding projnum for the register */
185 if (get_irn_mode(irn) != mode_T) {
186 reg = arch_get_irn_register(arch_env, irn);
188 else if (is_ia32_irn(irn)) {
189 reg = get_ia32_out_reg(irn, pos);
192 const ir_edge_t *edge;
194 foreach_out_edge(irn, edge) {
195 proj = get_edge_src_irn(edge);
196 assert(is_Proj(proj) && "non-Proj from mode_T node");
197 if (get_Proj_proj(proj) == pos) {
198 reg = arch_get_irn_register(arch_env, proj);
204 assert(reg && "no out register found");
214 * Returns the name of the in register at position pos.
216 static const char *get_ia32_reg_name(ir_node *irn, int pos, enum io_direction in_out) {
217 const arch_register_t *reg;
219 if (in_out == IN_REG) {
220 reg = get_in_reg(irn, pos);
222 if (reg->reg_class == &ia32_reg_classes[CLASS_ia32_vfp]) {
223 /* FIXME: works for binop only */
224 assert(2 <= pos && pos <= 3);
225 reg = get_ia32_attr(irn)->x87[pos - 2];
229 /* destination address mode nodes don't have outputs */
230 if (is_ia32_irn(irn) && get_ia32_op_type(irn) == ia32_AddrModeD) {
234 reg = get_out_reg(irn, pos);
235 if (reg->reg_class == &ia32_reg_classes[CLASS_ia32_vfp])
236 reg = get_ia32_attr(irn)->x87[pos + 2];
238 return arch_register_get_name(reg);
242 * Get the register name for a node.
244 static int ia32_get_reg_name(lc_appendable_t *app,
245 const lc_arg_occ_t *occ, const lc_arg_value_t *arg)
248 ir_node *irn = arg->v_ptr;
249 int nr = occ->width - 1;
252 return lc_appendable_snadd(app, "(null)", 6);
254 buf = get_ia32_reg_name(irn, nr, occ->conversion == 'S' ? IN_REG : OUT_REG);
256 /* append the stupid % to register names */
257 lc_appendable_chadd(app, '%');
258 return lc_appendable_snadd(app, buf, strlen(buf));
262 * Get the x87 register name for a node.
264 static int ia32_get_x87_name(lc_appendable_t *app,
265 const lc_arg_occ_t *occ, const lc_arg_value_t *arg)
268 ir_node *irn = arg->v_ptr;
269 int nr = occ->width - 1;
273 return lc_appendable_snadd(app, "(null)", 6);
275 attr = get_ia32_attr(irn);
276 buf = attr->x87[nr]->name;
277 lc_appendable_chadd(app, '%');
278 return lc_appendable_snadd(app, buf, strlen(buf));
282 * Returns the tarval, offset or scale of an ia32 as a string.
284 static int ia32_const_to_str(lc_appendable_t *app,
285 const lc_arg_occ_t *occ, const lc_arg_value_t *arg)
288 ir_node *irn = arg->v_ptr;
291 return lc_arg_append(app, occ, "(null)", 6);
293 if (occ->conversion == 'C') {
294 buf = get_ia32_cnst(irn);
297 buf = get_ia32_am_offs(irn);
300 return buf ? lc_appendable_snadd(app, buf, strlen(buf)) : 0;
304 * Determines the SSE suffix depending on the mode.
306 static int ia32_get_mode_suffix(lc_appendable_t *app,
307 const lc_arg_occ_t *occ, const lc_arg_value_t *arg)
309 ir_node *irn = arg->v_ptr;
310 ir_mode *mode = get_irn_mode(irn);
312 if (mode == mode_T) {
313 mode = get_ia32_res_mode(irn);
315 mode = get_ia32_ls_mode(irn);
319 return lc_arg_append(app, occ, "(null)", 6);
321 if (mode_is_float(mode)) {
322 return lc_appendable_chadd(app, get_mode_size_bits(mode) == 32 ? 's' : 'd');
325 return lc_appendable_chadd(app, mode_is_signed(mode) ? 's' : 'z');
330 * Return the ia32 printf arg environment.
331 * We use the firm environment with some additional handlers.
333 const lc_arg_env_t *ia32_get_arg_env(void) {
334 static lc_arg_env_t *env = NULL;
336 static const lc_arg_handler_t ia32_reg_handler = { ia32_get_arg_type, ia32_get_reg_name };
337 static const lc_arg_handler_t ia32_const_handler = { ia32_get_arg_type, ia32_const_to_str };
338 static const lc_arg_handler_t ia32_mode_handler = { ia32_get_arg_type, ia32_get_mode_suffix };
339 static const lc_arg_handler_t ia32_x87_handler = { ia32_get_arg_type, ia32_get_x87_name };
342 /* extend the firm printer */
343 env = firm_get_arg_env();
345 lc_arg_register(env, "ia32:sreg", 'S', &ia32_reg_handler);
346 lc_arg_register(env, "ia32:dreg", 'D', &ia32_reg_handler);
347 lc_arg_register(env, "ia32:cnst", 'C', &ia32_const_handler);
348 lc_arg_register(env, "ia32:offs", 'O', &ia32_const_handler);
349 lc_arg_register(env, "ia32:mode", 'M', &ia32_mode_handler);
350 lc_arg_register(env, "ia32:x87", 'X', &ia32_x87_handler);
356 static const char *ia32_get_reg_name_for_mode(ia32_emit_env_t *env, ir_mode *mode, const arch_register_t *reg) {
357 switch(get_mode_size_bits(mode)) {
359 return ia32_get_mapped_reg_name(env->isa->regs_8bit, reg);
361 return ia32_get_mapped_reg_name(env->isa->regs_16bit, reg);
363 return (char *)arch_register_get_name(reg);
368 * Emits registers and/or address mode of a binary operation.
370 const char *ia32_emit_binop(const ir_node *n, ia32_emit_env_t *env) {
371 static char *buf = NULL;
373 /* verify that this function is never called on non-AM supporting operations */
374 //assert(get_ia32_am_support(n) != ia32_am_None && "emit binop expects addressmode support");
376 #define PRODUCES_RESULT(n) \
377 (!(is_ia32_St(n) || \
378 is_ia32_Store8Bit(n) || \
379 is_ia32_CondJmp(n) || \
380 is_ia32_xCondJmp(n) || \
381 is_ia32_CmpSet(n) || \
382 is_ia32_xCmpSet(n) || \
383 is_ia32_SwitchJmp(n)))
386 buf = xcalloc(1, SNPRINTF_BUF_LEN);
389 memset(buf, 0, SNPRINTF_BUF_LEN);
392 switch(get_ia32_op_type(n)) {
394 if (is_ia32_ImmConst(n)) {
395 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%3S, %s", n, get_ia32_cnst(n));
397 else if (is_ia32_ImmSymConst(n)) {
398 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%3S, OFFSET FLAT:%s", n, get_ia32_cnst(n));
401 const arch_register_t *in1 = get_in_reg(n, 2);
402 const arch_register_t *in2 = get_in_reg(n, 3);
403 const arch_register_t *out = PRODUCES_RESULT(n) ? get_out_reg(n, 0) : NULL;
404 const arch_register_t *in;
407 in = out ? (REGS_ARE_EQUAL(out, in2) ? in1 : in2) : in2;
408 out = out ? out : in1;
409 in_name = arch_register_get_name(in);
411 if (is_ia32_emit_cl(n)) {
412 assert(REGS_ARE_EQUAL(&ia32_gp_regs[REG_ECX], in) && "shift operation needs ecx");
416 snprintf(buf, SNPRINTF_BUF_LEN, "%%%s, %%%s", arch_register_get_name(out), in_name);
420 if (is_ia32_ImmConst(n) || is_ia32_ImmSymConst(n)) {
421 assert(! PRODUCES_RESULT(n) && "Source AM with Const must not produce result");
422 snprintf(buf, SNPRINTF_BUF_LEN, "%s, %s", get_ia32_cnst(n), ia32_emit_am(n, env));
425 if (PRODUCES_RESULT(n)) {
426 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%1D, %s", n, ia32_emit_am(n, env));
429 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%3S, %s", n, ia32_emit_am(n, env));
434 if (is_ia32_ImmConst(n) || is_ia32_ImmSymConst(n)) {
435 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%s,%s%s",
436 ia32_emit_am(n, env),
437 is_ia32_ImmSymConst(n) ? " OFFSET FLAT:" : " ", /* In case of a symconst we must add OFFSET to */
438 get_ia32_cnst(n)); /* tell the assembler to store it's address. */
441 const arch_register_t *in1 = get_in_reg(n, get_irn_arity(n) == 5 ? 3 : 2);
442 ir_mode *mode = get_ia32_res_mode(n);
445 mode = mode ? mode : get_ia32_ls_mode(n);
446 in_name = ia32_get_reg_name_for_mode(env, mode, in1);
448 if (is_ia32_emit_cl(n)) {
449 assert(REGS_ARE_EQUAL(&ia32_gp_regs[REG_ECX], in1) && "shift operation needs ecx");
453 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%s, %%%s", ia32_emit_am(n, env), in_name);
457 assert(0 && "unsupported op type");
460 #undef PRODUCES_RESULT
466 * Returns the xxx PTR string for a given mode
468 * @param mode the mode
469 * @param x87_insn if non-zero returns the string for a x87 instruction
470 * else for a SSE instruction
472 static const char *pointer_size(ir_mode *mode, int x87_insn)
475 switch (get_mode_size_bits(mode)) {
476 case 8: return "BYTE PTR";
477 case 16: return "WORD PTR";
478 case 32: return "DWORD PTR";
484 case 96: return "XWORD PTR";
485 default: return NULL;
492 * Emits registers and/or address mode of a binary operation.
494 const char *ia32_emit_x87_binop(const ir_node *n, ia32_emit_env_t *env) {
495 static char *buf = NULL;
497 /* verify that this function is never called on non-AM supporting operations */
498 //assert(get_ia32_am_support(n) != ia32_am_None && "emit binop expects addressmode support");
501 buf = xcalloc(1, SNPRINTF_BUF_LEN);
504 memset(buf, 0, SNPRINTF_BUF_LEN);
507 switch(get_ia32_op_type(n)) {
509 if (is_ia32_ImmConst(n) || is_ia32_ImmSymConst(n)) {
510 ir_mode *mode = get_ia32_ls_mode(n);
511 const char *p = pointer_size(mode, 1);
512 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%s %s", p, get_ia32_cnst(n));
515 ia32_attr_t *attr = get_ia32_attr(n);
516 const arch_register_t *in1 = attr->x87[0];
517 const arch_register_t *in2 = attr->x87[1];
518 const arch_register_t *out = attr->x87[2];
519 const arch_register_t *in;
522 in = out ? (REGS_ARE_EQUAL(out, in2) ? in1 : in2) : in2;
523 out = out ? out : in1;
524 in_name = arch_register_get_name(in);
526 snprintf(buf, SNPRINTF_BUF_LEN, "%%%s, %%%s", arch_register_get_name(out), in_name);
531 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%s", ia32_emit_am(n, env));
534 assert(0 && "unsupported op type");
541 * Emits registers and/or address mode of a unary operation.
543 const char *ia32_emit_unop(const ir_node *n, ia32_emit_env_t *env) {
544 static char *buf = NULL;
547 buf = xcalloc(1, SNPRINTF_BUF_LEN);
550 memset(buf, 0, SNPRINTF_BUF_LEN);
553 switch(get_ia32_op_type(n)) {
555 if (is_ia32_ImmConst(n) || is_ia32_ImmSymConst(n)) {
556 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%C", n);
559 if (is_ia32_MulS(n) || is_ia32_Mulh(n)) {
560 /* MulS and Mulh implicitly multiply by EAX */
561 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%4S", n);
564 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%1D", n);
568 snprintf(buf, SNPRINTF_BUF_LEN, "%s", ia32_emit_am(n, env));
572 Mulh is emitted via emit_unop
573 imul [MEM] means EDX:EAX <- EAX * [MEM]
575 assert((is_ia32_Mulh(n) || is_ia32_MulS(n)) && "Only MulS and Mulh can have AM source as unop");
576 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%s", ia32_emit_am(n, env));
579 assert(0 && "unsupported op type");
586 * Emits address mode.
588 const char *ia32_emit_am(const ir_node *n, ia32_emit_env_t *env) {
589 ia32_am_flavour_t am_flav = get_ia32_am_flavour(n);
593 static struct obstack *obst = NULL;
594 ir_mode *mode = get_ia32_ls_mode(n);
596 if (! is_ia32_Lea(n))
597 assert(mode && "AM node must have ls_mode attribute set.");
600 obst = xcalloc(1, sizeof(*obst));
603 obstack_free(obst, NULL);
606 /* obstack_free with NULL results in an uninitialized obstack */
609 p = pointer_size(mode, has_x87_register(n) || is_ia32_GetST0(n) || is_ia32_SetST0(n));
611 obstack_printf(obst, "%s ", p);
613 /* emit address mode symconst */
614 if (get_ia32_am_sc(n)) {
615 if (is_ia32_am_sc_sign(n))
616 obstack_printf(obst, "-");
617 obstack_printf(obst, "%s", get_id_str(get_ia32_am_sc(n)));
620 if (am_flav & ia32_B) {
621 obstack_printf(obst, "[");
622 lc_eoprintf(ia32_get_arg_env(), obst, "%1S", n);
626 if (am_flav & ia32_I) {
628 obstack_printf(obst, "+");
631 obstack_printf(obst, "[");
634 lc_eoprintf(ia32_get_arg_env(), obst, "%2S", n);
636 if (am_flav & ia32_S) {
637 obstack_printf(obst, "*%d", 1 << get_ia32_am_scale(n));
643 if (am_flav & ia32_O) {
644 s = get_ia32_am_offs(n);
647 /* omit explicit + if there was no base or index */
649 obstack_printf(obst, "[");
654 obstack_printf(obst, s);
660 obstack_printf(obst, "] ");
662 obstack_1grow(obst, '\0');
663 s = obstack_finish(obst);
671 const char *ia32_emit_adr(const ir_node *irn, ia32_emit_env_t *env)
673 static char buf[SNPRINTF_BUF_LEN];
674 ir_mode *mode = get_ia32_ls_mode(irn);
675 const char *adr = get_ia32_cnst(irn);
676 const char *pref = pointer_size(mode, has_x87_register(irn));
678 snprintf(buf, SNPRINTF_BUF_LEN, "%s %s", pref ? pref : "", adr);
683 * Formated print of commands and comments.
685 static void ia32_fprintf_format(FILE *F, const ir_node *irn, char *cmd_buf, char *cmnt_buf) {
687 const char *name = irn ? be_retrieve_dbg_info(get_irn_dbg_info((ir_node *)irn), &lineno) : NULL;
690 fprintf(F, "\t%-35s %-60s /* %s:%u */\n", cmd_buf, cmnt_buf, name, lineno);
692 fprintf(F, "\t%-35s %-60s\n", cmd_buf, cmnt_buf);
698 * Add a number to a prefix. This number will not be used a second time.
700 static char *get_unique_label(char *buf, size_t buflen, const char *prefix) {
701 static unsigned long id = 0;
702 snprintf(buf, buflen, "%s%lu", prefix, ++id);
708 /*************************************************
711 * ___ _ __ ___ _| |_ ___ ___ _ __ __| |
712 * / _ \ '_ ` _ \| | __| / __/ _ \| '_ \ / _` |
713 * | __/ | | | | | | |_ | (_| (_) | | | | (_| |
714 * \___|_| |_| |_|_|\__| \___\___/|_| |_|\__,_|
716 *************************************************/
719 #define IA32_DO_EMIT(irn) ia32_fprintf_format(F, irn, cmd_buf, cmnt_buf)
722 * coding of conditions
724 struct cmp2conditon_t {
730 * positive conditions for signed compares
732 static const struct cmp2conditon_t cmp2condition_s[] = {
733 { NULL, pn_Cmp_False }, /* always false */
734 { "e", pn_Cmp_Eq }, /* == */
735 { "l", pn_Cmp_Lt }, /* < */
736 { "le", pn_Cmp_Le }, /* <= */
737 { "g", pn_Cmp_Gt }, /* > */
738 { "ge", pn_Cmp_Ge }, /* >= */
739 { "ne", pn_Cmp_Lg }, /* != */
740 { "ordered", pn_Cmp_Leg }, /* Floating point: ordered */
741 { "unordered", pn_Cmp_Uo }, /* FLoting point: unordered */
742 { "e", pn_Cmp_Ue }, /* Floating point: unordered or == */
743 { "b", pn_Cmp_Ul }, /* Floating point: unordered or < */
744 { "be", pn_Cmp_Ule }, /* Floating point: unordered or <= */
745 { "a", pn_Cmp_Ug }, /* Floating point: unordered or > */
746 { "ae", pn_Cmp_Uge }, /* Floating point: unordered or >= */
747 { "ne", pn_Cmp_Ne }, /* Floating point: unordered or != */
748 { NULL, pn_Cmp_True }, /* always true */
752 * positive conditions for unsigned compares
754 static const struct cmp2conditon_t cmp2condition_u[] = {
755 { NULL, pn_Cmp_False }, /* always false */
756 { "e", pn_Cmp_Eq }, /* == */
757 { "b", pn_Cmp_Lt }, /* < */
758 { "be", pn_Cmp_Le }, /* <= */
759 { "a", pn_Cmp_Gt }, /* > */
760 { "ae", pn_Cmp_Ge }, /* >= */
761 { "ne", pn_Cmp_Lg }, /* != */
762 { "ordered", pn_Cmp_Leg }, /* Floating point: ordered */
763 { "unordered", pn_Cmp_Uo }, /* FLoting point: unordered */
764 { "e", pn_Cmp_Ue }, /* Floating point: unordered or == */
765 { "b", pn_Cmp_Ul }, /* Floating point: unordered or < */
766 { "be", pn_Cmp_Ule }, /* Floating point: unordered or <= */
767 { "a", pn_Cmp_Ug }, /* Floating point: unordered or > */
768 { "ae", pn_Cmp_Uge }, /* Floating point: unordered or >= */
769 { "ne", pn_Cmp_Ne }, /* Floating point: unordered or != */
770 { NULL, pn_Cmp_True }, /* always true */
774 * returns the condition code
776 static const char *get_cmp_suffix(int cmp_code, int unsigned_cmp)
778 assert(cmp2condition_s[cmp_code].num == cmp_code);
779 assert(cmp2condition_u[cmp_code].num == cmp_code);
781 return unsigned_cmp ? cmp2condition_u[cmp_code & 7].name : cmp2condition_s[cmp_code & 7].name;
785 * Returns the target block for a control flow node.
787 static ir_node *get_cfop_target_block(const ir_node *irn) {
788 return get_irn_link(irn);
792 * Returns the target label for a control flow node.
794 static char *get_cfop_target(const ir_node *irn, char *buf) {
795 ir_node *bl = get_cfop_target_block(irn);
797 snprintf(buf, SNPRINTF_BUF_LEN, BLOCK_PREFIX("%ld"), get_irn_node_nr(bl));
801 /** Return the next block in Block schedule */
802 static ir_node *next_blk_sched(const ir_node *block) {
803 return get_irn_link(block);
807 * Returns the Proj with projection number proj and NOT mode_M
809 static ir_node *get_proj(const ir_node *irn, long proj) {
810 const ir_edge_t *edge;
813 assert(get_irn_mode(irn) == mode_T && "expected mode_T node");
815 foreach_out_edge(irn, edge) {
816 src = get_edge_src_irn(edge);
818 assert(is_Proj(src) && "Proj expected");
819 if (get_irn_mode(src) == mode_M)
822 if (get_Proj_proj(src) == proj)
829 * Emits the jump sequence for a conditional jump (cmp + jmp_true + jmp_false)
831 static void finish_CondJmp(FILE *F, const ir_node *irn, ir_mode *mode) {
832 const ir_node *proj1, *proj2 = NULL;
833 const ir_node *block, *next_bl = NULL;
834 char buf[SNPRINTF_BUF_LEN];
835 char cmd_buf[SNPRINTF_BUF_LEN];
836 char cmnt_buf[SNPRINTF_BUF_LEN];
839 /* get both Proj's */
840 proj1 = get_proj(irn, pn_Cond_true);
841 assert(proj1 && "CondJmp without true Proj");
843 proj2 = get_proj(irn, pn_Cond_false);
844 assert(proj2 && "CondJmp without false Proj");
846 /* for now, the code works for scheduled and non-schedules blocks */
847 block = get_nodes_block(irn);
849 /* we have a block schedule */
850 next_bl = next_blk_sched(block);
852 if (get_cfop_target_block(proj1) == next_bl) {
853 /* exchange both proj's so the second one can be omitted */
854 const ir_node *t = proj1;
859 /* the first Proj must always be created */
860 is_unsigned = mode_is_float(mode) || ! mode_is_signed(mode);
861 if (get_Proj_proj(proj1) == pn_Cond_true) {
862 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "j%s %s",
863 get_cmp_suffix(get_ia32_pncode(irn), is_unsigned),
864 get_cfop_target(proj1, buf));
865 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* cmp(a, b) == TRUE */");
868 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "j%s %s",
869 get_cmp_suffix(get_negated_pnc(get_ia32_pncode(irn), mode), is_unsigned),
870 get_cfop_target(proj1, buf));
871 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* cmp(a, b) == FALSE */");
875 /* the second Proj might be a fallthrough */
876 if (get_cfop_target_block(proj2) != next_bl) {
877 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "jmp %s", get_cfop_target(proj2, buf));
878 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* otherwise */");
882 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* fallthrough %s */", get_cfop_target(proj2, buf));
888 * Emits code for conditional jump.
890 static void CondJmp_emitter(const ir_node *irn, ia32_emit_env_t *env) {
892 char cmd_buf[SNPRINTF_BUF_LEN];
893 char cmnt_buf[SNPRINTF_BUF_LEN];
895 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "cmp %s", ia32_emit_binop(irn, env));
896 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F */", irn);
898 finish_CondJmp(F, irn, get_ia32_res_mode(irn));
902 * Emits code for conditional jump with two variables.
904 static void emit_ia32_CondJmp(const ir_node *irn, ia32_emit_env_t *env) {
905 CondJmp_emitter(irn, env);
909 * Emits code for conditional test and jump.
911 static void TestJmp_emitter(const ir_node *irn, ia32_emit_env_t *env) {
913 #define IA32_IS_IMMOP (is_ia32_ImmConst(irn) || is_ia32_ImmSymConst(irn))
916 const char *op1 = arch_register_get_name(get_in_reg(irn, 0));
917 const char *op2 = IA32_IS_IMMOP ? get_ia32_cnst(irn) : NULL;
918 char cmd_buf[SNPRINTF_BUF_LEN];
919 char cmnt_buf[SNPRINTF_BUF_LEN];
922 op2 = arch_register_get_name(get_in_reg(irn, 1));
924 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "test %%%s,%s%s ", op1, IA32_IS_IMMOP ? " " : " %", op2);
925 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F */", irn);
928 finish_CondJmp(F, irn, get_ia32_res_mode(irn));
934 * Emits code for conditional test and jump with two variables.
936 static void emit_ia32_TestJmp(const ir_node *irn, ia32_emit_env_t *env) {
937 TestJmp_emitter(irn, env);
940 static void emit_ia32_CJmp(const ir_node *irn, ia32_emit_env_t *env) {
942 char cmd_buf[SNPRINTF_BUF_LEN];
943 char cmnt_buf[SNPRINTF_BUF_LEN];
945 snprintf(cmd_buf, SNPRINTF_BUF_LEN, " ");
946 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F omitted redundant test */", irn);
948 finish_CondJmp(F, irn, get_ia32_res_mode(irn));
951 static void emit_ia32_CJmpAM(const ir_node *irn, ia32_emit_env_t *env) {
953 char cmd_buf[SNPRINTF_BUF_LEN];
954 char cmnt_buf[SNPRINTF_BUF_LEN];
956 snprintf(cmd_buf, SNPRINTF_BUF_LEN, " ");
957 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F omitted redundant test/cmp */", irn);
959 finish_CondJmp(F, irn, get_ia32_res_mode(irn));
963 * Emits code for conditional SSE floating point jump with two variables.
965 static void emit_ia32_xCondJmp(ir_node *irn, ia32_emit_env_t *env) {
967 char cmd_buf[SNPRINTF_BUF_LEN];
968 char cmnt_buf[SNPRINTF_BUF_LEN];
970 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "ucomis%M %s", irn, ia32_emit_binop(irn, env));
971 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F */", irn);
973 finish_CondJmp(F, irn, mode_F);
978 * Emits code for conditional x87 floating point jump with two variables.
980 static void emit_ia32_x87CondJmp(ir_node *irn, ia32_emit_env_t *env) {
982 char cmd_buf[SNPRINTF_BUF_LEN];
983 char cmnt_buf[SNPRINTF_BUF_LEN];
984 ia32_attr_t *attr = get_ia32_attr(irn);
985 const char *reg = attr->x87[1]->name;
986 const char *instr = "fcom";
989 switch (get_ia32_irn_opcode(irn)) {
990 case iro_ia32_fcomrJmp:
992 case iro_ia32_fcomJmp:
996 case iro_ia32_fcomrpJmp:
998 case iro_ia32_fcompJmp:
1001 case iro_ia32_fcomrppJmp:
1003 case iro_ia32_fcomppJmp:
1010 set_ia32_pncode(irn, (long)get_inversed_pnc(get_ia32_pncode(irn)));
1012 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "%s %s%s", instr, reg[0] == '\0' ? "" : "%", reg);
1013 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F */", irn);
1015 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "fnstsw %%ax", irn);
1016 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* Store x87 FPU Control Word */");
1018 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "sahf");
1019 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* Store ah into flags */");
1022 /* the compare flags must be evaluated using carry , ie unsigned */
1023 finish_CondJmp(F, irn, mode_Iu);
1026 static void CMov_emitter(ir_node *irn, ia32_emit_env_t *env) {
1028 const lc_arg_env_t *arg_env = ia32_get_arg_env();
1029 ir_mode *mode = get_irn_mode(get_irn_n(irn, 0));
1030 int is_unsigned = mode_is_float(mode) || ! mode_is_signed(mode);
1031 const char *cmp_suffix = get_cmp_suffix(get_ia32_pncode(irn), is_unsigned);
1032 int is_PsiCondCMov = is_ia32_PsiCondCMov(irn);
1033 int idx_left = 2 - is_PsiCondCMov;
1034 int idx_right = 3 - is_PsiCondCMov;
1036 char cmd_buf[SNPRINTF_BUF_LEN];
1037 char cmnt_buf[SNPRINTF_BUF_LEN];
1038 const arch_register_t *in1, *in2, *out;
1040 out = arch_get_irn_register(env->arch_env, irn);
1041 in1 = arch_get_irn_register(env->arch_env, get_irn_n(irn, idx_left));
1042 in2 = arch_get_irn_register(env->arch_env, get_irn_n(irn, idx_right));
1044 /* we have to emit the cmp first, because the destination register */
1045 /* could be one of the compare registers */
1046 if (is_ia32_CmpCMov(irn)) {
1047 lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "cmp %1S, %2S", irn, irn);
1049 else if (is_ia32_xCmpCMov(irn)) {
1050 lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "ucomis%M %1S, %2S", get_irn_n(irn, 0), irn, irn);
1052 else if (is_PsiCondCMov) {
1053 /* omit compare because flags are already set by And/Or */
1054 lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "test %1S, %1S", irn, irn);
1057 assert(0 && "unsupported CMov");
1059 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* Psi condition */" );
1062 if (REGS_ARE_EQUAL(out, in2)) {
1063 /* best case: default in == out -> do nothing */
1065 else if (REGS_ARE_EQUAL(out, in1)) {
1066 /* true in == out -> need complement compare and exchange true and default in */
1067 ir_node *t = get_irn_n(irn, idx_left);
1068 set_irn_n(irn, idx_left, get_irn_n(irn, idx_right));
1069 set_irn_n(irn, idx_right, t);
1071 cmp_suffix = get_cmp_suffix(get_negated_pnc(get_ia32_pncode(irn), get_irn_mode(irn)), is_unsigned);
1075 /* out is different from in: need copy default -> out */
1077 lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "mov %1D, %3S", irn, irn);
1079 lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "mov %1D, %4S", irn, irn);
1081 lc_esnprintf(arg_env, cmnt_buf, SNPRINTF_BUF_LEN, "/* copy default -> out */" );
1086 lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "cmov%s %1D, %2S", cmp_suffix, irn, irn);
1088 lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "cmov%s %1D, %3S", cmp_suffix, irn, irn);
1090 lc_esnprintf(arg_env, cmnt_buf, SNPRINTF_BUF_LEN, "/* condition is true case */" );
1094 static void emit_ia32_CmpCMov(ir_node *irn, ia32_emit_env_t *env) {
1095 CMov_emitter(irn, env);
1098 static void emit_ia32_PsiCondCMov(ir_node *irn, ia32_emit_env_t *env) {
1099 CMov_emitter(irn, env);
1102 static void emit_ia32_xCmpCMov(ir_node *irn, ia32_emit_env_t *env) {
1103 CMov_emitter(irn, env);
1106 static void Set_emitter(ir_node *irn, ir_mode *mode, ia32_emit_env_t *env) {
1108 const lc_arg_env_t *arg_env = ia32_get_arg_env();
1109 int is_unsigned = mode_is_float(mode) || ! mode_is_signed(mode);
1110 const char *cmp_suffix = get_cmp_suffix(get_ia32_pncode(irn), is_unsigned);
1111 const char *reg8bit;
1113 char cmd_buf[SNPRINTF_BUF_LEN];
1114 char cmnt_buf[SNPRINTF_BUF_LEN];
1115 const arch_register_t *out;
1117 out = arch_get_irn_register(env->arch_env, irn);
1118 reg8bit = ia32_get_mapped_reg_name(env->isa->regs_8bit, out);
1120 if (is_ia32_CmpSet(irn)) {
1121 lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "cmp %s", ia32_emit_binop(irn, env));
1123 else if (is_ia32_xCmpSet(irn)) {
1124 lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "ucomis%M %s", get_irn_n(irn, 2), ia32_emit_binop(irn, env));
1126 else if (is_ia32_PsiCondSet(irn)) {
1127 /* omit compare because flags are already set by And/Or */
1128 snprintf(cmd_buf, SNPRINTF_BUF_LEN, " ");
1131 assert(0 && "unsupported Set");
1133 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* calculate Psi condition */" );
1136 /* use mov to clear target because it doesn't affect the eflags */
1137 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "mov %%%s, 0", arch_register_get_name(out));
1138 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* clear target as set modifies only lower 8 bit */");
1141 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "set%s %%%s", cmp_suffix, reg8bit);
1142 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* set 1 iff true, 0 otherweise */" );
1146 static void emit_ia32_CmpSet(ir_node *irn, ia32_emit_env_t *env) {
1147 Set_emitter(irn, get_irn_mode(get_irn_n(irn, 2)), env);
1150 static void emit_ia32_PsiCondSet(ir_node *irn, ia32_emit_env_t *env) {
1151 Set_emitter(irn, get_irn_mode(get_irn_n(irn, 0)), env);
1154 static void emit_ia32_xCmpSet(ir_node *irn, ia32_emit_env_t *env) {
1155 Set_emitter(irn, get_irn_mode(get_irn_n(irn, 2)), env);
1158 static void emit_ia32_xCmp(ir_node *irn, ia32_emit_env_t *env) {
1160 const lc_arg_env_t *arg_env = ia32_get_arg_env();
1162 long pnc = get_ia32_pncode(irn);
1163 long unord = pnc & pn_Cmp_Uo;
1164 char cmd_buf[SNPRINTF_BUF_LEN];
1165 char cmnt_buf[SNPRINTF_BUF_LEN];
1168 case pn_Cmp_Leg: /* odered */
1171 case pn_Cmp_Uo: /* unordered */
1175 case pn_Cmp_Eq: /* == */
1179 case pn_Cmp_Lt: /* < */
1183 case pn_Cmp_Le: /* <= */
1187 case pn_Cmp_Gt: /* > */
1191 case pn_Cmp_Ge: /* >= */
1195 case pn_Cmp_Lg: /* != */
1200 assert(sse_pnc >= 0 && "unsupported compare");
1202 if (unord && sse_pnc != 3) {
1204 We need a separate compare against unordered.
1205 Quick and Dirty solution:
1206 - get some memory on stack
1210 - and result and stored result
1213 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "sub %%esp, 8");
1214 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* reserve some space for unordered compare result */");
1216 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "cmpsd %s, 3", ia32_emit_binop(irn, env));
1217 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* SSE compare: unordered */");
1219 lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "movsd [%%esp], %1D", irn);
1220 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* store compare result */");
1224 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "cmpsd %s, %d", ia32_emit_binop(irn, env), sse_pnc);
1225 lc_esnprintf(arg_env, cmnt_buf, SNPRINTF_BUF_LEN, "/* SSE compare (%+F) with result in %1D */", irn, irn);
1228 if (unord && sse_pnc != 3) {
1229 lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "andpd %1D, [%%esp]", irn);
1230 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* build the final result */");
1232 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "add %%esp, 8");
1233 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* free allocated space */");
1238 /*********************************************************
1241 * ___ _ __ ___ _| |_ _ _ _ _ __ ___ _ __ ___
1242 * / _ \ '_ ` _ \| | __| | | | | | '_ ` _ \| '_ \/ __|
1243 * | __/ | | | | | | |_ | | |_| | | | | | | |_) \__ \
1244 * \___|_| |_| |_|_|\__| | |\__,_|_| |_| |_| .__/|___/
1247 *********************************************************/
1249 /* jump table entry (target and corresponding number) */
1250 typedef struct _branch_t {
1255 /* jump table for switch generation */
1256 typedef struct _jmp_tbl_t {
1257 ir_node *defProj; /**< default target */
1258 int min_value; /**< smallest switch case */
1259 int max_value; /**< largest switch case */
1260 int num_branches; /**< number of jumps */
1261 char *label; /**< label of the jump table */
1262 branch_t *branches; /**< jump array */
1266 * Compare two variables of type branch_t. Used to sort all switch cases
1268 static int ia32_cmp_branch_t(const void *a, const void *b) {
1269 branch_t *b1 = (branch_t *)a;
1270 branch_t *b2 = (branch_t *)b;
1272 if (b1->value <= b2->value)
1279 * Emits code for a SwitchJmp (creates a jump table if
1280 * possible otherwise a cmp-jmp cascade). Port from
1283 static void emit_ia32_SwitchJmp(const ir_node *irn, ia32_emit_env_t *emit_env) {
1284 unsigned long interval;
1285 char buf[SNPRINTF_BUF_LEN];
1286 int last_value, i, pn;
1289 const ir_edge_t *edge;
1290 const lc_arg_env_t *env = ia32_get_arg_env();
1291 FILE *F = emit_env->out;
1292 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1294 /* fill the table structure */
1295 tbl.label = xmalloc(SNPRINTF_BUF_LEN);
1296 tbl.label = get_unique_label(tbl.label, SNPRINTF_BUF_LEN, ".TBL_");
1298 tbl.num_branches = get_irn_n_edges(irn);
1299 tbl.branches = xcalloc(tbl.num_branches, sizeof(tbl.branches[0]));
1300 tbl.min_value = INT_MAX;
1301 tbl.max_value = INT_MIN;
1304 /* go over all proj's and collect them */
1305 foreach_out_edge(irn, edge) {
1306 proj = get_edge_src_irn(edge);
1307 assert(is_Proj(proj) && "Only proj allowed at SwitchJmp");
1309 pn = get_Proj_proj(proj);
1311 /* create branch entry */
1312 tbl.branches[i].target = proj;
1313 tbl.branches[i].value = pn;
1315 tbl.min_value = pn < tbl.min_value ? pn : tbl.min_value;
1316 tbl.max_value = pn > tbl.max_value ? pn : tbl.max_value;
1318 /* check for default proj */
1319 if (pn == get_ia32_pncode(irn)) {
1320 assert(tbl.defProj == NULL && "found two defProjs at SwitchJmp");
1327 /* sort the branches by their number */
1328 qsort(tbl.branches, tbl.num_branches, sizeof(tbl.branches[0]), ia32_cmp_branch_t);
1330 /* two-complement's magic make this work without overflow */
1331 interval = tbl.max_value - tbl.min_value;
1333 /* emit the table */
1334 lc_esnprintf(env, cmd_buf, SNPRINTF_BUF_LEN, "cmp %1S, %u", irn, interval);
1335 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* compare for switch */");
1338 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "ja %s", get_cfop_target(tbl.defProj, buf));
1339 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* default jump if out of range */");
1342 if (tbl.num_branches > 1) {
1345 lc_esnprintf(env, cmd_buf, SNPRINTF_BUF_LEN, "jmp %s[%1S*4]", tbl.label, irn);
1346 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* get jump table entry as target */");
1349 ia32_switch_section(F, SECTION_RODATA);
1350 fprintf(F, "\t.align 4\n");
1352 fprintf(F, "%s:\n", tbl.label);
1354 snprintf(cmd_buf, SNPRINTF_BUF_LEN, ".long %s", get_cfop_target(tbl.branches[0].target, buf));
1355 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* case %d */", tbl.branches[0].value);
1358 last_value = tbl.branches[0].value;
1359 for (i = 1; i < tbl.num_branches; ++i) {
1360 while (++last_value < tbl.branches[i].value) {
1361 snprintf(cmd_buf, SNPRINTF_BUF_LEN, ".long %s", get_cfop_target(tbl.defProj, buf));
1362 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* default case */");
1365 snprintf(cmd_buf, SNPRINTF_BUF_LEN, ".long %s", get_cfop_target(tbl.branches[i].target, buf));
1366 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* case %d */", last_value);
1369 ia32_switch_section(F, SECTION_TEXT);
1372 /* one jump is enough */
1373 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "jmp %s", get_cfop_target(tbl.branches[0].target, buf));
1374 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* only one case given */");
1385 * Emits code for a unconditional jump.
1387 static void emit_Jmp(const ir_node *irn, ia32_emit_env_t *env) {
1388 ir_node *block, *next_bl;
1390 char buf[SNPRINTF_BUF_LEN], cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1392 /* for now, the code works for scheduled and non-schedules blocks */
1393 block = get_nodes_block(irn);
1395 /* we have a block schedule */
1396 next_bl = next_blk_sched(block);
1397 if (get_cfop_target_block(irn) != next_bl) {
1398 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "jmp %s", get_cfop_target(irn, buf));
1399 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F(%+F) */", irn, get_cfop_target_block(irn));
1403 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* fallthrough %s */", get_cfop_target(irn, buf));
1408 /****************************
1411 * _ __ _ __ ___ _ ___
1412 * | '_ \| '__/ _ \| |/ __|
1413 * | |_) | | | (_) | |\__ \
1414 * | .__/|_| \___/| ||___/
1417 ****************************/
1420 * Emits code for a proj -> node
1422 static void emit_Proj(const ir_node *irn, ia32_emit_env_t *env) {
1423 ir_node *pred = get_Proj_pred(irn);
1425 if (get_irn_op(pred) == op_Start) {
1426 switch(get_Proj_proj(irn)) {
1427 case pn_Start_X_initial_exec:
1436 /**********************************
1439 * | | ___ _ __ _ _| |_) |
1440 * | | / _ \| '_ \| | | | _ <
1441 * | |___| (_) | |_) | |_| | |_) |
1442 * \_____\___/| .__/ \__, |____/
1445 **********************************/
1448 * Emit movsb/w instructions to make mov count divideable by 4
1450 static void emit_CopyB_prolog(FILE *F, const ir_node *irn, int rem) {
1451 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1453 ir_fprintf(F, "\t/* memcopy prolog %+F */\n", irn);
1455 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "cld");
1456 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* copy direction forward */");
1461 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "movsb");
1462 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* memcopy remainder 1 */");
1466 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "movsw");
1467 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* memcopy remainder 2 */");
1471 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "movsb");
1472 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* memcopy remainder 3 */");
1474 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "movsw");
1475 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* memcopy remainder 3 */");
1483 * Emit rep movsd instruction for memcopy.
1485 static void emit_ia32_CopyB(const ir_node *irn, ia32_emit_env_t *emit_env) {
1486 FILE *F = emit_env->out;
1487 tarval *tv = get_ia32_Immop_tarval(irn);
1488 int rem = get_tarval_long(tv);
1489 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1491 emit_CopyB_prolog(F, irn, rem);
1493 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "rep movsd");
1494 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* memcopy */");
1499 * Emits unrolled memcopy.
1501 static void emit_ia32_CopyB_i(const ir_node *irn, ia32_emit_env_t *emit_env) {
1502 tarval *tv = get_ia32_Immop_tarval(irn);
1503 int size = get_tarval_long(tv);
1504 FILE *F = emit_env->out;
1505 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1507 emit_CopyB_prolog(F, irn, size & 0x3);
1511 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "movsd");
1512 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* memcopy unrolled */");
1519 /***************************
1523 * | | / _ \| '_ \ \ / /
1524 * | |___| (_) | | | \ V /
1525 * \_____\___/|_| |_|\_/
1527 ***************************/
1530 * Emit code for conversions (I, FP), (FP, I) and (FP, FP).
1532 static void emit_ia32_Conv_with_FP(const ir_node *irn, ia32_emit_env_t *emit_env) {
1533 FILE *F = emit_env->out;
1534 const lc_arg_env_t *env = ia32_get_arg_env();
1535 ir_mode *src_mode = get_ia32_src_mode(irn);
1536 ir_mode *tgt_mode = get_ia32_tgt_mode(irn);
1537 char *from, *to, buf[64];
1538 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1540 from = mode_is_float(src_mode) ? (get_mode_size_bits(src_mode) == 32 ? "ss" : "sd") : "si";
1541 to = mode_is_float(tgt_mode) ? (get_mode_size_bits(tgt_mode) == 32 ? "ss" : "sd") : "si";
1543 switch(get_ia32_op_type(irn)) {
1545 lc_esnprintf(env, buf, sizeof(buf), "%1D, %3S", irn, irn);
1547 case ia32_AddrModeS:
1548 lc_esnprintf(env, buf, sizeof(buf), "%1D, %s", irn, ia32_emit_am(irn, emit_env));
1551 assert(0 && "unsupported op type for Conv");
1554 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "cvt%s2%s %s", from, to, buf);
1555 lc_esnprintf(env, cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F(%+F, %+F) */", irn, src_mode, tgt_mode);
1559 static void emit_ia32_Conv_I2FP(const ir_node *irn, ia32_emit_env_t *emit_env) {
1560 emit_ia32_Conv_with_FP(irn, emit_env);
1563 static void emit_ia32_Conv_FP2I(const ir_node *irn, ia32_emit_env_t *emit_env) {
1564 emit_ia32_Conv_with_FP(irn, emit_env);
1567 static void emit_ia32_Conv_FP2FP(const ir_node *irn, ia32_emit_env_t *emit_env) {
1568 emit_ia32_Conv_with_FP(irn, emit_env);
1572 * Emits code for an Int conversion.
1574 static void emit_ia32_Conv_I2I(const ir_node *irn, ia32_emit_env_t *emit_env) {
1575 FILE *F = emit_env->out;
1576 const lc_arg_env_t *env = ia32_get_arg_env();
1577 char *move_cmd = "movzx";
1578 char *conv_cmd = NULL;
1579 ir_mode *src_mode = get_ia32_src_mode(irn);
1580 ir_mode *tgt_mode = get_ia32_tgt_mode(irn);
1582 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1583 const arch_register_t *in_reg, *out_reg;
1585 n = get_mode_size_bits(src_mode);
1586 m = get_mode_size_bits(tgt_mode);
1588 if (mode_is_signed(n < m ? src_mode : tgt_mode)) {
1590 if (n == 8 || m == 8)
1592 else if (n == 16 || m == 16)
1595 printf("%d -> %d unsupported\n", n, m);
1596 assert(0 && "unsupported Conv_I2I");
1600 switch(get_ia32_op_type(irn)) {
1602 in_reg = get_in_reg(irn, 2);
1603 out_reg = get_out_reg(irn, 0);
1605 if (REGS_ARE_EQUAL(in_reg, &ia32_gp_regs[REG_EAX]) &&
1606 REGS_ARE_EQUAL(out_reg, in_reg) &&
1607 mode_is_signed(n < m ? src_mode : tgt_mode))
1609 /* argument and result are both in EAX and */
1610 /* signedness is ok: -> use converts */
1611 lc_esnprintf(env, cmd_buf, SNPRINTF_BUF_LEN, "%s", conv_cmd);
1613 else if (REGS_ARE_EQUAL(out_reg, in_reg) &&
1614 ! mode_is_signed(n < m ? src_mode : tgt_mode))
1616 /* argument and result are in the same register */
1617 /* and signedness is ok: -> use and with mask */
1618 int mask = (1 << (n < m ? n : m)) - 1;
1619 lc_esnprintf(env, cmd_buf, SNPRINTF_BUF_LEN, "and %1D, 0x%x", irn, mask);
1622 /* use move w/o sign extension */
1623 lc_esnprintf(env, cmd_buf, SNPRINTF_BUF_LEN, "%s %1D, %%%s",
1624 move_cmd, irn, ia32_get_reg_name_for_mode(emit_env, n < m ? src_mode : tgt_mode, in_reg));
1628 case ia32_AddrModeS:
1629 lc_esnprintf(env, cmd_buf, SNPRINTF_BUF_LEN, "%s %1D, %s",
1630 move_cmd, irn, ia32_emit_am(irn, emit_env));
1633 assert(0 && "unsupported op type for Conv");
1636 lc_esnprintf(env, cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F(%d Bit mode_%F -> %d Bit mode_%F) */",
1637 irn, n, src_mode, m, tgt_mode);
1643 * Emits code for an 8Bit Int conversion.
1645 void emit_ia32_Conv_I2I8Bit(const ir_node *irn, ia32_emit_env_t *emit_env) {
1646 emit_ia32_Conv_I2I(irn, emit_env);
1650 /*******************************************
1653 * | |__ ___ _ __ ___ __| | ___ ___
1654 * | '_ \ / _ \ '_ \ / _ \ / _` |/ _ \/ __|
1655 * | |_) | __/ | | | (_) | (_| | __/\__ \
1656 * |_.__/ \___|_| |_|\___/ \__,_|\___||___/
1658 *******************************************/
1661 * Emits a backend call
1663 static void emit_be_Call(const ir_node *irn, ia32_emit_env_t *emit_env) {
1664 FILE *F = emit_env->out;
1665 entity *ent = be_Call_get_entity(irn);
1666 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1669 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "call %s", get_entity_ld_name(ent));
1672 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "call %1D", get_irn_n(irn, be_pos_Call_ptr));
1675 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F (be_Call) */", irn);
1681 * Emits code to increase stack pointer.
1683 static void emit_be_IncSP(const ir_node *irn, ia32_emit_env_t *emit_env) {
1684 FILE *F = emit_env->out;
1685 int offs = be_get_IncSP_offset(irn);
1686 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1690 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "sub %1S, %u", irn, offs);
1692 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "add %1S, %u", irn, -offs);
1693 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F (IncSP) */", irn);
1696 snprintf(cmd_buf, SNPRINTF_BUF_LEN, " ");
1697 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* omitted %+F (IncSP) with 0 */", irn);
1704 * Emits code to set stack pointer.
1706 static void emit_be_SetSP(const ir_node *irn, ia32_emit_env_t *emit_env) {
1707 FILE *F = emit_env->out;
1708 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1710 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "mov %1D, %3S", irn, irn);
1711 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F (restore SP) */", irn);
1716 * Emits code for Copy/CopyKeep.
1718 static void Copy_emitter(const ir_node *irn, ir_node *op, ia32_emit_env_t *emit_env) {
1719 FILE *F = emit_env->out;
1720 const arch_env_t *aenv = emit_env->arch_env;
1721 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1723 if (REGS_ARE_EQUAL(arch_get_irn_register(aenv, irn), arch_get_irn_register(aenv, op)) ||
1724 be_is_unknown_reg(arch_get_irn_register(aenv, op)))
1727 if (mode_is_float(get_irn_mode(irn)))
1728 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "movs%M %1D, %1S", irn, irn, irn);
1730 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "mov %1D, %1S", irn, irn);
1731 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F */", irn);
1735 static void emit_be_Copy(const ir_node *irn, ia32_emit_env_t *emit_env) {
1736 Copy_emitter(irn, be_get_Copy_op(irn), emit_env);
1739 static void emit_be_CopyKeep(const ir_node *irn, ia32_emit_env_t *emit_env) {
1740 Copy_emitter(irn, be_get_CopyKeep_op(irn), emit_env);
1744 * Emits code for exchange.
1746 static void emit_be_Perm(const ir_node *irn, ia32_emit_env_t *emit_env) {
1747 FILE *F = emit_env->out;
1748 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1749 const arch_register_t *in1, *in2;
1750 const arch_register_class_t *cls1, *cls2;
1752 in1 = arch_get_irn_register(emit_env->arch_env, get_irn_n(irn, 0));
1753 in2 = arch_get_irn_register(emit_env->arch_env, get_irn_n(irn, 1));
1755 cls1 = arch_register_get_class(in1);
1756 cls2 = arch_register_get_class(in2);
1758 assert(cls1 == cls2 && "Register class mismatch at Perm");
1760 if (cls1 == &ia32_reg_classes[CLASS_ia32_gp]) {
1761 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "xchg %1S, %2S", irn, irn);
1763 else if (cls1 == &ia32_reg_classes[CLASS_ia32_xmm]) {
1764 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN,
1765 "pxor %1S, %2S\n\tpxor %2S, %1S\n\tpxor %1S, %2S", irn, irn, irn, irn, irn, irn);
1767 else if (cls1 == &ia32_reg_classes[CLASS_ia32_vfp]) {
1771 else if (cls1 == &ia32_reg_classes[CLASS_ia32_st]) {
1776 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F(%1A, %2A) */", irn, irn, irn);
1781 * Emits code for Constant loading.
1783 static void emit_ia32_Const(const ir_node *n, ia32_emit_env_t *env) {
1785 char cmd_buf[256], cmnt_buf[256];
1786 const lc_arg_env_t *arg_env = ia32_get_arg_env();
1788 if (get_ia32_Immop_tarval(n) == get_tarval_null(get_irn_mode(n))) {
1789 const char *instr = "xor";
1790 if (env->isa->opt_arch == arch_pentium_4) {
1791 /* P4 prefers sub r, r, others xor r, r */
1794 lc_esnprintf(arg_env, cmd_buf, 256, "%s %1D, %1D ", instr, n, n);
1795 lc_esnprintf(arg_env, cmnt_buf, 256, "/* optimized mov 0 to register */");
1798 if (get_ia32_op_type(n) == ia32_SymConst) {
1799 lc_esnprintf(arg_env, cmd_buf, 256, "mov %1D, OFFSET FLAT:%C ", n, n);
1800 lc_esnprintf(arg_env, cmnt_buf, 256, "/* Move address of SymConst into register */");
1803 lc_esnprintf(arg_env, cmd_buf, 256, "mov %1D, %C ", n, n);
1804 lc_esnprintf(arg_env, cmnt_buf, 256, "/* Mov Const into register */");
1807 lc_efprintf(arg_env, F, "\t%-35s %-60s /* %+F (%+G) */\n", cmd_buf, cmnt_buf, n, n);
1811 * Emits code to increase stack pointer.
1813 static void emit_ia32_AddSP(const ir_node *irn, ia32_emit_env_t *emit_env) {
1814 FILE *F = emit_env->out;
1815 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1817 if (is_ia32_ImmConst(irn)) {
1818 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "sub %1D, %C", irn, irn);
1820 else if (is_ia32_ImmSymConst(irn)) {
1821 if (get_ia32_op_type(irn) == ia32_Normal)
1822 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "sub %1D, OFFSET_FLAT:%C", irn, irn);
1823 else /* source address mode */
1824 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "sub %1D, [%s%s]", irn, get_id_str(get_ia32_am_sc(irn)), get_ia32_am_offs(irn));
1827 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "sub %1D, %2S", irn, irn);
1829 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* reserve space on stack */");
1835 * Emits code to load the TLS base
1837 static void emit_ia32_LdTls(const ir_node *irn, ia32_emit_env_t *emit_env) {
1838 FILE *F = emit_env->out;
1839 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1841 switch (asm_flavour) {
1843 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "mov %1D, DWORD PTR %%gs:0", irn);
1846 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "mov %1D, DWORD PTR %%gs:0", irn);
1849 assert(0 && "unsupported TLS");
1852 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* get thread local storage base */");
1857 static void emit_be_Return(const ir_node *n, ia32_emit_env_t *env) {
1859 const lc_arg_env_t *arg_env = ia32_get_arg_env();
1861 lc_efprintf(arg_env, F, "\t%-35s %-60s /* %+F (%+G) */\n", "ret", "/* be_Return */", n, n);
1864 static void emit_Nothing(const ir_node *n, ia32_emit_env_t *env) {
1867 ir_fprintf(F, "\t%35s /* %+F (%+G) */\n", " ", n, n);
1871 /***********************************************************************************
1874 * _ __ ___ __ _ _ _ __ | |_ _ __ __ _ _ __ ___ _____ _____ _ __| | __
1875 * | '_ ` _ \ / _` | | '_ \ | _| '__/ _` | '_ ` _ \ / _ \ \ /\ / / _ \| '__| |/ /
1876 * | | | | | | (_| | | | | | | | | | | (_| | | | | | | __/\ V V / (_) | | | <
1877 * |_| |_| |_|\__,_|_|_| |_| |_| |_| \__,_|_| |_| |_|\___| \_/\_/ \___/|_| |_|\_\
1879 ***********************************************************************************/
1882 * Enters the emitter functions for handled nodes into the generic
1883 * pointer of an opcode.
1885 static void ia32_register_emitters(void) {
1887 #define IA32_EMIT2(a,b) op_ia32_##a->ops.generic = (op_func)emit_ia32_##b
1888 #define IA32_EMIT(a) IA32_EMIT2(a,a)
1889 #define EMIT(a) op_##a->ops.generic = (op_func)emit_##a
1890 #define IGN(a) op_##a->ops.generic = (op_func)emit_Nothing
1891 #define BE_EMIT(a) op_be_##a->ops.generic = (op_func)emit_be_##a
1892 #define BE_IGN(a) op_be_##a->ops.generic = (op_func)emit_Nothing
1894 /* first clear the generic function pointer for all ops */
1895 clear_irp_opcodes_generic_func();
1897 /* register all emitter functions defined in spec */
1898 ia32_register_spec_emitters();
1900 /* other ia32 emitter functions */
1906 IA32_EMIT(PsiCondCMov);
1908 IA32_EMIT(PsiCondSet);
1909 IA32_EMIT(SwitchJmp);
1912 IA32_EMIT(Conv_I2FP);
1913 IA32_EMIT(Conv_FP2I);
1914 IA32_EMIT(Conv_FP2FP);
1915 IA32_EMIT(Conv_I2I);
1916 IA32_EMIT(Conv_I2I8Bit);
1922 IA32_EMIT(xCmpCMov);
1923 IA32_EMIT(xCondJmp);
1924 IA32_EMIT2(fcomJmp, x87CondJmp);
1925 IA32_EMIT2(fcompJmp, x87CondJmp);
1926 IA32_EMIT2(fcomppJmp, x87CondJmp);
1927 IA32_EMIT2(fcomrJmp, x87CondJmp);
1928 IA32_EMIT2(fcomrpJmp, x87CondJmp);
1929 IA32_EMIT2(fcomrppJmp, x87CondJmp);
1931 /* benode emitter */
1958 * Emits code for a node.
1960 static void ia32_emit_node(const ir_node *irn, void *env) {
1961 ia32_emit_env_t *emit_env = env;
1962 ir_op *op = get_irn_op(irn);
1963 DEBUG_ONLY(firm_dbg_module_t *mod = emit_env->mod;)
1965 DBG((mod, LEVEL_1, "emitting code for %+F\n", irn));
1967 if (op->ops.generic) {
1968 void (*emit)(const ir_node *, void *) = (void (*)(const ir_node *, void *))op->ops.generic;
1972 emit_Nothing(irn, env);
1973 ir_fprintf(stderr, "Warning: No emit handler for node %+F (%+G)\n", irn, irn);
1978 * Emits gas alignment directives
1980 static void ia32_emit_alignment(FILE *F, unsigned align, unsigned skip) {
1981 fprintf(F, "\t.p2align %u,,%u\n", align, skip);
1985 * Emits gas alignment directives for Functions depended on cpu architecture.
1987 static void ia32_emit_align_func(FILE *F, cpu_support cpu) {
1988 unsigned align; unsigned maximum_skip;
1990 /* gcc doesn't emit alignment for p4 ?*/
1991 if (cpu == arch_pentium_4)
1996 align = 2; maximum_skip = 3;
1999 align = 4; maximum_skip = 15;
2002 align = 5; maximum_skip = 31;
2005 align = 4; maximum_skip = 15;
2007 ia32_emit_alignment(F, align, maximum_skip);
2011 * Emits gas alignment directives for Labels depended on cpu architecture.
2013 static void ia32_emit_align_label(FILE *F, cpu_support cpu) {
2014 unsigned align; unsigned maximum_skip;
2016 /* gcc doesn't emit alignment for p4 ?*/
2017 if (cpu == arch_pentium_4)
2022 align = 2; maximum_skip = 3;
2025 align = 4; maximum_skip = 15;
2028 align = 5; maximum_skip = 7;
2031 align = 4; maximum_skip = 7;
2033 ia32_emit_alignment(F, align, maximum_skip);
2037 * Walks over the nodes in a block connected by scheduling edges
2038 * and emits code for each node.
2040 static void ia32_gen_block(ir_node *block, void *env) {
2041 ia32_emit_env_t *emit_env = env;
2043 int need_label = block != get_irg_start_block(get_irn_irg(block));
2044 FILE *F = emit_env->out;
2046 if (! is_Block(block))
2049 if (need_label && (emit_env->cg->opt & IA32_OPT_EXTBB)) {
2050 /* if the extended block scheduler is used, only leader blocks need
2052 need_label = (block == get_extbb_leader(get_nodes_extbb(block)));
2056 char cmd_buf[SNPRINTF_BUF_LEN];
2059 ia32_emit_align_label(emit_env->out, emit_env->isa->opt_arch);
2061 ir_snprintf(cmd_buf, sizeof(cmd_buf), BLOCK_PREFIX("%d:"),
2062 get_irn_node_nr(block));
2063 fprintf(F, "%-43s ", cmd_buf);
2065 /* emit list of pred blocks in comment */
2066 fprintf(F, "/* preds:");
2068 arity = get_irn_arity(block);
2069 for(i = 0; i < arity; ++i) {
2070 ir_node *predblock = get_Block_cfgpred_block(block, i);
2071 fprintf(F, " %ld", get_irn_node_nr(predblock));
2073 fprintf(F, " */\n");
2076 /* emit the contents of the block */
2077 sched_foreach(block, irn) {
2078 ia32_emit_node(irn, env);
2083 * Emits code for function start.
2085 static void ia32_emit_func_prolog(FILE *F, ir_graph *irg, cpu_support cpu) {
2086 entity *irg_ent = get_irg_entity(irg);
2087 const char *irg_name = get_entity_ld_name(irg_ent);
2090 ia32_switch_section(F, SECTION_TEXT);
2091 ia32_emit_align_func(F, cpu);
2092 if (get_entity_visibility(irg_ent) == visibility_external_visible) {
2093 fprintf(F, ".globl %s\n", irg_name);
2095 ia32_dump_function_object(F, irg_name);
2096 fprintf(F, "%s:\n", irg_name);
2100 * Emits code for function end
2102 static void ia32_emit_func_epilog(FILE *F, ir_graph *irg) {
2103 const char *irg_name = get_entity_ld_name(get_irg_entity(irg));
2105 ia32_dump_function_size(F, irg_name);
2111 * Sets labels for control flow nodes (jump target)
2112 * TODO: Jump optimization
2114 static void ia32_gen_labels(ir_node *block, void *env) {
2116 int n = get_Block_n_cfgpreds(block);
2118 for (n--; n >= 0; n--) {
2119 pred = get_Block_cfgpred(block, n);
2120 set_irn_link(pred, block);
2125 * Main driver. Emits the code for one routine.
2127 void ia32_gen_routine(FILE *F, ir_graph *irg, const ia32_code_gen_t *cg) {
2128 ia32_emit_env_t emit_env;
2132 emit_env.arch_env = cg->arch_env;
2134 emit_env.isa = (ia32_isa_t *)cg->arch_env->isa;
2135 FIRM_DBG_REGISTER(emit_env.mod, "firm.be.ia32.emitter");
2137 /* set the global arch_env (needed by print hooks) */
2138 arch_env = cg->arch_env;
2140 ia32_register_emitters();
2142 ia32_emit_func_prolog(F, irg, emit_env.isa->opt_arch);
2143 irg_block_walk_graph(irg, ia32_gen_labels, NULL, &emit_env);
2145 if ((cg->opt & IA32_OPT_EXTBB) && cg->blk_sched) {
2146 int i, n = ARR_LEN(cg->blk_sched);
2148 for (i = 0; i < n;) {
2151 block = cg->blk_sched[i];
2153 next_bl = i < n ? cg->blk_sched[i] : NULL;
2155 /* set here the link. the emitter expects to find the next block here */
2156 set_irn_link(block, next_bl);
2157 ia32_gen_block(block, &emit_env);
2161 /* "normal" block schedule: Note the get_next_block() returns the NUMBER of the block
2162 in the block schedule. As this number should NEVER be equal the next block,
2163 we does not need a clear block link here. */
2164 irg_walk_blkwise_graph(irg, NULL, ia32_gen_block, &emit_env);
2167 ia32_emit_func_epilog(F, irg);