2 * This file implements the node emitter.
3 * @author Christian Wuerdig
22 #include "iredges_t.h"
25 #include "../besched_t.h"
26 #include "../benode_t.h"
28 #include "../be_dbgout.h"
30 #include "ia32_emitter.h"
31 #include "gen_ia32_emitter.h"
32 #include "gen_ia32_regalloc_if.h"
33 #include "ia32_nodes_attr.h"
34 #include "ia32_new_nodes.h"
35 #include "ia32_map_regs.h"
36 #include "bearch_ia32_t.h"
38 #define BLOCK_PREFIX(x) ".L" x
40 #define SNPRINTF_BUF_LEN 128
42 /* global arch_env for lc_printf functions */
43 static const arch_env_t *arch_env = NULL;
45 /** by default, we generate assembler code for the Linux gas */
46 asm_flavour_t asm_flavour = ASM_LINUX_GAS;
49 * Switch to a new section
51 void ia32_switch_section(FILE *F, section_t sec) {
52 static section_t curr_sec = NO_SECTION;
53 static const char *text[ASM_MAX][SECTION_MAX] = {
59 ".section\t.tbss,\"awT\",@nobits",
60 ".section\t.ctors,\"aw\",@progbits"
65 ".section .rdata,\"dr\"",
67 ".section\t.tbss,\"awT\",@nobits",
68 ".section\t.ctors,\"aw\",@progbits"
87 fprintf(F, "\t%s\n", text[asm_flavour][sec]);
95 static void ia32_dump_function_object(FILE *F, const char *name)
97 switch (asm_flavour) {
99 fprintf(F, "\t.type\t%s, @function\n", name);
102 fprintf(F, "\t.def\t%s;\t.scl\t2;\t.type\t32;\t.endef\n", name);
109 static void ia32_dump_function_size(FILE *F, const char *name)
111 switch (asm_flavour) {
113 fprintf(F, "\t.size\t%s, .-%s\n", name, name);
120 /*************************************************************
122 * (_) | | / _| | | | |
123 * _ __ _ __ _ _ __ | |_| |_ | |__ ___| |_ __ ___ _ __
124 * | '_ \| '__| | '_ \| __| _| | '_ \ / _ \ | '_ \ / _ \ '__|
125 * | |_) | | | | | | | |_| | | | | | __/ | |_) | __/ |
126 * | .__/|_| |_|_| |_|\__|_| |_| |_|\___|_| .__/ \___|_|
129 *************************************************************/
132 * returns true if a node has x87 registers
134 static INLINE int has_x87_register(const ir_node *n) {
135 return is_irn_machine_user(n, 0);
138 /* We always pass the ir_node which is a pointer. */
139 static int ia32_get_arg_type(const lc_arg_occ_t *occ) {
140 return lc_arg_type_ptr;
145 * Returns the register at in position pos.
147 static const arch_register_t *get_in_reg(const ir_node *irn, int pos) {
149 const arch_register_t *reg = NULL;
151 assert(get_irn_arity(irn) > pos && "Invalid IN position");
153 /* The out register of the operator at position pos is the
154 in register we need. */
155 op = get_irn_n(irn, pos);
157 reg = arch_get_irn_register(arch_env, op);
159 assert(reg && "no in register found");
161 /* in case of a joker register: just return a valid register */
162 if (arch_register_type_is(reg, joker)) {
163 arch_register_req_t req;
164 const arch_register_req_t *p_req;
166 /* ask for the requirements */
167 p_req = arch_get_register_req(arch_env, &req, irn, pos);
169 if (arch_register_req_is(p_req, limited)) {
170 /* in case of limited requirements: get the first allowed register */
172 bitset_t *bs = bitset_alloca(arch_register_class_n_regs(p_req->cls));
175 p_req->limited(p_req->limited_env, bs);
176 idx = bitset_next_set(bs, 0);
177 reg = arch_register_for_index(p_req->cls, idx);
180 /* otherwise get first register in class */
181 reg = arch_register_for_index(p_req->cls, 0);
189 * Returns the register at out position pos.
191 static const arch_register_t *get_out_reg(const ir_node *irn, int pos) {
193 const arch_register_t *reg = NULL;
195 /* 1st case: irn is not of mode_T, so it has only */
196 /* one OUT register -> good */
197 /* 2nd case: irn is of mode_T -> collect all Projs and ask the */
198 /* Proj with the corresponding projnum for the register */
200 if (get_irn_mode(irn) != mode_T) {
201 reg = arch_get_irn_register(arch_env, irn);
203 else if (is_ia32_irn(irn)) {
204 reg = get_ia32_out_reg(irn, pos);
207 const ir_edge_t *edge;
209 foreach_out_edge(irn, edge) {
210 proj = get_edge_src_irn(edge);
211 assert(is_Proj(proj) && "non-Proj from mode_T node");
212 if (get_Proj_proj(proj) == pos) {
213 reg = arch_get_irn_register(arch_env, proj);
219 assert(reg && "no out register found");
229 * Returns the name of the in register at position pos.
231 static const char *get_ia32_reg_name(ir_node *irn, int pos, enum io_direction in_out) {
232 const arch_register_t *reg;
234 if (in_out == IN_REG) {
235 reg = get_in_reg(irn, pos);
237 if (reg->reg_class == &ia32_reg_classes[CLASS_ia32_vfp]) {
238 /* FIXME: works for binop only */
239 assert(2 <= pos && pos <= 3);
240 reg = get_ia32_attr(irn)->x87[pos - 2];
244 /* destination address mode nodes don't have outputs */
245 if (is_ia32_irn(irn) && get_ia32_op_type(irn) == ia32_AddrModeD) {
249 reg = get_out_reg(irn, pos);
250 if (reg->reg_class == &ia32_reg_classes[CLASS_ia32_vfp])
251 reg = get_ia32_attr(irn)->x87[pos + 2];
253 return arch_register_get_name(reg);
257 * Get the register name for a node.
259 static int ia32_get_reg_name(lc_appendable_t *app,
260 const lc_arg_occ_t *occ, const lc_arg_value_t *arg)
263 ir_node *irn = arg->v_ptr;
264 int nr = occ->width - 1;
267 return lc_appendable_snadd(app, "(null)", 6);
269 buf = get_ia32_reg_name(irn, nr, occ->conversion == 'S' ? IN_REG : OUT_REG);
271 /* append the stupid % to register names */
272 lc_appendable_chadd(app, '%');
273 return lc_appendable_snadd(app, buf, strlen(buf));
277 * Get the x87 register name for a node.
279 static int ia32_get_x87_name(lc_appendable_t *app,
280 const lc_arg_occ_t *occ, const lc_arg_value_t *arg)
283 ir_node *irn = arg->v_ptr;
284 int nr = occ->width - 1;
288 return lc_appendable_snadd(app, "(null)", 6);
290 attr = get_ia32_attr(irn);
291 buf = attr->x87[nr]->name;
292 lc_appendable_chadd(app, '%');
293 return lc_appendable_snadd(app, buf, strlen(buf));
297 * Returns the tarval, offset or scale of an ia32 as a string.
299 static int ia32_const_to_str(lc_appendable_t *app,
300 const lc_arg_occ_t *occ, const lc_arg_value_t *arg)
303 ir_node *irn = arg->v_ptr;
306 return lc_arg_append(app, occ, "(null)", 6);
308 if (occ->conversion == 'C') {
309 buf = get_ia32_cnst(irn);
312 buf = get_ia32_am_offs(irn);
315 return buf ? lc_appendable_snadd(app, buf, strlen(buf)) : 0;
319 * Determines the SSE suffix depending on the mode.
321 static int ia32_get_mode_suffix(lc_appendable_t *app,
322 const lc_arg_occ_t *occ, const lc_arg_value_t *arg)
324 ir_node *irn = arg->v_ptr;
325 ir_mode *mode = get_irn_mode(irn);
327 if (mode == mode_T) {
328 mode = get_ia32_res_mode(irn);
330 mode = get_ia32_ls_mode(irn);
334 return lc_arg_append(app, occ, "(null)", 6);
336 if (mode_is_float(mode)) {
337 return lc_appendable_chadd(app, get_mode_size_bits(mode) == 32 ? 's' : 'd');
340 return lc_appendable_chadd(app, mode_is_signed(mode) ? 's' : 'z');
345 * Return the ia32 printf arg environment.
346 * We use the firm environment with some additional handlers.
348 const lc_arg_env_t *ia32_get_arg_env(void) {
349 static lc_arg_env_t *env = NULL;
351 static const lc_arg_handler_t ia32_reg_handler = { ia32_get_arg_type, ia32_get_reg_name };
352 static const lc_arg_handler_t ia32_const_handler = { ia32_get_arg_type, ia32_const_to_str };
353 static const lc_arg_handler_t ia32_mode_handler = { ia32_get_arg_type, ia32_get_mode_suffix };
354 static const lc_arg_handler_t ia32_x87_handler = { ia32_get_arg_type, ia32_get_x87_name };
357 /* extend the firm printer */
358 env = firm_get_arg_env();
360 lc_arg_register(env, "ia32:sreg", 'S', &ia32_reg_handler);
361 lc_arg_register(env, "ia32:dreg", 'D', &ia32_reg_handler);
362 lc_arg_register(env, "ia32:cnst", 'C', &ia32_const_handler);
363 lc_arg_register(env, "ia32:offs", 'O', &ia32_const_handler);
364 lc_arg_register(env, "ia32:mode", 'M', &ia32_mode_handler);
365 lc_arg_register(env, "ia32:x87", 'X', &ia32_x87_handler);
371 static const char *ia32_get_reg_name_for_mode(ia32_emit_env_t *env, ir_mode *mode, const arch_register_t *reg) {
372 switch(get_mode_size_bits(mode)) {
374 return ia32_get_mapped_reg_name(env->isa->regs_8bit, reg);
376 return ia32_get_mapped_reg_name(env->isa->regs_16bit, reg);
378 return (char *)arch_register_get_name(reg);
383 * Emits registers and/or address mode of a binary operation.
385 const char *ia32_emit_binop(const ir_node *n, ia32_emit_env_t *env) {
386 static char *buf = NULL;
388 /* verify that this function is never called on non-AM supporting operations */
389 //assert(get_ia32_am_support(n) != ia32_am_None && "emit binop expects addressmode support");
391 #define PRODUCES_RESULT(n) \
392 (!(is_ia32_St(n) || \
393 is_ia32_Store8Bit(n) || \
394 is_ia32_CondJmp(n) || \
395 is_ia32_xCondJmp(n) || \
396 is_ia32_CmpSet(n) || \
397 is_ia32_xCmpSet(n) || \
398 is_ia32_SwitchJmp(n)))
401 buf = xcalloc(1, SNPRINTF_BUF_LEN);
404 memset(buf, 0, SNPRINTF_BUF_LEN);
407 switch(get_ia32_op_type(n)) {
409 if (is_ia32_ImmConst(n)) {
410 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%3S, %s", n, get_ia32_cnst(n));
412 else if (is_ia32_ImmSymConst(n)) {
413 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%3S, OFFSET FLAT:%s", n, get_ia32_cnst(n));
416 const arch_register_t *in1 = get_in_reg(n, 2);
417 const arch_register_t *in2 = get_in_reg(n, 3);
418 const arch_register_t *out = PRODUCES_RESULT(n) ? get_out_reg(n, 0) : NULL;
419 const arch_register_t *in;
422 in = out ? (REGS_ARE_EQUAL(out, in2) ? in1 : in2) : in2;
423 out = out ? out : in1;
424 in_name = arch_register_get_name(in);
426 if (is_ia32_emit_cl(n)) {
427 assert(REGS_ARE_EQUAL(&ia32_gp_regs[REG_ECX], in) && "shift operation needs ecx");
431 snprintf(buf, SNPRINTF_BUF_LEN, "%%%s, %%%s", arch_register_get_name(out), in_name);
435 if (is_ia32_ImmConst(n) || is_ia32_ImmSymConst(n)) {
436 assert(! PRODUCES_RESULT(n) && "Source AM with Const must not produce result");
437 snprintf(buf, SNPRINTF_BUF_LEN, "%s, %s", get_ia32_cnst(n), ia32_emit_am(n, env));
440 if (PRODUCES_RESULT(n)) {
441 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%1D, %s", n, ia32_emit_am(n, env));
444 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%3S, %s", n, ia32_emit_am(n, env));
449 if (is_ia32_ImmConst(n) || is_ia32_ImmSymConst(n)) {
450 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%s,%s%s",
451 ia32_emit_am(n, env),
452 is_ia32_ImmSymConst(n) ? " OFFSET FLAT:" : " ", /* In case of a symconst we must add OFFSET to */
453 get_ia32_cnst(n)); /* tell the assembler to store it's address. */
456 const arch_register_t *in1 = get_in_reg(n, get_irn_arity(n) == 5 ? 3 : 2);
457 ir_mode *mode = get_ia32_res_mode(n);
460 mode = mode ? mode : get_ia32_ls_mode(n);
461 in_name = ia32_get_reg_name_for_mode(env, mode, in1);
463 if (is_ia32_emit_cl(n)) {
464 assert(REGS_ARE_EQUAL(&ia32_gp_regs[REG_ECX], in1) && "shift operation needs ecx");
468 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%s, %%%s", ia32_emit_am(n, env), in_name);
472 assert(0 && "unsupported op type");
475 #undef PRODUCES_RESULT
481 * Returns the xxx PTR string for a given mode
483 * @param mode the mode
484 * @param x87_insn if non-zero returns the string for a x87 instruction
485 * else for a SSE instruction
487 static const char *pointer_size(ir_mode *mode, int x87_insn)
490 switch (get_mode_size_bits(mode)) {
491 case 8: return "BYTE PTR";
492 case 16: return "WORD PTR";
493 case 32: return "DWORD PTR";
499 case 96: return "XWORD PTR";
500 default: return NULL;
507 * Emits registers and/or address mode of a binary operation.
509 const char *ia32_emit_x87_binop(const ir_node *n, ia32_emit_env_t *env) {
510 static char *buf = NULL;
512 /* verify that this function is never called on non-AM supporting operations */
513 //assert(get_ia32_am_support(n) != ia32_am_None && "emit binop expects addressmode support");
516 buf = xcalloc(1, SNPRINTF_BUF_LEN);
519 memset(buf, 0, SNPRINTF_BUF_LEN);
522 switch(get_ia32_op_type(n)) {
524 if (is_ia32_ImmConst(n) || is_ia32_ImmSymConst(n)) {
525 ir_mode *mode = get_ia32_ls_mode(n);
526 const char *p = pointer_size(mode, 1);
527 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%s %s", p, get_ia32_cnst(n));
530 ia32_attr_t *attr = get_ia32_attr(n);
531 const arch_register_t *in1 = attr->x87[0];
532 const arch_register_t *in2 = attr->x87[1];
533 const arch_register_t *out = attr->x87[2];
534 const arch_register_t *in;
537 in = out ? (REGS_ARE_EQUAL(out, in2) ? in1 : in2) : in2;
538 out = out ? out : in1;
539 in_name = arch_register_get_name(in);
541 snprintf(buf, SNPRINTF_BUF_LEN, "%%%s, %%%s", arch_register_get_name(out), in_name);
546 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%s", ia32_emit_am(n, env));
549 assert(0 && "unsupported op type");
556 * Emits registers and/or address mode of a unary operation.
558 const char *ia32_emit_unop(const ir_node *n, ia32_emit_env_t *env) {
559 static char *buf = NULL;
562 buf = xcalloc(1, SNPRINTF_BUF_LEN);
565 memset(buf, 0, SNPRINTF_BUF_LEN);
568 switch(get_ia32_op_type(n)) {
570 if (is_ia32_ImmConst(n)) {
571 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%C", n);
573 else if (is_ia32_ImmSymConst(n)) {
574 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "OFFSET FLAT:%C", n);
577 if (is_ia32_MulS(n) || is_ia32_Mulh(n)) {
578 /* MulS and Mulh implicitly multiply by EAX */
579 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%4S", n);
580 } else if(is_ia32_Push(n)) {
581 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%3S", n);
583 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%1D", n);
588 assert(!is_ia32_Push(n));
589 snprintf(buf, SNPRINTF_BUF_LEN, "%s", ia32_emit_am(n, env));
593 Mulh is emitted via emit_unop
594 imul [MEM] means EDX:EAX <- EAX * [MEM]
596 assert((is_ia32_Mulh(n) || is_ia32_MulS(n) || is_ia32_Push(n)) && "Only MulS and Mulh can have AM source as unop");
597 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%s", ia32_emit_am(n, env));
600 assert(0 && "unsupported op type");
607 * Emits address mode.
609 const char *ia32_emit_am(const ir_node *n, ia32_emit_env_t *env) {
610 ia32_am_flavour_t am_flav = get_ia32_am_flavour(n);
614 static struct obstack *obst = NULL;
615 ir_mode *mode = get_ia32_ls_mode(n);
617 if (! is_ia32_Lea(n))
618 assert(mode && "AM node must have ls_mode attribute set.");
621 obst = xcalloc(1, sizeof(*obst));
624 obstack_free(obst, NULL);
627 /* obstack_free with NULL results in an uninitialized obstack */
630 p = pointer_size(mode, has_x87_register(n) || is_ia32_GetST0(n) || is_ia32_SetST0(n));
632 obstack_printf(obst, "%s ", p);
634 /* emit address mode symconst */
635 if (get_ia32_am_sc(n)) {
636 if (is_ia32_am_sc_sign(n))
637 obstack_printf(obst, "-");
638 obstack_printf(obst, "%s", get_id_str(get_ia32_am_sc(n)));
641 if (am_flav & ia32_B) {
642 obstack_printf(obst, "[");
643 lc_eoprintf(ia32_get_arg_env(), obst, "%1S", n);
647 if (am_flav & ia32_I) {
649 obstack_printf(obst, "+");
652 obstack_printf(obst, "[");
655 lc_eoprintf(ia32_get_arg_env(), obst, "%2S", n);
657 if (am_flav & ia32_S) {
658 obstack_printf(obst, "*%d", 1 << get_ia32_am_scale(n));
664 if (am_flav & ia32_O) {
665 int offs = get_ia32_am_offs_int(n);
668 /* omit explicit + if there was no base or index */
670 obstack_printf(obst, "[%d", offs);
672 obstack_printf(obst, "%+d", offs);
680 obstack_printf(obst, "] ");
682 obstack_1grow(obst, '\0');
683 s = obstack_finish(obst);
691 const char *ia32_emit_adr(const ir_node *irn, ia32_emit_env_t *env)
693 static char buf[SNPRINTF_BUF_LEN];
694 ir_mode *mode = get_ia32_ls_mode(irn);
695 const char *adr = get_ia32_cnst(irn);
696 const char *pref = pointer_size(mode, has_x87_register(irn));
698 snprintf(buf, SNPRINTF_BUF_LEN, "%s %s", pref ? pref : "", adr);
703 * Formated print of commands and comments.
705 static void ia32_fprintf_format(FILE *F, const ir_node *irn, char *cmd_buf, char *cmnt_buf) {
707 const char *name = irn ? be_retrieve_dbg_info(get_irn_dbg_info((ir_node *)irn), &lineno) : NULL;
710 fprintf(F, "\t%-35s %-60s /* %s:%u */\n", cmd_buf, cmnt_buf, name, lineno);
712 fprintf(F, "\t%-35s %-60s\n", cmd_buf, cmnt_buf);
718 * Add a number to a prefix. This number will not be used a second time.
720 static char *get_unique_label(char *buf, size_t buflen, const char *prefix) {
721 static unsigned long id = 0;
722 snprintf(buf, buflen, "%s%lu", prefix, ++id);
728 /*************************************************
731 * ___ _ __ ___ _| |_ ___ ___ _ __ __| |
732 * / _ \ '_ ` _ \| | __| / __/ _ \| '_ \ / _` |
733 * | __/ | | | | | | |_ | (_| (_) | | | | (_| |
734 * \___|_| |_| |_|_|\__| \___\___/|_| |_|\__,_|
736 *************************************************/
739 #define IA32_DO_EMIT(irn) ia32_fprintf_format(F, irn, cmd_buf, cmnt_buf)
742 * coding of conditions
744 struct cmp2conditon_t {
750 * positive conditions for signed compares
752 static const struct cmp2conditon_t cmp2condition_s[] = {
753 { NULL, pn_Cmp_False }, /* always false */
754 { "e", pn_Cmp_Eq }, /* == */
755 { "l", pn_Cmp_Lt }, /* < */
756 { "le", pn_Cmp_Le }, /* <= */
757 { "g", pn_Cmp_Gt }, /* > */
758 { "ge", pn_Cmp_Ge }, /* >= */
759 { "ne", pn_Cmp_Lg }, /* != */
760 { "ordered", pn_Cmp_Leg }, /* Floating point: ordered */
761 { "unordered", pn_Cmp_Uo }, /* FLoting point: unordered */
762 { "e", pn_Cmp_Ue }, /* Floating point: unordered or == */
763 { "b", pn_Cmp_Ul }, /* Floating point: unordered or < */
764 { "be", pn_Cmp_Ule }, /* Floating point: unordered or <= */
765 { "a", pn_Cmp_Ug }, /* Floating point: unordered or > */
766 { "ae", pn_Cmp_Uge }, /* Floating point: unordered or >= */
767 { "ne", pn_Cmp_Ne }, /* Floating point: unordered or != */
768 { NULL, pn_Cmp_True }, /* always true */
772 * positive conditions for unsigned compares
774 static const struct cmp2conditon_t cmp2condition_u[] = {
775 { NULL, pn_Cmp_False }, /* always false */
776 { "e", pn_Cmp_Eq }, /* == */
777 { "b", pn_Cmp_Lt }, /* < */
778 { "be", pn_Cmp_Le }, /* <= */
779 { "a", pn_Cmp_Gt }, /* > */
780 { "ae", pn_Cmp_Ge }, /* >= */
781 { "ne", pn_Cmp_Lg }, /* != */
782 { "ordered", pn_Cmp_Leg }, /* Floating point: ordered */
783 { "unordered", pn_Cmp_Uo }, /* FLoting point: unordered */
784 { "e", pn_Cmp_Ue }, /* Floating point: unordered or == */
785 { "b", pn_Cmp_Ul }, /* Floating point: unordered or < */
786 { "be", pn_Cmp_Ule }, /* Floating point: unordered or <= */
787 { "a", pn_Cmp_Ug }, /* Floating point: unordered or > */
788 { "ae", pn_Cmp_Uge }, /* Floating point: unordered or >= */
789 { "ne", pn_Cmp_Ne }, /* Floating point: unordered or != */
790 { NULL, pn_Cmp_True }, /* always true */
794 * returns the condition code
796 static const char *get_cmp_suffix(int cmp_code, int unsigned_cmp)
798 assert(cmp2condition_s[cmp_code].num == cmp_code);
799 assert(cmp2condition_u[cmp_code].num == cmp_code);
801 return unsigned_cmp ? cmp2condition_u[cmp_code & 7].name : cmp2condition_s[cmp_code & 7].name;
805 * Returns the target block for a control flow node.
807 static ir_node *get_cfop_target_block(const ir_node *irn) {
808 return get_irn_link(irn);
812 * Returns the target label for a control flow node.
814 static char *get_cfop_target(const ir_node *irn, char *buf) {
815 ir_node *bl = get_cfop_target_block(irn);
817 snprintf(buf, SNPRINTF_BUF_LEN, BLOCK_PREFIX("%ld"), get_irn_node_nr(bl));
821 /** Return the next block in Block schedule */
822 static ir_node *next_blk_sched(const ir_node *block) {
823 return get_irn_link(block);
827 * Returns the Proj with projection number proj and NOT mode_M
829 static ir_node *get_proj(const ir_node *irn, long proj) {
830 const ir_edge_t *edge;
833 assert(get_irn_mode(irn) == mode_T && "expected mode_T node");
835 foreach_out_edge(irn, edge) {
836 src = get_edge_src_irn(edge);
838 assert(is_Proj(src) && "Proj expected");
839 if (get_irn_mode(src) == mode_M)
842 if (get_Proj_proj(src) == proj)
849 * Emits the jump sequence for a conditional jump (cmp + jmp_true + jmp_false)
851 static void finish_CondJmp(FILE *F, const ir_node *irn, ir_mode *mode) {
852 const ir_node *proj_true;
853 const ir_node *proj_false;
854 const ir_node *block;
855 const ir_node *next_block;
856 char buf[SNPRINTF_BUF_LEN];
857 char cmd_buf[SNPRINTF_BUF_LEN];
858 char cmnt_buf[SNPRINTF_BUF_LEN];
863 /* get both Proj's */
864 proj_true = get_proj(irn, pn_Cond_true);
865 assert(proj_true && "CondJmp without true Proj");
867 proj_false = get_proj(irn, pn_Cond_false);
868 assert(proj_false && "CondJmp without false Proj");
870 pnc = get_ia32_pncode(irn);
872 /* for now, the code works for scheduled and non-schedules blocks */
873 block = get_nodes_block(irn);
875 /* we have a block schedule */
876 next_block = next_blk_sched(block);
878 if (get_cfop_target_block(proj_true) == next_block) {
879 /* exchange both proj's so the second one can be omitted */
880 const ir_node *t = proj_true;
881 proj_true = proj_false;
885 pnc = get_negated_pnc(pnc, mode);
888 /* the first Proj must always be created */
889 is_unsigned = mode_is_float(mode) || ! mode_is_signed(mode);
890 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "j%s %s",
891 get_cmp_suffix(pnc, is_unsigned),
892 get_cfop_target(proj_true, buf));
893 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* %s(a, b) %s*/",
894 get_pnc_string(pnc), flipped ? "(was flipped)" : "");
897 /* the second Proj might be a fallthrough */
898 if (get_cfop_target_block(proj_false) != next_block) {
899 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "jmp %s", get_cfop_target(proj_false, buf));
900 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* otherwise */");
904 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* fallthrough %s */", get_cfop_target(proj_false, buf));
910 * Emits code for conditional jump.
912 static void CondJmp_emitter(const ir_node *irn, ia32_emit_env_t *env) {
914 char cmd_buf[SNPRINTF_BUF_LEN];
915 char cmnt_buf[SNPRINTF_BUF_LEN];
917 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "cmp %s", ia32_emit_binop(irn, env));
918 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F */", irn);
920 finish_CondJmp(F, irn, get_ia32_res_mode(irn));
924 * Emits code for conditional jump with two variables.
926 static void emit_ia32_CondJmp(const ir_node *irn, ia32_emit_env_t *env) {
927 CondJmp_emitter(irn, env);
931 * Emits code for conditional test and jump.
933 static void TestJmp_emitter(const ir_node *irn, ia32_emit_env_t *env) {
935 #define IA32_IS_IMMOP (is_ia32_ImmConst(irn) || is_ia32_ImmSymConst(irn))
938 const char *op1 = arch_register_get_name(get_in_reg(irn, 0));
939 const char *op2 = IA32_IS_IMMOP ? get_ia32_cnst(irn) : NULL;
940 char cmd_buf[SNPRINTF_BUF_LEN];
941 char cmnt_buf[SNPRINTF_BUF_LEN];
944 op2 = arch_register_get_name(get_in_reg(irn, 1));
946 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "test %%%s,%s%s ", op1, IA32_IS_IMMOP ? " " : " %", op2);
947 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F */", irn);
950 finish_CondJmp(F, irn, get_ia32_res_mode(irn));
956 * Emits code for conditional test and jump with two variables.
958 static void emit_ia32_TestJmp(const ir_node *irn, ia32_emit_env_t *env) {
959 TestJmp_emitter(irn, env);
962 static void emit_ia32_CJmp(const ir_node *irn, ia32_emit_env_t *env) {
964 char cmd_buf[SNPRINTF_BUF_LEN];
965 char cmnt_buf[SNPRINTF_BUF_LEN];
967 snprintf(cmd_buf, SNPRINTF_BUF_LEN, " ");
968 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F omitted redundant test */", irn);
970 finish_CondJmp(F, irn, get_ia32_res_mode(irn));
973 static void emit_ia32_CJmpAM(const ir_node *irn, ia32_emit_env_t *env) {
975 char cmd_buf[SNPRINTF_BUF_LEN];
976 char cmnt_buf[SNPRINTF_BUF_LEN];
978 snprintf(cmd_buf, SNPRINTF_BUF_LEN, " ");
979 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F omitted redundant test/cmp */", irn);
981 finish_CondJmp(F, irn, get_ia32_res_mode(irn));
985 * Emits code for conditional SSE floating point jump with two variables.
987 static void emit_ia32_xCondJmp(ir_node *irn, ia32_emit_env_t *env) {
989 char cmd_buf[SNPRINTF_BUF_LEN];
990 char cmnt_buf[SNPRINTF_BUF_LEN];
992 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "ucomis%M %s", irn, ia32_emit_binop(irn, env));
993 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F */", irn);
995 finish_CondJmp(F, irn, mode_F);
1000 * Emits code for conditional x87 floating point jump with two variables.
1002 static void emit_ia32_x87CondJmp(ir_node *irn, ia32_emit_env_t *env) {
1004 char cmd_buf[SNPRINTF_BUF_LEN];
1005 char cmnt_buf[SNPRINTF_BUF_LEN];
1006 ia32_attr_t *attr = get_ia32_attr(irn);
1007 const char *reg = attr->x87[1]->name;
1008 const char *instr = "fcom";
1011 switch (get_ia32_irn_opcode(irn)) {
1012 case iro_ia32_fcomrJmp:
1014 case iro_ia32_fcomJmp:
1018 case iro_ia32_fcomrpJmp:
1020 case iro_ia32_fcompJmp:
1023 case iro_ia32_fcomrppJmp:
1025 case iro_ia32_fcomppJmp:
1032 set_ia32_pncode(irn, (long)get_inversed_pnc(get_ia32_pncode(irn)));
1034 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "%s %s%s", instr, reg[0] == '\0' ? "" : "%", reg);
1035 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F */", irn);
1037 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "fnstsw %%ax", irn);
1038 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* Store x87 FPU Control Word */");
1040 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "sahf");
1041 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* Store ah into flags */");
1044 /* the compare flags must be evaluated using carry , ie unsigned */
1045 finish_CondJmp(F, irn, mode_Iu);
1048 static void CMov_emitter(ir_node *irn, ia32_emit_env_t *env) {
1050 const lc_arg_env_t *arg_env = ia32_get_arg_env();
1051 ir_mode *mode = get_irn_mode(get_irn_n(irn, 0));
1052 int is_unsigned = mode_is_float(mode) || ! mode_is_signed(mode);
1053 const char *cmp_suffix = get_cmp_suffix(get_ia32_pncode(irn), is_unsigned);
1054 int is_PsiCondCMov = is_ia32_PsiCondCMov(irn);
1055 int idx_left = 2 - is_PsiCondCMov;
1056 int idx_right = 3 - is_PsiCondCMov;
1058 char cmd_buf[SNPRINTF_BUF_LEN];
1059 char cmnt_buf[SNPRINTF_BUF_LEN];
1060 const arch_register_t *in1, *in2, *out;
1062 out = arch_get_irn_register(env->arch_env, irn);
1063 in1 = arch_get_irn_register(env->arch_env, get_irn_n(irn, idx_left));
1064 in2 = arch_get_irn_register(env->arch_env, get_irn_n(irn, idx_right));
1066 /* we have to emit the cmp first, because the destination register */
1067 /* could be one of the compare registers */
1068 if (is_ia32_CmpCMov(irn)) {
1069 lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "cmp %1S, %2S", irn, irn);
1071 else if (is_ia32_xCmpCMov(irn)) {
1072 lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "ucomis%M %1S, %2S", get_irn_n(irn, 0), irn, irn);
1074 else if (is_PsiCondCMov) {
1075 /* omit compare because flags are already set by And/Or */
1076 lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "test %1S, %1S", irn, irn);
1079 assert(0 && "unsupported CMov");
1081 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* Psi condition */" );
1084 if (REGS_ARE_EQUAL(out, in2)) {
1085 /* best case: default in == out -> do nothing */
1087 else if (REGS_ARE_EQUAL(out, in1)) {
1088 /* true in == out -> need complement compare and exchange true and default in */
1089 ir_node *t = get_irn_n(irn, idx_left);
1090 set_irn_n(irn, idx_left, get_irn_n(irn, idx_right));
1091 set_irn_n(irn, idx_right, t);
1093 cmp_suffix = get_cmp_suffix(get_negated_pnc(get_ia32_pncode(irn), get_irn_mode(irn)), is_unsigned);
1097 /* out is different from in: need copy default -> out */
1099 lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "mov %1D, %3S", irn, irn);
1101 lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "mov %1D, %4S", irn, irn);
1103 lc_esnprintf(arg_env, cmnt_buf, SNPRINTF_BUF_LEN, "/* copy default -> out */" );
1108 lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "cmov%s %1D, %2S", cmp_suffix, irn, irn);
1110 lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "cmov%s %1D, %3S", cmp_suffix, irn, irn);
1112 lc_esnprintf(arg_env, cmnt_buf, SNPRINTF_BUF_LEN, "/* condition is true case */" );
1116 static void emit_ia32_CmpCMov(ir_node *irn, ia32_emit_env_t *env) {
1117 CMov_emitter(irn, env);
1120 static void emit_ia32_PsiCondCMov(ir_node *irn, ia32_emit_env_t *env) {
1121 CMov_emitter(irn, env);
1124 static void emit_ia32_xCmpCMov(ir_node *irn, ia32_emit_env_t *env) {
1125 CMov_emitter(irn, env);
1128 static void Set_emitter(ir_node *irn, ir_mode *mode, ia32_emit_env_t *env) {
1130 const lc_arg_env_t *arg_env = ia32_get_arg_env();
1131 int is_unsigned = mode_is_float(mode) || ! mode_is_signed(mode);
1132 const char *cmp_suffix = get_cmp_suffix(get_ia32_pncode(irn), is_unsigned);
1133 const char *reg8bit;
1135 char cmd_buf[SNPRINTF_BUF_LEN];
1136 char cmnt_buf[SNPRINTF_BUF_LEN];
1137 const arch_register_t *out;
1139 out = arch_get_irn_register(env->arch_env, irn);
1140 reg8bit = ia32_get_mapped_reg_name(env->isa->regs_8bit, out);
1142 if (is_ia32_CmpSet(irn)) {
1143 lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "cmp %s", ia32_emit_binop(irn, env));
1145 else if (is_ia32_xCmpSet(irn)) {
1146 lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "ucomis%M %s", get_irn_n(irn, 2), ia32_emit_binop(irn, env));
1148 else if (is_ia32_PsiCondSet(irn)) {
1149 /* omit compare because flags are already set by And/Or */
1150 snprintf(cmd_buf, SNPRINTF_BUF_LEN, " ");
1153 assert(0 && "unsupported Set");
1155 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* calculate Psi condition */" );
1158 /* use mov to clear target because it doesn't affect the eflags */
1159 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "mov %%%s, 0", arch_register_get_name(out));
1160 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* clear target as set modifies only lower 8 bit */");
1163 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "set%s %%%s", cmp_suffix, reg8bit);
1164 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* set 1 iff true, 0 otherweise */" );
1168 static void emit_ia32_CmpSet(ir_node *irn, ia32_emit_env_t *env) {
1169 Set_emitter(irn, get_irn_mode(get_irn_n(irn, 2)), env);
1172 static void emit_ia32_PsiCondSet(ir_node *irn, ia32_emit_env_t *env) {
1173 Set_emitter(irn, get_irn_mode(get_irn_n(irn, 0)), env);
1176 static void emit_ia32_xCmpSet(ir_node *irn, ia32_emit_env_t *env) {
1177 Set_emitter(irn, get_irn_mode(get_irn_n(irn, 2)), env);
1180 static void emit_ia32_xCmp(ir_node *irn, ia32_emit_env_t *env) {
1182 const lc_arg_env_t *arg_env = ia32_get_arg_env();
1184 long pnc = get_ia32_pncode(irn);
1185 long unord = pnc & pn_Cmp_Uo;
1186 char cmd_buf[SNPRINTF_BUF_LEN];
1187 char cmnt_buf[SNPRINTF_BUF_LEN];
1190 case pn_Cmp_Leg: /* odered */
1193 case pn_Cmp_Uo: /* unordered */
1197 case pn_Cmp_Eq: /* == */
1201 case pn_Cmp_Lt: /* < */
1205 case pn_Cmp_Le: /* <= */
1209 case pn_Cmp_Gt: /* > */
1213 case pn_Cmp_Ge: /* >= */
1217 case pn_Cmp_Lg: /* != */
1222 assert(sse_pnc >= 0 && "unsupported compare");
1224 if (unord && sse_pnc != 3) {
1226 We need a separate compare against unordered.
1227 Quick and Dirty solution:
1228 - get some memory on stack
1232 - and result and stored result
1235 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "sub %%esp, 8");
1236 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* reserve some space for unordered compare result */");
1238 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "cmpsd %s, 3", ia32_emit_binop(irn, env));
1239 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* SSE compare: unordered */");
1241 lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "movsd [%%esp], %1D", irn);
1242 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* store compare result */");
1246 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "cmpsd %s, %d", ia32_emit_binop(irn, env), sse_pnc);
1247 lc_esnprintf(arg_env, cmnt_buf, SNPRINTF_BUF_LEN, "/* SSE compare (%+F) with result in %1D */", irn, irn);
1250 if (unord && sse_pnc != 3) {
1251 lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "andpd %1D, [%%esp]", irn);
1252 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* build the final result */");
1254 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "add %%esp, 8");
1255 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* free allocated space */");
1260 /*********************************************************
1263 * ___ _ __ ___ _| |_ _ _ _ _ __ ___ _ __ ___
1264 * / _ \ '_ ` _ \| | __| | | | | | '_ ` _ \| '_ \/ __|
1265 * | __/ | | | | | | |_ | | |_| | | | | | | |_) \__ \
1266 * \___|_| |_| |_|_|\__| | |\__,_|_| |_| |_| .__/|___/
1269 *********************************************************/
1271 /* jump table entry (target and corresponding number) */
1272 typedef struct _branch_t {
1277 /* jump table for switch generation */
1278 typedef struct _jmp_tbl_t {
1279 ir_node *defProj; /**< default target */
1280 int min_value; /**< smallest switch case */
1281 int max_value; /**< largest switch case */
1282 int num_branches; /**< number of jumps */
1283 char *label; /**< label of the jump table */
1284 branch_t *branches; /**< jump array */
1288 * Compare two variables of type branch_t. Used to sort all switch cases
1290 static int ia32_cmp_branch_t(const void *a, const void *b) {
1291 branch_t *b1 = (branch_t *)a;
1292 branch_t *b2 = (branch_t *)b;
1294 if (b1->value <= b2->value)
1301 * Emits code for a SwitchJmp (creates a jump table if
1302 * possible otherwise a cmp-jmp cascade). Port from
1305 static void emit_ia32_SwitchJmp(const ir_node *irn, ia32_emit_env_t *emit_env) {
1306 unsigned long interval;
1307 char buf[SNPRINTF_BUF_LEN];
1308 int last_value, i, pn;
1311 const ir_edge_t *edge;
1312 const lc_arg_env_t *env = ia32_get_arg_env();
1313 FILE *F = emit_env->out;
1314 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1316 /* fill the table structure */
1317 tbl.label = xmalloc(SNPRINTF_BUF_LEN);
1318 tbl.label = get_unique_label(tbl.label, SNPRINTF_BUF_LEN, ".TBL_");
1320 tbl.num_branches = get_irn_n_edges(irn);
1321 tbl.branches = xcalloc(tbl.num_branches, sizeof(tbl.branches[0]));
1322 tbl.min_value = INT_MAX;
1323 tbl.max_value = INT_MIN;
1326 /* go over all proj's and collect them */
1327 foreach_out_edge(irn, edge) {
1328 proj = get_edge_src_irn(edge);
1329 assert(is_Proj(proj) && "Only proj allowed at SwitchJmp");
1331 pn = get_Proj_proj(proj);
1333 /* create branch entry */
1334 tbl.branches[i].target = proj;
1335 tbl.branches[i].value = pn;
1337 tbl.min_value = pn < tbl.min_value ? pn : tbl.min_value;
1338 tbl.max_value = pn > tbl.max_value ? pn : tbl.max_value;
1340 /* check for default proj */
1341 if (pn == get_ia32_pncode(irn)) {
1342 assert(tbl.defProj == NULL && "found two defProjs at SwitchJmp");
1349 /* sort the branches by their number */
1350 qsort(tbl.branches, tbl.num_branches, sizeof(tbl.branches[0]), ia32_cmp_branch_t);
1352 /* two-complement's magic make this work without overflow */
1353 interval = tbl.max_value - tbl.min_value;
1355 /* emit the table */
1356 lc_esnprintf(env, cmd_buf, SNPRINTF_BUF_LEN, "cmp %1S, %u", irn, interval);
1357 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* compare for switch */");
1360 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "ja %s", get_cfop_target(tbl.defProj, buf));
1361 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* default jump if out of range */");
1364 if (tbl.num_branches > 1) {
1367 lc_esnprintf(env, cmd_buf, SNPRINTF_BUF_LEN, "jmp %s[%1S*4]", tbl.label, irn);
1368 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* get jump table entry as target */");
1371 ia32_switch_section(F, SECTION_RODATA);
1372 fprintf(F, "\t.align 4\n");
1374 fprintf(F, "%s:\n", tbl.label);
1376 snprintf(cmd_buf, SNPRINTF_BUF_LEN, ".long %s", get_cfop_target(tbl.branches[0].target, buf));
1377 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* case %d */", tbl.branches[0].value);
1380 last_value = tbl.branches[0].value;
1381 for (i = 1; i < tbl.num_branches; ++i) {
1382 while (++last_value < tbl.branches[i].value) {
1383 snprintf(cmd_buf, SNPRINTF_BUF_LEN, ".long %s", get_cfop_target(tbl.defProj, buf));
1384 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* default case */");
1387 snprintf(cmd_buf, SNPRINTF_BUF_LEN, ".long %s", get_cfop_target(tbl.branches[i].target, buf));
1388 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* case %d */", last_value);
1391 ia32_switch_section(F, SECTION_TEXT);
1394 /* one jump is enough */
1395 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "jmp %s", get_cfop_target(tbl.branches[0].target, buf));
1396 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* only one case given */");
1407 * Emits code for a unconditional jump.
1409 static void emit_Jmp(const ir_node *irn, ia32_emit_env_t *env) {
1410 ir_node *block, *next_bl;
1412 char buf[SNPRINTF_BUF_LEN], cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1414 /* for now, the code works for scheduled and non-schedules blocks */
1415 block = get_nodes_block(irn);
1417 /* we have a block schedule */
1418 next_bl = next_blk_sched(block);
1419 if (get_cfop_target_block(irn) != next_bl) {
1420 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "jmp %s", get_cfop_target(irn, buf));
1421 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F(%+F) */", irn, get_cfop_target_block(irn));
1425 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* fallthrough %s */", get_cfop_target(irn, buf));
1430 /****************************
1433 * _ __ _ __ ___ _ ___
1434 * | '_ \| '__/ _ \| |/ __|
1435 * | |_) | | | (_) | |\__ \
1436 * | .__/|_| \___/| ||___/
1439 ****************************/
1442 * Emits code for a proj -> node
1444 static void emit_Proj(const ir_node *irn, ia32_emit_env_t *env) {
1445 ir_node *pred = get_Proj_pred(irn);
1447 if (get_irn_op(pred) == op_Start) {
1448 switch(get_Proj_proj(irn)) {
1449 case pn_Start_X_initial_exec:
1458 /**********************************
1461 * | | ___ _ __ _ _| |_) |
1462 * | | / _ \| '_ \| | | | _ <
1463 * | |___| (_) | |_) | |_| | |_) |
1464 * \_____\___/| .__/ \__, |____/
1467 **********************************/
1470 * Emit movsb/w instructions to make mov count divideable by 4
1472 static void emit_CopyB_prolog(FILE *F, const ir_node *irn, int rem) {
1473 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1475 ir_fprintf(F, "\t/* memcopy prolog %+F */\n", irn);
1477 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "cld");
1478 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* copy direction forward */");
1483 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "movsb");
1484 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* memcopy remainder 1 */");
1488 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "movsw");
1489 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* memcopy remainder 2 */");
1493 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "movsb");
1494 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* memcopy remainder 3 */");
1496 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "movsw");
1497 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* memcopy remainder 3 */");
1505 * Emit rep movsd instruction for memcopy.
1507 static void emit_ia32_CopyB(const ir_node *irn, ia32_emit_env_t *emit_env) {
1508 FILE *F = emit_env->out;
1509 tarval *tv = get_ia32_Immop_tarval(irn);
1510 int rem = get_tarval_long(tv);
1511 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1513 emit_CopyB_prolog(F, irn, rem);
1515 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "rep movsd");
1516 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* memcopy */");
1521 * Emits unrolled memcopy.
1523 static void emit_ia32_CopyB_i(const ir_node *irn, ia32_emit_env_t *emit_env) {
1524 tarval *tv = get_ia32_Immop_tarval(irn);
1525 int size = get_tarval_long(tv);
1526 FILE *F = emit_env->out;
1527 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1529 emit_CopyB_prolog(F, irn, size & 0x3);
1533 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "movsd");
1534 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* memcopy unrolled */");
1541 /***************************
1545 * | | / _ \| '_ \ \ / /
1546 * | |___| (_) | | | \ V /
1547 * \_____\___/|_| |_|\_/
1549 ***************************/
1552 * Emit code for conversions (I, FP), (FP, I) and (FP, FP).
1554 static void emit_ia32_Conv_with_FP(const ir_node *irn, ia32_emit_env_t *emit_env) {
1555 FILE *F = emit_env->out;
1556 const lc_arg_env_t *env = ia32_get_arg_env();
1557 ir_mode *src_mode = get_ia32_src_mode(irn);
1558 ir_mode *tgt_mode = get_ia32_tgt_mode(irn);
1559 char *from, *to, buf[64];
1560 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1562 from = mode_is_float(src_mode) ? (get_mode_size_bits(src_mode) == 32 ? "ss" : "sd") : "si";
1563 to = mode_is_float(tgt_mode) ? (get_mode_size_bits(tgt_mode) == 32 ? "ss" : "sd") : "si";
1565 switch(get_ia32_op_type(irn)) {
1567 lc_esnprintf(env, buf, sizeof(buf), "%1D, %3S", irn, irn);
1569 case ia32_AddrModeS:
1570 lc_esnprintf(env, buf, sizeof(buf), "%1D, %s", irn, ia32_emit_am(irn, emit_env));
1573 assert(0 && "unsupported op type for Conv");
1576 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "cvt%s2%s %s", from, to, buf);
1577 lc_esnprintf(env, cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F(%+F, %+F) */", irn, src_mode, tgt_mode);
1581 static void emit_ia32_Conv_I2FP(const ir_node *irn, ia32_emit_env_t *emit_env) {
1582 emit_ia32_Conv_with_FP(irn, emit_env);
1585 static void emit_ia32_Conv_FP2I(const ir_node *irn, ia32_emit_env_t *emit_env) {
1586 emit_ia32_Conv_with_FP(irn, emit_env);
1589 static void emit_ia32_Conv_FP2FP(const ir_node *irn, ia32_emit_env_t *emit_env) {
1590 emit_ia32_Conv_with_FP(irn, emit_env);
1594 * Emits code for an Int conversion.
1596 static void emit_ia32_Conv_I2I(const ir_node *irn, ia32_emit_env_t *emit_env) {
1597 FILE *F = emit_env->out;
1598 const lc_arg_env_t *env = ia32_get_arg_env();
1599 char *move_cmd = "movzx";
1600 char *conv_cmd = NULL;
1601 ir_mode *src_mode = get_ia32_src_mode(irn);
1602 ir_mode *tgt_mode = get_ia32_tgt_mode(irn);
1605 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1606 const arch_register_t *in_reg, *out_reg;
1608 n = get_mode_size_bits(src_mode);
1609 m = get_mode_size_bits(tgt_mode);
1611 assert(n == 8 || n == 16 || n == 32);
1612 assert(m == 8 || m == 16 || m == 32);
1615 signed_mode = mode_is_signed(n < m ? src_mode : tgt_mode);
1620 switch(get_ia32_op_type(irn)) {
1622 in_reg = get_in_reg(irn, 2);
1623 out_reg = get_out_reg(irn, 0);
1625 if (REGS_ARE_EQUAL(in_reg, &ia32_gp_regs[REG_EAX]) &&
1626 REGS_ARE_EQUAL(out_reg, in_reg) &&
1629 if (n == 8 || m == 8)
1631 else if (n == 16 || m == 16)
1634 /* argument and result are both in EAX and */
1635 /* signedness is ok: -> use converts */
1636 lc_esnprintf(env, cmd_buf, SNPRINTF_BUF_LEN, "%s", conv_cmd);
1638 else if (REGS_ARE_EQUAL(out_reg, in_reg) && ! signed_mode)
1640 /* argument and result are in the same register */
1641 /* and signedness is ok: -> use and with mask */
1642 int mask = (1 << (n < m ? n : m)) - 1;
1643 lc_esnprintf(env, cmd_buf, SNPRINTF_BUF_LEN, "and %1D, 0x%x", irn, mask);
1646 /* use move w/o sign extension */
1647 lc_esnprintf(env, cmd_buf, SNPRINTF_BUF_LEN, "%s %1D, %%%s",
1648 move_cmd, irn, ia32_get_reg_name_for_mode(emit_env, n < m ? src_mode : tgt_mode, in_reg));
1652 case ia32_AddrModeS:
1653 lc_esnprintf(env, cmd_buf, SNPRINTF_BUF_LEN, "%s %1D, %s",
1654 move_cmd, irn, ia32_emit_am(irn, emit_env));
1657 assert(0 && "unsupported op type for Conv");
1660 lc_esnprintf(env, cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F(%d Bit mode_%F -> %d Bit mode_%F) */",
1661 irn, n, src_mode, m, tgt_mode);
1667 * Emits code for an 8Bit Int conversion.
1669 void emit_ia32_Conv_I2I8Bit(const ir_node *irn, ia32_emit_env_t *emit_env) {
1670 emit_ia32_Conv_I2I(irn, emit_env);
1674 /*******************************************
1677 * | |__ ___ _ __ ___ __| | ___ ___
1678 * | '_ \ / _ \ '_ \ / _ \ / _` |/ _ \/ __|
1679 * | |_) | __/ | | | (_) | (_| | __/\__ \
1680 * |_.__/ \___|_| |_|\___/ \__,_|\___||___/
1682 *******************************************/
1685 * Emits a backend call
1687 static void emit_be_Call(const ir_node *irn, ia32_emit_env_t *emit_env) {
1688 FILE *F = emit_env->out;
1689 entity *ent = be_Call_get_entity(irn);
1690 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1693 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "call %s", get_entity_ld_name(ent));
1696 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "call %1D", get_irn_n(irn, be_pos_Call_ptr));
1699 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F (be_Call) */", irn);
1705 * Emits code to increase stack pointer.
1707 static void emit_be_IncSP(const ir_node *irn, ia32_emit_env_t *emit_env) {
1708 FILE *F = emit_env->out;
1709 int offs = be_get_IncSP_offset(irn);
1710 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1714 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "sub %1S, %u", irn, offs);
1716 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "add %1S, %u", irn, -offs);
1717 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F (IncSP) */", irn);
1720 snprintf(cmd_buf, SNPRINTF_BUF_LEN, " ");
1721 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* omitted %+F (IncSP) with 0 */", irn);
1728 * Emits code to set stack pointer.
1730 static void emit_be_SetSP(const ir_node *irn, ia32_emit_env_t *emit_env) {
1731 FILE *F = emit_env->out;
1732 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1734 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "mov %1D, %3S", irn, irn);
1735 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F (restore SP) */", irn);
1740 * Emits code for Copy/CopyKeep.
1742 static void Copy_emitter(const ir_node *irn, ir_node *op, ia32_emit_env_t *emit_env) {
1743 FILE *F = emit_env->out;
1744 const arch_env_t *aenv = emit_env->arch_env;
1745 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1747 if (REGS_ARE_EQUAL(arch_get_irn_register(aenv, irn), arch_get_irn_register(aenv, op)) ||
1748 arch_register_type_is(arch_get_irn_register(aenv, op), joker))
1751 if (mode_is_float(get_irn_mode(irn)))
1752 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "movs%M %1D, %1S", irn, irn, irn);
1754 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "mov %1D, %1S", irn, irn);
1755 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F */", irn);
1759 static void emit_be_Copy(const ir_node *irn, ia32_emit_env_t *emit_env) {
1760 Copy_emitter(irn, be_get_Copy_op(irn), emit_env);
1763 static void emit_be_CopyKeep(const ir_node *irn, ia32_emit_env_t *emit_env) {
1764 Copy_emitter(irn, be_get_CopyKeep_op(irn), emit_env);
1768 * Emits code for exchange.
1770 static void emit_be_Perm(const ir_node *irn, ia32_emit_env_t *emit_env) {
1771 FILE *F = emit_env->out;
1772 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1773 const arch_register_t *in1, *in2;
1774 const arch_register_class_t *cls1, *cls2;
1776 in1 = arch_get_irn_register(emit_env->arch_env, get_irn_n(irn, 0));
1777 in2 = arch_get_irn_register(emit_env->arch_env, get_irn_n(irn, 1));
1779 cls1 = arch_register_get_class(in1);
1780 cls2 = arch_register_get_class(in2);
1782 assert(cls1 == cls2 && "Register class mismatch at Perm");
1784 if (cls1 == &ia32_reg_classes[CLASS_ia32_gp]) {
1785 if(emit_env->isa->opt_arch == arch_athlon) {
1786 // xchg commands are Vector path on athlons and therefore stall the DirectPath pipeline
1787 // it is nearly always beneficial to use the 3 xor trick instead of an xchg
1789 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "xor %1S, %2S", irn, irn);
1791 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "xor %2S, %1S", irn, irn);
1793 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "xor %1S, %2S", irn, irn);
1795 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "xchg %1S, %2S", irn, irn);
1798 else if (cls1 == &ia32_reg_classes[CLASS_ia32_xmm]) {
1799 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN,
1800 "pxor %1S, %2S\n\tpxor %2S, %1S\n\tpxor %1S, %2S", irn, irn, irn, irn, irn, irn);
1802 else if (cls1 == &ia32_reg_classes[CLASS_ia32_vfp]) {
1806 else if (cls1 == &ia32_reg_classes[CLASS_ia32_st]) {
1811 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F(%1A, %2A) */", irn, irn, irn);
1816 * Emits code for Constant loading.
1818 static void emit_ia32_Const(const ir_node *n, ia32_emit_env_t *env) {
1820 char cmd_buf[256], cmnt_buf[256];
1821 const lc_arg_env_t *arg_env = ia32_get_arg_env();
1822 ir_mode *mode = get_irn_mode(n);
1823 tarval *tv = get_ia32_Immop_tarval(n);
1825 if (get_ia32_op_type(n) == ia32_SymConst) {
1826 lc_esnprintf(arg_env, cmd_buf, 256, "mov %1D, OFFSET FLAT:%C ", n, n);
1827 lc_esnprintf(arg_env, cmnt_buf, 256, "/* Move address of SymConst into register */");
1829 assert(mode == get_tarval_mode(tv));
1830 /* beware: in some rare cases mode is mode_b which has no tarval_null() */
1831 if (tv == get_tarval_b_false() || tv == get_tarval_null(mode)) {
1832 const char *instr = "xor";
1833 if (env->isa->opt_arch == arch_pentium_4) {
1834 /* P4 prefers sub r, r, others xor r, r */
1837 lc_esnprintf(arg_env, cmd_buf, 256, "%s %1D, %1D ", instr, n, n);
1838 lc_esnprintf(arg_env, cmnt_buf, 256, "/* optimized mov 0 to register */");
1840 lc_esnprintf(arg_env, cmd_buf, 256, "mov %1D, %C ", n, n);
1841 lc_esnprintf(arg_env, cmnt_buf, 256, "/* Mov Const into register */");
1844 lc_efprintf(arg_env, F, "\t%-35s %-60s /* %+F (%+G) */\n", cmd_buf, cmnt_buf, n, n);
1848 * Emits code to increase stack pointer.
1850 static void emit_ia32_AddSP(const ir_node *irn, ia32_emit_env_t *emit_env) {
1851 FILE *F = emit_env->out;
1852 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1854 if (is_ia32_ImmConst(irn)) {
1855 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "sub %1D, %C", irn, irn);
1857 else if (is_ia32_ImmSymConst(irn)) {
1858 if (get_ia32_op_type(irn) == ia32_Normal)
1859 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "sub %1D, OFFSET_FLAT:%C", irn, irn);
1860 else /* source address mode */
1861 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "sub %1D, [%s%s]", irn, get_id_str(get_ia32_am_sc(irn)), get_ia32_am_offs(irn));
1864 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "sub %1D, %2S", irn, irn);
1866 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* reserve space on stack */");
1872 * Emits code to increase stack pointer.
1874 static void emit_ia32_SubSP(const ir_node *irn, ia32_emit_env_t *emit_env) {
1875 FILE *F = emit_env->out;
1876 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1878 if (is_ia32_ImmConst(irn)) {
1879 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "add %1D, %C", irn, irn);
1881 else if (is_ia32_ImmSymConst(irn)) {
1882 if (get_ia32_op_type(irn) == ia32_Normal)
1883 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "add %1D, OFFSET_FLAT:%C", irn, irn);
1884 else /* source address mode */
1885 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "add %1D, [%s%s]", irn, get_id_str(get_ia32_am_sc(irn)), get_ia32_am_offs(irn));
1888 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "add %1D, %2S", irn, irn);
1890 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* free space on stack */");
1896 * Emits code to load the TLS base
1898 static void emit_ia32_LdTls(const ir_node *irn, ia32_emit_env_t *emit_env) {
1899 FILE *F = emit_env->out;
1900 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1902 switch (asm_flavour) {
1904 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "mov %1D, DWORD PTR %%gs:0", irn);
1907 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "mov %1D, DWORD PTR %%gs:0", irn);
1910 assert(0 && "unsupported TLS");
1913 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* get thread local storage base */");
1918 static void emit_be_Return(const ir_node *n, ia32_emit_env_t *env) {
1920 const lc_arg_env_t *arg_env = ia32_get_arg_env();
1922 lc_efprintf(arg_env, F, "\t%-35s %-60s /* %+F (%+G) */\n", "ret", "/* be_Return */", n, n);
1925 static void emit_Nothing(const ir_node *n, ia32_emit_env_t *env) {
1928 ir_fprintf(F, "\t%35s /* %+F (%+G) */\n", " ", n, n);
1932 /***********************************************************************************
1935 * _ __ ___ __ _ _ _ __ | |_ _ __ __ _ _ __ ___ _____ _____ _ __| | __
1936 * | '_ ` _ \ / _` | | '_ \ | _| '__/ _` | '_ ` _ \ / _ \ \ /\ / / _ \| '__| |/ /
1937 * | | | | | | (_| | | | | | | | | | | (_| | | | | | | __/\ V V / (_) | | | <
1938 * |_| |_| |_|\__,_|_|_| |_| |_| |_| \__,_|_| |_| |_|\___| \_/\_/ \___/|_| |_|\_\
1940 ***********************************************************************************/
1943 * Enters the emitter functions for handled nodes into the generic
1944 * pointer of an opcode.
1946 static void ia32_register_emitters(void) {
1948 #define IA32_EMIT2(a,b) op_ia32_##a->ops.generic = (op_func)emit_ia32_##b
1949 #define IA32_EMIT(a) IA32_EMIT2(a,a)
1950 #define EMIT(a) op_##a->ops.generic = (op_func)emit_##a
1951 #define IGN(a) op_##a->ops.generic = (op_func)emit_Nothing
1952 #define BE_EMIT(a) op_be_##a->ops.generic = (op_func)emit_be_##a
1953 #define BE_IGN(a) op_be_##a->ops.generic = (op_func)emit_Nothing
1955 /* first clear the generic function pointer for all ops */
1956 clear_irp_opcodes_generic_func();
1958 /* register all emitter functions defined in spec */
1959 ia32_register_spec_emitters();
1961 /* other ia32 emitter functions */
1967 IA32_EMIT(PsiCondCMov);
1969 IA32_EMIT(PsiCondSet);
1970 IA32_EMIT(SwitchJmp);
1973 IA32_EMIT(Conv_I2FP);
1974 IA32_EMIT(Conv_FP2I);
1975 IA32_EMIT(Conv_FP2FP);
1976 IA32_EMIT(Conv_I2I);
1977 IA32_EMIT(Conv_I2I8Bit);
1984 IA32_EMIT(xCmpCMov);
1985 IA32_EMIT(xCondJmp);
1986 IA32_EMIT2(fcomJmp, x87CondJmp);
1987 IA32_EMIT2(fcompJmp, x87CondJmp);
1988 IA32_EMIT2(fcomppJmp, x87CondJmp);
1989 IA32_EMIT2(fcomrJmp, x87CondJmp);
1990 IA32_EMIT2(fcomrpJmp, x87CondJmp);
1991 IA32_EMIT2(fcomrppJmp, x87CondJmp);
1993 /* benode emitter */
2019 static const char *last_name = NULL;
2020 static unsigned last_line = -1;
2021 static unsigned num = -1;
2024 * Emit the debug support for node irn.
2026 static void ia32_emit_dbg(const ir_node *irn, ia32_emit_env_t *env) {
2027 dbg_info *db = get_irn_dbg_info(irn);
2029 const char *fname = be_retrieve_dbg_info(db, &lineno);
2032 if (last_name != fname) {
2034 be_dbg_include_begin(env->cg->birg->main_env->db_handle, fname);
2037 if (last_line != lineno) {
2041 snprintf(name, sizeof(name), ".LM%u", ++num);
2043 be_dbg_line(env->cg->birg->main_env->db_handle, lineno, name);
2044 fprintf(F, "%s:\n", name);
2050 * Emits code for a node.
2052 static void ia32_emit_node(const ir_node *irn, void *env) {
2053 ia32_emit_env_t *emit_env = env;
2054 ir_op *op = get_irn_op(irn);
2055 DEBUG_ONLY(firm_dbg_module_t *mod = emit_env->mod;)
2057 DBG((mod, LEVEL_1, "emitting code for %+F\n", irn));
2059 if (op->ops.generic) {
2060 void (*emit)(const ir_node *, void *) = (void (*)(const ir_node *, void *))op->ops.generic;
2061 ia32_emit_dbg(irn, emit_env);
2065 emit_Nothing(irn, env);
2066 ir_fprintf(stderr, "Warning: No emit handler for node %+F (%+G)\n", irn, irn);
2071 * Emits gas alignment directives
2073 static void ia32_emit_alignment(FILE *F, unsigned align, unsigned skip) {
2074 fprintf(F, "\t.p2align %u,,%u\n", align, skip);
2078 * Emits gas alignment directives for Functions depended on cpu architecture.
2080 static void ia32_emit_align_func(FILE *F, cpu_support cpu) {
2082 unsigned maximum_skip;
2097 maximum_skip = (1 << align) - 1;
2098 ia32_emit_alignment(F, align, maximum_skip);
2102 * Emits gas alignment directives for Labels depended on cpu architecture.
2104 static void ia32_emit_align_label(FILE *F, cpu_support cpu) {
2105 unsigned align; unsigned maximum_skip;
2120 maximum_skip = (1 << align) - 1;
2121 ia32_emit_alignment(F, align, maximum_skip);
2124 static int is_first_loop_block(ir_node *block, ir_node *prev_block, ia32_emit_env_t *env) {
2125 ir_exec_freq *execfreqs = env->cg->birg->execfreqs;
2126 double block_freq, prev_freq;
2127 static const double DELTA = .0001;
2128 cpu_support cpu = env->isa->opt_arch;
2130 if(execfreqs == NULL)
2132 if(cpu == arch_i386 || cpu == arch_i486)
2135 block_freq = get_block_execfreq(execfreqs, block);
2136 prev_freq = get_block_execfreq(execfreqs, prev_block);
2138 if(block_freq < DELTA || prev_freq < DELTA)
2141 block_freq /= prev_freq;
2145 case arch_athlon_64:
2147 return block_freq > 3;
2152 return block_freq > 2;
2156 * Walks over the nodes in a block connected by scheduling edges
2157 * and emits code for each node.
2159 static void ia32_gen_block(ir_node *block, ir_node *last_block, ia32_emit_env_t *env) {
2160 ir_graph *irg = get_irn_irg(block);
2161 ir_node *start_block = get_irg_start_block(irg);
2166 assert(is_Block(block));
2168 if(block == start_block)
2171 if (need_label && get_irn_arity(block) == 1) {
2172 ir_node *pred_block = get_Block_cfgpred_block(block, 0);
2174 if(pred_block == last_block && get_irn_n_edges_kind(pred_block, EDGE_KIND_BLOCK) <= 2)
2178 // special case because the start block contains no jump instruction
2179 if(last_block == start_block) {
2180 const ir_edge_t *edge;
2181 ir_node *startsucc = NULL;
2183 foreach_block_succ(start_block, edge) {
2184 startsucc = get_edge_src_irn(edge);
2185 if(startsucc != start_block)
2188 assert(startsucc != NULL);
2190 if(startsucc != block) {
2191 char buf[SNPRINTF_BUF_LEN];
2192 ir_snprintf(buf, sizeof(buf), BLOCK_PREFIX("%d"),
2193 get_irn_node_nr(startsucc));
2194 ir_fprintf(F, "\tjmp %s\n", buf);
2199 char cmd_buf[SNPRINTF_BUF_LEN];
2202 ir_exec_freq *execfreqs = env->cg->birg->execfreqs;
2204 // align the loop headers
2205 if(!is_first_loop_block(block, last_block, env)) {
2207 // align blocks where the previous block has no fallthrough
2208 arity = get_irn_arity(block);
2209 for(i = 0; i < arity; ++i) {
2210 ir_node *predblock = get_Block_cfgpred_block(block, i);
2211 if(predblock == last_block) {
2219 ia32_emit_align_label(env->out, env->isa->opt_arch);
2221 ir_snprintf(cmd_buf, sizeof(cmd_buf), BLOCK_PREFIX("%d:"),
2222 get_irn_node_nr(block));
2223 fprintf(F, "%-43s ", cmd_buf);
2225 /* emit list of pred blocks in comment */
2226 fprintf(F, "/* preds:");
2228 arity = get_irn_arity(block);
2229 for(i = 0; i < arity; ++i) {
2230 ir_node *predblock = get_Block_cfgpred_block(block, i);
2231 fprintf(F, " %ld", get_irn_node_nr(predblock));
2233 if(execfreqs != NULL) {
2234 fprintf(F, " freq: %f", get_block_execfreq(execfreqs, block));
2237 fprintf(F, " */\n");
2240 /* emit the contents of the block */
2241 ia32_emit_dbg(block, env);
2242 sched_foreach(block, irn) {
2243 ia32_emit_node(irn, env);
2248 * Emits code for function start.
2250 static void ia32_emit_func_prolog(FILE *F, ir_graph *irg, ia32_emit_env_t *emit_env) {
2251 entity *irg_ent = get_irg_entity(irg);
2252 const char *irg_name = get_entity_ld_name(irg_ent);
2253 cpu_support cpu = emit_env->isa->opt_arch;
2254 const be_irg_t *birg = emit_env->cg->birg;
2257 ia32_switch_section(F, SECTION_TEXT);
2258 be_dbg_method_begin(birg->main_env->db_handle, irg_ent, be_abi_get_stack_layout(birg->abi));
2259 ia32_emit_align_func(F, cpu);
2260 if (get_entity_visibility(irg_ent) == visibility_external_visible) {
2261 fprintf(F, ".globl %s\n", irg_name);
2263 ia32_dump_function_object(F, irg_name);
2264 fprintf(F, "%s:\n", irg_name);
2268 * Emits code for function end
2270 static void ia32_emit_func_epilog(FILE *F, ir_graph *irg, ia32_emit_env_t *emit_env) {
2271 const char *irg_name = get_entity_ld_name(get_irg_entity(irg));
2272 const be_irg_t *birg = emit_env->cg->birg;
2274 ia32_dump_function_size(F, irg_name);
2275 be_dbg_method_end(birg->main_env->db_handle);
2281 * Sets labels for control flow nodes (jump target)
2282 * TODO: Jump optimization
2284 static void ia32_gen_labels(ir_node *block, void *env) {
2286 int n = get_Block_n_cfgpreds(block);
2288 for (n--; n >= 0; n--) {
2289 pred = get_Block_cfgpred(block, n);
2290 set_irn_link(pred, block);
2295 * Main driver. Emits the code for one routine.
2297 void ia32_gen_routine(FILE *F, ir_graph *irg, const ia32_code_gen_t *cg) {
2298 ia32_emit_env_t emit_env;
2300 ir_node *last_block = NULL;
2303 emit_env.arch_env = cg->arch_env;
2305 emit_env.isa = (ia32_isa_t *)cg->arch_env->isa;
2306 FIRM_DBG_REGISTER(emit_env.mod, "firm.be.ia32.emitter");
2308 /* set the global arch_env (needed by print hooks) */
2309 arch_env = cg->arch_env;
2311 ia32_register_emitters();
2313 ia32_emit_func_prolog(F, irg, &emit_env);
2314 irg_block_walk_graph(irg, ia32_gen_labels, NULL, &emit_env);
2316 if ((cg->opt & IA32_OPT_EXTBB) && cg->blk_sched) {
2317 int i, n = ARR_LEN(cg->blk_sched);
2319 for (i = 0; i < n;) {
2322 block = cg->blk_sched[i];
2324 next_bl = i < n ? cg->blk_sched[i] : NULL;
2326 /* set here the link. the emitter expects to find the next block here */
2327 set_irn_link(block, next_bl);
2328 ia32_gen_block(block, last_block, &emit_env);
2333 /* "normal" block schedule: Note the get_next_block() returns the NUMBER of the block
2334 in the block schedule. As this number should NEVER be equal the next block,
2335 we does not need a clear block link here. */
2337 //irg_walk_blkwise_graph(irg, NULL, ia32_gen_block, &emit_env);
2341 ia32_emit_func_epilog(F, irg, &emit_env);