2 * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This file implements the ia32 node emitter.
23 * @author Christian Wuerdig, Matthias Braun
39 #include "iredges_t.h"
43 #include "raw_bitset.h"
47 #include "../besched.h"
48 #include "../benode.h"
50 #include "../be_dbgout.h"
51 #include "../beemitter.h"
52 #include "../begnuas.h"
54 #include "../be_dbgout.h"
56 #include "ia32_emitter.h"
57 #include "gen_ia32_emitter.h"
58 #include "gen_ia32_regalloc_if.h"
59 #include "ia32_nodes_attr.h"
60 #include "ia32_new_nodes.h"
61 #include "ia32_map_regs.h"
62 #include "ia32_architecture.h"
63 #include "bearch_ia32_t.h"
65 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
67 #define BLOCK_PREFIX ".L"
69 #define SNPRINTF_BUF_LEN 128
71 static const ia32_isa_t *isa;
72 static ia32_code_gen_t *cg;
73 static char pic_base_label[128];
74 static ir_label_t exc_label_id;
75 static int mark_spill_reload = 0;
78 /** Return the next block in Block schedule */
79 static ir_node *get_prev_block_sched(const ir_node *block)
81 return get_irn_link(block);
84 /** Checks if the current block is a fall-through target. */
85 static int is_fallthrough(const ir_node *cfgpred)
89 if (!is_Proj(cfgpred))
91 pred = get_Proj_pred(cfgpred);
92 if (is_ia32_SwitchJmp(pred))
99 * returns non-zero if the given block needs a label
100 * because of being a jump-target (and not a fall-through)
102 static int block_needs_label(const ir_node *block)
105 int n_cfgpreds = get_Block_n_cfgpreds(block);
107 if (has_Block_entity(block))
110 if (n_cfgpreds == 0) {
112 } else if (n_cfgpreds == 1) {
113 ir_node *cfgpred = get_Block_cfgpred(block, 0);
114 ir_node *cfgpred_block = get_nodes_block(cfgpred);
116 if (get_prev_block_sched(block) == cfgpred_block
117 && is_fallthrough(cfgpred)) {
126 * Returns the register at in position pos.
128 static const arch_register_t *get_in_reg(const ir_node *irn, int pos)
131 const arch_register_t *reg = NULL;
133 assert(get_irn_arity(irn) > pos && "Invalid IN position");
135 /* The out register of the operator at position pos is the
136 in register we need. */
137 op = get_irn_n(irn, pos);
139 reg = arch_get_irn_register(op);
141 assert(reg && "no in register found");
143 if (reg == &ia32_gp_regs[REG_GP_NOREG])
144 panic("trying to emit noreg for %+F input %d", irn, pos);
146 /* in case of unknown register: just return a valid register */
147 if (reg == &ia32_gp_regs[REG_GP_UKNWN]) {
148 const arch_register_req_t *req = arch_get_register_req(irn, pos);
150 if (arch_register_req_is(req, limited)) {
151 /* in case of limited requirements: get the first allowed register */
152 unsigned idx = rbitset_next(req->limited, 0, 1);
153 reg = arch_register_for_index(req->cls, idx);
155 /* otherwise get first register in class */
156 reg = arch_register_for_index(req->cls, 0);
164 * Returns the register at out position pos.
166 static const arch_register_t *get_out_reg(const ir_node *irn, int pos)
169 const arch_register_t *reg = NULL;
171 /* 1st case: irn is not of mode_T, so it has only */
172 /* one OUT register -> good */
173 /* 2nd case: irn is of mode_T -> collect all Projs and ask the */
174 /* Proj with the corresponding projnum for the register */
176 if (get_irn_mode(irn) != mode_T) {
178 reg = arch_get_irn_register(irn);
179 } else if (is_ia32_irn(irn)) {
180 reg = arch_irn_get_register(irn, pos);
182 const ir_edge_t *edge;
184 foreach_out_edge(irn, edge) {
185 proj = get_edge_src_irn(edge);
186 assert(is_Proj(proj) && "non-Proj from mode_T node");
187 if (get_Proj_proj(proj) == pos) {
188 reg = arch_get_irn_register(proj);
194 assert(reg && "no out register found");
199 * Add a number to a prefix. This number will not be used a second time.
201 static char *get_unique_label(char *buf, size_t buflen, const char *prefix)
203 static unsigned long id = 0;
204 snprintf(buf, buflen, "%s%lu", prefix, ++id);
208 /*************************************************************
210 * (_) | | / _| | | | |
211 * _ __ _ __ _ _ __ | |_| |_ | |__ ___| |_ __ ___ _ __
212 * | '_ \| '__| | '_ \| __| _| | '_ \ / _ \ | '_ \ / _ \ '__|
213 * | |_) | | | | | | | |_| | | | | | __/ | |_) | __/ |
214 * | .__/|_| |_|_| |_|\__|_| |_| |_|\___|_| .__/ \___|_|
217 *************************************************************/
220 * Emit the name of the 8bit low register
222 static void emit_8bit_register(const arch_register_t *reg)
224 const char *reg_name = arch_register_get_name(reg);
227 be_emit_char(reg_name[1]);
232 * Emit the name of the 8bit high register
234 static void emit_8bit_register_high(const arch_register_t *reg)
236 const char *reg_name = arch_register_get_name(reg);
239 be_emit_char(reg_name[1]);
243 static void emit_16bit_register(const arch_register_t *reg)
245 const char *reg_name = ia32_get_mapped_reg_name(isa->regs_16bit, reg);
248 be_emit_string(reg_name);
252 * emit a register, possible shortened by a mode
254 * @param reg the register
255 * @param mode the mode of the register or NULL for full register
257 static void emit_register(const arch_register_t *reg, const ir_mode *mode)
259 const char *reg_name;
262 int size = get_mode_size_bits(mode);
264 case 8: emit_8bit_register(reg); return;
265 case 16: emit_16bit_register(reg); return;
267 assert(mode_is_float(mode) || size == 32);
270 reg_name = arch_register_get_name(reg);
273 be_emit_string(reg_name);
276 void ia32_emit_source_register(const ir_node *node, int pos)
278 const arch_register_t *reg = get_in_reg(node, pos);
280 emit_register(reg, NULL);
283 static void ia32_emit_entity(ir_entity *entity, int no_pic_adjust)
285 set_entity_backend_marked(entity, 1);
286 be_gas_emit_entity(entity);
288 if (get_entity_owner(entity) == get_tls_type()) {
289 if (get_entity_visibility(entity) == visibility_external_allocated) {
290 be_emit_cstring("@INDNTPOFF");
292 be_emit_cstring("@NTPOFF");
296 if (do_pic && !no_pic_adjust) {
298 be_emit_string(pic_base_label);
302 static void emit_ia32_Immediate_no_prefix(const ir_node *node)
304 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(node);
306 if (attr->symconst != NULL) {
309 ia32_emit_entity(attr->symconst, attr->no_pic_adjust);
311 if (attr->symconst == NULL || attr->offset != 0) {
312 if (attr->symconst != NULL) {
313 be_emit_irprintf("%+d", attr->offset);
315 be_emit_irprintf("0x%X", attr->offset);
320 static void emit_ia32_Immediate(const ir_node *node)
323 emit_ia32_Immediate_no_prefix(node);
326 void ia32_emit_8bit_source_register_or_immediate(const ir_node *node, int pos)
328 const arch_register_t *reg;
329 const ir_node *in = get_irn_n(node, pos);
330 if (is_ia32_Immediate(in)) {
331 emit_ia32_Immediate(in);
335 reg = get_in_reg(node, pos);
336 emit_8bit_register(reg);
339 void ia32_emit_8bit_high_source_register(const ir_node *node, int pos)
341 const arch_register_t *reg = get_in_reg(node, pos);
342 emit_8bit_register_high(reg);
345 void ia32_emit_16bit_source_register_or_immediate(const ir_node *node, int pos)
347 const arch_register_t *reg;
348 const ir_node *in = get_irn_n(node, pos);
349 if (is_ia32_Immediate(in)) {
350 emit_ia32_Immediate(in);
354 reg = get_in_reg(node, pos);
355 emit_16bit_register(reg);
358 void ia32_emit_dest_register(const ir_node *node, int pos)
360 const arch_register_t *reg = get_out_reg(node, pos);
362 emit_register(reg, NULL);
365 void ia32_emit_dest_register_size(const ir_node *node, int pos)
367 const arch_register_t *reg = get_out_reg(node, pos);
369 emit_register(reg, get_ia32_ls_mode(node));
372 void ia32_emit_8bit_dest_register(const ir_node *node, int pos)
374 const arch_register_t *reg = get_out_reg(node, pos);
376 emit_register(reg, mode_Bu);
379 void ia32_emit_x87_register(const ir_node *node, int pos)
381 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
385 be_emit_string(attr->x87[pos]->name);
388 static void ia32_emit_mode_suffix_mode(const ir_mode *mode)
390 assert(mode_is_int(mode) || mode_is_reference(mode));
391 switch (get_mode_size_bits(mode)) {
392 case 8: be_emit_char('b'); return;
393 case 16: be_emit_char('w'); return;
394 case 32: be_emit_char('l'); return;
395 /* gas docu says q is the suffix but gcc, objdump and icc use ll
397 case 64: be_emit_cstring("ll"); return;
399 panic("Can't output mode_suffix for %+F", mode);
402 void ia32_emit_mode_suffix(const ir_node *node)
404 ir_mode *mode = get_ia32_ls_mode(node);
408 ia32_emit_mode_suffix_mode(mode);
411 void ia32_emit_x87_mode_suffix(const ir_node *node)
415 /* we only need to emit the mode on address mode */
416 if (get_ia32_op_type(node) == ia32_Normal)
419 mode = get_ia32_ls_mode(node);
420 assert(mode != NULL);
422 if (mode_is_float(mode)) {
423 switch (get_mode_size_bits(mode)) {
424 case 32: be_emit_char('s'); return;
425 case 64: be_emit_char('l'); return;
427 case 96: be_emit_char('t'); return;
430 assert(mode_is_int(mode));
431 switch (get_mode_size_bits(mode)) {
432 case 16: be_emit_char('s'); return;
433 case 32: be_emit_char('l'); return;
434 /* gas docu says q is the suffix but gcc, objdump and icc use ll
436 case 64: be_emit_cstring("ll"); return;
439 panic("Can't output mode_suffix for %+F", mode);
442 static char get_xmm_mode_suffix(ir_mode *mode)
444 assert(mode_is_float(mode));
445 switch(get_mode_size_bits(mode)) {
448 default: panic("Invalid XMM mode");
452 void ia32_emit_xmm_mode_suffix(const ir_node *node)
454 ir_mode *mode = get_ia32_ls_mode(node);
455 assert(mode != NULL);
457 be_emit_char(get_xmm_mode_suffix(mode));
460 void ia32_emit_xmm_mode_suffix_s(const ir_node *node)
462 ir_mode *mode = get_ia32_ls_mode(node);
463 assert(mode != NULL);
464 be_emit_char(get_xmm_mode_suffix(mode));
467 void ia32_emit_extend_suffix(const ir_node *node)
469 ir_mode *mode = get_ia32_ls_mode(node);
470 if (get_mode_size_bits(mode) == 32)
472 be_emit_char(mode_is_signed(mode) ? 's' : 'z');
473 ia32_emit_mode_suffix_mode(mode);
476 void ia32_emit_source_register_or_immediate(const ir_node *node, int pos)
478 ir_node *in = get_irn_n(node, pos);
479 if (is_ia32_Immediate(in)) {
480 emit_ia32_Immediate(in);
482 const ir_mode *mode = get_ia32_ls_mode(node);
483 const arch_register_t *reg = get_in_reg(node, pos);
484 emit_register(reg, mode);
489 * Returns the target block for a control flow node.
491 static ir_node *get_cfop_target_block(const ir_node *irn)
493 assert(get_irn_mode(irn) == mode_X);
494 return get_irn_link(irn);
498 * Emits a block label for the given block.
500 static void ia32_emit_block_name(const ir_node *block)
502 if (has_Block_entity(block)) {
503 ir_entity *entity = get_Block_entity(block);
504 be_gas_emit_entity(entity);
506 be_emit_cstring(BLOCK_PREFIX);
507 be_emit_irprintf("%ld", get_irn_node_nr(block));
512 * Emits the target label for a control flow node.
514 static void ia32_emit_cfop_target(const ir_node *node)
516 ir_node *block = get_cfop_target_block(node);
517 ia32_emit_block_name(block);
521 * positive conditions for signed compares
523 static const char *const cmp2condition_s[] = {
524 NULL, /* always false */
531 NULL /* always true */
535 * positive conditions for unsigned compares
537 static const char *const cmp2condition_u[] = {
538 NULL, /* always false */
545 NULL /* always true */
549 * Emit the suffix for a compare instruction.
551 static void ia32_emit_cmp_suffix(int pnc)
555 if (pnc == ia32_pn_Cmp_parity) {
559 if (pnc & ia32_pn_Cmp_float || pnc & ia32_pn_Cmp_unsigned) {
560 str = cmp2condition_u[pnc & 7];
562 str = cmp2condition_s[pnc & 7];
568 typedef enum ia32_emit_mod_t {
569 EMIT_RESPECT_LS = 1U << 0,
570 EMIT_ALTERNATE_AM = 1U << 1,
575 * Emits address mode.
577 void ia32_emit_am(const ir_node *node)
579 ir_entity *ent = get_ia32_am_sc(node);
580 int offs = get_ia32_am_offs_int(node);
581 ir_node *base = get_irn_n(node, n_ia32_base);
582 int has_base = !is_ia32_NoReg_GP(base);
583 ir_node *index = get_irn_n(node, n_ia32_index);
584 int has_index = !is_ia32_NoReg_GP(index);
586 /* just to be sure... */
587 assert(!is_ia32_use_frame(node) || get_ia32_frame_ent(node) != NULL);
591 const ia32_attr_t *attr = get_ia32_attr_const(node);
592 if (is_ia32_am_sc_sign(node))
594 ia32_emit_entity(ent, attr->data.am_sc_no_pic_adjust);
597 /* also handle special case if nothing is set */
598 if (offs != 0 || (ent == NULL && !has_base && !has_index)) {
600 be_emit_irprintf("%+d", offs);
602 be_emit_irprintf("%d", offs);
606 if (has_base || has_index) {
611 const arch_register_t *reg = get_in_reg(node, n_ia32_base);
612 emit_register(reg, NULL);
615 /* emit index + scale */
617 const arch_register_t *reg = get_in_reg(node, n_ia32_index);
620 emit_register(reg, NULL);
622 scale = get_ia32_am_scale(node);
624 be_emit_irprintf(",%d", 1 << scale);
632 * fmt parameter output
633 * ---- ---------------------- ---------------------------------------------
635 * %AM <node> address mode of the node
636 * %AR const arch_register_t* address mode of the node or register
637 * %ASx <node> address mode of the node or source register x
638 * %Dx <node> destination register x
639 * %I <node> immediate of the node
640 * %L <node> control flow target of the node
641 * %M <node> mode suffix of the node
642 * %P int condition code
643 * %R const arch_register_t* register
644 * %Sx <node> source register x
645 * %s const char* string
646 * %u unsigned int unsigned int
647 * %d signed int signed int
650 * # modifier for %ASx, %D and %S uses ls mode of node to alter register width
651 * * modifier does not prefix immediates with $, but AM with *
652 * l modifier for %lu and %ld
654 static void ia32_emitf(const ir_node *node, const char *fmt, ...)
660 const char *start = fmt;
661 ia32_emit_mod_t mod = 0;
663 while (*fmt != '%' && *fmt != '\n' && *fmt != '\0')
666 be_emit_string_len(start, fmt - start);
670 be_emit_finish_line_gas(node);
682 mod |= EMIT_ALTERNATE_AM;
687 mod |= EMIT_RESPECT_LS;
704 if (mod & EMIT_ALTERNATE_AM)
711 const arch_register_t *reg = va_arg(ap, const arch_register_t*);
712 if (mod & EMIT_ALTERNATE_AM)
714 if (get_ia32_op_type(node) == ia32_AddrModeS) {
717 emit_register(reg, NULL);
723 if (get_ia32_op_type(node) == ia32_AddrModeS) {
724 if (mod & EMIT_ALTERNATE_AM)
729 assert(get_ia32_op_type(node) == ia32_Normal);
734 default: goto unknown;
741 const arch_register_t *reg;
743 if (*fmt < '0' || '9' <= *fmt)
747 reg = get_out_reg(node, pos);
748 emit_register(reg, mod & EMIT_RESPECT_LS ? get_ia32_ls_mode(node) : NULL);
753 if (!(mod & EMIT_ALTERNATE_AM))
755 emit_ia32_Immediate_no_prefix(node);
759 ia32_emit_cfop_target(node);
763 ia32_emit_mode_suffix_mode(get_ia32_ls_mode(node));
768 int pnc = va_arg(ap, int);
769 ia32_emit_cmp_suffix(pnc);
774 const arch_register_t *reg = va_arg(ap, const arch_register_t*);
775 emit_register(reg, NULL);
784 if (*fmt < '0' || '9' <= *fmt)
788 in = get_irn_n(node, pos);
789 if (is_ia32_Immediate(in)) {
790 if (!(mod & EMIT_ALTERNATE_AM))
792 emit_ia32_Immediate_no_prefix(in);
794 const arch_register_t *reg;
796 if (mod & EMIT_ALTERNATE_AM)
798 reg = get_in_reg(node, pos);
799 emit_register(reg, mod & EMIT_RESPECT_LS ? get_ia32_ls_mode(node) : NULL);
805 const char *str = va_arg(ap, const char*);
811 if (mod & EMIT_LONG) {
812 unsigned long num = va_arg(ap, unsigned long);
813 be_emit_irprintf("%lu", num);
815 unsigned num = va_arg(ap, unsigned);
816 be_emit_irprintf("%u", num);
821 if (mod & EMIT_LONG) {
822 long num = va_arg(ap, long);
823 be_emit_irprintf("%ld", num);
825 int num = va_arg(ap, int);
826 be_emit_irprintf("%d", num);
832 panic("unknown format conversion in ia32_emitf()");
840 * Emits registers and/or address mode of a binary operation.
842 void ia32_emit_binop(const ir_node *node)
844 if (is_ia32_Immediate(get_irn_n(node, n_ia32_binary_right))) {
845 ia32_emitf(node, "%#S4, %#AS3");
847 ia32_emitf(node, "%#AS4, %#S3");
852 * Emits registers and/or address mode of a binary operation.
854 void ia32_emit_x87_binop(const ir_node *node)
856 switch(get_ia32_op_type(node)) {
859 const ia32_x87_attr_t *x87_attr = get_ia32_x87_attr_const(node);
860 const arch_register_t *in1 = x87_attr->x87[0];
861 const arch_register_t *in = x87_attr->x87[1];
862 const arch_register_t *out = x87_attr->x87[2];
866 } else if (out == in) {
871 be_emit_string(arch_register_get_name(in));
872 be_emit_cstring(", %");
873 be_emit_string(arch_register_get_name(out));
881 assert(0 && "unsupported op type");
886 * Emits registers and/or address mode of a unary operation.
888 void ia32_emit_unop(const ir_node *node, int pos)
892 ia32_emitf(node, fmt);
895 static void emit_ia32_IMul(const ir_node *node)
897 ir_node *left = get_irn_n(node, n_ia32_IMul_left);
898 const arch_register_t *out_reg = get_out_reg(node, pn_ia32_IMul_res);
900 /* do we need the 3-address form? */
901 if (is_ia32_NoReg_GP(left) ||
902 get_in_reg(node, n_ia32_IMul_left) != out_reg) {
903 ia32_emitf(node, "\timul%M %#S4, %#AS3, %#D0\n");
905 ia32_emitf(node, "\timul%M %#AS4, %#S3\n");
910 * walks up a tree of copies/perms/spills/reloads to find the original value
911 * that is moved around
913 static ir_node *find_original_value(ir_node *node)
915 if (irn_visited(node))
918 mark_irn_visited(node);
919 if (be_is_Copy(node)) {
920 return find_original_value(be_get_Copy_op(node));
921 } else if (be_is_CopyKeep(node)) {
922 return find_original_value(be_get_CopyKeep_op(node));
923 } else if (is_Proj(node)) {
924 ir_node *pred = get_Proj_pred(node);
925 if (be_is_Perm(pred)) {
926 return find_original_value(get_irn_n(pred, get_Proj_proj(node)));
927 } else if (be_is_MemPerm(pred)) {
928 return find_original_value(get_irn_n(pred, get_Proj_proj(node) + 1));
929 } else if (is_ia32_Load(pred)) {
930 return find_original_value(get_irn_n(pred, n_ia32_Load_mem));
934 } else if (is_ia32_Store(node)) {
935 return find_original_value(get_irn_n(node, n_ia32_Store_val));
936 } else if (is_Phi(node)) {
938 arity = get_irn_arity(node);
939 for (i = 0; i < arity; ++i) {
940 ir_node *in = get_irn_n(node, i);
941 ir_node *res = find_original_value(in);
952 static int determine_final_pnc(const ir_node *node, int flags_pos,
955 ir_node *flags = get_irn_n(node, flags_pos);
956 const ia32_attr_t *flags_attr;
957 flags = skip_Proj(flags);
959 if (is_ia32_Sahf(flags)) {
960 ir_node *cmp = get_irn_n(flags, n_ia32_Sahf_val);
961 if (!(is_ia32_FucomFnstsw(cmp) || is_ia32_FucompFnstsw(cmp)
962 || is_ia32_FucomppFnstsw(cmp) || is_ia32_FtstFnstsw(cmp))) {
963 inc_irg_visited(current_ir_graph);
964 cmp = find_original_value(cmp);
966 assert(is_ia32_FucomFnstsw(cmp) || is_ia32_FucompFnstsw(cmp)
967 || is_ia32_FucomppFnstsw(cmp) || is_ia32_FtstFnstsw(cmp));
970 flags_attr = get_ia32_attr_const(cmp);
971 if (flags_attr->data.ins_permuted)
972 pnc = get_mirrored_pnc(pnc);
973 pnc |= ia32_pn_Cmp_float;
974 } else if (is_ia32_Ucomi(flags) || is_ia32_Fucomi(flags)
975 || is_ia32_Fucompi(flags)) {
976 flags_attr = get_ia32_attr_const(flags);
978 if (flags_attr->data.ins_permuted)
979 pnc = get_mirrored_pnc(pnc);
980 pnc |= ia32_pn_Cmp_float;
982 flags_attr = get_ia32_attr_const(flags);
984 if (flags_attr->data.ins_permuted)
985 pnc = get_mirrored_pnc(pnc);
986 if (flags_attr->data.cmp_unsigned)
987 pnc |= ia32_pn_Cmp_unsigned;
993 static pn_Cmp ia32_get_negated_pnc(pn_Cmp pnc)
995 ir_mode *mode = pnc & ia32_pn_Cmp_float ? mode_F : mode_Iu;
996 return get_negated_pnc(pnc, mode);
999 void ia32_emit_cmp_suffix_node(const ir_node *node,
1002 const ia32_attr_t *attr = get_ia32_attr_const(node);
1004 pn_Cmp pnc = get_ia32_condcode(node);
1006 pnc = determine_final_pnc(node, flags_pos, pnc);
1007 if (attr->data.ins_permuted)
1008 pnc = ia32_get_negated_pnc(pnc);
1010 ia32_emit_cmp_suffix(pnc);
1014 * Emits an exception label for a given node.
1016 static void ia32_emit_exc_label(const ir_node *node)
1018 be_emit_string(be_gas_insn_label_prefix());
1019 be_emit_irprintf("%lu", get_ia32_exc_label_id(node));
1023 * Returns the Proj with projection number proj and NOT mode_M
1025 static ir_node *get_proj(const ir_node *node, long proj)
1027 const ir_edge_t *edge;
1030 assert(get_irn_mode(node) == mode_T && "expected mode_T node");
1032 foreach_out_edge(node, edge) {
1033 src = get_edge_src_irn(edge);
1035 assert(is_Proj(src) && "Proj expected");
1036 if (get_irn_mode(src) == mode_M)
1039 if (get_Proj_proj(src) == proj)
1045 static int can_be_fallthrough(const ir_node *node)
1047 ir_node *target_block = get_cfop_target_block(node);
1048 ir_node *block = get_nodes_block(node);
1049 return get_prev_block_sched(target_block) == block;
1053 * Emits the jump sequence for a conditional jump (cmp + jmp_true + jmp_false)
1055 static void emit_ia32_Jcc(const ir_node *node)
1057 int need_parity_label = 0;
1058 const ir_node *proj_true;
1059 const ir_node *proj_false;
1060 const ir_node *block;
1061 pn_Cmp pnc = get_ia32_condcode(node);
1063 pnc = determine_final_pnc(node, 0, pnc);
1065 /* get both Projs */
1066 proj_true = get_proj(node, pn_ia32_Jcc_true);
1067 assert(proj_true && "Jcc without true Proj");
1069 proj_false = get_proj(node, pn_ia32_Jcc_false);
1070 assert(proj_false && "Jcc without false Proj");
1072 block = get_nodes_block(node);
1074 if (can_be_fallthrough(proj_true)) {
1075 /* exchange both proj's so the second one can be omitted */
1076 const ir_node *t = proj_true;
1078 proj_true = proj_false;
1080 pnc = ia32_get_negated_pnc(pnc);
1083 if (pnc & ia32_pn_Cmp_float) {
1084 /* Some floating point comparisons require a test of the parity flag,
1085 * which indicates that the result is unordered */
1088 ia32_emitf(proj_true, "\tjp %L\n");
1093 ia32_emitf(proj_true, "\tjnp %L\n");
1099 /* we need a local label if the false proj is a fallthrough
1100 * as the falseblock might have no label emitted then */
1101 if (can_be_fallthrough(proj_false)) {
1102 need_parity_label = 1;
1103 ia32_emitf(proj_false, "\tjp 1f\n");
1105 ia32_emitf(proj_false, "\tjp %L\n");
1112 ia32_emitf(proj_true, "\tjp %L\n");
1120 ia32_emitf(proj_true, "\tj%P %L\n", pnc);
1123 if (need_parity_label) {
1124 ia32_emitf(NULL, "1:\n");
1127 /* the second Proj might be a fallthrough */
1128 if (can_be_fallthrough(proj_false)) {
1129 ia32_emitf(proj_false, "\t/* fallthrough to %L */\n");
1131 ia32_emitf(proj_false, "\tjmp %L\n");
1135 static void emit_ia32_CMov(const ir_node *node)
1137 const ia32_attr_t *attr = get_ia32_attr_const(node);
1138 int ins_permuted = attr->data.ins_permuted;
1139 const arch_register_t *out = arch_irn_get_register(node, pn_ia32_res);
1140 pn_Cmp pnc = get_ia32_condcode(node);
1141 const arch_register_t *in_true;
1142 const arch_register_t *in_false;
1144 pnc = determine_final_pnc(node, n_ia32_CMov_eflags, pnc);
1146 in_true = arch_get_irn_register(get_irn_n(node, n_ia32_CMov_val_true));
1147 in_false = arch_get_irn_register(get_irn_n(node, n_ia32_CMov_val_false));
1149 /* should be same constraint fullfilled? */
1150 if (out == in_false) {
1151 /* yes -> nothing to do */
1152 } else if (out == in_true) {
1153 const arch_register_t *tmp;
1155 assert(get_ia32_op_type(node) == ia32_Normal);
1157 ins_permuted = !ins_permuted;
1164 ia32_emitf(node, "\tmovl %R, %R\n", in_false, out);
1168 pnc = ia32_get_negated_pnc(pnc);
1170 /* TODO: handling of Nans isn't correct yet */
1172 ia32_emitf(node, "\tcmov%P %#AR, %#R\n", pnc, in_true, out);
1175 /*********************************************************
1178 * ___ _ __ ___ _| |_ _ _ _ _ __ ___ _ __ ___
1179 * / _ \ '_ ` _ \| | __| | | | | | '_ ` _ \| '_ \/ __|
1180 * | __/ | | | | | | |_ | | |_| | | | | | | |_) \__ \
1181 * \___|_| |_| |_|_|\__| | |\__,_|_| |_| |_| .__/|___/
1184 *********************************************************/
1186 /* jump table entry (target and corresponding number) */
1187 typedef struct _branch_t {
1192 /* jump table for switch generation */
1193 typedef struct _jmp_tbl_t {
1194 ir_node *defProj; /**< default target */
1195 long min_value; /**< smallest switch case */
1196 long max_value; /**< largest switch case */
1197 long num_branches; /**< number of jumps */
1198 char label[SNPRINTF_BUF_LEN]; /**< label of the jump table */
1199 branch_t *branches; /**< jump array */
1203 * Compare two variables of type branch_t. Used to sort all switch cases
1205 static int ia32_cmp_branch_t(const void *a, const void *b)
1207 branch_t *b1 = (branch_t *)a;
1208 branch_t *b2 = (branch_t *)b;
1210 if (b1->value <= b2->value)
1216 static void generate_jump_table(jmp_tbl_t *tbl, const ir_node *node)
1222 const ir_edge_t *edge;
1224 /* fill the table structure */
1225 get_unique_label(tbl->label, SNPRINTF_BUF_LEN, ".TBL_");
1226 tbl->defProj = NULL;
1227 tbl->num_branches = get_irn_n_edges(node) - 1;
1228 tbl->branches = XMALLOCNZ(branch_t, tbl->num_branches);
1229 tbl->min_value = INT_MAX;
1230 tbl->max_value = INT_MIN;
1232 default_pn = get_ia32_condcode(node);
1234 /* go over all proj's and collect them */
1235 foreach_out_edge(node, edge) {
1236 proj = get_edge_src_irn(edge);
1237 assert(is_Proj(proj) && "Only proj allowed at SwitchJmp");
1239 pnc = get_Proj_proj(proj);
1241 /* check for default proj */
1242 if (pnc == default_pn) {
1243 assert(tbl->defProj == NULL && "found two default Projs at SwitchJmp");
1244 tbl->defProj = proj;
1246 tbl->min_value = pnc < tbl->min_value ? pnc : tbl->min_value;
1247 tbl->max_value = pnc > tbl->max_value ? pnc : tbl->max_value;
1249 /* create branch entry */
1250 tbl->branches[i].target = proj;
1251 tbl->branches[i].value = pnc;
1256 assert(i == tbl->num_branches);
1258 /* sort the branches by their number */
1259 qsort(tbl->branches, tbl->num_branches, sizeof(tbl->branches[0]), ia32_cmp_branch_t);
1263 * Emits code for a SwitchJmp (creates a jump table if
1264 * possible otherwise a cmp-jmp cascade). Port from
1267 static void emit_ia32_SwitchJmp(const ir_node *node)
1269 unsigned long interval;
1273 /* fill the table structure */
1274 generate_jump_table(&tbl, node);
1276 /* two-complement's magic make this work without overflow */
1277 interval = tbl.max_value - tbl.min_value;
1279 /* emit the table */
1280 ia32_emitf(node, "\tcmpl $%u, %S0\n", interval);
1281 ia32_emitf(tbl.defProj, "\tja %L\n");
1283 if (tbl.num_branches > 1) {
1285 ia32_emitf(node, "\tjmp *%s(,%S0,4)\n", tbl.label);
1287 be_gas_emit_switch_section(GAS_SECTION_RODATA);
1288 ia32_emitf(NULL, "\t.align 4\n");
1289 ia32_emitf(NULL, "%s:\n", tbl.label);
1291 last_value = tbl.branches[0].value;
1292 for (i = 0; i != tbl.num_branches; ++i) {
1293 while (last_value != tbl.branches[i].value) {
1294 ia32_emitf(tbl.defProj, ".long %L\n");
1297 ia32_emitf(tbl.branches[i].target, ".long %L\n");
1300 be_gas_emit_switch_section(GAS_SECTION_TEXT);
1302 /* one jump is enough */
1303 ia32_emitf(tbl.branches[0].target, "\tjmp %L\n");
1310 * Emits code for a unconditional jump.
1312 static void emit_ia32_Jmp(const ir_node *node)
1316 /* for now, the code works for scheduled and non-schedules blocks */
1317 block = get_nodes_block(node);
1319 /* we have a block schedule */
1320 if (can_be_fallthrough(node)) {
1321 ia32_emitf(node, "\t/* fallthrough to %L */\n");
1323 ia32_emitf(node, "\tjmp %L\n");
1328 * Emit an inline assembler operand.
1330 * @param node the ia32_ASM node
1331 * @param s points to the operand (a %c)
1333 * @return pointer to the first char in s NOT in the current operand
1335 static const char* emit_asm_operand(const ir_node *node, const char *s)
1337 const ia32_attr_t *ia32_attr = get_ia32_attr_const(node);
1338 const ia32_asm_attr_t *attr = CONST_CAST_IA32_ATTR(ia32_asm_attr_t,
1340 const arch_register_t *reg;
1341 const ia32_asm_reg_t *asm_regs = attr->register_map;
1342 const ia32_asm_reg_t *asm_reg;
1343 const char *reg_name;
1352 /* parse modifiers */
1355 ir_fprintf(stderr, "Warning: asm text (%+F) ends with %%\n", node);
1380 "Warning: asm text (%+F) contains unknown modifier '%c' for asm op\n",
1387 sscanf(s, "%d%n", &num, &p);
1389 ir_fprintf(stderr, "Warning: Couldn't parse assembler operand (%+F)\n",
1396 if (num < 0 || ARR_LEN(asm_regs) <= num) {
1398 "Error: Custom assembler references invalid input/output (%+F)\n",
1402 asm_reg = & asm_regs[num];
1403 assert(asm_reg->valid);
1406 if (asm_reg->use_input == 0) {
1407 reg = get_out_reg(node, asm_reg->inout_pos);
1409 ir_node *pred = get_irn_n(node, asm_reg->inout_pos);
1411 /* might be an immediate value */
1412 if (is_ia32_Immediate(pred)) {
1413 emit_ia32_Immediate(pred);
1416 reg = get_in_reg(node, asm_reg->inout_pos);
1420 "Warning: no register assigned for %d asm op (%+F)\n",
1425 if (asm_reg->memory) {
1430 if (modifier != 0) {
1434 reg_name = ia32_get_mapped_reg_name(isa->regs_8bit, reg);
1437 reg_name = ia32_get_mapped_reg_name(isa->regs_8bit_high, reg);
1440 reg_name = ia32_get_mapped_reg_name(isa->regs_16bit, reg);
1443 panic("Invalid asm op modifier");
1445 be_emit_string(reg_name);
1447 emit_register(reg, asm_reg->mode);
1450 if (asm_reg->memory) {
1458 * Emits code for an ASM pseudo op.
1460 static void emit_ia32_Asm(const ir_node *node)
1462 const void *gen_attr = get_irn_generic_attr_const(node);
1463 const ia32_asm_attr_t *attr
1464 = CONST_CAST_IA32_ATTR(ia32_asm_attr_t, gen_attr);
1465 ident *asm_text = attr->asm_text;
1466 const char *s = get_id_str(asm_text);
1468 ia32_emitf(node, "#APP\t\n");
1475 s = emit_asm_operand(node, s);
1481 ia32_emitf(NULL, "\n#NO_APP\n");
1484 /**********************************
1487 * | | ___ _ __ _ _| |_) |
1488 * | | / _ \| '_ \| | | | _ <
1489 * | |___| (_) | |_) | |_| | |_) |
1490 * \_____\___/| .__/ \__, |____/
1493 **********************************/
1496 * Emit movsb/w instructions to make mov count divideable by 4
1498 static void emit_CopyB_prolog(unsigned size)
1501 ia32_emitf(NULL, "\tmovsb\n");
1503 ia32_emitf(NULL, "\tmovsw\n");
1507 * Emit rep movsd instruction for memcopy.
1509 static void emit_ia32_CopyB(const ir_node *node)
1511 unsigned size = get_ia32_copyb_size(node);
1513 emit_CopyB_prolog(size);
1514 ia32_emitf(node, "\trep movsd\n");
1518 * Emits unrolled memcopy.
1520 static void emit_ia32_CopyB_i(const ir_node *node)
1522 unsigned size = get_ia32_copyb_size(node);
1524 emit_CopyB_prolog(size);
1528 ia32_emitf(NULL, "\tmovsd\n");
1534 /***************************
1538 * | | / _ \| '_ \ \ / /
1539 * | |___| (_) | | | \ V /
1540 * \_____\___/|_| |_|\_/
1542 ***************************/
1545 * Emit code for conversions (I, FP), (FP, I) and (FP, FP).
1547 static void emit_ia32_Conv_with_FP(const ir_node *node, const char* conv_f,
1550 ir_mode *ls_mode = get_ia32_ls_mode(node);
1551 int ls_bits = get_mode_size_bits(ls_mode);
1552 const char *conv = ls_bits == 32 ? conv_f : conv_d;
1554 ia32_emitf(node, "\tcvt%s %AS3, %D0\n", conv);
1557 static void emit_ia32_Conv_I2FP(const ir_node *node)
1559 emit_ia32_Conv_with_FP(node, "si2ss", "si2sd");
1562 static void emit_ia32_Conv_FP2I(const ir_node *node)
1564 emit_ia32_Conv_with_FP(node, "ss2si", "sd2si");
1567 static void emit_ia32_Conv_FP2FP(const ir_node *node)
1569 emit_ia32_Conv_with_FP(node, "sd2ss", "ss2sd");
1573 * Emits code for an Int conversion.
1575 static void emit_ia32_Conv_I2I(const ir_node *node)
1577 ir_mode *smaller_mode = get_ia32_ls_mode(node);
1578 int signed_mode = mode_is_signed(smaller_mode);
1579 const char *sign_suffix;
1581 assert(!mode_is_float(smaller_mode));
1583 sign_suffix = signed_mode ? "s" : "z";
1584 ia32_emitf(node, "\tmov%s%Ml %#AS3, %D0\n", sign_suffix);
1590 static void emit_ia32_Call(const ir_node *node)
1592 /* Special case: Call must not have its immediates prefixed by $, instead
1593 * address mode is prefixed by *. */
1594 ia32_emitf(node, "\tcall %*AS3\n");
1598 /*******************************************
1601 * | |__ ___ _ __ ___ __| | ___ ___
1602 * | '_ \ / _ \ '_ \ / _ \ / _` |/ _ \/ __|
1603 * | |_) | __/ | | | (_) | (_| | __/\__ \
1604 * |_.__/ \___|_| |_|\___/ \__,_|\___||___/
1606 *******************************************/
1609 * Emits code to increase stack pointer.
1611 static void emit_be_IncSP(const ir_node *node)
1613 int offs = be_get_IncSP_offset(node);
1619 ia32_emitf(node, "\tsubl $%u, %D0\n", offs);
1621 ia32_emitf(node, "\taddl $%u, %D0\n", -offs);
1625 static inline bool is_unknown_reg(const arch_register_t *reg)
1627 if(reg == &ia32_gp_regs[REG_GP_UKNWN]
1628 || reg == &ia32_xmm_regs[REG_XMM_UKNWN]
1629 || reg == &ia32_vfp_regs[REG_VFP_UKNWN])
1636 * Emits code for Copy/CopyKeep.
1638 static void Copy_emitter(const ir_node *node, const ir_node *op)
1640 const arch_register_t *in = arch_get_irn_register(op);
1641 const arch_register_t *out = arch_get_irn_register(node);
1646 if (is_unknown_reg(in))
1648 /* copies of vf nodes aren't real... */
1649 if (arch_register_get_class(in) == &ia32_reg_classes[CLASS_ia32_vfp])
1652 if (get_irn_mode(node) == mode_E) {
1653 ia32_emitf(node, "\tmovsd %R, %R\n", in, out);
1655 ia32_emitf(node, "\tmovl %R, %R\n", in, out);
1659 static void emit_be_Copy(const ir_node *node)
1661 Copy_emitter(node, be_get_Copy_op(node));
1664 static void emit_be_CopyKeep(const ir_node *node)
1666 Copy_emitter(node, be_get_CopyKeep_op(node));
1670 * Emits code for exchange.
1672 static void emit_be_Perm(const ir_node *node)
1674 const arch_register_t *in0, *in1;
1675 const arch_register_class_t *cls0, *cls1;
1677 in0 = arch_get_irn_register(get_irn_n(node, 0));
1678 in1 = arch_get_irn_register(get_irn_n(node, 1));
1680 cls0 = arch_register_get_class(in0);
1681 cls1 = arch_register_get_class(in1);
1683 assert(cls0 == cls1 && "Register class mismatch at Perm");
1685 if (cls0 == &ia32_reg_classes[CLASS_ia32_gp]) {
1686 ia32_emitf(node, "\txchg %R, %R\n", in1, in0);
1687 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_xmm]) {
1688 ia32_emitf(NULL, "\txorpd %R, %R\n", in1, in0);
1689 ia32_emitf(NULL, "\txorpd %R, %R\n", in0, in1);
1690 ia32_emitf(node, "\txorpd %R, %R\n", in1, in0);
1691 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_vfp]) {
1693 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_st]) {
1696 panic("unexpected register class in be_Perm (%+F)", node);
1701 * Emits code for Constant loading.
1703 static void emit_ia32_Const(const ir_node *node)
1705 ia32_emitf(node, "\tmovl %I, %D0\n");
1709 * Emits code to load the TLS base
1711 static void emit_ia32_LdTls(const ir_node *node)
1713 ia32_emitf(node, "\tmovl %%gs:0, %D0\n");
1716 /* helper function for emit_ia32_Minus64Bit */
1717 static void emit_mov(const ir_node* node, const arch_register_t *src, const arch_register_t *dst)
1719 ia32_emitf(node, "\tmovl %R, %R\n", src, dst);
1722 /* helper function for emit_ia32_Minus64Bit */
1723 static void emit_neg(const ir_node* node, const arch_register_t *reg)
1725 ia32_emitf(node, "\tnegl %R\n", reg);
1728 /* helper function for emit_ia32_Minus64Bit */
1729 static void emit_sbb0(const ir_node* node, const arch_register_t *reg)
1731 ia32_emitf(node, "\tsbbl $0, %R\n", reg);
1734 /* helper function for emit_ia32_Minus64Bit */
1735 static void emit_sbb(const ir_node* node, const arch_register_t *src, const arch_register_t *dst)
1737 ia32_emitf(node, "\tsbbl %R, %R\n", src, dst);
1740 /* helper function for emit_ia32_Minus64Bit */
1741 static void emit_xchg(const ir_node* node, const arch_register_t *src, const arch_register_t *dst)
1743 ia32_emitf(node, "\txchgl %R, %R\n", src, dst);
1746 /* helper function for emit_ia32_Minus64Bit */
1747 static void emit_zero(const ir_node* node, const arch_register_t *reg)
1749 ia32_emitf(node, "\txorl %R, %R\n", reg, reg);
1752 static void emit_ia32_Minus64Bit(const ir_node *node)
1754 const arch_register_t *in_lo = get_in_reg(node, 0);
1755 const arch_register_t *in_hi = get_in_reg(node, 1);
1756 const arch_register_t *out_lo = get_out_reg(node, 0);
1757 const arch_register_t *out_hi = get_out_reg(node, 1);
1759 if (out_lo == in_lo) {
1760 if (out_hi != in_hi) {
1761 /* a -> a, b -> d */
1764 /* a -> a, b -> b */
1767 } else if (out_lo == in_hi) {
1768 if (out_hi == in_lo) {
1769 /* a -> b, b -> a */
1770 emit_xchg(node, in_lo, in_hi);
1773 /* a -> b, b -> d */
1774 emit_mov(node, in_hi, out_hi);
1775 emit_mov(node, in_lo, out_lo);
1779 if (out_hi == in_lo) {
1780 /* a -> c, b -> a */
1781 emit_mov(node, in_lo, out_lo);
1783 } else if (out_hi == in_hi) {
1784 /* a -> c, b -> b */
1785 emit_mov(node, in_lo, out_lo);
1788 /* a -> c, b -> d */
1789 emit_mov(node, in_lo, out_lo);
1795 emit_neg( node, out_hi);
1796 emit_neg( node, out_lo);
1797 emit_sbb0(node, out_hi);
1801 emit_zero(node, out_hi);
1802 emit_neg( node, out_lo);
1803 emit_sbb( node, in_hi, out_hi);
1806 static void emit_ia32_GetEIP(const ir_node *node)
1808 ia32_emitf(node, "\tcall %s\n", pic_base_label);
1809 ia32_emitf(NULL, "%s:\n", pic_base_label);
1810 ia32_emitf(node, "\tpopl %D0\n");
1813 static void emit_ia32_ClimbFrame(const ir_node *node)
1815 const ia32_climbframe_attr_t *attr = get_ia32_climbframe_attr_const(node);
1817 ia32_emitf(node, "\tmovl %S0, %D0\n");
1818 ia32_emitf(node, "\tmovl $%u, %S1\n", attr->count);
1819 ia32_emitf(NULL, BLOCK_PREFIX "%ld:\n", get_irn_node_nr(node));
1820 ia32_emitf(node, "\tmovl (%D0), %D0\n");
1821 ia32_emitf(node, "\tdec %S1\n");
1822 ia32_emitf(node, "\tjnz " BLOCK_PREFIX "%ld\n", get_irn_node_nr(node));
1825 static void emit_be_Return(const ir_node *node)
1827 unsigned pop = be_Return_get_pop(node);
1829 if (pop > 0 || be_Return_get_emit_pop(node)) {
1830 ia32_emitf(node, "\tret $%u\n", pop);
1832 ia32_emitf(node, "\tret\n");
1836 static void emit_Nothing(const ir_node *node)
1842 /***********************************************************************************
1845 * _ __ ___ __ _ _ _ __ | |_ _ __ __ _ _ __ ___ _____ _____ _ __| | __
1846 * | '_ ` _ \ / _` | | '_ \ | _| '__/ _` | '_ ` _ \ / _ \ \ /\ / / _ \| '__| |/ /
1847 * | | | | | | (_| | | | | | | | | | | (_| | | | | | | __/\ V V / (_) | | | <
1848 * |_| |_| |_|\__,_|_|_| |_| |_| |_| \__,_|_| |_| |_|\___| \_/\_/ \___/|_| |_|\_\
1850 ***********************************************************************************/
1853 * Enters the emitter functions for handled nodes into the generic
1854 * pointer of an opcode.
1856 static void ia32_register_emitters(void)
1858 #define IA32_EMIT2(a,b) op_ia32_##a->ops.generic = (op_func)emit_ia32_##b
1859 #define IA32_EMIT(a) IA32_EMIT2(a,a)
1860 #define EMIT(a) op_##a->ops.generic = (op_func)emit_##a
1861 #define IGN(a) op_##a->ops.generic = (op_func)emit_Nothing
1862 #define BE_EMIT(a) op_be_##a->ops.generic = (op_func)emit_be_##a
1863 #define BE_IGN(a) op_be_##a->ops.generic = (op_func)emit_Nothing
1865 /* first clear the generic function pointer for all ops */
1866 clear_irp_opcodes_generic_func();
1868 /* register all emitter functions defined in spec */
1869 ia32_register_spec_emitters();
1871 /* other ia32 emitter functions */
1872 IA32_EMIT2(Conv_I2I8Bit, Conv_I2I);
1877 IA32_EMIT(Conv_FP2FP);
1878 IA32_EMIT(Conv_FP2I);
1879 IA32_EMIT(Conv_I2FP);
1880 IA32_EMIT(Conv_I2I);
1887 IA32_EMIT(Minus64Bit);
1888 IA32_EMIT(SwitchJmp);
1889 IA32_EMIT(ClimbFrame);
1892 /* benode emitter */
1913 typedef void (*emit_func_ptr) (const ir_node *);
1916 * Assign and emit an exception label if the current instruction can fail.
1918 static void ia32_assign_exc_label(ir_node *node)
1920 /* assign a new ID to the instruction */
1921 set_ia32_exc_label_id(node, ++exc_label_id);
1923 ia32_emit_exc_label(node);
1925 be_emit_pad_comment();
1926 be_emit_cstring("/* exception to Block ");
1927 ia32_emit_cfop_target(node);
1928 be_emit_cstring(" */\n");
1929 be_emit_write_line();
1933 * Emits code for a node.
1935 static void ia32_emit_node(ir_node *node)
1937 ir_op *op = get_irn_op(node);
1939 DBG((dbg, LEVEL_1, "emitting code for %+F\n", node));
1941 if (is_ia32_irn(node)) {
1942 if (get_ia32_exc_label(node)) {
1943 /* emit the exception label of this instruction */
1944 ia32_assign_exc_label(node);
1946 if (mark_spill_reload) {
1947 if (is_ia32_is_spill(node)) {
1948 ia32_emitf(NULL, "\txchg %ebx, %ebx /* spill mark */\n");
1950 if (is_ia32_is_reload(node)) {
1951 ia32_emitf(NULL, "\txchg %edx, %edx /* reload mark */\n");
1953 if (is_ia32_is_remat(node)) {
1954 ia32_emitf(NULL, "\txchg %ecx, %ecx /* remat mark */\n");
1958 if (op->ops.generic) {
1959 emit_func_ptr func = (emit_func_ptr) op->ops.generic;
1961 be_dbg_set_dbg_info(get_irn_dbg_info(node));
1966 ir_fprintf(stderr, "Error: No emit handler for node %+F (%+G, graph %+F)\n", node, node, current_ir_graph);
1972 * Emits gas alignment directives
1974 static void ia32_emit_alignment(unsigned align, unsigned skip)
1976 ia32_emitf(NULL, "\t.p2align %u,,%u\n", align, skip);
1980 * Emits gas alignment directives for Labels depended on cpu architecture.
1982 static void ia32_emit_align_label(void)
1984 unsigned align = ia32_cg_config.label_alignment;
1985 unsigned maximum_skip = ia32_cg_config.label_alignment_max_skip;
1986 ia32_emit_alignment(align, maximum_skip);
1990 * Test whether a block should be aligned.
1991 * For cpus in the P4/Athlon class it is useful to align jump labels to
1992 * 16 bytes. However we should only do that if the alignment nops before the
1993 * label aren't executed more often than we have jumps to the label.
1995 static int should_align_block(const ir_node *block)
1997 static const double DELTA = .0001;
1998 ir_exec_freq *exec_freq = cg->birg->exec_freq;
1999 ir_node *prev = get_prev_block_sched(block);
2001 double prev_freq = 0; /**< execfreq of the fallthrough block */
2002 double jmp_freq = 0; /**< execfreq of all non-fallthrough blocks */
2005 if (exec_freq == NULL)
2007 if (ia32_cg_config.label_alignment_factor <= 0)
2010 block_freq = get_block_execfreq(exec_freq, block);
2011 if (block_freq < DELTA)
2014 n_cfgpreds = get_Block_n_cfgpreds(block);
2015 for(i = 0; i < n_cfgpreds; ++i) {
2016 const ir_node *pred = get_Block_cfgpred_block(block, i);
2017 double pred_freq = get_block_execfreq(exec_freq, pred);
2020 prev_freq += pred_freq;
2022 jmp_freq += pred_freq;
2026 if (prev_freq < DELTA && !(jmp_freq < DELTA))
2029 jmp_freq /= prev_freq;
2031 return jmp_freq > ia32_cg_config.label_alignment_factor;
2035 * Emit the block header for a block.
2037 * @param block the block
2038 * @param prev_block the previous block
2040 static void ia32_emit_block_header(ir_node *block)
2042 ir_graph *irg = current_ir_graph;
2043 int need_label = block_needs_label(block);
2045 ir_exec_freq *exec_freq = cg->birg->exec_freq;
2047 if (block == get_irg_end_block(irg))
2050 if (ia32_cg_config.label_alignment > 0) {
2051 /* align the current block if:
2052 * a) if should be aligned due to its execution frequency
2053 * b) there is no fall-through here
2055 if (should_align_block(block)) {
2056 ia32_emit_align_label();
2058 /* if the predecessor block has no fall-through,
2059 we can always align the label. */
2061 int has_fallthrough = 0;
2063 for (i = get_Block_n_cfgpreds(block) - 1; i >= 0; --i) {
2064 ir_node *cfg_pred = get_Block_cfgpred(block, i);
2065 if (can_be_fallthrough(cfg_pred)) {
2066 has_fallthrough = 1;
2071 if (!has_fallthrough)
2072 ia32_emit_align_label();
2077 ia32_emit_block_name(block);
2080 be_emit_pad_comment();
2081 be_emit_cstring(" /* ");
2083 be_emit_cstring("\t/* ");
2084 ia32_emit_block_name(block);
2085 be_emit_cstring(": ");
2088 be_emit_cstring("preds:");
2090 /* emit list of pred blocks in comment */
2091 arity = get_irn_arity(block);
2093 be_emit_cstring(" none");
2095 for (i = 0; i < arity; ++i) {
2096 ir_node *predblock = get_Block_cfgpred_block(block, i);
2097 be_emit_irprintf(" %d", get_irn_node_nr(predblock));
2100 if (exec_freq != NULL) {
2101 be_emit_irprintf(", freq: %f",
2102 get_block_execfreq(exec_freq, block));
2104 be_emit_cstring(" */\n");
2105 be_emit_write_line();
2109 * Walks over the nodes in a block connected by scheduling edges
2110 * and emits code for each node.
2112 static void ia32_gen_block(ir_node *block)
2116 ia32_emit_block_header(block);
2118 /* emit the contents of the block */
2119 be_dbg_set_dbg_info(get_irn_dbg_info(block));
2120 sched_foreach(block, node) {
2121 ia32_emit_node(node);
2125 typedef struct exc_entry {
2126 ir_node *exc_instr; /** The instruction that can issue an exception. */
2127 ir_node *block; /** The block to call then. */
2132 * Sets labels for control flow nodes (jump target).
2133 * Links control predecessors to there destination blocks.
2135 static void ia32_gen_labels(ir_node *block, void *data)
2137 exc_entry **exc_list = data;
2141 for (n = get_Block_n_cfgpreds(block) - 1; n >= 0; --n) {
2142 pred = get_Block_cfgpred(block, n);
2143 set_irn_link(pred, block);
2145 pred = skip_Proj(pred);
2146 if (is_ia32_irn(pred) && get_ia32_exc_label(pred)) {
2151 ARR_APP1(exc_entry, *exc_list, e);
2152 set_irn_link(pred, block);
2158 * Compare two exception_entries.
2160 static int cmp_exc_entry(const void *a, const void *b)
2162 const exc_entry *ea = a;
2163 const exc_entry *eb = b;
2165 if (get_ia32_exc_label_id(ea->exc_instr) < get_ia32_exc_label_id(eb->exc_instr))
2171 * Main driver. Emits the code for one routine.
2173 void ia32_gen_routine(ia32_code_gen_t *ia32_cg, ir_graph *irg)
2175 ir_entity *entity = get_irg_entity(irg);
2176 exc_entry *exc_list = NEW_ARR_F(exc_entry, 0);
2181 do_pic = cg->birg->main_env->options->pic;
2183 ia32_register_emitters();
2185 get_unique_label(pic_base_label, sizeof(pic_base_label), ".PIC_BASE");
2187 be_dbg_method_begin(entity, be_abi_get_stack_layout(cg->birg->abi));
2188 be_gas_emit_function_prolog(entity, ia32_cg_config.function_alignment);
2190 /* we use links to point to target blocks */
2191 ir_reserve_resources(irg, IR_RESOURCE_IRN_LINK);
2192 irg_block_walk_graph(irg, ia32_gen_labels, NULL, &exc_list);
2194 /* initialize next block links */
2195 n = ARR_LEN(cg->blk_sched);
2196 for (i = 0; i < n; ++i) {
2197 ir_node *block = cg->blk_sched[i];
2198 ir_node *prev = i > 0 ? cg->blk_sched[i-1] : NULL;
2200 set_irn_link(block, prev);
2203 for (i = 0; i < n; ++i) {
2204 ir_node *block = cg->blk_sched[i];
2206 ia32_gen_block(block);
2209 be_gas_emit_function_epilog(entity);
2210 be_dbg_method_end();
2212 be_emit_write_line();
2214 ir_free_resources(irg, IR_RESOURCE_IRN_LINK);
2216 /* Sort the exception table using the exception label id's.
2217 Those are ascending with ascending addresses. */
2218 qsort(exc_list, ARR_LEN(exc_list), sizeof(exc_list[0]), cmp_exc_entry);
2222 for (i = 0; i < ARR_LEN(exc_list); ++i) {
2223 be_emit_cstring("\t.long ");
2224 ia32_emit_exc_label(exc_list[i].exc_instr);
2226 be_emit_cstring("\t.long ");
2227 ia32_emit_block_name(exc_list[i].block);
2231 DEL_ARR_F(exc_list);
2234 static const lc_opt_table_entry_t ia32_emitter_options[] = {
2235 LC_OPT_ENT_BOOL("mark_spill_reload", "mark spills and reloads with ud opcodes", &mark_spill_reload),
2239 /* ==== Experimental binary emitter ==== */
2241 static unsigned char reg_gp_map[N_ia32_gp_REGS];
2242 static unsigned char reg_mmx_map[N_ia32_mmx_REGS];
2243 static unsigned char reg_sse_map[N_ia32_xmm_REGS];
2244 static unsigned char pnc_map_signed[8];
2245 static unsigned char pnc_map_unsigned[8];
2247 static void build_reg_map(void)
2249 reg_gp_map[REG_EAX] = 0x0;
2250 reg_gp_map[REG_ECX] = 0x1;
2251 reg_gp_map[REG_EDX] = 0x2;
2252 reg_gp_map[REG_EBX] = 0x3;
2253 reg_gp_map[REG_ESP] = 0x4;
2254 reg_gp_map[REG_EBP] = 0x5;
2255 reg_gp_map[REG_ESI] = 0x6;
2256 reg_gp_map[REG_EDI] = 0x7;
2258 pnc_map_signed[pn_Cmp_Eq] = 0x04;
2259 pnc_map_signed[pn_Cmp_Lt] = 0x0C;
2260 pnc_map_signed[pn_Cmp_Le] = 0x0E;
2261 pnc_map_signed[pn_Cmp_Gt] = 0x0F;
2262 pnc_map_signed[pn_Cmp_Ge] = 0x0D;
2263 pnc_map_signed[pn_Cmp_Lg] = 0x05;
2265 pnc_map_unsigned[pn_Cmp_Eq] = 0x04;
2266 pnc_map_unsigned[pn_Cmp_Lt] = 0x02;
2267 pnc_map_unsigned[pn_Cmp_Le] = 0x06;
2268 pnc_map_unsigned[pn_Cmp_Gt] = 0x07;
2269 pnc_map_unsigned[pn_Cmp_Ge] = 0x03;
2270 pnc_map_unsigned[pn_Cmp_Lg] = 0x05;
2273 static unsigned char pnc2cc(int pnc)
2276 if (pnc == ia32_pn_Cmp_parity) {
2278 } else if (pnc & ia32_pn_Cmp_float || pnc & ia32_pn_Cmp_unsigned) {
2279 cc = pnc_map_unsigned[pnc & 0x07];
2281 cc = pnc_map_signed[pnc & 0x07];
2287 /** Sign extension bit values for binops */
2289 UNSIGNED_IMM = 0, /**< unsigned immediate */
2290 SIGNEXT_IMM = 2, /**< sign extended immediate */
2293 /** The mod encoding of the ModR/M */
2295 MOD_IND = 0x00, /**< [reg1] */
2296 MOD_IND_BYTE_OFS = 0x40, /**< [reg1 + byte ofs] */
2297 MOD_IND_WORD_OFS = 0x80, /**< [reg1 + word ofs] */
2298 MOD_REG = 0xC0 /**< reg1 */
2301 /** create R/M encoding for ModR/M */
2302 #define ENC_RM(x) (x)
2303 /** create REG encoding for ModR/M */
2304 #define ENC_REG(x) ((x) << 3)
2306 /** create encoding for a SIB byte */
2307 #define ENC_SIB(scale, index, base) ((scale) << 6 | (index) << 3 | (base))
2309 /* Node: The following routines are supposed to append bytes, words, dwords
2310 to the output stream.
2311 Currently the implementation is stupid in that it still creates output
2312 for an "assembler" in the form of .byte, .long
2313 We will change this when enough infrastructure is there to create complete
2314 machine code in memory/object files */
2316 static void bemit8(const unsigned char byte)
2318 be_emit_irprintf("\t.byte 0x%x\n", byte);
2319 be_emit_write_line();
2322 static void bemit16(const unsigned short u16)
2324 be_emit_irprintf("\t.word 0x%x\n", u16);
2325 be_emit_write_line();
2328 static void bemit32(const unsigned u32)
2330 be_emit_irprintf("\t.long 0x%x\n", u32);
2331 be_emit_write_line();
2335 * Emit address of an entity. If @p is_relative is true then a relative
2336 * offset from behind the address to the entity is created.
2338 static void bemit_entity(ir_entity *entity, bool entity_sign, int offset,
2341 if (entity == NULL) {
2350 /* the final version should remember the position in the bytestream
2351 and patch it with the correct address at linktime... */
2352 be_emit_cstring("\t.long ");
2355 set_entity_backend_marked(entity, 1);
2356 be_gas_emit_entity(entity);
2359 be_emit_cstring("-.");
2363 be_emit_irprintf("%+d", offset);
2366 be_emit_write_line();
2369 static void bemit_jmp_destination(const ir_node *dest_block)
2371 be_emit_cstring("\t.long ");
2372 ia32_emit_block_name(dest_block);
2373 be_emit_cstring(" - . - 4\n");
2374 be_emit_write_line();
2377 /* end emit routines, all emitters following here should only use the functions
2380 /** Create a ModR/M byte for src1,src2 registers */
2381 static void bemit_modrr(const arch_register_t *src1,
2382 const arch_register_t *src2)
2384 unsigned char modrm = MOD_REG;
2385 modrm |= ENC_RM(reg_gp_map[src1->index]);
2386 modrm |= ENC_REG(reg_gp_map[src2->index]);
2390 /** Create a ModR/M byte for one register and extension */
2391 static void bemit_modru(const arch_register_t *reg, unsigned ext)
2393 unsigned char modrm = MOD_REG;
2395 modrm |= ENC_RM(reg_gp_map[reg->index]);
2396 modrm |= ENC_REG(ext);
2401 * Calculate the size of an signed immediate in bytes.
2403 * @param offset an offset
2405 static unsigned get_signed_imm_size(int offset)
2407 if (-128 <= offset && offset < 128) {
2409 } else if (-32768 <= offset && offset < 32768) {
2417 * Emit an address mode.
2419 * @param reg content of the reg field: either a register index or an opcode extension
2420 * @param node the node
2422 static void bemit_mod_am(unsigned reg, const ir_node *node)
2424 ir_entity *ent = get_ia32_am_sc(node);
2425 int offs = get_ia32_am_offs_int(node);
2426 ir_node *base = get_irn_n(node, n_ia32_base);
2427 int has_base = !is_ia32_NoReg_GP(base);
2428 ir_node *index = get_irn_n(node, n_ia32_index);
2429 int has_index = !is_ia32_NoReg_GP(index);
2432 unsigned emitoffs = 0;
2433 bool emitsib = false;
2436 /* set the mod part depending on displacement */
2438 modrm |= MOD_IND_WORD_OFS;
2440 } else if (offs == 0) {
2443 } else if (-128 <= offs && offs < 128) {
2444 modrm |= MOD_IND_BYTE_OFS;
2447 modrm |= MOD_IND_WORD_OFS;
2452 const arch_register_t *base_reg = arch_get_irn_register(base);
2453 base_enc = reg_gp_map[base_reg->index];
2455 /* Use the EBP encoding + MOD_IND if NO base register. There is
2456 * always a 32bit offset present in this case. */
2462 /* Determine if we need a SIB byte. */
2464 const arch_register_t *reg_index = arch_get_irn_register(index);
2465 int scale = get_ia32_am_scale(node);
2467 /* R/M set to ESP means SIB in 32bit mode. */
2468 modrm |= ENC_RM(0x04);
2469 sib = ENC_SIB(scale, reg_gp_map[reg_index->index], base_enc);
2471 } else if (base_enc == 0x04) {
2472 /* for the above reason we are forced to emit a SIB when base is ESP.
2473 * Only the base is used, index must be ESP too, which means no index.
2475 modrm |= ENC_RM(0x04);
2476 sib = ENC_SIB(0, 0x04, 0x04);
2479 modrm |= ENC_RM(base_enc);
2482 /* We are forced to emit an 8bit offset as EBP base without offset is a
2483 * special case for SIB without base register. */
2484 if (base_enc == 0x05 && emitoffs == 0) {
2485 modrm |= MOD_IND_BYTE_OFS;
2489 modrm |= ENC_REG(reg);
2495 /* emit displacement */
2496 if (emitoffs == 8) {
2497 bemit8((unsigned) offs);
2498 } else if (emitoffs == 32) {
2499 bemit_entity(ent, is_ia32_am_sc_sign(node), offs, false);
2504 * Emit a binop with a immediate operand.
2506 * @param node the node to emit
2507 * @param opcode_eax the opcode for the op eax, imm variant
2508 * @param opcode the opcode for the reg, imm variant
2509 * @param ruval the opcode extension for opcode
2511 static void bemit_binop_with_imm(
2512 const ir_node *node,
2513 unsigned char opcode_ax,
2514 unsigned char opcode, unsigned char ruval)
2516 /* Use in-reg, because some instructions (cmp, test) have no out-reg. */
2517 const ir_node *op = get_irn_n(node, n_ia32_binary_right);
2518 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(op);
2521 /* Some instructions (test) have no short form with 32bit value + 8bit
2523 if (attr->symconst != NULL || opcode & SIGNEXT_IMM) {
2526 /* check for sign extension */
2527 size = get_signed_imm_size(attr->offset);
2532 bemit8(opcode | SIGNEXT_IMM);
2533 /* cmp has this special mode */
2534 if (get_ia32_op_type(node) == ia32_AddrModeS) {
2535 bemit_mod_am(ruval, node);
2537 const arch_register_t *reg = get_in_reg(node, n_ia32_binary_left);
2538 bemit_modru(reg, ruval);
2540 bemit8((unsigned char)attr->offset);
2544 /* check for eax variant: this variant is shorter for 32bit immediates only */
2545 if (get_ia32_op_type(node) == ia32_AddrModeS) {
2547 bemit_mod_am(ruval, node);
2549 const arch_register_t *reg = get_in_reg(node, n_ia32_binary_left);
2550 if (reg->index == REG_EAX) {
2554 bemit_modru(reg, ruval);
2557 bemit_entity(attr->symconst, attr->sc_sign, attr->offset, false);
2560 panic("invalid imm size?!?");
2566 static void bemit_binop_2(const ir_node *node, unsigned code)
2568 const arch_register_t *out = get_in_reg(node, n_ia32_binary_left);
2570 if (get_ia32_op_type(node) == ia32_Normal) {
2571 const arch_register_t *op2 = get_in_reg(node, n_ia32_binary_right);
2572 bemit_modrr(op2, out);
2574 bemit_mod_am(reg_gp_map[out->index], node);
2581 static void bemit_binop(const ir_node *node, const unsigned char opcodes[4])
2583 ir_node *right = get_irn_n(node, n_ia32_binary_right);
2584 if (is_ia32_Immediate(right)) {
2585 bemit_binop_with_imm(node, opcodes[1], opcodes[2], opcodes[3]);
2587 bemit_binop_2(node, opcodes[0]);
2594 static void bemit_unop(const ir_node *node, unsigned char code, unsigned char ext, int input)
2597 if (get_ia32_op_type(node) == ia32_Normal) {
2598 const arch_register_t *in = get_in_reg(node, input);
2599 bemit_modru(in, ext);
2601 bemit_mod_am(ext, node);
2605 static void bemit_unop_reg(const ir_node *node, unsigned char code, int input)
2607 const arch_register_t *out = get_out_reg(node, 0);
2608 bemit_unop(node, code, reg_gp_map[out->index], input);
2611 static void bemit_unop_mem(const ir_node *node, unsigned char code, unsigned char ext)
2613 unsigned size = get_mode_size_bits(get_ia32_ls_mode(node));
2616 bemit8(size == 8 ? code : code + 1);
2617 bemit_mod_am(ext, node);
2620 static void bemit_immediate(const ir_node *node, bool relative)
2622 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(node);
2623 bemit_entity(attr->symconst, attr->sc_sign, attr->offset, relative);
2626 static void bemit_copy(const ir_node *copy)
2628 const arch_register_t *in = get_in_reg(copy, 0);
2629 const arch_register_t *out = get_out_reg(copy, 0);
2631 if (in == out || is_unknown_reg(in))
2633 /* copies of vf nodes aren't real... */
2634 if (arch_register_get_class(in) == &ia32_reg_classes[CLASS_ia32_vfp])
2637 if (get_irn_mode(copy) == mode_E) {
2640 assert(arch_register_get_class(in) == &ia32_reg_classes[CLASS_ia32_gp]);
2642 bemit_modrr(in, out);
2646 static void bemit_perm(const ir_node *node)
2648 const arch_register_t *in0 = arch_get_irn_register(get_irn_n(node, 0));
2649 const arch_register_t *in1 = arch_get_irn_register(get_irn_n(node, 1));
2650 const arch_register_class_t *cls0 = arch_register_get_class(in0);
2652 assert(cls0 == arch_register_get_class(in1) && "Register class mismatch at Perm");
2654 if (cls0 == &ia32_reg_classes[CLASS_ia32_gp]) {
2655 if (in0->index == REG_EAX) {
2656 bemit8(0x90 + reg_gp_map[in1->index]);
2657 } else if (in1->index == REG_EAX) {
2658 bemit8(0x90 + reg_gp_map[in0->index]);
2661 bemit_modrr(in0, in1);
2663 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_xmm]) {
2664 panic("unimplemented"); // TODO implement
2665 //ia32_emitf(NULL, "\txorpd %R, %R\n", in1, in0);
2666 //ia32_emitf(NULL, "\txorpd %R, %R\n", in0, in1);
2667 //ia32_emitf(node, "\txorpd %R, %R\n", in1, in0);
2668 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_vfp]) {
2670 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_st]) {
2673 panic("unexpected register class in be_Perm (%+F)", node);
2677 static void bemit_xor0(const ir_node *node)
2679 const arch_register_t *out = get_out_reg(node, 0);
2681 bemit_modrr(out, out);
2684 static void bemit_mov_const(const ir_node *node)
2686 const arch_register_t *out = get_out_reg(node, 0);
2687 bemit8(0xB8 + reg_gp_map[out->index]);
2688 bemit_immediate(node, false);
2692 * Creates a function for a Binop with 3 possible encodings.
2694 #define BINOP(op, op0, op1, op2, op2_ext) \
2695 static void bemit_ ## op(const ir_node *node) { \
2696 static const unsigned char op ## _codes[] = {op0, op1, op2, op2_ext}; \
2697 bemit_binop(node, op ## _codes); \
2700 /* insn def eax,imm imm */
2701 BINOP(add, 0x03, 0x05, 0x81, 0)
2702 BINOP(or, 0x0B, 0x0D, 0x81, 1)
2703 BINOP(adc, 0x13, 0x15, 0x81, 2)
2704 BINOP(sbb, 0x1B, 0x1D, 0x81, 3)
2705 BINOP(and, 0x23, 0x25, 0x81, 4)
2706 BINOP(sub, 0x2B, 0x2D, 0x81, 5)
2707 BINOP(xor, 0x33, 0x35, 0x81, 6)
2708 BINOP(test, 0x85, 0xA9, 0xF7, 0)
2710 #define BINOPMEM(op, ext) \
2711 static void bemit_##op(const ir_node *node) \
2713 unsigned size = get_mode_size_bits(get_ia32_ls_mode(node)); \
2716 ir_node *val = get_irn_n(node, n_ia32_unary_op); \
2717 if (is_ia32_Immediate(val)) { \
2718 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(val); \
2719 int offset = attr->offset; \
2720 if (attr->symconst == NULL && get_signed_imm_size(offset) == 1) { \
2722 bemit_mod_am(ext, node); \
2726 bemit_mod_am(ext, node); \
2730 bemit_entity(attr->symconst, attr->sc_sign, offset, false); \
2734 bemit8(ext << 3 | 1); \
2735 bemit_mod_am(reg_gp_map[get_out_reg(val, 0)->index], node); \
2739 static void bemit_##op##8bit(const ir_node *node) \
2741 ir_node *val = get_irn_n(node, n_ia32_unary_op); \
2742 if (is_ia32_Immediate(val)) { \
2744 bemit_mod_am(ext, node); \
2745 bemit8(get_ia32_immediate_attr_const(val)->offset); \
2748 bemit_mod_am(reg_gp_map[get_out_reg(val, 0)->index], node); \
2760 * Creates a function for an Unop with code /ext encoding.
2762 #define UNOP(op, code, ext, input) \
2763 static void bemit_ ## op(const ir_node *node) { \
2764 bemit_unop(node, code, ext, input); \
2767 UNOP(not, 0xF7, 2, n_ia32_Not_val)
2768 UNOP(neg, 0xF7, 3, n_ia32_Neg_val)
2769 UNOP(mul, 0xF7, 4, n_ia32_Mul_right)
2770 UNOP(imul1op, 0xF7, 5, n_ia32_IMul1OP_right)
2771 UNOP(div, 0xF7, 6, n_ia32_Div_divisor)
2772 UNOP(idiv, 0xF7, 7, n_ia32_IDiv_divisor)
2774 /* TODO: am support for IJmp */
2775 UNOP(ijmp, 0xFF, 4, n_ia32_IJmp_target)
2777 #define SHIFT(op, ext) \
2778 static void bemit_##op(const ir_node *node) \
2780 const arch_register_t *out = get_out_reg(node, 0); \
2781 ir_node *count = get_irn_n(node, 1); \
2782 if (is_ia32_Immediate(count)) { \
2783 int offset = get_ia32_immediate_attr_const(count)->offset; \
2784 if (offset == 1) { \
2786 bemit_modru(out, ext); \
2789 bemit_modru(out, ext); \
2794 bemit_modru(out, ext); \
2798 static void bemit_##op##mem(const ir_node *node) \
2800 unsigned size = get_mode_size_bits(get_ia32_ls_mode(node)); \
2803 ir_node *count = get_irn_n(node, 1); \
2804 if (is_ia32_Immediate(count)) { \
2805 int offset = get_ia32_immediate_attr_const(count)->offset; \
2806 if (offset == 1) { \
2807 bemit8(size == 8 ? 0xD0 : 0xD1); \
2808 bemit_mod_am(ext, node); \
2810 bemit8(size == 8 ? 0xC0 : 0xC1); \
2811 bemit_mod_am(ext, node); \
2815 bemit8(size == 8 ? 0xD2 : 0xD3); \
2816 bemit_mod_am(ext, node); \
2826 static void bemit_shld(const ir_node *node)
2828 const arch_register_t *in = get_in_reg(node, n_ia32_ShlD_val_low);
2829 const arch_register_t *out = get_out_reg(node, pn_ia32_ShlD_res);
2830 ir_node *count = get_irn_n(node, n_ia32_ShlD_count);
2832 if (is_ia32_Immediate(count)) {
2834 bemit_modrr(out, in);
2835 bemit8(get_ia32_immediate_attr_const(count)->offset);
2838 bemit_modrr(out, in);
2842 static void bemit_shrd(const ir_node *node)
2844 const arch_register_t *in = get_in_reg(node, n_ia32_ShrD_val_low);
2845 const arch_register_t *out = get_out_reg(node, pn_ia32_ShrD_res);
2846 ir_node *count = get_irn_n(node, n_ia32_ShrD_count);
2848 if (is_ia32_Immediate(count)) {
2850 bemit_modrr(out, in);
2851 bemit8(get_ia32_immediate_attr_const(count)->offset);
2854 bemit_modrr(out, in);
2858 static void bemit_cmov(const ir_node *node)
2860 const ia32_attr_t *attr = get_ia32_attr_const(node);
2861 int ins_permuted = attr->data.ins_permuted;
2862 const arch_register_t *out = arch_irn_get_register(node, pn_ia32_res);
2863 pn_Cmp pnc = get_ia32_condcode(node);
2864 const arch_register_t *in_true;
2865 const arch_register_t *in_false;
2867 pnc = determine_final_pnc(node, n_ia32_CMov_eflags, pnc);
2869 in_true = arch_get_irn_register(get_irn_n(node, n_ia32_CMov_val_true));
2870 in_false = arch_get_irn_register(get_irn_n(node, n_ia32_CMov_val_false));
2872 /* should be same constraint fullfilled? */
2873 if (out == in_false) {
2874 /* yes -> nothing to do */
2875 } else if (out == in_true) {
2876 assert(get_ia32_op_type(node) == ia32_Normal);
2877 ins_permuted = !ins_permuted;
2881 bemit8(0x8B); // mov %in_false, %out
2882 bemit_modrr(in_false, out);
2886 pnc = ia32_get_negated_pnc(pnc);
2888 /* TODO: handling of Nans isn't correct yet */
2891 bemit8(0x40 + pnc2cc(pnc));
2892 if (get_ia32_op_type(node) == ia32_Normal) {
2893 bemit_modrr(in_true, out);
2895 bemit_mod_am(reg_gp_map[out->index], node);
2899 static void bemit_cmp(const ir_node *node)
2901 unsigned ls_size = get_mode_size_bits(get_ia32_ls_mode(node));
2907 right = get_irn_n(node, n_ia32_binary_right);
2908 if (is_ia32_Immediate(right)) {
2909 /* Use in-reg, because some instructions (cmp, test) have no out-reg. */
2910 const ir_node *op = get_irn_n(node, n_ia32_binary_right);
2911 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(op);
2914 if (attr->symconst != NULL) {
2917 /* check for sign extension */
2918 size = get_signed_imm_size(attr->offset);
2923 bemit8(0x81 | SIGNEXT_IMM);
2924 /* cmp has this special mode */
2925 if (get_ia32_op_type(node) == ia32_AddrModeS) {
2926 bemit_mod_am(7, node);
2928 const arch_register_t *reg = get_in_reg(node, n_ia32_binary_left);
2929 bemit_modru(reg, 7);
2931 bemit8((unsigned char)attr->offset);
2935 /* check for eax variant: this variant is shorter for 32bit immediates only */
2936 if (get_ia32_op_type(node) == ia32_AddrModeS) {
2938 bemit_mod_am(7, node);
2940 const arch_register_t *reg = get_in_reg(node, n_ia32_binary_left);
2941 if (reg->index == REG_EAX) {
2945 bemit_modru(reg, 7);
2948 if (ls_size == 16) {
2949 bemit16(attr->offset);
2951 bemit_entity(attr->symconst, attr->sc_sign, attr->offset, false);
2955 panic("invalid imm size?!?");
2957 const arch_register_t *out = get_in_reg(node, n_ia32_binary_left);
2959 if (get_ia32_op_type(node) == ia32_Normal) {
2960 const arch_register_t *op2 = get_in_reg(node, n_ia32_binary_right);
2961 bemit_modrr(op2, out);
2963 bemit_mod_am(reg_gp_map[out->index], node);
2968 static void bemit_cmp8bit(const ir_node *node)
2970 ir_node *right = get_irn_n(node, n_ia32_binary_right);
2971 if (is_ia32_Immediate(right)) {
2972 if (get_ia32_op_type(node) == ia32_Normal) {
2973 const arch_register_t *out = get_in_reg(node, n_ia32_Cmp_left);
2974 if (out->index == REG_EAX) {
2978 bemit_modru(out, 7);
2982 bemit_mod_am(7, node);
2984 bemit8(get_ia32_immediate_attr_const(right)->offset);
2987 const arch_register_t *out = get_in_reg(node, n_ia32_Cmp_left);
2988 if (get_ia32_op_type(node) == ia32_Normal) {
2989 const arch_register_t *in = get_in_reg(node, n_ia32_Cmp_right);
2990 bemit_modrr(out, in);
2992 bemit_mod_am(reg_gp_map[out->index], node);
2997 static void bemit_test8bit(const ir_node *node)
2999 ir_node *right = get_irn_n(node, n_ia32_Test8Bit_right);
3000 if (is_ia32_Immediate(right)) {
3001 if (get_ia32_op_type(node) == ia32_Normal) {
3002 const arch_register_t *out = get_in_reg(node, n_ia32_Test8Bit_left);
3003 if (out->index == REG_EAX) {
3007 bemit_modru(out, 0);
3011 bemit_mod_am(0, node);
3013 bemit8(get_ia32_immediate_attr_const(right)->offset);
3016 const arch_register_t *out = get_in_reg(node, n_ia32_Test8Bit_left);
3017 if (get_ia32_op_type(node) == ia32_Normal) {
3018 const arch_register_t *in = get_in_reg(node, n_ia32_Test8Bit_right);
3019 bemit_modrr(out, in);
3021 bemit_mod_am(reg_gp_map[out->index], node);
3026 static void bemit_imul(const ir_node *node)
3028 ir_node *right = get_irn_n(node, n_ia32_IMul_right);
3029 /* Do we need the immediate form? */
3030 if (is_ia32_Immediate(right)) {
3031 int imm = get_ia32_immediate_attr_const(right)->offset;
3032 if (get_signed_imm_size(imm) == 1) {
3033 bemit_unop_reg(node, 0x6B, n_ia32_IMul_left);
3036 bemit_unop_reg(node, 0x69, n_ia32_IMul_left);
3041 bemit_unop_reg(node, 0xAF, n_ia32_IMul_right);
3045 static void bemit_dec(const ir_node *node)
3047 const arch_register_t *out = get_out_reg(node, pn_ia32_Dec_res);
3048 bemit8(0x48 + reg_gp_map[out->index]);
3051 static void bemit_inc(const ir_node *node)
3053 const arch_register_t *out = get_out_reg(node, pn_ia32_Inc_res);
3054 bemit8(0x40 + reg_gp_map[out->index]);
3057 #define UNOPMEM(op, code, ext) \
3058 static void bemit_##op(const ir_node *node) \
3060 bemit_unop_mem(node, code, ext); \
3063 UNOPMEM(notmem, 0xF6, 2)
3064 UNOPMEM(negmem, 0xF6, 3)
3065 UNOPMEM(incmem, 0xFE, 0)
3066 UNOPMEM(decmem, 0xFE, 1)
3068 static void bemit_set(const ir_node *node)
3074 pnc = get_ia32_condcode(node);
3075 pnc = determine_final_pnc(node, n_ia32_Set_eflags, pnc);
3076 if (get_ia32_attr_const(node)->data.ins_permuted)
3077 pnc = ia32_get_negated_pnc(pnc);
3079 bemit8(0x90 + pnc2cc(pnc));
3080 bemit_modru(get_out_reg(node, pn_ia32_Set_res), 2);
3083 static void bemit_ldtls(const ir_node *node)
3085 const arch_register_t *out = get_out_reg(node, 0);
3087 bemit8(0x65); // gs:
3088 if (out->index == REG_EAX) {
3089 bemit8(0xA1); // movl 0, %eax
3091 bemit8(0x8B); // movl 0, %reg
3092 bemit8(MOD_IND | ENC_REG(reg_gp_map[out->index]) | ENC_RM(0x05));
3100 static void bemit_lea(const ir_node *node)
3102 const arch_register_t *out = get_out_reg(node, 0);
3104 bemit_mod_am(reg_gp_map[out->index], node);
3107 /* helper function for bemit_minus64bit */
3108 static void bemit_helper_mov(const arch_register_t *src, const arch_register_t *dst)
3110 bemit8(0x8B); // movl %src, %dst
3111 bemit_modrr(src, dst);
3114 /* helper function for bemit_minus64bit */
3115 static void bemit_helper_neg(const arch_register_t *reg)
3117 bemit8(0xF7); // negl %reg
3118 bemit_modru(reg, 3);
3121 /* helper function for bemit_minus64bit */
3122 static void bemit_helper_sbb0(const arch_register_t *reg)
3124 bemit8(0x83); // sbbl $0, %reg
3125 bemit_modru(reg, 3);
3129 /* helper function for bemit_minus64bit */
3130 static void bemit_helper_sbb(const arch_register_t *src, const arch_register_t *dst)
3132 bemit8(0x1B); // sbbl %src, %dst
3133 bemit_modrr(src, dst);
3136 /* helper function for bemit_minus64bit */
3137 static void bemit_helper_xchg(const arch_register_t *src, const arch_register_t *dst)
3139 if (src->index == REG_EAX) {
3140 bemit8(0x90 + reg_gp_map[dst->index]); // xchgl %eax, %dst
3141 } else if (dst->index == REG_EAX) {
3142 bemit8(0x90 + reg_gp_map[src->index]); // xchgl %src, %eax
3144 bemit8(0x87); // xchgl %src, %dst
3145 bemit_modrr(src, dst);
3149 /* helper function for bemit_minus64bit */
3150 static void bemit_helper_zero(const arch_register_t *reg)
3152 bemit8(0x33); // xorl %reg, %reg
3153 bemit_modrr(reg, reg);
3156 static void bemit_minus64bit(const ir_node *node)
3158 const arch_register_t *in_lo = get_in_reg(node, 0);
3159 const arch_register_t *in_hi = get_in_reg(node, 1);
3160 const arch_register_t *out_lo = get_out_reg(node, 0);
3161 const arch_register_t *out_hi = get_out_reg(node, 1);
3163 if (out_lo == in_lo) {
3164 if (out_hi != in_hi) {
3165 /* a -> a, b -> d */
3168 /* a -> a, b -> b */
3171 } else if (out_lo == in_hi) {
3172 if (out_hi == in_lo) {
3173 /* a -> b, b -> a */
3174 bemit_helper_xchg(in_lo, in_hi);
3177 /* a -> b, b -> d */
3178 bemit_helper_mov(in_hi, out_hi);
3179 bemit_helper_mov(in_lo, out_lo);
3183 if (out_hi == in_lo) {
3184 /* a -> c, b -> a */
3185 bemit_helper_mov(in_lo, out_lo);
3187 } else if (out_hi == in_hi) {
3188 /* a -> c, b -> b */
3189 bemit_helper_mov(in_lo, out_lo);
3192 /* a -> c, b -> d */
3193 bemit_helper_mov(in_lo, out_lo);
3199 bemit_helper_neg( out_hi);
3200 bemit_helper_neg( out_lo);
3201 bemit_helper_sbb0(out_hi);
3205 bemit_helper_zero(out_hi);
3206 bemit_helper_neg( out_lo);
3207 bemit_helper_sbb( in_hi, out_hi);
3211 * Emit a single opcode.
3213 #define EMIT_SINGLEOP(op, code) \
3214 static void bemit_ ## op(const ir_node *node) { \
3219 //EMIT_SINGLEOP(daa, 0x27)
3220 //EMIT_SINGLEOP(das, 0x2F)
3221 //EMIT_SINGLEOP(aaa, 0x37)
3222 //EMIT_SINGLEOP(aas, 0x3F)
3223 //EMIT_SINGLEOP(nop, 0x90)
3224 EMIT_SINGLEOP(cwtl, 0x98)
3225 EMIT_SINGLEOP(cltd, 0x99)
3226 //EMIT_SINGLEOP(fwait, 0x9B)
3227 EMIT_SINGLEOP(sahf, 0x9E)
3228 //EMIT_SINGLEOP(popf, 0x9D)
3229 EMIT_SINGLEOP(leave, 0xC9)
3230 EMIT_SINGLEOP(int3, 0xCC)
3231 //EMIT_SINGLEOP(iret, 0xCF)
3232 //EMIT_SINGLEOP(xlat, 0xD7)
3233 //EMIT_SINGLEOP(lock, 0xF0)
3234 EMIT_SINGLEOP(rep, 0xF3)
3235 //EMIT_SINGLEOP(halt, 0xF4)
3236 EMIT_SINGLEOP(cmc, 0xF5)
3237 EMIT_SINGLEOP(stc, 0xF9)
3238 //EMIT_SINGLEOP(cli, 0xFA)
3239 //EMIT_SINGLEOP(sti, 0xFB)
3240 //EMIT_SINGLEOP(std, 0xFD)
3243 * Emits a MOV out, [MEM].
3245 static void bemit_load(const ir_node *node)
3247 const arch_register_t *out = get_out_reg(node, 0);
3249 if (out->index == REG_EAX) {
3250 ir_node *base = get_irn_n(node, n_ia32_base);
3251 int has_base = !is_ia32_NoReg_GP(base);
3252 ir_node *index = get_irn_n(node, n_ia32_index);
3253 int has_index = !is_ia32_NoReg_GP(index);
3254 if (!has_base && !has_index) {
3255 ir_entity *ent = get_ia32_am_sc(node);
3256 int offs = get_ia32_am_offs_int(node);
3257 /* load from constant address to EAX can be encoded
3260 bemit_entity(ent, 0, offs, false);
3265 bemit_mod_am(reg_gp_map[out->index], node);
3269 * Emits a MOV [mem], in.
3271 static void bemit_store(const ir_node *node)
3273 const ir_node *value = get_irn_n(node, n_ia32_Store_val);
3274 unsigned size = get_mode_size_bits(get_ia32_ls_mode(node));
3276 if (is_ia32_Immediate(value)) {
3279 bemit_mod_am(0, node);
3280 bemit8(get_ia32_immediate_attr_const(value)->offset);
3281 } else if (size == 16) {
3284 bemit_mod_am(0, node);
3285 bemit16(get_ia32_immediate_attr_const(value)->offset);
3288 bemit_mod_am(0, node);
3289 bemit_immediate(value, false);
3292 const arch_register_t *in = get_in_reg(node, n_ia32_Store_val);
3294 if (in->index == REG_EAX) {
3295 ir_node *base = get_irn_n(node, n_ia32_base);
3296 int has_base = !is_ia32_NoReg_GP(base);
3297 ir_node *index = get_irn_n(node, n_ia32_index);
3298 int has_index = !is_ia32_NoReg_GP(index);
3299 if (!has_base && !has_index) {
3300 ir_entity *ent = get_ia32_am_sc(node);
3301 int offs = get_ia32_am_offs_int(node);
3302 /* store to constant address from EAX can be encoded as
3303 * 0xA2/0xA3 [offset]*/
3311 bemit_entity(ent, 0, offs, false);
3323 bemit_mod_am(reg_gp_map[in->index], node);
3327 static void bemit_conv_i2i(const ir_node *node)
3329 ir_mode *smaller_mode = get_ia32_ls_mode(node);
3338 if (mode_is_signed(smaller_mode)) opcode |= 0x08;
3339 if (get_mode_size_bits(smaller_mode) == 16) opcode |= 0x01;
3340 bemit_unop_reg(node, opcode, n_ia32_Conv_I2I_val);
3346 static void bemit_push(const ir_node *node)
3348 const ir_node *value = get_irn_n(node, n_ia32_Push_val);
3350 if (is_ia32_Immediate(value)) {
3351 const ia32_immediate_attr_t *attr
3352 = get_ia32_immediate_attr_const(value);
3353 unsigned size = get_signed_imm_size(attr->offset);
3359 bemit8((unsigned char)attr->offset);
3364 bemit_immediate(value, false);
3367 } else if (is_ia32_NoReg_GP(value)) {
3369 bemit_mod_am(6, node);
3371 const arch_register_t *reg = get_in_reg(node, n_ia32_Push_val);
3372 bemit8(0x50 + reg_gp_map[reg->index]);
3379 static void bemit_pop(const ir_node *node)
3381 const arch_register_t *reg = get_out_reg(node, pn_ia32_Pop_res);
3382 bemit8(0x58 + reg_gp_map[reg->index]);
3385 static void bemit_popmem(const ir_node *node)
3388 bemit_mod_am(0, node);
3391 static void bemit_call(const ir_node *node)
3393 ir_node *proc = get_irn_n(node, n_ia32_Call_addr);
3395 if (is_ia32_Immediate(proc)) {
3397 bemit_immediate(proc, true);
3399 bemit_unop(node, 0xFF, 2, n_ia32_Call_addr);
3403 static void bemit_jmp(const ir_node *dest_block)
3406 bemit_jmp_destination(dest_block);
3409 static void bemit_jump(const ir_node *node)
3411 if (can_be_fallthrough(node))
3414 bemit_jmp(get_cfop_target_block(node));
3417 static void bemit_jcc(int pnc, const ir_node *dest_block)
3419 unsigned char cc = pnc2cc(pnc);
3422 bemit_jmp_destination(dest_block);
3425 static void bemit_jp(bool odd, const ir_node *dest_block)
3429 bemit_jmp_destination(dest_block);
3432 static void bemit_ia32_jcc(const ir_node *node)
3434 int pnc = get_ia32_condcode(node);
3435 const ir_node *proj_true;
3436 const ir_node *proj_false;
3437 const ir_node *dest_true;
3438 const ir_node *dest_false;
3439 const ir_node *block;
3441 pnc = determine_final_pnc(node, 0, pnc);
3443 /* get both Projs */
3444 proj_true = get_proj(node, pn_ia32_Jcc_true);
3445 assert(proj_true && "Jcc without true Proj");
3447 proj_false = get_proj(node, pn_ia32_Jcc_false);
3448 assert(proj_false && "Jcc without false Proj");
3450 block = get_nodes_block(node);
3452 if (can_be_fallthrough(proj_true)) {
3453 /* exchange both proj's so the second one can be omitted */
3454 const ir_node *t = proj_true;
3456 proj_true = proj_false;
3458 pnc = ia32_get_negated_pnc(pnc);
3461 dest_true = get_cfop_target_block(proj_true);
3462 dest_false = get_cfop_target_block(proj_false);
3464 if (pnc & ia32_pn_Cmp_float) {
3465 /* Some floating point comparisons require a test of the parity flag,
3466 * which indicates that the result is unordered */
3469 bemit_jp(false, dest_true);
3474 bemit_jp(true, dest_true);
3480 /* we need a local label if the false proj is a fallthrough
3481 * as the falseblock might have no label emitted then */
3482 if (can_be_fallthrough(proj_false)) {
3484 bemit8(0x06); // jp + 6
3486 bemit_jp(false, dest_false);
3493 bemit_jp(false, dest_true);
3501 bemit_jcc(pnc, dest_true);
3504 /* the second Proj might be a fallthrough */
3505 if (can_be_fallthrough(proj_false)) {
3506 /* it's a fallthrough */
3508 bemit_jmp(dest_false);
3512 static void bemit_switchjmp(const ir_node *node)
3514 unsigned long interval;
3518 const arch_register_t *in;
3520 /* fill the table structure */
3521 generate_jump_table(&tbl, node);
3523 /* two-complement's magic make this work without overflow */
3524 interval = tbl.max_value - tbl.min_value;
3526 in = get_in_reg(node, 0);
3527 /* emit the table */
3528 if (get_signed_imm_size(interval) == 1) {
3529 bemit8(0x83); // cmpl $imm8, %in
3533 bemit8(0x81); // cmpl $imm32, %in
3537 bemit8(0x0F); // ja tbl.defProj
3539 ia32_emitf(tbl.defProj, ".long %L - . - 4\n");
3541 if (tbl.num_branches > 1) {
3543 bemit8(0xFF); // jmp *tbl.label(,%in,4)
3544 bemit8(MOD_IND | ENC_REG(4) | ENC_RM(0x04));
3545 bemit8(ENC_SIB(2, reg_gp_map[in->index], 0x05));
3546 be_emit_irprintf("\t.long %s\n", tbl.label);
3548 be_gas_emit_switch_section(GAS_SECTION_RODATA);
3549 be_emit_cstring(".align 4\n");
3550 be_emit_irprintf("%s:\n", tbl.label);
3552 last_value = tbl.branches[0].value;
3553 for (i = 0; i != tbl.num_branches; ++i) {
3554 while (last_value != tbl.branches[i].value) {
3555 ia32_emitf(tbl.defProj, ".long %L\n");
3558 ia32_emitf(tbl.branches[i].target, ".long %L\n");
3561 be_gas_emit_switch_section(GAS_SECTION_TEXT);
3563 /* one jump is enough */
3564 panic("switch only has one case");
3565 //ia32_emitf(tbl.branches[0].target, "\tjmp %L\n");
3568 be_emit_write_line();
3576 static void bemit_return(const ir_node *node)
3578 unsigned pop = be_Return_get_pop(node);
3579 if (pop > 0 || be_Return_get_emit_pop(node)) {
3581 assert(pop <= 0xffff);
3588 static void bemit_subsp(const ir_node *node)
3590 const arch_register_t *out;
3593 /* mov %esp, %out */
3595 out = get_out_reg(node, 1);
3596 bemit8(MOD_REG | ENC_REG(reg_gp_map[out->index]) | ENC_RM(0x04));
3599 static void bemit_incsp(const ir_node *node)
3602 const arch_register_t *reg;
3606 offs = be_get_IncSP_offset(node);
3617 size = get_signed_imm_size(offs);
3618 bemit8(size == 1 ? 0x83 : 0x81);
3620 reg = get_out_reg(node, 0);
3621 bemit_modru(reg, ext);
3630 static void bemit_copybi(const ir_node *node)
3632 unsigned size = get_ia32_copyb_size(node);
3634 bemit8(0xA4); // movsb
3637 bemit8(0xA5); // movsw
3641 bemit8(0xA5); // movsl
3645 static void bemit_fbinop(const ir_node *node, unsigned code, unsigned code_to)
3647 if (get_ia32_op_type(node) == ia32_Normal) {
3648 const ia32_x87_attr_t *x87_attr = get_ia32_x87_attr_const(node);
3649 const arch_register_t *in1 = x87_attr->x87[0];
3650 const arch_register_t *in = x87_attr->x87[1];
3651 const arch_register_t *out = x87_attr->x87[2];
3655 } else if (out == in) {
3659 if (out->index == 0) {
3661 bemit8(MOD_REG | ENC_REG(code) | ENC_RM(in->index));
3664 bemit8(MOD_REG | ENC_REG(code_to) | ENC_RM(out->index));
3667 if (get_mode_size_bits(get_ia32_ls_mode(node)) == 32) {
3672 bemit_mod_am(code, node);
3676 static void bemit_fbinopp(const ir_node *node, unsigned const code)
3678 const ia32_x87_attr_t *x87_attr = get_ia32_x87_attr_const(node);
3679 const arch_register_t *out = x87_attr->x87[2];
3681 bemit8(code + out->index);
3684 static void bemit_fabs(const ir_node *node)
3692 static void bemit_fadd(const ir_node *node)
3694 bemit_fbinop(node, 0, 0);
3697 static void bemit_faddp(const ir_node *node)
3699 bemit_fbinopp(node, 0xC0);
3702 static void bemit_fchs(const ir_node *node)
3710 static void bemit_fdiv(const ir_node *node)
3712 bemit_fbinop(node, 6, 7);
3715 static void bemit_fdivp(const ir_node *node)
3717 bemit_fbinopp(node, 0xF8);
3720 static void bemit_fdivr(const ir_node *node)
3722 bemit_fbinop(node, 7, 6);
3725 static void bemit_fdivrp(const ir_node *node)
3727 bemit_fbinopp(node, 0xF0);
3730 static void bemit_fild(const ir_node *node)
3732 switch (get_mode_size_bits(get_ia32_ls_mode(node))) {
3734 bemit8(0xDF); // filds
3735 bemit_mod_am(0, node);
3739 bemit8(0xDB); // fildl
3740 bemit_mod_am(0, node);
3744 bemit8(0xDF); // fildll
3745 bemit_mod_am(5, node);
3749 panic("invalid mode size");
3753 static void bemit_fist(const ir_node *node)
3755 switch (get_mode_size_bits(get_ia32_ls_mode(node))) {
3757 bemit8(0xDF); // fists
3761 bemit8(0xDB); // fistl
3765 panic("invalid mode size");
3767 bemit_mod_am(2, node);
3770 static void bemit_fistp(const ir_node *node)
3772 switch (get_mode_size_bits(get_ia32_ls_mode(node))) {
3774 bemit8(0xDF); // fistps
3775 bemit_mod_am(3, node);
3779 bemit8(0xDB); // fistpl
3780 bemit_mod_am(3, node);
3784 bemit8(0xDF); // fistpll
3785 bemit_mod_am(7, node);
3789 panic("invalid mode size");
3793 static void bemit_fld(const ir_node *node)
3795 switch (get_mode_size_bits(get_ia32_ls_mode(node))) {
3797 bemit8(0xD9); // flds
3798 bemit_mod_am(0, node);
3802 bemit8(0xDD); // fldl
3803 bemit_mod_am(0, node);
3808 bemit8(0xDB); // fldt
3809 bemit_mod_am(5, node);
3813 panic("invalid mode size");
3817 static void bemit_fld1(const ir_node *node)
3821 bemit8(0xE8); // fld1
3824 static void bemit_fldcw(const ir_node *node)
3826 bemit8(0xD9); // fldcw
3827 bemit_mod_am(5, node);
3830 static void bemit_fldz(const ir_node *node)
3834 bemit8(0xEE); // fldz
3837 static void bemit_fmul(const ir_node *node)
3839 bemit_fbinop(node, 1, 1);
3842 static void bemit_fmulp(const ir_node *node)
3844 bemit_fbinopp(node, 0xC8);
3847 static void bemit_fpop(const ir_node *node)
3849 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
3851 bemit8(0xD8 + attr->x87[0]->index);
3854 static void bemit_fpush(const ir_node *node)
3856 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
3858 bemit8(0xC0 + attr->x87[0]->index);
3861 static void bemit_fpushcopy(const ir_node *node)
3863 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
3865 bemit8(0xC0 + attr->x87[0]->index);
3868 static void bemit_fst(const ir_node *node)
3870 switch (get_mode_size_bits(get_ia32_ls_mode(node))) {
3872 bemit8(0xD9); // fsts
3876 bemit8(0xDD); // fstl
3880 panic("invalid mode size");
3882 bemit_mod_am(2, node);
3885 static void bemit_fstp(const ir_node *node)
3887 switch (get_mode_size_bits(get_ia32_ls_mode(node))) {
3889 bemit8(0xD9); // fstps
3890 bemit_mod_am(3, node);
3894 bemit8(0xDD); // fstpl
3895 bemit_mod_am(3, node);
3900 bemit8(0xDB); // fstpt
3901 bemit_mod_am(7, node);
3905 panic("invalid mode size");
3909 static void bemit_fsub(const ir_node *node)
3911 bemit_fbinop(node, 4, 5);
3914 static void bemit_fsubp(const ir_node *node)
3916 bemit_fbinopp(node, 0xE8);
3919 static void bemit_fsubr(const ir_node *node)
3921 bemit_fbinop(node, 5, 4);
3924 static void bemit_fsubrp(const ir_node *node)
3926 bemit_fbinopp(node, 0xE0);
3929 static void bemit_fnstcw(const ir_node *node)
3931 bemit8(0xD9); // fnstcw
3932 bemit_mod_am(7, node);
3935 static void bemit_fnstsw(void)
3937 bemit8(0xDF); // fnstsw %ax
3941 static void bemit_ftstfnstsw(const ir_node *node)
3945 bemit8(0xD9); // ftst
3950 static void bemit_fucomi(const ir_node *node)
3952 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
3953 bemit8(0xDB); // fucomi
3954 bemit8(0xE8 + attr->x87[1]->index);
3957 static void bemit_fucomip(const ir_node *node)
3959 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
3960 bemit8(0xDF); // fucomip
3961 bemit8(0xE8 + attr->x87[1]->index);
3964 static void bemit_fucomfnstsw(const ir_node *node)
3966 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
3967 bemit8(0xDD); // fucom
3968 bemit8(0xE0 + attr->x87[1]->index);
3972 static void bemit_fucompfnstsw(const ir_node *node)
3974 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
3975 bemit8(0xDD); // fucomp
3976 bemit8(0xE8 + attr->x87[1]->index);
3980 static void bemit_fucomppfnstsw(const ir_node *node)
3984 bemit8(0xDA); // fucompp
3989 static void bemit_fxch(const ir_node *node)
3991 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
3993 bemit8(0xC8 + attr->x87[0]->index);
3997 * The type of a emitter function.
3999 typedef void (*emit_func) (const ir_node *);
4002 * Set a node emitter. Make it a bit more type safe.
4004 static void register_emitter(ir_op *op, emit_func func)
4006 op->ops.generic = (op_func) func;
4009 static void ia32_register_binary_emitters(void)
4011 /* first clear the generic function pointer for all ops */
4012 clear_irp_opcodes_generic_func();
4014 /* benode emitter */
4015 register_emitter(op_be_Copy, bemit_copy);
4016 register_emitter(op_be_CopyKeep, bemit_copy);
4017 register_emitter(op_be_IncSP, bemit_incsp);
4018 register_emitter(op_be_Perm, bemit_perm);
4019 register_emitter(op_be_Return, bemit_return);
4020 register_emitter(op_ia32_Adc, bemit_adc);
4021 register_emitter(op_ia32_Add, bemit_add);
4022 register_emitter(op_ia32_AddMem, bemit_addmem);
4023 register_emitter(op_ia32_AddMem8Bit, bemit_addmem8bit);
4024 register_emitter(op_ia32_And, bemit_and);
4025 register_emitter(op_ia32_AndMem, bemit_andmem);
4026 register_emitter(op_ia32_AndMem8Bit, bemit_andmem8bit);
4027 register_emitter(op_ia32_Breakpoint, bemit_int3);
4028 register_emitter(op_ia32_CMov, bemit_cmov);
4029 register_emitter(op_ia32_Call, bemit_call);
4030 register_emitter(op_ia32_Cltd, bemit_cltd);
4031 register_emitter(op_ia32_Cmc, bemit_cmc);
4032 register_emitter(op_ia32_Cmp, bemit_cmp);
4033 register_emitter(op_ia32_Cmp8Bit, bemit_cmp8bit);
4034 register_emitter(op_ia32_Const, bemit_mov_const);
4035 register_emitter(op_ia32_Conv_I2I, bemit_conv_i2i);
4036 register_emitter(op_ia32_Conv_I2I8Bit, bemit_conv_i2i);
4037 register_emitter(op_ia32_CopyB_i, bemit_copybi);
4038 register_emitter(op_ia32_Cwtl, bemit_cwtl);
4039 register_emitter(op_ia32_Dec, bemit_dec);
4040 register_emitter(op_ia32_DecMem, bemit_decmem);
4041 register_emitter(op_ia32_Div, bemit_div);
4042 register_emitter(op_ia32_FldCW, bemit_fldcw);
4043 register_emitter(op_ia32_FnstCW, bemit_fnstcw);
4044 register_emitter(op_ia32_FtstFnstsw, bemit_ftstfnstsw);
4045 register_emitter(op_ia32_FucomFnstsw, bemit_fucomfnstsw);
4046 register_emitter(op_ia32_Fucomi, bemit_fucomi);
4047 register_emitter(op_ia32_FucompFnstsw, bemit_fucompfnstsw);
4048 register_emitter(op_ia32_Fucompi, bemit_fucomip);
4049 register_emitter(op_ia32_FucomppFnstsw, bemit_fucomppfnstsw);
4050 register_emitter(op_ia32_IDiv, bemit_idiv);
4051 register_emitter(op_ia32_IJmp, bemit_ijmp);
4052 register_emitter(op_ia32_IMul, bemit_imul);
4053 register_emitter(op_ia32_IMul1OP, bemit_imul1op);
4054 register_emitter(op_ia32_Inc, bemit_inc);
4055 register_emitter(op_ia32_IncMem, bemit_incmem);
4056 register_emitter(op_ia32_Jcc, bemit_ia32_jcc);
4057 register_emitter(op_ia32_Jmp, bemit_jump);
4058 register_emitter(op_ia32_LdTls, bemit_ldtls);
4059 register_emitter(op_ia32_Lea, bemit_lea);
4060 register_emitter(op_ia32_Leave, bemit_leave);
4061 register_emitter(op_ia32_Load, bemit_load);
4062 register_emitter(op_ia32_Minus64Bit, bemit_minus64bit);
4063 register_emitter(op_ia32_Mul, bemit_mul);
4064 register_emitter(op_ia32_Neg, bemit_neg);
4065 register_emitter(op_ia32_NegMem, bemit_negmem);
4066 register_emitter(op_ia32_Not, bemit_not);
4067 register_emitter(op_ia32_NotMem, bemit_notmem);
4068 register_emitter(op_ia32_Or, bemit_or);
4069 register_emitter(op_ia32_OrMem, bemit_ormem);
4070 register_emitter(op_ia32_OrMem8Bit, bemit_ormem8bit);
4071 register_emitter(op_ia32_Pop, bemit_pop);
4072 register_emitter(op_ia32_PopEbp, bemit_pop);
4073 register_emitter(op_ia32_PopMem, bemit_popmem);
4074 register_emitter(op_ia32_Push, bemit_push);
4075 register_emitter(op_ia32_RepPrefix, bemit_rep);
4076 register_emitter(op_ia32_Rol, bemit_rol);
4077 register_emitter(op_ia32_RolMem, bemit_rolmem);
4078 register_emitter(op_ia32_Ror, bemit_ror);
4079 register_emitter(op_ia32_RorMem, bemit_rormem);
4080 register_emitter(op_ia32_Sahf, bemit_sahf);
4081 register_emitter(op_ia32_Sar, bemit_sar);
4082 register_emitter(op_ia32_SarMem, bemit_sarmem);
4083 register_emitter(op_ia32_Sbb, bemit_sbb);
4084 register_emitter(op_ia32_Set, bemit_set);
4085 register_emitter(op_ia32_Shl, bemit_shl);
4086 register_emitter(op_ia32_ShlD, bemit_shld);
4087 register_emitter(op_ia32_ShlMem, bemit_shlmem);
4088 register_emitter(op_ia32_Shr, bemit_shr);
4089 register_emitter(op_ia32_ShrD, bemit_shrd);
4090 register_emitter(op_ia32_ShrMem, bemit_shrmem);
4091 register_emitter(op_ia32_Stc, bemit_stc);
4092 register_emitter(op_ia32_Store, bemit_store);
4093 register_emitter(op_ia32_Store8Bit, bemit_store);
4094 register_emitter(op_ia32_Sub, bemit_sub);
4095 register_emitter(op_ia32_SubMem, bemit_submem);
4096 register_emitter(op_ia32_SubMem8Bit, bemit_submem8bit);
4097 register_emitter(op_ia32_SubSP, bemit_subsp);
4098 register_emitter(op_ia32_SwitchJmp, bemit_switchjmp);
4099 register_emitter(op_ia32_Test, bemit_test);
4100 register_emitter(op_ia32_Test8Bit, bemit_test8bit);
4101 register_emitter(op_ia32_Xor, bemit_xor);
4102 register_emitter(op_ia32_Xor0, bemit_xor0);
4103 register_emitter(op_ia32_XorMem, bemit_xormem);
4104 register_emitter(op_ia32_XorMem8Bit, bemit_xormem8bit);
4105 register_emitter(op_ia32_fabs, bemit_fabs);
4106 register_emitter(op_ia32_fadd, bemit_fadd);
4107 register_emitter(op_ia32_faddp, bemit_faddp);
4108 register_emitter(op_ia32_fchs, bemit_fchs);
4109 register_emitter(op_ia32_fdiv, bemit_fdiv);
4110 register_emitter(op_ia32_fdivp, bemit_fdivp);
4111 register_emitter(op_ia32_fdivr, bemit_fdivr);
4112 register_emitter(op_ia32_fdivrp, bemit_fdivrp);
4113 register_emitter(op_ia32_fild, bemit_fild);
4114 register_emitter(op_ia32_fist, bemit_fist);
4115 register_emitter(op_ia32_fistp, bemit_fistp);
4116 register_emitter(op_ia32_fld, bemit_fld);
4117 register_emitter(op_ia32_fld1, bemit_fld1);
4118 register_emitter(op_ia32_fldz, bemit_fldz);
4119 register_emitter(op_ia32_fmul, bemit_fmul);
4120 register_emitter(op_ia32_fmulp, bemit_fmulp);
4121 register_emitter(op_ia32_fpop, bemit_fpop);
4122 register_emitter(op_ia32_fpush, bemit_fpush);
4123 register_emitter(op_ia32_fpushCopy, bemit_fpushcopy);
4124 register_emitter(op_ia32_fst, bemit_fst);
4125 register_emitter(op_ia32_fstp, bemit_fstp);
4126 register_emitter(op_ia32_fsub, bemit_fsub);
4127 register_emitter(op_ia32_fsubp, bemit_fsubp);
4128 register_emitter(op_ia32_fsubr, bemit_fsubr);
4129 register_emitter(op_ia32_fsubrp, bemit_fsubrp);
4130 register_emitter(op_ia32_fxch, bemit_fxch);
4132 /* ignore the following nodes */
4133 register_emitter(op_ia32_ProduceVal, emit_Nothing);
4134 register_emitter(op_be_Barrier, emit_Nothing);
4135 register_emitter(op_be_Keep, emit_Nothing);
4136 register_emitter(op_be_Start, emit_Nothing);
4137 register_emitter(op_Phi, emit_Nothing);
4138 register_emitter(op_Start, emit_Nothing);
4141 static void gen_binary_block(ir_node *block)
4145 ia32_emit_block_header(block);
4147 /* emit the contents of the block */
4148 sched_foreach(block, node) {
4149 ia32_emit_node(node);
4153 void ia32_gen_binary_routine(ia32_code_gen_t *ia32_cg, ir_graph *irg)
4155 ir_entity *entity = get_irg_entity(irg);
4161 ia32_register_binary_emitters();
4163 be_gas_emit_function_prolog(entity, ia32_cg_config.function_alignment);
4165 /* we use links to point to target blocks */
4166 ir_reserve_resources(irg, IR_RESOURCE_IRN_LINK);
4167 irg_block_walk_graph(irg, ia32_gen_labels, NULL, NULL);
4169 /* initialize next block links */
4170 n = ARR_LEN(cg->blk_sched);
4171 for (i = 0; i < n; ++i) {
4172 ir_node *block = cg->blk_sched[i];
4173 ir_node *prev = i > 0 ? cg->blk_sched[i-1] : NULL;
4175 set_irn_link(block, prev);
4178 for (i = 0; i < n; ++i) {
4179 ir_node *block = cg->blk_sched[i];
4180 gen_binary_block(block);
4183 be_gas_emit_function_epilog(entity);
4184 be_dbg_method_end();
4186 be_emit_write_line();
4188 ir_free_resources(irg, IR_RESOURCE_IRN_LINK);
4194 void ia32_init_emitter(void)
4196 lc_opt_entry_t *be_grp;
4197 lc_opt_entry_t *ia32_grp;
4199 be_grp = lc_opt_get_grp(firm_opt_get_root(), "be");
4200 ia32_grp = lc_opt_get_grp(be_grp, "ia32");
4202 lc_opt_add_table(ia32_grp, ia32_emitter_options);
4206 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.emitter");