2 * Copyright (C) 1995-2007 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This file implements the ia32 node emitter.
23 * @author Christian Wuerdig, Matthias Braun
41 #include "iredges_t.h"
44 #include "raw_bitset.h"
46 #include "../besched_t.h"
47 #include "../benode_t.h"
49 #include "../be_dbgout.h"
50 #include "../beemitter.h"
51 #include "../begnuas.h"
52 #include "../beirg_t.h"
54 #include "ia32_emitter.h"
55 #include "gen_ia32_emitter.h"
56 #include "gen_ia32_regalloc_if.h"
57 #include "ia32_nodes_attr.h"
58 #include "ia32_new_nodes.h"
59 #include "ia32_map_regs.h"
60 #include "ia32_architecture.h"
61 #include "bearch_ia32_t.h"
63 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
65 #define BLOCK_PREFIX ".L"
67 #define SNPRINTF_BUF_LEN 128
69 static const arch_env_t *arch_env;
70 static const ia32_isa_t *isa;
71 static ia32_code_gen_t *cg;
74 * Returns the register at in position pos.
76 static const arch_register_t *get_in_reg(const ir_node *irn, int pos)
79 const arch_register_t *reg = NULL;
81 assert(get_irn_arity(irn) > pos && "Invalid IN position");
83 /* The out register of the operator at position pos is the
84 in register we need. */
85 op = get_irn_n(irn, pos);
87 reg = arch_get_irn_register(arch_env, op);
89 assert(reg && "no in register found");
91 if(reg == &ia32_gp_regs[REG_GP_NOREG])
92 panic("trying to emit noreg for %+F input %d", irn, pos);
94 /* in case of unknown register: just return a valid register */
95 if (reg == &ia32_gp_regs[REG_GP_UKNWN]) {
96 const arch_register_req_t *req;
98 /* ask for the requirements */
99 req = arch_get_register_req(arch_env, irn, pos);
101 if (arch_register_req_is(req, limited)) {
102 /* in case of limited requirements: get the first allowed register */
103 unsigned idx = rbitset_next(req->limited, 0, 1);
104 reg = arch_register_for_index(req->cls, idx);
106 /* otherwise get first register in class */
107 reg = arch_register_for_index(req->cls, 0);
115 * Returns the register at out position pos.
117 static const arch_register_t *get_out_reg(const ir_node *irn, int pos)
120 const arch_register_t *reg = NULL;
122 /* 1st case: irn is not of mode_T, so it has only */
123 /* one OUT register -> good */
124 /* 2nd case: irn is of mode_T -> collect all Projs and ask the */
125 /* Proj with the corresponding projnum for the register */
127 if (get_irn_mode(irn) != mode_T) {
129 reg = arch_get_irn_register(arch_env, irn);
130 } else if (is_ia32_irn(irn)) {
131 reg = get_ia32_out_reg(irn, pos);
133 const ir_edge_t *edge;
135 foreach_out_edge(irn, edge) {
136 proj = get_edge_src_irn(edge);
137 assert(is_Proj(proj) && "non-Proj from mode_T node");
138 if (get_Proj_proj(proj) == pos) {
139 reg = arch_get_irn_register(arch_env, proj);
145 assert(reg && "no out register found");
150 * Add a number to a prefix. This number will not be used a second time.
152 static char *get_unique_label(char *buf, size_t buflen, const char *prefix)
154 static unsigned long id = 0;
155 snprintf(buf, buflen, "%s%lu", prefix, ++id);
159 /*************************************************************
161 * (_) | | / _| | | | |
162 * _ __ _ __ _ _ __ | |_| |_ | |__ ___| |_ __ ___ _ __
163 * | '_ \| '__| | '_ \| __| _| | '_ \ / _ \ | '_ \ / _ \ '__|
164 * | |_) | | | | | | | |_| | | | | | __/ | |_) | __/ |
165 * | .__/|_| |_|_| |_|\__|_| |_| |_|\___|_| .__/ \___|_|
168 *************************************************************/
170 static void emit_8bit_register(const arch_register_t *reg)
172 const char *reg_name = arch_register_get_name(reg);
175 be_emit_char(reg_name[1]);
179 static void emit_16bit_register(const arch_register_t *reg)
181 const char *reg_name = ia32_get_mapped_reg_name(isa->regs_16bit, reg);
184 be_emit_string(reg_name);
187 static void emit_register(const arch_register_t *reg, const ir_mode *mode)
189 const char *reg_name;
192 int size = get_mode_size_bits(mode);
194 emit_8bit_register(reg);
196 } else if(size == 16) {
197 emit_16bit_register(reg);
200 assert(mode_is_float(mode) || size == 32);
204 reg_name = arch_register_get_name(reg);
207 be_emit_string(reg_name);
210 void ia32_emit_source_register(const ir_node *node, int pos)
212 const arch_register_t *reg = get_in_reg(node, pos);
214 emit_register(reg, NULL);
217 static void emit_ia32_Immediate(const ir_node *node);
219 void ia32_emit_8bit_source_register_or_immediate(const ir_node *node, int pos)
221 const arch_register_t *reg;
222 ir_node *in = get_irn_n(node, pos);
223 if(is_ia32_Immediate(in)) {
224 emit_ia32_Immediate(in);
228 reg = get_in_reg(node, pos);
229 emit_8bit_register(reg);
232 void ia32_emit_dest_register(const ir_node *node, int pos)
234 const arch_register_t *reg = get_out_reg(node, pos);
236 emit_register(reg, NULL);
239 void ia32_emit_8bit_dest_register(const ir_node *node, int pos)
241 const arch_register_t *reg = get_out_reg(node, pos);
243 emit_register(reg, mode_Bu);
246 void ia32_emit_x87_register(const ir_node *node, int pos)
248 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
252 be_emit_string(attr->x87[pos]->name);
255 static void ia32_emit_mode_suffix_mode(const ir_mode *mode)
257 if(mode_is_float(mode)) {
258 switch(get_mode_size_bits(mode)) {
259 case 32: be_emit_char('s'); return;
260 case 64: be_emit_char('l'); return;
262 case 96: be_emit_char('t'); return;
265 assert(mode_is_int(mode) || mode_is_reference(mode));
266 switch(get_mode_size_bits(mode)) {
267 case 64: be_emit_cstring("ll"); return;
268 /* gas docu says q is the suffix but gcc, objdump and icc use
270 case 32: be_emit_char('l'); return;
271 case 16: be_emit_char('w'); return;
272 case 8: be_emit_char('b'); return;
275 panic("Can't output mode_suffix for %+F\n", mode);
278 void ia32_emit_mode_suffix(const ir_node *node)
280 ir_mode *mode = get_ia32_ls_mode(node);
284 ia32_emit_mode_suffix_mode(mode);
287 void ia32_emit_x87_mode_suffix(const ir_node *node)
289 ir_mode *mode = get_ia32_ls_mode(node);
290 assert(mode != NULL);
291 /* we only need to emit the mode on address mode */
292 if(get_ia32_op_type(node) != ia32_Normal)
293 ia32_emit_mode_suffix_mode(mode);
297 char get_xmm_mode_suffix(ir_mode *mode)
299 assert(mode_is_float(mode));
300 switch(get_mode_size_bits(mode)) {
311 void ia32_emit_xmm_mode_suffix(const ir_node *node)
313 ir_mode *mode = get_ia32_ls_mode(node);
314 assert(mode != NULL);
316 be_emit_char(get_xmm_mode_suffix(mode));
319 void ia32_emit_xmm_mode_suffix_s(const ir_node *node)
321 ir_mode *mode = get_ia32_ls_mode(node);
322 assert(mode != NULL);
323 be_emit_char(get_xmm_mode_suffix(mode));
326 void ia32_emit_extend_suffix(const ir_mode *mode)
328 if(get_mode_size_bits(mode) == 32)
330 if(mode_is_signed(mode)) {
338 void ia32_emit_function_object(const char *name)
340 switch (be_gas_flavour) {
341 case GAS_FLAVOUR_NORMAL:
342 be_emit_cstring("\t.type\t");
343 be_emit_string(name);
344 be_emit_cstring(", @function\n");
345 be_emit_write_line();
347 case GAS_FLAVOUR_MINGW:
348 be_emit_cstring("\t.def\t");
349 be_emit_string(name);
350 be_emit_cstring(";\t.scl\t2;\t.type\t32;\t.endef\n");
351 be_emit_write_line();
359 void ia32_emit_function_size(const char *name)
361 switch (be_gas_flavour) {
362 case GAS_FLAVOUR_NORMAL:
363 be_emit_cstring("\t.size\t");
364 be_emit_string(name);
365 be_emit_cstring(", .-");
366 be_emit_string(name);
368 be_emit_write_line();
376 void ia32_emit_source_register_or_immediate(const ir_node *node, int pos)
378 ir_node *in = get_irn_n(node, pos);
379 if(is_ia32_Immediate(in)) {
380 emit_ia32_Immediate(in);
382 const ir_mode *mode = get_ia32_ls_mode(node);
383 const arch_register_t *reg = get_in_reg(node, pos);
384 emit_register(reg, mode);
389 * Emits registers and/or address mode of a binary operation.
391 void ia32_emit_binop(const ir_node *node) {
392 const ir_node *right_op = get_irn_n(node, n_ia32_binary_right);
393 const ir_mode *mode = get_ia32_ls_mode(node);
394 const arch_register_t *reg_left;
396 switch(get_ia32_op_type(node)) {
398 reg_left = get_in_reg(node, n_ia32_binary_left);
399 if(is_ia32_Immediate(right_op)) {
400 emit_ia32_Immediate(right_op);
401 be_emit_cstring(", ");
402 emit_register(reg_left, mode);
405 const arch_register_t *reg_right
406 = get_in_reg(node, n_ia32_binary_right);
407 emit_register(reg_right, mode);
408 be_emit_cstring(", ");
409 emit_register(reg_left, mode);
413 if(is_ia32_Immediate(right_op)) {
414 emit_ia32_Immediate(right_op);
415 be_emit_cstring(", ");
418 reg_left = get_in_reg(node, n_ia32_binary_left);
420 be_emit_cstring(", ");
421 emit_register(reg_left, mode);
425 panic("DestMode can't be output by %%binop anymore");
428 assert(0 && "unsupported op type");
433 * Emits registers and/or address mode of a binary operation.
435 void ia32_emit_x87_binop(const ir_node *node) {
436 switch(get_ia32_op_type(node)) {
439 const ia32_x87_attr_t *x87_attr = get_ia32_x87_attr_const(node);
440 const arch_register_t *in1 = x87_attr->x87[0];
441 const arch_register_t *in2 = x87_attr->x87[1];
442 const arch_register_t *out = x87_attr->x87[2];
443 const arch_register_t *in;
445 in = out ? ((out == in2) ? in1 : in2) : in2;
446 out = out ? out : in1;
449 be_emit_string(arch_register_get_name(in));
450 be_emit_cstring(", %");
451 be_emit_string(arch_register_get_name(out));
459 assert(0 && "unsupported op type");
463 void ia32_emit_am_or_dest_register(const ir_node *node,
465 if(get_ia32_op_type(node) == ia32_Normal) {
466 ia32_emit_dest_register(node, pos);
468 assert(get_ia32_op_type(node) == ia32_AddrModeD);
474 * Emits registers and/or address mode of a unary operation.
476 void ia32_emit_unop(const ir_node *node, int pos) {
479 switch(get_ia32_op_type(node)) {
481 op = get_irn_n(node, pos);
482 if (is_ia32_Immediate(op)) {
483 emit_ia32_Immediate(op);
485 ia32_emit_source_register(node, pos);
493 assert(0 && "unsupported op type");
498 * Emits address mode.
500 void ia32_emit_am(const ir_node *node) {
501 ir_entity *ent = get_ia32_am_sc(node);
502 int offs = get_ia32_am_offs_int(node);
503 ir_node *base = get_irn_n(node, 0);
504 int has_base = !is_ia32_NoReg_GP(base);
505 ir_node *index = get_irn_n(node, 1);
506 int has_index = !is_ia32_NoReg_GP(index);
508 /* just to be sure... */
509 assert(!is_ia32_use_frame(node) || get_ia32_frame_ent(node) != NULL);
515 set_entity_backend_marked(ent, 1);
516 id = get_entity_ld_ident(ent);
517 if (is_ia32_am_sc_sign(node))
521 if(get_entity_owner(ent) == get_tls_type()) {
522 if (get_entity_visibility(ent) == visibility_external_allocated) {
523 be_emit_cstring("@INDNTPOFF");
525 be_emit_cstring("@NTPOFF");
532 be_emit_irprintf("%+d", offs);
534 be_emit_irprintf("%d", offs);
538 if (has_base || has_index) {
543 const arch_register_t *reg = get_in_reg(node, n_ia32_base);
544 emit_register(reg, NULL);
547 /* emit index + scale */
549 const arch_register_t *reg = get_in_reg(node, n_ia32_index);
552 emit_register(reg, NULL);
554 scale = get_ia32_am_scale(node);
556 be_emit_irprintf(",%d", 1 << get_ia32_am_scale(node));
562 /* special case if nothing is set */
563 if(ent == NULL && offs == 0 && !has_base && !has_index) {
568 static void emit_ia32_IMul(const ir_node *node)
570 ir_node *left = get_irn_n(node, n_ia32_IMul_left);
571 const arch_register_t *out_reg = get_out_reg(node, pn_ia32_IMul_res);
573 be_emit_cstring("\timul");
574 ia32_emit_mode_suffix(node);
577 ia32_emit_binop(node);
579 /* do we need the 3-address form? */
580 if(is_ia32_NoReg_GP(left) ||
581 get_in_reg(node, n_ia32_IMul_left) != out_reg) {
582 be_emit_cstring(", ");
583 emit_register(out_reg, get_ia32_ls_mode(node));
585 be_emit_finish_line_gas(node);
588 /*************************************************
591 * ___ _ __ ___ _| |_ ___ ___ _ __ __| |
592 * / _ \ '_ ` _ \| | __| / __/ _ \| '_ \ / _` |
593 * | __/ | | | | | | |_ | (_| (_) | | | | (_| |
594 * \___|_| |_| |_|_|\__| \___\___/|_| |_|\__,_|
596 *************************************************/
599 #define IA32_DO_EMIT(irn) ia32_fprintf_format(F, irn, cmd_buf, cmnt_buf)
602 * coding of conditions
604 struct cmp2conditon_t {
610 * positive conditions for signed compares
612 static const struct cmp2conditon_t cmp2condition_s[] = {
613 { NULL, pn_Cmp_False }, /* always false */
614 { "e", pn_Cmp_Eq }, /* == */
615 { "l", pn_Cmp_Lt }, /* < */
616 { "le", pn_Cmp_Le }, /* <= */
617 { "g", pn_Cmp_Gt }, /* > */
618 { "ge", pn_Cmp_Ge }, /* >= */
619 { "ne", pn_Cmp_Lg }, /* != */
620 { NULL, pn_Cmp_Leg}, /* always true */
624 * positive conditions for unsigned compares
626 static const struct cmp2conditon_t cmp2condition_u[] = {
627 { NULL, pn_Cmp_False }, /* always false */
628 { "e", pn_Cmp_Eq }, /* == */
629 { "b", pn_Cmp_Lt }, /* < */
630 { "be", pn_Cmp_Le }, /* <= */
631 { "a", pn_Cmp_Gt }, /* > */
632 { "ae", pn_Cmp_Ge }, /* >= */
633 { "ne", pn_Cmp_Lg }, /* != */
634 { NULL, pn_Cmp_Leg }, /* always true */
638 ia32_pn_Cmp_unsigned = 0x1000,
639 ia32_pn_Cmp_float = 0x2000,
643 * walks up a tree of copies/perms/spills/reloads to find the original value
644 * that is moved around
646 static ir_node *find_original_value(ir_node *node)
648 inc_irg_visited(current_ir_graph);
650 mark_irn_visited(node);
651 if(be_is_Copy(node)) {
652 node = be_get_Copy_op(node);
653 } else if(be_is_CopyKeep(node)) {
654 node = be_get_CopyKeep_op(node);
655 } else if(is_Proj(node)) {
656 ir_node *pred = get_Proj_pred(node);
657 if(be_is_Perm(pred)) {
658 node = get_irn_n(pred, get_Proj_proj(node));
659 } else if(be_is_MemPerm(pred)) {
660 node = get_irn_n(pred, get_Proj_proj(node) + 1);
661 } else if(is_ia32_Load(pred)) {
662 node = get_irn_n(pred, n_ia32_Load_mem);
666 } else if(is_ia32_Store(node)) {
667 node = get_irn_n(node, n_ia32_Store_val);
668 } else if(is_Phi(node)) {
670 arity = get_irn_arity(node);
671 for(i = 0; i < arity; ++i) {
672 ir_node *in = get_irn_n(node, i);
685 static int determine_final_pnc(const ir_node *node, int flags_pos,
688 ir_node *flags = get_irn_n(node, flags_pos);
689 const ia32_attr_t *flags_attr;
690 flags = skip_Proj(flags);
692 if(is_ia32_Sahf(flags)) {
693 ir_node *cmp = get_irn_n(flags, n_ia32_Sahf_val);
694 if(!(is_ia32_FucomFnstsw(cmp) || is_ia32_FucompFnstsw(cmp)
695 || is_ia32_FucomppFnstsw(cmp) || is_ia32_FtstFnstsw(cmp))) {
696 cmp = find_original_value(cmp);
697 assert(is_ia32_FucomFnstsw(cmp) || is_ia32_FucompFnstsw(cmp)
698 || is_ia32_FucomppFnstsw(cmp) || is_ia32_FtstFnstsw(cmp));
701 flags_attr = get_ia32_attr_const(cmp);
702 if(flags_attr->data.ins_permuted)
703 pnc = get_mirrored_pnc(pnc);
704 pnc |= ia32_pn_Cmp_float;
705 } else if(is_ia32_Ucomi(flags) || is_ia32_Fucomi(flags)
706 || is_ia32_Fucompi(flags)) {
707 flags_attr = get_ia32_attr_const(flags);
709 if(flags_attr->data.ins_permuted)
710 pnc = get_mirrored_pnc(pnc);
711 pnc |= ia32_pn_Cmp_float;
713 assert(is_ia32_Cmp(flags) || is_ia32_Test(flags)
714 || is_ia32_Cmp8Bit(flags) || is_ia32_Test8Bit(flags));
715 flags_attr = get_ia32_attr_const(flags);
717 if(flags_attr->data.ins_permuted)
718 pnc = get_mirrored_pnc(pnc);
719 if(flags_attr->data.cmp_unsigned)
720 pnc |= ia32_pn_Cmp_unsigned;
726 static void ia32_emit_cmp_suffix(int pnc)
730 if((pnc & ia32_pn_Cmp_float) || (pnc & ia32_pn_Cmp_unsigned)) {
732 assert(cmp2condition_u[pnc].num == pnc);
733 str = cmp2condition_u[pnc].name;
736 assert(cmp2condition_s[pnc].num == pnc);
737 str = cmp2condition_s[pnc].name;
743 void ia32_emit_cmp_suffix_node(const ir_node *node,
746 const ia32_attr_t *attr = get_ia32_attr_const(node);
748 pn_Cmp pnc = get_ia32_condcode(node);
750 pnc = determine_final_pnc(node, flags_pos, pnc);
751 if(attr->data.ins_permuted) {
752 if(pnc & ia32_pn_Cmp_float) {
753 pnc = get_negated_pnc(pnc, mode_F);
755 pnc = get_negated_pnc(pnc, mode_Iu);
759 ia32_emit_cmp_suffix(pnc);
763 * Returns the target block for a control flow node.
766 ir_node *get_cfop_target_block(const ir_node *irn) {
767 return get_irn_link(irn);
771 * Emits a block label for the given block.
774 void ia32_emit_block_name(const ir_node *block)
776 if (has_Block_label(block)) {
777 be_emit_string(be_gas_label_prefix());
778 be_emit_irprintf("%u", (unsigned)get_Block_label(block));
780 be_emit_cstring(BLOCK_PREFIX);
781 be_emit_irprintf("%d", get_irn_node_nr(block));
786 * Emits the target label for a control flow node.
788 static void ia32_emit_cfop_target(const ir_node *node)
790 ir_node *block = get_cfop_target_block(node);
792 ia32_emit_block_name(block);
795 /** Return the next block in Block schedule */
796 static ir_node *next_blk_sched(const ir_node *block)
798 return get_irn_link(block);
802 * Returns the Proj with projection number proj and NOT mode_M
804 static ir_node *get_proj(const ir_node *node, long proj) {
805 const ir_edge_t *edge;
808 assert(get_irn_mode(node) == mode_T && "expected mode_T node");
810 foreach_out_edge(node, edge) {
811 src = get_edge_src_irn(edge);
813 assert(is_Proj(src) && "Proj expected");
814 if (get_irn_mode(src) == mode_M)
817 if (get_Proj_proj(src) == proj)
824 * Emits the jump sequence for a conditional jump (cmp + jmp_true + jmp_false)
826 static void emit_ia32_Jcc(const ir_node *node)
828 const ir_node *proj_true;
829 const ir_node *proj_false;
830 const ir_node *block;
831 const ir_node *next_block;
832 pn_Cmp pnc = get_ia32_condcode(node);
834 pnc = determine_final_pnc(node, 0, pnc);
837 proj_true = get_proj(node, pn_ia32_Jcc_true);
838 assert(proj_true && "Jcc without true Proj");
840 proj_false = get_proj(node, pn_ia32_Jcc_false);
841 assert(proj_false && "Jcc without false Proj");
843 block = get_nodes_block(node);
844 next_block = next_blk_sched(block);
846 if (get_cfop_target_block(proj_true) == next_block) {
847 /* exchange both proj's so the second one can be omitted */
848 const ir_node *t = proj_true;
850 proj_true = proj_false;
852 if(pnc & ia32_pn_Cmp_float) {
853 pnc = get_negated_pnc(pnc, mode_F);
855 pnc = get_negated_pnc(pnc, mode_Iu);
859 if (pnc & ia32_pn_Cmp_float) {
860 /* Some floating point comparisons require a test of the parity flag,
861 * which indicates that the result is unordered */
864 be_emit_cstring("\tjp ");
865 ia32_emit_cfop_target(proj_true);
866 be_emit_finish_line_gas(proj_true);
870 be_emit_cstring("\tjnp ");
871 ia32_emit_cfop_target(proj_true);
872 be_emit_finish_line_gas(proj_true);
878 be_emit_cstring("\tjp ");
879 ia32_emit_cfop_target(proj_false);
880 be_emit_finish_line_gas(proj_false);
886 be_emit_cstring("\tjp ");
887 ia32_emit_cfop_target(proj_true);
888 be_emit_finish_line_gas(proj_true);
896 be_emit_cstring("\tj");
897 ia32_emit_cmp_suffix(pnc);
899 ia32_emit_cfop_target(proj_true);
900 be_emit_finish_line_gas(proj_true);
903 /* the second Proj might be a fallthrough */
904 if (get_cfop_target_block(proj_false) != next_block) {
905 be_emit_cstring("\tjmp ");
906 ia32_emit_cfop_target(proj_false);
907 be_emit_finish_line_gas(proj_false);
909 be_emit_cstring("\t/* fallthrough to ");
910 ia32_emit_cfop_target(proj_false);
911 be_emit_cstring(" */");
912 be_emit_finish_line_gas(proj_false);
916 static void emit_ia32_CMov(const ir_node *node)
918 const ia32_attr_t *attr = get_ia32_attr_const(node);
919 int ins_permuted = attr->data.ins_permuted;
920 const arch_register_t *out = arch_get_irn_register(arch_env, node);
921 pn_Cmp pnc = get_ia32_condcode(node);
922 const arch_register_t *in_true;
923 const arch_register_t *in_false;
925 pnc = determine_final_pnc(node, n_ia32_CMov_eflags, pnc);
927 in_true = arch_get_irn_register(arch_env,
928 get_irn_n(node, n_ia32_CMov_val_true));
929 in_false = arch_get_irn_register(arch_env,
930 get_irn_n(node, n_ia32_CMov_val_false));
932 /* should be same constraint fullfilled? */
933 if(out == in_false) {
934 /* yes -> nothing to do */
935 } else if(out == in_true) {
936 const arch_register_t *tmp;
938 assert(get_ia32_op_type(node) == ia32_Normal);
940 ins_permuted = !ins_permuted;
947 be_emit_cstring("\tmovl ");
948 emit_register(in_false, NULL);
949 be_emit_cstring(", ");
950 emit_register(out, NULL);
951 be_emit_finish_line_gas(node);
955 if(pnc & ia32_pn_Cmp_float) {
956 pnc = get_negated_pnc(pnc, mode_F);
958 pnc = get_negated_pnc(pnc, mode_Iu);
962 /* TODO: handling of Nans isn't correct yet */
964 be_emit_cstring("\tcmov");
965 ia32_emit_cmp_suffix(pnc);
967 if(get_ia32_op_type(node) == ia32_AddrModeS) {
970 emit_register(in_true, get_ia32_ls_mode(node));
972 be_emit_cstring(", ");
973 emit_register(out, get_ia32_ls_mode(node));
974 be_emit_finish_line_gas(node);
977 /*********************************************************
980 * ___ _ __ ___ _| |_ _ _ _ _ __ ___ _ __ ___
981 * / _ \ '_ ` _ \| | __| | | | | | '_ ` _ \| '_ \/ __|
982 * | __/ | | | | | | |_ | | |_| | | | | | | |_) \__ \
983 * \___|_| |_| |_|_|\__| | |\__,_|_| |_| |_| .__/|___/
986 *********************************************************/
988 /* jump table entry (target and corresponding number) */
989 typedef struct _branch_t {
994 /* jump table for switch generation */
995 typedef struct _jmp_tbl_t {
996 ir_node *defProj; /**< default target */
997 long min_value; /**< smallest switch case */
998 long max_value; /**< largest switch case */
999 long num_branches; /**< number of jumps */
1000 char *label; /**< label of the jump table */
1001 branch_t *branches; /**< jump array */
1005 * Compare two variables of type branch_t. Used to sort all switch cases
1008 int ia32_cmp_branch_t(const void *a, const void *b) {
1009 branch_t *b1 = (branch_t *)a;
1010 branch_t *b2 = (branch_t *)b;
1012 if (b1->value <= b2->value)
1019 * Emits code for a SwitchJmp (creates a jump table if
1020 * possible otherwise a cmp-jmp cascade). Port from
1024 void emit_ia32_SwitchJmp(const ir_node *node) {
1025 unsigned long interval;
1030 const ir_edge_t *edge;
1032 /* fill the table structure */
1033 tbl.label = xmalloc(SNPRINTF_BUF_LEN);
1034 tbl.label = get_unique_label(tbl.label, SNPRINTF_BUF_LEN, ".TBL_");
1036 tbl.num_branches = get_irn_n_edges(node);
1037 tbl.branches = xcalloc(tbl.num_branches, sizeof(tbl.branches[0]));
1038 tbl.min_value = INT_MAX;
1039 tbl.max_value = INT_MIN;
1042 /* go over all proj's and collect them */
1043 foreach_out_edge(node, edge) {
1044 proj = get_edge_src_irn(edge);
1045 assert(is_Proj(proj) && "Only proj allowed at SwitchJmp");
1047 pnc = get_Proj_proj(proj);
1049 /* create branch entry */
1050 tbl.branches[i].target = proj;
1051 tbl.branches[i].value = pnc;
1053 tbl.min_value = pnc < tbl.min_value ? pnc : tbl.min_value;
1054 tbl.max_value = pnc > tbl.max_value ? pnc : tbl.max_value;
1056 /* check for default proj */
1057 if (pnc == get_ia32_condcode(node)) {
1058 assert(tbl.defProj == NULL && "found two defProjs at SwitchJmp");
1065 /* sort the branches by their number */
1066 qsort(tbl.branches, tbl.num_branches, sizeof(tbl.branches[0]), ia32_cmp_branch_t);
1068 /* two-complement's magic make this work without overflow */
1069 interval = tbl.max_value - tbl.min_value;
1071 /* emit the table */
1072 be_emit_cstring("\tcmpl $");
1073 be_emit_irprintf("%u, ", interval);
1074 ia32_emit_source_register(node, 0);
1075 be_emit_finish_line_gas(node);
1077 be_emit_cstring("\tja ");
1078 ia32_emit_cfop_target(tbl.defProj);
1079 be_emit_finish_line_gas(node);
1081 if (tbl.num_branches > 1) {
1083 be_emit_cstring("\tjmp *");
1084 be_emit_string(tbl.label);
1085 be_emit_cstring("(,");
1086 ia32_emit_source_register(node, 0);
1087 be_emit_cstring(",4)");
1088 be_emit_finish_line_gas(node);
1090 be_gas_emit_switch_section(GAS_SECTION_RODATA);
1091 be_emit_cstring("\t.align 4\n");
1092 be_emit_write_line();
1094 be_emit_string(tbl.label);
1095 be_emit_cstring(":\n");
1096 be_emit_write_line();
1098 be_emit_cstring(".long ");
1099 ia32_emit_cfop_target(tbl.branches[0].target);
1100 be_emit_finish_line_gas(NULL);
1102 last_value = tbl.branches[0].value;
1103 for (i = 1; i < tbl.num_branches; ++i) {
1104 while (++last_value < tbl.branches[i].value) {
1105 be_emit_cstring(".long ");
1106 ia32_emit_cfop_target(tbl.defProj);
1107 be_emit_finish_line_gas(NULL);
1109 be_emit_cstring(".long ");
1110 ia32_emit_cfop_target(tbl.branches[i].target);
1111 be_emit_finish_line_gas(NULL);
1113 be_gas_emit_switch_section(GAS_SECTION_TEXT);
1115 /* one jump is enough */
1116 be_emit_cstring("\tjmp ");
1117 ia32_emit_cfop_target(tbl.branches[0].target);
1118 be_emit_finish_line_gas(node);
1128 * Emits code for a unconditional jump.
1130 static void emit_Jmp(const ir_node *node)
1132 ir_node *block, *next_block;
1134 /* for now, the code works for scheduled and non-schedules blocks */
1135 block = get_nodes_block(node);
1137 /* we have a block schedule */
1138 next_block = next_blk_sched(block);
1139 if (get_cfop_target_block(node) != next_block) {
1140 be_emit_cstring("\tjmp ");
1141 ia32_emit_cfop_target(node);
1143 be_emit_cstring("\t/* fallthrough to ");
1144 ia32_emit_cfop_target(node);
1145 be_emit_cstring(" */");
1147 be_emit_finish_line_gas(node);
1150 static void emit_ia32_Immediate(const ir_node *node)
1152 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(node);
1155 if(attr->symconst != NULL) {
1156 ident *id = get_entity_ld_ident(attr->symconst);
1162 if(attr->symconst == NULL || attr->offset != 0) {
1163 if(attr->symconst != NULL) {
1164 be_emit_irprintf("%+d", attr->offset);
1166 be_emit_irprintf("0x%X", attr->offset);
1172 * Emit an inline assembler operand.
1174 * @param node the ia32_ASM node
1175 * @param s points to the operand (a %c)
1177 * @return pointer to the first char in s NOT in the current operand
1179 static const char* emit_asm_operand(const ir_node *node, const char *s)
1181 const ia32_attr_t *ia32_attr = get_ia32_attr_const(node);
1182 const ia32_asm_attr_t *attr = CONST_CAST_IA32_ATTR(ia32_asm_attr_t,
1184 const arch_register_t *reg;
1185 const ia32_asm_reg_t *asm_regs = attr->register_map;
1186 const ia32_asm_reg_t *asm_reg;
1187 const char *reg_name;
1196 /* parse modifiers */
1199 ir_fprintf(stderr, "Warning: asm text (%+F) ends with %\n", node);
1223 ir_fprintf(stderr, "Warning: asm text (%+F) contains unknown modifier "
1224 "'%c' for asm op\n", node, c);
1230 sscanf(s, "%d%n", &num, &p);
1232 ir_fprintf(stderr, "Warning: Couldn't parse assembler operand (%+F)\n",
1239 if(num < 0 || num >= ARR_LEN(asm_regs)) {
1240 ir_fprintf(stderr, "Error: Custom assembler references invalid "
1241 "input/output (%+F)\n", node);
1244 asm_reg = & asm_regs[num];
1245 assert(asm_reg->valid);
1248 if(asm_reg->use_input == 0) {
1249 reg = get_out_reg(node, asm_reg->inout_pos);
1251 ir_node *pred = get_irn_n(node, asm_reg->inout_pos);
1253 /* might be an immediate value */
1254 if(is_ia32_Immediate(pred)) {
1255 emit_ia32_Immediate(pred);
1258 reg = get_in_reg(node, asm_reg->inout_pos);
1261 ir_fprintf(stderr, "Warning: no register assigned for %d asm op "
1262 "(%+F)\n", num, node);
1266 if(asm_reg->memory) {
1275 reg_name = ia32_get_mapped_reg_name(isa->regs_8bit, reg);
1278 reg_name = ia32_get_mapped_reg_name(isa->regs_8bit_high, reg);
1281 reg_name = ia32_get_mapped_reg_name(isa->regs_16bit, reg);
1284 panic("Invalid asm op modifier");
1286 be_emit_string(reg_name);
1288 emit_register(reg, asm_reg->mode);
1291 if(asm_reg->memory) {
1299 * Emits code for an ASM pseudo op.
1301 static void emit_ia32_Asm(const ir_node *node)
1303 const void *gen_attr = get_irn_generic_attr_const(node);
1304 const ia32_asm_attr_t *attr
1305 = CONST_CAST_IA32_ATTR(ia32_asm_attr_t, gen_attr);
1306 ident *asm_text = attr->asm_text;
1307 const char *s = get_id_str(asm_text);
1309 be_emit_cstring("# Begin ASM \t");
1310 be_emit_finish_line_gas(node);
1317 s = emit_asm_operand(node, s);
1326 be_emit_write_line();
1328 be_emit_cstring("# End ASM\n");
1329 be_emit_write_line();
1332 /**********************************
1335 * | | ___ _ __ _ _| |_) |
1336 * | | / _ \| '_ \| | | | _ <
1337 * | |___| (_) | |_) | |_| | |_) |
1338 * \_____\___/| .__/ \__, |____/
1341 **********************************/
1344 * Emit movsb/w instructions to make mov count divideable by 4
1346 static void emit_CopyB_prolog(unsigned size) {
1347 be_emit_cstring("\tcld");
1348 be_emit_finish_line_gas(NULL);
1352 be_emit_cstring("\tmovsb");
1353 be_emit_finish_line_gas(NULL);
1356 be_emit_cstring("\tmovsw");
1357 be_emit_finish_line_gas(NULL);
1360 be_emit_cstring("\tmovsb");
1361 be_emit_finish_line_gas(NULL);
1362 be_emit_cstring("\tmovsw");
1363 be_emit_finish_line_gas(NULL);
1369 * Emit rep movsd instruction for memcopy.
1371 static void emit_ia32_CopyB(const ir_node *node)
1373 unsigned size = get_ia32_copyb_size(node);
1375 emit_CopyB_prolog(size);
1377 be_emit_cstring("\trep movsd");
1378 be_emit_finish_line_gas(node);
1382 * Emits unrolled memcopy.
1384 static void emit_ia32_CopyB_i(const ir_node *node)
1386 unsigned size = get_ia32_copyb_size(node);
1388 emit_CopyB_prolog(size & 0x3);
1392 be_emit_cstring("\tmovsd");
1393 be_emit_finish_line_gas(NULL);
1399 /***************************
1403 * | | / _ \| '_ \ \ / /
1404 * | |___| (_) | | | \ V /
1405 * \_____\___/|_| |_|\_/
1407 ***************************/
1410 * Emit code for conversions (I, FP), (FP, I) and (FP, FP).
1412 static void emit_ia32_Conv_with_FP(const ir_node *node)
1414 ir_mode *ls_mode = get_ia32_ls_mode(node);
1415 int ls_bits = get_mode_size_bits(ls_mode);
1417 be_emit_cstring("\tcvt");
1419 if(is_ia32_Conv_I2FP(node)) {
1421 be_emit_cstring("si2ss");
1423 be_emit_cstring("si2sd");
1425 } else if(is_ia32_Conv_FP2I(node)) {
1427 be_emit_cstring("ss2si");
1429 be_emit_cstring("sd2si");
1432 assert(is_ia32_Conv_FP2FP(node));
1434 be_emit_cstring("sd2ss");
1436 be_emit_cstring("ss2sd");
1441 switch(get_ia32_op_type(node)) {
1443 ia32_emit_source_register(node, n_ia32_unary_op);
1445 case ia32_AddrModeS:
1449 assert(0 && "unsupported op type for Conv");
1451 be_emit_cstring(", ");
1452 ia32_emit_dest_register(node, 0);
1453 be_emit_finish_line_gas(node);
1456 static void emit_ia32_Conv_I2FP(const ir_node *node)
1458 emit_ia32_Conv_with_FP(node);
1461 static void emit_ia32_Conv_FP2I(const ir_node *node)
1463 emit_ia32_Conv_with_FP(node);
1466 static void emit_ia32_Conv_FP2FP(const ir_node *node)
1468 emit_ia32_Conv_with_FP(node);
1472 * Emits code for an Int conversion.
1474 static void emit_ia32_Conv_I2I(const ir_node *node)
1476 const char *sign_suffix;
1477 ir_mode *smaller_mode = get_ia32_ls_mode(node);
1478 int smaller_bits = get_mode_size_bits(smaller_mode);
1480 const arch_register_t *in_reg, *out_reg;
1482 assert(!mode_is_float(smaller_mode));
1483 assert(smaller_bits == 8 || smaller_bits == 16 || smaller_bits == 32);
1485 signed_mode = mode_is_signed(smaller_mode);
1486 if(smaller_bits == 32) {
1487 // this should not happen as it's no convert
1491 sign_suffix = signed_mode ? "s" : "z";
1494 out_reg = get_out_reg(node, 0);
1496 switch(get_ia32_op_type(node)) {
1498 in_reg = get_in_reg(node, n_ia32_unary_op);
1500 if (in_reg == &ia32_gp_regs[REG_EAX] &&
1501 out_reg == &ia32_gp_regs[REG_EAX] &&
1505 /* argument and result are both in EAX and */
1506 /* signedness is ok: -> use the smaller cwtl opcode */
1507 be_emit_cstring("\tcwtl");
1509 be_emit_cstring("\tmov");
1510 be_emit_string(sign_suffix);
1511 ia32_emit_mode_suffix_mode(smaller_mode);
1512 be_emit_cstring("l ");
1513 emit_register(in_reg, smaller_mode);
1514 be_emit_cstring(", ");
1515 emit_register(out_reg, NULL);
1518 case ia32_AddrModeS: {
1519 be_emit_cstring("\tmov");
1520 be_emit_string(sign_suffix);
1521 ia32_emit_mode_suffix_mode(smaller_mode);
1522 be_emit_cstring("l ");
1524 be_emit_cstring(", ");
1525 emit_register(out_reg, NULL);
1529 assert(0 && "unsupported op type for Conv");
1531 be_emit_finish_line_gas(node);
1535 /*******************************************
1538 * | |__ ___ _ __ ___ __| | ___ ___
1539 * | '_ \ / _ \ '_ \ / _ \ / _` |/ _ \/ __|
1540 * | |_) | __/ | | | (_) | (_| | __/\__ \
1541 * |_.__/ \___|_| |_|\___/ \__,_|\___||___/
1543 *******************************************/
1546 * Emits a backend call
1548 static void emit_be_Call(const ir_node *node)
1550 ir_entity *ent = be_Call_get_entity(node);
1552 be_emit_cstring("\tcall ");
1554 set_entity_backend_marked(ent, 1);
1555 be_emit_string(get_entity_ld_name(ent));
1557 const arch_register_t *reg = get_in_reg(node, be_pos_Call_ptr);
1559 emit_register(reg, NULL);
1561 be_emit_finish_line_gas(node);
1565 * Emits code to increase stack pointer.
1567 static void emit_be_IncSP(const ir_node *node)
1569 int offs = be_get_IncSP_offset(node);
1570 const arch_register_t *reg = arch_get_irn_register(arch_env, node);
1576 be_emit_cstring("\tsubl $");
1577 be_emit_irprintf("%u, ", offs);
1578 emit_register(reg, NULL);
1580 be_emit_cstring("\taddl $");
1581 be_emit_irprintf("%u, ", -offs);
1582 emit_register(reg, NULL);
1584 be_emit_finish_line_gas(node);
1588 * Emits code for Copy/CopyKeep.
1590 static void Copy_emitter(const ir_node *node, const ir_node *op)
1592 const arch_register_t *in = arch_get_irn_register(arch_env, op);
1593 const arch_register_t *out = arch_get_irn_register(arch_env, node);
1599 if(is_unknown_reg(in))
1601 /* copies of vf nodes aren't real... */
1602 if(arch_register_get_class(in) == &ia32_reg_classes[CLASS_ia32_vfp])
1605 mode = get_irn_mode(node);
1606 if (mode == mode_E) {
1607 be_emit_cstring("\tmovsd ");
1608 emit_register(in, NULL);
1609 be_emit_cstring(", ");
1610 emit_register(out, NULL);
1612 be_emit_cstring("\tmovl ");
1613 emit_register(in, NULL);
1614 be_emit_cstring(", ");
1615 emit_register(out, NULL);
1617 be_emit_finish_line_gas(node);
1620 static void emit_be_Copy(const ir_node *node)
1622 Copy_emitter(node, be_get_Copy_op(node));
1625 static void emit_be_CopyKeep(const ir_node *node)
1627 Copy_emitter(node, be_get_CopyKeep_op(node));
1631 * Emits code for exchange.
1633 static void emit_be_Perm(const ir_node *node)
1635 const arch_register_t *in0, *in1;
1636 const arch_register_class_t *cls0, *cls1;
1638 in0 = arch_get_irn_register(arch_env, get_irn_n(node, 0));
1639 in1 = arch_get_irn_register(arch_env, get_irn_n(node, 1));
1641 cls0 = arch_register_get_class(in0);
1642 cls1 = arch_register_get_class(in1);
1644 assert(cls0 == cls1 && "Register class mismatch at Perm");
1646 if (cls0 == &ia32_reg_classes[CLASS_ia32_gp]) {
1647 be_emit_cstring("\txchg ");
1648 emit_register(in1, NULL);
1649 be_emit_cstring(", ");
1650 emit_register(in0, NULL);
1651 be_emit_finish_line_gas(node);
1652 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_xmm]) {
1653 be_emit_cstring("\txorpd ");
1654 emit_register(in1, NULL);
1655 be_emit_cstring(", ");
1656 emit_register(in0, NULL);
1657 be_emit_finish_line_gas(NULL);
1659 be_emit_cstring("\txorpd ");
1660 emit_register(in0, NULL);
1661 be_emit_cstring(", ");
1662 emit_register(in1, NULL);
1663 be_emit_finish_line_gas(NULL);
1665 be_emit_cstring("\txorpd ");
1666 emit_register(in1, NULL);
1667 be_emit_cstring(", ");
1668 emit_register(in0, NULL);
1669 be_emit_finish_line_gas(node);
1670 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_vfp]) {
1672 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_st]) {
1675 panic("unexpected register class in be_Perm (%+F)\n", node);
1680 * Emits code for Constant loading.
1682 static void emit_ia32_Const(const ir_node *node)
1684 be_emit_cstring("\tmovl ");
1685 emit_ia32_Immediate(node);
1686 be_emit_cstring(", ");
1687 ia32_emit_dest_register(node, 0);
1689 be_emit_finish_line_gas(node);
1693 * Emits code to load the TLS base
1695 static void emit_ia32_LdTls(const ir_node *node)
1697 be_emit_cstring("\tmovl %gs:0, ");
1698 ia32_emit_dest_register(node, 0);
1699 be_emit_finish_line_gas(node);
1702 /* helper function for emit_ia32_Minus64Bit */
1703 static void emit_mov(const ir_node* node, const arch_register_t *src, const arch_register_t *dst)
1705 be_emit_cstring("\tmovl ");
1706 emit_register(src, NULL);
1707 be_emit_cstring(", ");
1708 emit_register(dst, NULL);
1709 be_emit_finish_line_gas(node);
1712 /* helper function for emit_ia32_Minus64Bit */
1713 static void emit_neg(const ir_node* node, const arch_register_t *reg)
1715 be_emit_cstring("\tnegl ");
1716 emit_register(reg, NULL);
1717 be_emit_finish_line_gas(node);
1720 /* helper function for emit_ia32_Minus64Bit */
1721 static void emit_sbb0(const ir_node* node, const arch_register_t *reg)
1723 be_emit_cstring("\tsbbl $0, ");
1724 emit_register(reg, NULL);
1725 be_emit_finish_line_gas(node);
1728 /* helper function for emit_ia32_Minus64Bit */
1729 static void emit_sbb(const ir_node* node, const arch_register_t *src, const arch_register_t *dst)
1731 be_emit_cstring("\tsbbl ");
1732 emit_register(src, NULL);
1733 be_emit_cstring(", ");
1734 emit_register(dst, NULL);
1735 be_emit_finish_line_gas(node);
1738 /* helper function for emit_ia32_Minus64Bit */
1739 static void emit_xchg(const ir_node* node, const arch_register_t *src, const arch_register_t *dst)
1741 be_emit_cstring("\txchgl ");
1742 emit_register(src, NULL);
1743 be_emit_cstring(", ");
1744 emit_register(dst, NULL);
1745 be_emit_finish_line_gas(node);
1748 /* helper function for emit_ia32_Minus64Bit */
1749 static void emit_zero(const ir_node* node, const arch_register_t *reg)
1751 be_emit_cstring("\txorl ");
1752 emit_register(reg, NULL);
1753 be_emit_cstring(", ");
1754 emit_register(reg, NULL);
1755 be_emit_finish_line_gas(node);
1758 static void emit_ia32_Minus64Bit(const ir_node *node)
1760 const arch_register_t *in_lo = get_in_reg(node, 0);
1761 const arch_register_t *in_hi = get_in_reg(node, 1);
1762 const arch_register_t *out_lo = get_out_reg(node, 0);
1763 const arch_register_t *out_hi = get_out_reg(node, 1);
1765 if (out_lo == in_lo) {
1766 if (out_hi != in_hi) {
1767 /* a -> a, b -> d */
1770 /* a -> a, b -> b */
1773 } else if (out_lo == in_hi) {
1774 if (out_hi == in_lo) {
1775 /* a -> b, b -> a */
1776 emit_xchg(node, in_lo, in_hi);
1779 /* a -> b, b -> d */
1780 emit_mov(node, in_hi, out_hi);
1781 emit_mov(node, in_lo, out_lo);
1785 if (out_hi == in_lo) {
1786 /* a -> c, b -> a */
1787 emit_mov(node, in_lo, out_lo);
1789 } else if (out_hi == in_hi) {
1790 /* a -> c, b -> b */
1791 emit_mov(node, in_lo, out_lo);
1794 /* a -> c, b -> d */
1795 emit_mov(node, in_lo, out_lo);
1801 emit_neg( node, out_hi);
1802 emit_neg( node, out_lo);
1803 emit_sbb0(node, out_hi);
1807 emit_zero(node, out_hi);
1808 emit_neg( node, out_lo);
1809 emit_sbb( node, in_hi, out_hi);
1812 static void emit_be_Return(const ir_node *node)
1815 be_emit_cstring("\tret");
1817 pop = be_Return_get_pop(node);
1819 be_emit_irprintf(" $%d", pop);
1821 be_emit_finish_line_gas(node);
1824 static void emit_Nothing(const ir_node *node)
1830 /***********************************************************************************
1833 * _ __ ___ __ _ _ _ __ | |_ _ __ __ _ _ __ ___ _____ _____ _ __| | __
1834 * | '_ ` _ \ / _` | | '_ \ | _| '__/ _` | '_ ` _ \ / _ \ \ /\ / / _ \| '__| |/ /
1835 * | | | | | | (_| | | | | | | | | | | (_| | | | | | | __/\ V V / (_) | | | <
1836 * |_| |_| |_|\__,_|_|_| |_| |_| |_| \__,_|_| |_| |_|\___| \_/\_/ \___/|_| |_|\_\
1838 ***********************************************************************************/
1841 * Enters the emitter functions for handled nodes into the generic
1842 * pointer of an opcode.
1845 void ia32_register_emitters(void) {
1847 #define IA32_EMIT2(a,b) op_ia32_##a->ops.generic = (op_func)emit_ia32_##b
1848 #define IA32_EMIT(a) IA32_EMIT2(a,a)
1849 #define EMIT(a) op_##a->ops.generic = (op_func)emit_##a
1850 #define IGN(a) op_##a->ops.generic = (op_func)emit_Nothing
1851 #define BE_EMIT(a) op_be_##a->ops.generic = (op_func)emit_be_##a
1852 #define BE_IGN(a) op_be_##a->ops.generic = (op_func)emit_Nothing
1854 /* first clear the generic function pointer for all ops */
1855 clear_irp_opcodes_generic_func();
1857 /* register all emitter functions defined in spec */
1858 ia32_register_spec_emitters();
1860 /* other ia32 emitter functions */
1864 IA32_EMIT(SwitchJmp);
1867 IA32_EMIT(Conv_I2FP);
1868 IA32_EMIT(Conv_FP2I);
1869 IA32_EMIT(Conv_FP2FP);
1870 IA32_EMIT(Conv_I2I);
1871 IA32_EMIT2(Conv_I2I8Bit, Conv_I2I);
1874 IA32_EMIT(Minus64Bit);
1877 /* benode emitter */
1902 static const char *last_name = NULL;
1903 static unsigned last_line = -1;
1904 static unsigned num = -1;
1907 * Emit the debug support for node node.
1909 static void ia32_emit_dbg(const ir_node *node)
1911 dbg_info *db = get_irn_dbg_info(node);
1913 const char *fname = be_retrieve_dbg_info(db, &lineno);
1915 if (! cg->birg->main_env->options->stabs_debug_support)
1919 if (last_name != fname) {
1921 be_dbg_include_begin(cg->birg->main_env->db_handle, fname);
1924 if (last_line != lineno) {
1927 snprintf(name, sizeof(name), ".LM%u", ++num);
1929 be_dbg_line(cg->birg->main_env->db_handle, lineno, name);
1930 be_emit_string(name);
1931 be_emit_cstring(":\n");
1932 be_emit_write_line();
1937 typedef void (*emit_func_ptr) (const ir_node *);
1940 * Emits code for a node.
1942 static void ia32_emit_node(const ir_node *node)
1944 ir_op *op = get_irn_op(node);
1946 DBG((dbg, LEVEL_1, "emitting code for %+F\n", node));
1948 if (op->ops.generic) {
1949 emit_func_ptr func = (emit_func_ptr) op->ops.generic;
1950 ia32_emit_dbg(node);
1954 ir_fprintf(stderr, "Error: No emit handler for node %+F (%+G, graph %+F)\n", node, node, current_ir_graph);
1960 * Emits gas alignment directives
1962 static void ia32_emit_alignment(unsigned align, unsigned skip)
1964 be_emit_cstring("\t.p2align ");
1965 be_emit_irprintf("%u,,%u\n", align, skip);
1966 be_emit_write_line();
1970 * Emits gas alignment directives for Functions depended on cpu architecture.
1972 static void ia32_emit_align_func(void)
1974 unsigned align = ia32_cg_config.function_alignment;
1975 unsigned maximum_skip = (1 << align) - 1;
1977 ia32_emit_alignment(align, maximum_skip);
1981 * Emits gas alignment directives for Labels depended on cpu architecture.
1983 static void ia32_emit_align_label(void)
1985 unsigned align = ia32_cg_config.label_alignment;
1986 unsigned maximum_skip = (1 << align) - 1;
1987 ia32_emit_alignment(align, maximum_skip);
1991 * Test wether a block should be aligned.
1992 * For cpus in the P4/Athlon class it is useful to align jump labels to
1993 * 16 bytes. However we should only do that if the alignment nops before the
1994 * label aren't executed more often than we have jumps to the label.
1996 static int should_align_block(ir_node *block, ir_node *prev)
1998 static const double DELTA = .0001;
1999 ir_exec_freq *exec_freq = cg->birg->exec_freq;
2001 double prev_freq = 0; /**< execfreq of the fallthrough block */
2002 double jmp_freq = 0; /**< execfreq of all non-fallthrough blocks */
2005 if(exec_freq == NULL)
2007 if(ia32_cg_config.label_alignment_factor <= 0)
2010 block_freq = get_block_execfreq(exec_freq, block);
2011 if(block_freq < DELTA)
2014 n_cfgpreds = get_Block_n_cfgpreds(block);
2015 for(i = 0; i < n_cfgpreds; ++i) {
2016 ir_node *pred = get_Block_cfgpred_block(block, i);
2017 double pred_freq = get_block_execfreq(exec_freq, pred);
2020 prev_freq += pred_freq;
2022 jmp_freq += pred_freq;
2026 if(prev_freq < DELTA && !(jmp_freq < DELTA))
2029 jmp_freq /= prev_freq;
2031 return jmp_freq > ia32_cg_config.label_alignment_factor;
2034 static void ia32_emit_block_header(ir_node *block, ir_node *prev)
2039 ir_exec_freq *exec_freq = cg->birg->exec_freq;
2041 n_cfgpreds = get_Block_n_cfgpreds(block);
2042 need_label = (n_cfgpreds != 0);
2044 if (should_align_block(block, prev)) {
2046 ia32_emit_align_label();
2050 ia32_emit_block_name(block);
2053 be_emit_pad_comment();
2054 be_emit_cstring(" /* preds:");
2056 /* emit list of pred blocks in comment */
2057 arity = get_irn_arity(block);
2058 for (i = 0; i < arity; ++i) {
2059 ir_node *predblock = get_Block_cfgpred_block(block, i);
2060 be_emit_irprintf(" %d", get_irn_node_nr(predblock));
2063 be_emit_cstring("\t/* ");
2064 ia32_emit_block_name(block);
2065 be_emit_cstring(": ");
2067 if (exec_freq != NULL) {
2068 be_emit_irprintf(" freq: %f",
2069 get_block_execfreq(exec_freq, block));
2071 be_emit_cstring(" */\n");
2072 be_emit_write_line();
2076 * Walks over the nodes in a block connected by scheduling edges
2077 * and emits code for each node.
2079 static void ia32_gen_block(ir_node *block, ir_node *last_block)
2081 const ir_node *node;
2083 ia32_emit_block_header(block, last_block);
2085 /* emit the contents of the block */
2086 ia32_emit_dbg(block);
2087 sched_foreach(block, node) {
2088 ia32_emit_node(node);
2093 * Emits code for function start.
2095 static void ia32_emit_func_prolog(ir_graph *irg)
2097 ir_entity *irg_ent = get_irg_entity(irg);
2098 const char *irg_name = get_entity_ld_name(irg_ent);
2099 const be_irg_t *birg = cg->birg;
2101 /* write the begin line (used by scripts processing the assembler... */
2102 be_emit_write_line();
2103 be_emit_cstring("# -- Begin ");
2104 be_emit_string(irg_name);
2106 be_emit_write_line();
2108 be_gas_emit_switch_section(GAS_SECTION_TEXT);
2109 be_dbg_method_begin(birg->main_env->db_handle, irg_ent, be_abi_get_stack_layout(birg->abi));
2110 ia32_emit_align_func();
2111 if (get_entity_visibility(irg_ent) == visibility_external_visible) {
2112 be_emit_cstring(".global ");
2113 be_emit_string(irg_name);
2115 be_emit_write_line();
2117 ia32_emit_function_object(irg_name);
2118 be_emit_string(irg_name);
2119 be_emit_cstring(":\n");
2120 be_emit_write_line();
2124 * Emits code for function end
2126 static void ia32_emit_func_epilog(ir_graph *irg)
2128 const char *irg_name = get_entity_ld_name(get_irg_entity(irg));
2129 const be_irg_t *birg = cg->birg;
2131 ia32_emit_function_size(irg_name);
2132 be_dbg_method_end(birg->main_env->db_handle);
2134 be_emit_cstring("# -- End ");
2135 be_emit_string(irg_name);
2137 be_emit_write_line();
2140 be_emit_write_line();
2145 * Sets labels for control flow nodes (jump target)
2147 static void ia32_gen_labels(ir_node *block, void *data)
2150 int n = get_Block_n_cfgpreds(block);
2153 for (n--; n >= 0; n--) {
2154 pred = get_Block_cfgpred(block, n);
2155 set_irn_link(pred, block);
2160 * Emit an exception label if the current instruction can fail.
2162 void ia32_emit_exc_label(const ir_node *node)
2164 if (get_ia32_exc_label(node)) {
2165 be_emit_irprintf(".EXL%u\n", 0);
2166 be_emit_write_line();
2171 * Main driver. Emits the code for one routine.
2173 void ia32_gen_routine(ia32_code_gen_t *ia32_cg, ir_graph *irg)
2176 ir_node *last_block = NULL;
2180 isa = (const ia32_isa_t*) cg->arch_env->isa;
2181 arch_env = cg->arch_env;
2183 ia32_register_emitters();
2185 ia32_emit_func_prolog(irg);
2186 irg_block_walk_graph(irg, ia32_gen_labels, NULL, NULL);
2188 n = ARR_LEN(cg->blk_sched);
2189 for (i = 0; i < n;) {
2192 block = cg->blk_sched[i];
2194 next_bl = i < n ? cg->blk_sched[i] : NULL;
2196 /* set here the link. the emitter expects to find the next block here */
2197 set_irn_link(block, next_bl);
2198 ia32_gen_block(block, last_block);
2202 ia32_emit_func_epilog(irg);
2205 void ia32_init_emitter(void)
2207 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.emitter");