2 * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This file implements the ia32 node emitter.
23 * @author Christian Wuerdig, Matthias Braun
39 #include "iredges_t.h"
42 #include "raw_bitset.h"
45 #include "../besched_t.h"
46 #include "../benode_t.h"
48 #include "../be_dbgout.h"
49 #include "../beemitter.h"
50 #include "../begnuas.h"
51 #include "../beirg_t.h"
52 #include "../be_dbgout.h"
54 #include "ia32_emitter.h"
55 #include "gen_ia32_emitter.h"
56 #include "gen_ia32_regalloc_if.h"
57 #include "ia32_nodes_attr.h"
58 #include "ia32_new_nodes.h"
59 #include "ia32_map_regs.h"
60 #include "ia32_architecture.h"
61 #include "bearch_ia32_t.h"
63 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
65 #define BLOCK_PREFIX ".L"
67 #define SNPRINTF_BUF_LEN 128
69 static const ia32_isa_t *isa;
70 static ia32_code_gen_t *cg;
72 static char pic_base_label[128];
73 static ir_label_t exc_label_id;
74 static int mark_spill_reload = 0;
76 /** Return the next block in Block schedule */
77 static ir_node *get_prev_block_sched(const ir_node *block)
79 return get_irn_link(block);
82 /** Checks if the current block is a fall-through target. */
83 static int is_fallthrough(const ir_node *cfgpred)
87 if (!is_Proj(cfgpred))
89 pred = get_Proj_pred(cfgpred);
90 if (is_ia32_SwitchJmp(pred))
97 * returns non-zero if the given block needs a label
98 * because of being a jump-target (and not a fall-through)
100 static int block_needs_label(const ir_node *block)
103 int n_cfgpreds = get_Block_n_cfgpreds(block);
105 if (n_cfgpreds == 0) {
107 } else if (n_cfgpreds == 1) {
108 ir_node *cfgpred = get_Block_cfgpred(block, 0);
109 ir_node *cfgpred_block = get_nodes_block(cfgpred);
111 if (get_prev_block_sched(block) == cfgpred_block
112 && is_fallthrough(cfgpred)) {
121 * Returns the register at in position pos.
123 static const arch_register_t *get_in_reg(const ir_node *irn, int pos)
126 const arch_register_t *reg = NULL;
128 assert(get_irn_arity(irn) > pos && "Invalid IN position");
130 /* The out register of the operator at position pos is the
131 in register we need. */
132 op = get_irn_n(irn, pos);
134 reg = arch_get_irn_register(op);
136 assert(reg && "no in register found");
138 if (reg == &ia32_gp_regs[REG_GP_NOREG])
139 panic("trying to emit noreg for %+F input %d", irn, pos);
141 /* in case of unknown register: just return a valid register */
142 if (reg == &ia32_gp_regs[REG_GP_UKNWN]) {
143 const arch_register_req_t *req = arch_get_register_req(irn, pos);
145 if (arch_register_req_is(req, limited)) {
146 /* in case of limited requirements: get the first allowed register */
147 unsigned idx = rbitset_next(req->limited, 0, 1);
148 reg = arch_register_for_index(req->cls, idx);
150 /* otherwise get first register in class */
151 reg = arch_register_for_index(req->cls, 0);
159 * Returns the register at out position pos.
161 static const arch_register_t *get_out_reg(const ir_node *irn, int pos)
164 const arch_register_t *reg = NULL;
166 /* 1st case: irn is not of mode_T, so it has only */
167 /* one OUT register -> good */
168 /* 2nd case: irn is of mode_T -> collect all Projs and ask the */
169 /* Proj with the corresponding projnum for the register */
171 if (get_irn_mode(irn) != mode_T) {
173 reg = arch_get_irn_register(irn);
174 } else if (is_ia32_irn(irn)) {
175 reg = arch_irn_get_register(irn, pos);
177 const ir_edge_t *edge;
179 foreach_out_edge(irn, edge) {
180 proj = get_edge_src_irn(edge);
181 assert(is_Proj(proj) && "non-Proj from mode_T node");
182 if (get_Proj_proj(proj) == pos) {
183 reg = arch_get_irn_register(proj);
189 assert(reg && "no out register found");
194 * Add a number to a prefix. This number will not be used a second time.
196 static char *get_unique_label(char *buf, size_t buflen, const char *prefix)
198 static unsigned long id = 0;
199 snprintf(buf, buflen, "%s%lu", prefix, ++id);
203 /*************************************************************
205 * (_) | | / _| | | | |
206 * _ __ _ __ _ _ __ | |_| |_ | |__ ___| |_ __ ___ _ __
207 * | '_ \| '__| | '_ \| __| _| | '_ \ / _ \ | '_ \ / _ \ '__|
208 * | |_) | | | | | | | |_| | | | | | __/ | |_) | __/ |
209 * | .__/|_| |_|_| |_|\__|_| |_| |_|\___|_| .__/ \___|_|
212 *************************************************************/
214 static void emit_8bit_register(const arch_register_t *reg)
216 const char *reg_name = arch_register_get_name(reg);
219 be_emit_char(reg_name[1]);
223 static void emit_16bit_register(const arch_register_t *reg)
225 const char *reg_name = ia32_get_mapped_reg_name(isa->regs_16bit, reg);
228 be_emit_string(reg_name);
231 static void emit_register(const arch_register_t *reg, const ir_mode *mode)
233 const char *reg_name;
236 int size = get_mode_size_bits(mode);
238 case 8: emit_8bit_register(reg); return;
239 case 16: emit_16bit_register(reg); return;
241 assert(mode_is_float(mode) || size == 32);
244 reg_name = arch_register_get_name(reg);
247 be_emit_string(reg_name);
250 void ia32_emit_source_register(const ir_node *node, int pos)
252 const arch_register_t *reg = get_in_reg(node, pos);
254 emit_register(reg, NULL);
257 static void ia32_emit_entity(ir_entity *entity, int no_pic_adjust)
261 set_entity_backend_marked(entity, 1);
262 id = get_entity_ld_ident(entity);
265 if (get_entity_owner(entity) == get_tls_type()) {
266 if (get_entity_visibility(entity) == visibility_external_allocated) {
267 be_emit_cstring("@INDNTPOFF");
269 be_emit_cstring("@NTPOFF");
273 if (!no_pic_adjust && do_pic) {
274 /* TODO: only do this when necessary */
276 be_emit_string(pic_base_label);
280 static void emit_ia32_Immediate_no_prefix(const ir_node *node)
282 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(node);
284 if (attr->symconst != NULL) {
287 ia32_emit_entity(attr->symconst, 0);
289 if (attr->symconst == NULL || attr->offset != 0) {
290 if (attr->symconst != NULL) {
291 be_emit_irprintf("%+d", attr->offset);
293 be_emit_irprintf("0x%X", attr->offset);
298 static void emit_ia32_Immediate(const ir_node *node)
301 emit_ia32_Immediate_no_prefix(node);
304 void ia32_emit_8bit_source_register_or_immediate(const ir_node *node, int pos)
306 const arch_register_t *reg;
307 ir_node *in = get_irn_n(node, pos);
308 if (is_ia32_Immediate(in)) {
309 emit_ia32_Immediate(in);
313 reg = get_in_reg(node, pos);
314 emit_8bit_register(reg);
317 void ia32_emit_dest_register(const ir_node *node, int pos)
319 const arch_register_t *reg = get_out_reg(node, pos);
321 emit_register(reg, NULL);
324 void ia32_emit_8bit_dest_register(const ir_node *node, int pos)
326 const arch_register_t *reg = get_out_reg(node, pos);
328 emit_register(reg, mode_Bu);
331 void ia32_emit_x87_register(const ir_node *node, int pos)
333 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
337 be_emit_string(attr->x87[pos]->name);
340 static void ia32_emit_mode_suffix_mode(const ir_mode *mode)
342 assert(mode_is_int(mode) || mode_is_reference(mode));
343 switch (get_mode_size_bits(mode)) {
344 case 8: be_emit_char('b'); return;
345 case 16: be_emit_char('w'); return;
346 case 32: be_emit_char('l'); return;
347 /* gas docu says q is the suffix but gcc, objdump and icc use ll
349 case 64: be_emit_cstring("ll"); return;
351 panic("Can't output mode_suffix for %+F", mode);
354 void ia32_emit_mode_suffix(const ir_node *node)
356 ir_mode *mode = get_ia32_ls_mode(node);
360 ia32_emit_mode_suffix_mode(mode);
363 void ia32_emit_x87_mode_suffix(const ir_node *node)
367 /* we only need to emit the mode on address mode */
368 if (get_ia32_op_type(node) == ia32_Normal)
371 mode = get_ia32_ls_mode(node);
372 assert(mode != NULL);
374 if (mode_is_float(mode)) {
375 switch (get_mode_size_bits(mode)) {
376 case 32: be_emit_char('s'); return;
377 case 64: be_emit_char('l'); return;
379 case 96: be_emit_char('t'); return;
382 assert(mode_is_int(mode));
383 switch (get_mode_size_bits(mode)) {
384 case 16: be_emit_char('s'); return;
385 case 32: be_emit_char('l'); return;
386 /* gas docu says q is the suffix but gcc, objdump and icc use ll
388 case 64: be_emit_cstring("ll"); return;
391 panic("Can't output mode_suffix for %+F", mode);
394 static char get_xmm_mode_suffix(ir_mode *mode)
396 assert(mode_is_float(mode));
397 switch(get_mode_size_bits(mode)) {
400 default: panic("Invalid XMM mode");
404 void ia32_emit_xmm_mode_suffix(const ir_node *node)
406 ir_mode *mode = get_ia32_ls_mode(node);
407 assert(mode != NULL);
409 be_emit_char(get_xmm_mode_suffix(mode));
412 void ia32_emit_xmm_mode_suffix_s(const ir_node *node)
414 ir_mode *mode = get_ia32_ls_mode(node);
415 assert(mode != NULL);
416 be_emit_char(get_xmm_mode_suffix(mode));
419 void ia32_emit_extend_suffix(const ir_mode *mode)
421 if (get_mode_size_bits(mode) == 32)
423 be_emit_char(mode_is_signed(mode) ? 's' : 'z');
426 void ia32_emit_source_register_or_immediate(const ir_node *node, int pos)
428 ir_node *in = get_irn_n(node, pos);
429 if (is_ia32_Immediate(in)) {
430 emit_ia32_Immediate(in);
432 const ir_mode *mode = get_ia32_ls_mode(node);
433 const arch_register_t *reg = get_in_reg(node, pos);
434 emit_register(reg, mode);
439 * Returns the target block for a control flow node.
441 static ir_node *get_cfop_target_block(const ir_node *irn)
443 assert(get_irn_mode(irn) == mode_X);
444 return get_irn_link(irn);
448 * Emits a block label for the given block.
450 static void ia32_emit_block_name(const ir_node *block)
452 if (has_Block_label(block)) {
453 be_emit_string(be_gas_block_label_prefix());
454 be_emit_irprintf("%lu", get_Block_label(block));
456 be_emit_cstring(BLOCK_PREFIX);
457 be_emit_irprintf("%ld", get_irn_node_nr(block));
462 * Emits the target label for a control flow node.
464 static void ia32_emit_cfop_target(const ir_node *node)
466 ir_node *block = get_cfop_target_block(node);
467 ia32_emit_block_name(block);
471 * positive conditions for signed compares
473 static const char *const cmp2condition_s[] = {
474 NULL, /* always false */
481 NULL /* always true */
485 * positive conditions for unsigned compares
487 static const char *const cmp2condition_u[] = {
488 NULL, /* always false */
495 NULL /* always true */
498 static void ia32_emit_cmp_suffix(int pnc)
502 if (pnc & ia32_pn_Cmp_float || pnc & ia32_pn_Cmp_unsigned) {
503 str = cmp2condition_u[pnc & 7];
505 str = cmp2condition_s[pnc & 7];
511 typedef enum ia32_emit_mod_t {
512 EMIT_RESPECT_LS = 1U << 0,
513 EMIT_ALTERNATE_AM = 1U << 1,
518 * fmt parameter output
519 * ---- ---------------------- ---------------------------------------------
521 * %AM <node> address mode of the node
522 * %AR const arch_register_t* address mode of the node or register
523 * %ASx <node> address mode of the node or source register x
524 * %Dx <node> destination register x
525 * %I <node> immediate of the node
526 * %L <node> control flow target of the node
527 * %M <node> mode suffix of the node
528 * %P int condition code
529 * %R const arch_register_t* register
530 * %Sx <node> source register x
531 * %s const char* string
532 * %u unsigned int unsigned int
533 * %d signed int signed int
536 * # modifier for %ASx, %D and %S uses ls mode of node to alter register width
537 * * modifier does not prefix immediates with $, but AM with *
538 * l modifier for %lu and %ld
540 static void ia32_emitf(const ir_node *node, const char *fmt, ...)
546 const char *start = fmt;
547 ia32_emit_mod_t mod = 0;
549 while (*fmt != '%' && *fmt != '\n' && *fmt != '\0')
552 be_emit_string_len(start, fmt - start);
556 be_emit_finish_line_gas(node);
568 mod |= EMIT_ALTERNATE_AM;
573 mod |= EMIT_RESPECT_LS;
590 if (mod & EMIT_ALTERNATE_AM)
596 const arch_register_t *reg = va_arg(ap, const arch_register_t*);
597 if (mod & EMIT_ALTERNATE_AM)
599 if (get_ia32_op_type(node) == ia32_AddrModeS) {
602 emit_register(reg, NULL);
608 if (get_ia32_op_type(node) == ia32_AddrModeS) {
609 if (mod & EMIT_ALTERNATE_AM)
614 assert(get_ia32_op_type(node) == ia32_Normal);
619 default: goto unknown;
626 const arch_register_t *reg;
628 if (*fmt < '0' || '9' <= *fmt)
632 reg = get_out_reg(node, pos);
633 emit_register(reg, mod & EMIT_RESPECT_LS ? get_ia32_ls_mode(node) : NULL);
638 if (!(mod & EMIT_ALTERNATE_AM))
640 emit_ia32_Immediate_no_prefix(node);
644 ia32_emit_cfop_target(node);
648 ia32_emit_mode_suffix_mode(get_ia32_ls_mode(node));
653 int pnc = va_arg(ap, int);
654 ia32_emit_cmp_suffix(pnc);
659 const arch_register_t *reg = va_arg(ap, const arch_register_t*);
660 emit_register(reg, NULL);
669 if (*fmt < '0' || '9' <= *fmt)
673 in = get_irn_n(node, pos);
674 if (is_ia32_Immediate(in)) {
675 if (!(mod & EMIT_ALTERNATE_AM))
677 emit_ia32_Immediate_no_prefix(in);
679 const arch_register_t *reg;
681 if (mod & EMIT_ALTERNATE_AM)
683 reg = get_in_reg(node, pos);
684 emit_register(reg, mod & EMIT_RESPECT_LS ? get_ia32_ls_mode(node) : NULL);
690 const char *str = va_arg(ap, const char*);
696 if (mod & EMIT_LONG) {
697 unsigned long num = va_arg(ap, unsigned long);
698 be_emit_irprintf("%lu", num);
700 unsigned num = va_arg(ap, unsigned);
701 be_emit_irprintf("%u", num);
706 if (mod & EMIT_LONG) {
707 long num = va_arg(ap, long);
708 be_emit_irprintf("%ld", num);
710 int num = va_arg(ap, int);
711 be_emit_irprintf("%d", num);
717 panic("unknown format conversion in ia32_emitf()");
725 * Emits registers and/or address mode of a binary operation.
727 void ia32_emit_binop(const ir_node *node)
729 if (is_ia32_Immediate(get_irn_n(node, n_ia32_binary_right))) {
730 ia32_emitf(node, "%#S4, %#AS3");
732 ia32_emitf(node, "%#AS4, %#S3");
737 * Emits registers and/or address mode of a binary operation.
739 void ia32_emit_x87_binop(const ir_node *node)
741 switch(get_ia32_op_type(node)) {
744 const ia32_x87_attr_t *x87_attr = get_ia32_x87_attr_const(node);
745 const arch_register_t *in1 = x87_attr->x87[0];
746 const arch_register_t *in = x87_attr->x87[1];
747 const arch_register_t *out = x87_attr->x87[2];
751 } else if (out == in) {
756 be_emit_string(arch_register_get_name(in));
757 be_emit_cstring(", %");
758 be_emit_string(arch_register_get_name(out));
766 assert(0 && "unsupported op type");
771 * Emits registers and/or address mode of a unary operation.
773 void ia32_emit_unop(const ir_node *node, int pos)
777 ia32_emitf(node, fmt);
781 * Emits address mode.
783 void ia32_emit_am(const ir_node *node)
785 ir_entity *ent = get_ia32_am_sc(node);
786 int offs = get_ia32_am_offs_int(node);
787 ir_node *base = get_irn_n(node, n_ia32_base);
788 int has_base = !is_ia32_NoReg_GP(base);
789 ir_node *index = get_irn_n(node, n_ia32_index);
790 int has_index = !is_ia32_NoReg_GP(index);
792 /* just to be sure... */
793 assert(!is_ia32_use_frame(node) || get_ia32_frame_ent(node) != NULL);
797 if (is_ia32_am_sc_sign(node))
799 ia32_emit_entity(ent, 0);
802 /* also handle special case if nothing is set */
803 if (offs != 0 || (ent == NULL && !has_base && !has_index)) {
805 be_emit_irprintf("%+d", offs);
807 be_emit_irprintf("%d", offs);
811 if (has_base || has_index) {
816 const arch_register_t *reg = get_in_reg(node, n_ia32_base);
817 emit_register(reg, NULL);
820 /* emit index + scale */
822 const arch_register_t *reg = get_in_reg(node, n_ia32_index);
825 emit_register(reg, NULL);
827 scale = get_ia32_am_scale(node);
829 be_emit_irprintf(",%d", 1 << scale);
836 static void emit_ia32_IMul(const ir_node *node)
838 ir_node *left = get_irn_n(node, n_ia32_IMul_left);
839 const arch_register_t *out_reg = get_out_reg(node, pn_ia32_IMul_res);
841 /* do we need the 3-address form? */
842 if (is_ia32_NoReg_GP(left) ||
843 get_in_reg(node, n_ia32_IMul_left) != out_reg) {
844 ia32_emitf(node, "\timul%M %#S4, %#AS3, %#D0\n");
846 ia32_emitf(node, "\timul%M %#AS4, %#S3\n");
851 * walks up a tree of copies/perms/spills/reloads to find the original value
852 * that is moved around
854 static ir_node *find_original_value(ir_node *node)
856 if (irn_visited(node))
859 mark_irn_visited(node);
860 if (be_is_Copy(node)) {
861 return find_original_value(be_get_Copy_op(node));
862 } else if (be_is_CopyKeep(node)) {
863 return find_original_value(be_get_CopyKeep_op(node));
864 } else if (is_Proj(node)) {
865 ir_node *pred = get_Proj_pred(node);
866 if (be_is_Perm(pred)) {
867 return find_original_value(get_irn_n(pred, get_Proj_proj(node)));
868 } else if (be_is_MemPerm(pred)) {
869 return find_original_value(get_irn_n(pred, get_Proj_proj(node) + 1));
870 } else if (is_ia32_Load(pred)) {
871 return find_original_value(get_irn_n(pred, n_ia32_Load_mem));
875 } else if (is_ia32_Store(node)) {
876 return find_original_value(get_irn_n(node, n_ia32_Store_val));
877 } else if (is_Phi(node)) {
879 arity = get_irn_arity(node);
880 for (i = 0; i < arity; ++i) {
881 ir_node *in = get_irn_n(node, i);
882 ir_node *res = find_original_value(in);
893 static int determine_final_pnc(const ir_node *node, int flags_pos,
896 ir_node *flags = get_irn_n(node, flags_pos);
897 const ia32_attr_t *flags_attr;
898 flags = skip_Proj(flags);
900 if (is_ia32_Sahf(flags)) {
901 ir_node *cmp = get_irn_n(flags, n_ia32_Sahf_val);
902 if (!(is_ia32_FucomFnstsw(cmp) || is_ia32_FucompFnstsw(cmp)
903 || is_ia32_FucomppFnstsw(cmp) || is_ia32_FtstFnstsw(cmp))) {
904 inc_irg_visited(current_ir_graph);
905 cmp = find_original_value(cmp);
907 assert(is_ia32_FucomFnstsw(cmp) || is_ia32_FucompFnstsw(cmp)
908 || is_ia32_FucomppFnstsw(cmp) || is_ia32_FtstFnstsw(cmp));
911 flags_attr = get_ia32_attr_const(cmp);
912 if (flags_attr->data.ins_permuted)
913 pnc = get_mirrored_pnc(pnc);
914 pnc |= ia32_pn_Cmp_float;
915 } else if (is_ia32_Ucomi(flags) || is_ia32_Fucomi(flags)
916 || is_ia32_Fucompi(flags)) {
917 flags_attr = get_ia32_attr_const(flags);
919 if (flags_attr->data.ins_permuted)
920 pnc = get_mirrored_pnc(pnc);
921 pnc |= ia32_pn_Cmp_float;
923 flags_attr = get_ia32_attr_const(flags);
925 if (flags_attr->data.ins_permuted)
926 pnc = get_mirrored_pnc(pnc);
927 if (flags_attr->data.cmp_unsigned)
928 pnc |= ia32_pn_Cmp_unsigned;
934 static pn_Cmp ia32_get_negated_pnc(pn_Cmp pnc)
936 ir_mode *mode = pnc & ia32_pn_Cmp_float ? mode_F : mode_Iu;
937 return get_negated_pnc(pnc, mode);
940 void ia32_emit_cmp_suffix_node(const ir_node *node,
943 const ia32_attr_t *attr = get_ia32_attr_const(node);
945 pn_Cmp pnc = get_ia32_condcode(node);
947 pnc = determine_final_pnc(node, flags_pos, pnc);
948 if (attr->data.ins_permuted)
949 pnc = ia32_get_negated_pnc(pnc);
951 ia32_emit_cmp_suffix(pnc);
955 * Emits an exception label for a given node.
957 static void ia32_emit_exc_label(const ir_node *node)
959 be_emit_string(be_gas_insn_label_prefix());
960 be_emit_irprintf("%lu", get_ia32_exc_label_id(node));
964 * Returns the Proj with projection number proj and NOT mode_M
966 static ir_node *get_proj(const ir_node *node, long proj)
968 const ir_edge_t *edge;
971 assert(get_irn_mode(node) == mode_T && "expected mode_T node");
973 foreach_out_edge(node, edge) {
974 src = get_edge_src_irn(edge);
976 assert(is_Proj(src) && "Proj expected");
977 if (get_irn_mode(src) == mode_M)
980 if (get_Proj_proj(src) == proj)
986 static int can_be_fallthrough(const ir_node *node)
988 ir_node *target_block = get_cfop_target_block(node);
989 ir_node *block = get_nodes_block(node);
990 return get_prev_block_sched(target_block) == block;
994 * Emits the jump sequence for a conditional jump (cmp + jmp_true + jmp_false)
996 static void emit_ia32_Jcc(const ir_node *node)
998 int need_parity_label = 0;
999 const ir_node *proj_true;
1000 const ir_node *proj_false;
1001 const ir_node *block;
1002 pn_Cmp pnc = get_ia32_condcode(node);
1004 pnc = determine_final_pnc(node, 0, pnc);
1006 /* get both Projs */
1007 proj_true = get_proj(node, pn_ia32_Jcc_true);
1008 assert(proj_true && "Jcc without true Proj");
1010 proj_false = get_proj(node, pn_ia32_Jcc_false);
1011 assert(proj_false && "Jcc without false Proj");
1013 block = get_nodes_block(node);
1015 if (can_be_fallthrough(proj_true)) {
1016 /* exchange both proj's so the second one can be omitted */
1017 const ir_node *t = proj_true;
1019 proj_true = proj_false;
1021 pnc = ia32_get_negated_pnc(pnc);
1024 if (pnc & ia32_pn_Cmp_float) {
1025 /* Some floating point comparisons require a test of the parity flag,
1026 * which indicates that the result is unordered */
1029 ia32_emitf(proj_true, "\tjp %L\n");
1034 ia32_emitf(proj_true, "\tjnp %L\n");
1040 /* we need a local label if the false proj is a fallthrough
1041 * as the falseblock might have no label emitted then */
1042 if (can_be_fallthrough(proj_false)) {
1043 need_parity_label = 1;
1044 ia32_emitf(proj_false, "\tjp 1f\n");
1046 ia32_emitf(proj_false, "\tjp %L\n");
1053 ia32_emitf(proj_true, "\tjp %L\n");
1061 ia32_emitf(proj_true, "\tj%P %L\n", pnc);
1064 if (need_parity_label) {
1065 ia32_emitf(NULL, "1:\n");
1068 /* the second Proj might be a fallthrough */
1069 if (can_be_fallthrough(proj_false)) {
1070 ia32_emitf(proj_false, "\t/* fallthrough to %L */\n");
1072 ia32_emitf(proj_false, "\tjmp %L\n");
1076 static void emit_ia32_CMov(const ir_node *node)
1078 const ia32_attr_t *attr = get_ia32_attr_const(node);
1079 int ins_permuted = attr->data.ins_permuted;
1080 const arch_register_t *out = arch_irn_get_register(node, pn_ia32_res);
1081 pn_Cmp pnc = get_ia32_condcode(node);
1082 const arch_register_t *in_true;
1083 const arch_register_t *in_false;
1085 pnc = determine_final_pnc(node, n_ia32_CMov_eflags, pnc);
1087 in_true = arch_get_irn_register(get_irn_n(node, n_ia32_CMov_val_true));
1088 in_false = arch_get_irn_register(get_irn_n(node, n_ia32_CMov_val_false));
1090 /* should be same constraint fullfilled? */
1091 if (out == in_false) {
1092 /* yes -> nothing to do */
1093 } else if (out == in_true) {
1094 const arch_register_t *tmp;
1096 assert(get_ia32_op_type(node) == ia32_Normal);
1098 ins_permuted = !ins_permuted;
1105 ia32_emitf(node, "\tmovl %R, %R\n", in_false, out);
1109 pnc = ia32_get_negated_pnc(pnc);
1111 /* TODO: handling of Nans isn't correct yet */
1113 ia32_emitf(node, "\tcmov%P %#AR, %#R\n", pnc, in_true, out);
1116 /*********************************************************
1119 * ___ _ __ ___ _| |_ _ _ _ _ __ ___ _ __ ___
1120 * / _ \ '_ ` _ \| | __| | | | | | '_ ` _ \| '_ \/ __|
1121 * | __/ | | | | | | |_ | | |_| | | | | | | |_) \__ \
1122 * \___|_| |_| |_|_|\__| | |\__,_|_| |_| |_| .__/|___/
1125 *********************************************************/
1127 /* jump table entry (target and corresponding number) */
1128 typedef struct _branch_t {
1133 /* jump table for switch generation */
1134 typedef struct _jmp_tbl_t {
1135 ir_node *defProj; /**< default target */
1136 long min_value; /**< smallest switch case */
1137 long max_value; /**< largest switch case */
1138 long num_branches; /**< number of jumps */
1139 char *label; /**< label of the jump table */
1140 branch_t *branches; /**< jump array */
1144 * Compare two variables of type branch_t. Used to sort all switch cases
1146 static int ia32_cmp_branch_t(const void *a, const void *b)
1148 branch_t *b1 = (branch_t *)a;
1149 branch_t *b2 = (branch_t *)b;
1151 if (b1->value <= b2->value)
1158 * Emits code for a SwitchJmp (creates a jump table if
1159 * possible otherwise a cmp-jmp cascade). Port from
1162 static void emit_ia32_SwitchJmp(const ir_node *node)
1164 unsigned long interval;
1170 const ir_edge_t *edge;
1172 /* fill the table structure */
1173 tbl.label = XMALLOCN(char, SNPRINTF_BUF_LEN);
1174 tbl.label = get_unique_label(tbl.label, SNPRINTF_BUF_LEN, ".TBL_");
1176 tbl.num_branches = get_irn_n_edges(node) - 1;
1177 tbl.branches = XMALLOCNZ(branch_t, tbl.num_branches);
1178 tbl.min_value = INT_MAX;
1179 tbl.max_value = INT_MIN;
1181 default_pn = get_ia32_condcode(node);
1183 /* go over all proj's and collect them */
1184 foreach_out_edge(node, edge) {
1185 proj = get_edge_src_irn(edge);
1186 assert(is_Proj(proj) && "Only proj allowed at SwitchJmp");
1188 pnc = get_Proj_proj(proj);
1190 /* check for default proj */
1191 if (pnc == default_pn) {
1192 assert(tbl.defProj == NULL && "found two default Projs at SwitchJmp");
1195 tbl.min_value = pnc < tbl.min_value ? pnc : tbl.min_value;
1196 tbl.max_value = pnc > tbl.max_value ? pnc : tbl.max_value;
1198 /* create branch entry */
1199 tbl.branches[i].target = proj;
1200 tbl.branches[i].value = pnc;
1205 assert(i == tbl.num_branches);
1207 /* sort the branches by their number */
1208 qsort(tbl.branches, tbl.num_branches, sizeof(tbl.branches[0]), ia32_cmp_branch_t);
1210 /* two-complement's magic make this work without overflow */
1211 interval = tbl.max_value - tbl.min_value;
1213 /* emit the table */
1214 ia32_emitf(node, "\tcmpl $%u, %S0\n", interval);
1215 ia32_emitf(tbl.defProj, "\tja %L\n");
1217 if (tbl.num_branches > 1) {
1219 ia32_emitf(node, "\tjmp *%s(,%S0,4)\n", tbl.label);
1221 be_gas_emit_switch_section(GAS_SECTION_RODATA);
1222 ia32_emitf(NULL, "\t.align 4\n");
1223 ia32_emitf(NULL, "%s:\n", tbl.label);
1225 last_value = tbl.branches[0].value;
1226 for (i = 0; i != tbl.num_branches; ++i) {
1227 while (last_value != tbl.branches[i].value) {
1228 ia32_emitf(tbl.defProj, ".long %L\n");
1231 ia32_emitf(tbl.branches[i].target, ".long %L\n");
1234 be_gas_emit_switch_section(GAS_SECTION_TEXT);
1236 /* one jump is enough */
1237 ia32_emitf(tbl.branches[0].target, "\tjmp %L\n");
1247 * Emits code for a unconditional jump.
1249 static void emit_Jmp(const ir_node *node)
1253 /* for now, the code works for scheduled and non-schedules blocks */
1254 block = get_nodes_block(node);
1256 /* we have a block schedule */
1257 if (can_be_fallthrough(node)) {
1258 ia32_emitf(node, "\t/* fallthrough to %L */\n");
1260 ia32_emitf(node, "\tjmp %L\n");
1265 * Emit an inline assembler operand.
1267 * @param node the ia32_ASM node
1268 * @param s points to the operand (a %c)
1270 * @return pointer to the first char in s NOT in the current operand
1272 static const char* emit_asm_operand(const ir_node *node, const char *s)
1274 const ia32_attr_t *ia32_attr = get_ia32_attr_const(node);
1275 const ia32_asm_attr_t *attr = CONST_CAST_IA32_ATTR(ia32_asm_attr_t,
1277 const arch_register_t *reg;
1278 const ia32_asm_reg_t *asm_regs = attr->register_map;
1279 const ia32_asm_reg_t *asm_reg;
1280 const char *reg_name;
1289 /* parse modifiers */
1292 ir_fprintf(stderr, "Warning: asm text (%+F) ends with %%\n", node);
1317 "Warning: asm text (%+F) contains unknown modifier '%c' for asm op\n",
1324 sscanf(s, "%d%n", &num, &p);
1326 ir_fprintf(stderr, "Warning: Couldn't parse assembler operand (%+F)\n",
1333 if (num < 0 || ARR_LEN(asm_regs) <= num) {
1335 "Error: Custom assembler references invalid input/output (%+F)\n",
1339 asm_reg = & asm_regs[num];
1340 assert(asm_reg->valid);
1343 if (asm_reg->use_input == 0) {
1344 reg = get_out_reg(node, asm_reg->inout_pos);
1346 ir_node *pred = get_irn_n(node, asm_reg->inout_pos);
1348 /* might be an immediate value */
1349 if (is_ia32_Immediate(pred)) {
1350 emit_ia32_Immediate(pred);
1353 reg = get_in_reg(node, asm_reg->inout_pos);
1357 "Warning: no register assigned for %d asm op (%+F)\n",
1362 if (asm_reg->memory) {
1367 if (modifier != 0) {
1371 reg_name = ia32_get_mapped_reg_name(isa->regs_8bit, reg);
1374 reg_name = ia32_get_mapped_reg_name(isa->regs_8bit_high, reg);
1377 reg_name = ia32_get_mapped_reg_name(isa->regs_16bit, reg);
1380 panic("Invalid asm op modifier");
1382 be_emit_string(reg_name);
1384 emit_register(reg, asm_reg->mode);
1387 if (asm_reg->memory) {
1395 * Emits code for an ASM pseudo op.
1397 static void emit_ia32_Asm(const ir_node *node)
1399 const void *gen_attr = get_irn_generic_attr_const(node);
1400 const ia32_asm_attr_t *attr
1401 = CONST_CAST_IA32_ATTR(ia32_asm_attr_t, gen_attr);
1402 ident *asm_text = attr->asm_text;
1403 const char *s = get_id_str(asm_text);
1405 ia32_emitf(node, "#APP\t\n");
1412 s = emit_asm_operand(node, s);
1418 ia32_emitf(NULL, "\n#NO_APP\n");
1421 /**********************************
1424 * | | ___ _ __ _ _| |_) |
1425 * | | / _ \| '_ \| | | | _ <
1426 * | |___| (_) | |_) | |_| | |_) |
1427 * \_____\___/| .__/ \__, |____/
1430 **********************************/
1433 * Emit movsb/w instructions to make mov count divideable by 4
1435 static void emit_CopyB_prolog(unsigned size)
1438 ia32_emitf(NULL, "\tmovsb\n");
1440 ia32_emitf(NULL, "\tmovsw\n");
1444 * Emit rep movsd instruction for memcopy.
1446 static void emit_ia32_CopyB(const ir_node *node)
1448 unsigned size = get_ia32_copyb_size(node);
1450 emit_CopyB_prolog(size);
1451 ia32_emitf(node, "\trep movsd\n");
1455 * Emits unrolled memcopy.
1457 static void emit_ia32_CopyB_i(const ir_node *node)
1459 unsigned size = get_ia32_copyb_size(node);
1461 emit_CopyB_prolog(size);
1465 ia32_emitf(NULL, "\tmovsd\n");
1471 /***************************
1475 * | | / _ \| '_ \ \ / /
1476 * | |___| (_) | | | \ V /
1477 * \_____\___/|_| |_|\_/
1479 ***************************/
1482 * Emit code for conversions (I, FP), (FP, I) and (FP, FP).
1484 static void emit_ia32_Conv_with_FP(const ir_node *node, const char* conv_f,
1487 ir_mode *ls_mode = get_ia32_ls_mode(node);
1488 int ls_bits = get_mode_size_bits(ls_mode);
1489 const char *conv = ls_bits == 32 ? conv_f : conv_d;
1491 ia32_emitf(node, "\tcvt%s %AS3, %D0\n", conv);
1494 static void emit_ia32_Conv_I2FP(const ir_node *node)
1496 emit_ia32_Conv_with_FP(node, "si2ss", "si2sd");
1499 static void emit_ia32_Conv_FP2I(const ir_node *node)
1501 emit_ia32_Conv_with_FP(node, "ss2si", "sd2si");
1504 static void emit_ia32_Conv_FP2FP(const ir_node *node)
1506 emit_ia32_Conv_with_FP(node, "sd2ss", "ss2sd");
1510 * Emits code for an Int conversion.
1512 static void emit_ia32_Conv_I2I(const ir_node *node)
1514 ir_mode *smaller_mode = get_ia32_ls_mode(node);
1515 int signed_mode = mode_is_signed(smaller_mode);
1516 const char *sign_suffix;
1518 assert(!mode_is_float(smaller_mode));
1520 sign_suffix = signed_mode ? "s" : "z";
1521 ia32_emitf(node, "\tmov%s%Ml %#AS3, %D0\n", sign_suffix);
1527 static void emit_ia32_Call(const ir_node *node)
1529 /* Special case: Call must not have its immediates prefixed by $, instead
1530 * address mode is prefixed by *. */
1531 ia32_emitf(node, "\tcall %*AS3\n");
1535 /*******************************************
1538 * | |__ ___ _ __ ___ __| | ___ ___
1539 * | '_ \ / _ \ '_ \ / _ \ / _` |/ _ \/ __|
1540 * | |_) | __/ | | | (_) | (_| | __/\__ \
1541 * |_.__/ \___|_| |_|\___/ \__,_|\___||___/
1543 *******************************************/
1546 * Emits code to increase stack pointer.
1548 static void emit_be_IncSP(const ir_node *node)
1550 int offs = be_get_IncSP_offset(node);
1556 ia32_emitf(node, "\tsubl $%u, %D0\n", offs);
1558 ia32_emitf(node, "\taddl $%u, %D0\n", -offs);
1563 * Emits code for Copy/CopyKeep.
1565 static void Copy_emitter(const ir_node *node, const ir_node *op)
1567 const arch_register_t *in = arch_get_irn_register(op);
1568 const arch_register_t *out = arch_get_irn_register(node);
1573 if (is_unknown_reg(in))
1575 /* copies of vf nodes aren't real... */
1576 if (arch_register_get_class(in) == &ia32_reg_classes[CLASS_ia32_vfp])
1579 if (get_irn_mode(node) == mode_E) {
1580 ia32_emitf(node, "\tmovsd %R, %R\n", in, out);
1582 ia32_emitf(node, "\tmovl %R, %R\n", in, out);
1586 static void emit_be_Copy(const ir_node *node)
1588 Copy_emitter(node, be_get_Copy_op(node));
1591 static void emit_be_CopyKeep(const ir_node *node)
1593 Copy_emitter(node, be_get_CopyKeep_op(node));
1597 * Emits code for exchange.
1599 static void emit_be_Perm(const ir_node *node)
1601 const arch_register_t *in0, *in1;
1602 const arch_register_class_t *cls0, *cls1;
1604 in0 = arch_get_irn_register(get_irn_n(node, 0));
1605 in1 = arch_get_irn_register(get_irn_n(node, 1));
1607 cls0 = arch_register_get_class(in0);
1608 cls1 = arch_register_get_class(in1);
1610 assert(cls0 == cls1 && "Register class mismatch at Perm");
1612 if (cls0 == &ia32_reg_classes[CLASS_ia32_gp]) {
1613 ia32_emitf(node, "\txchg %R, %R\n", in1, in0);
1614 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_xmm]) {
1615 ia32_emitf(NULL, "\txorpd %R, %R\n", in1, in0);
1616 ia32_emitf(NULL, "\txorpd %R, %R\n", in0, in1);
1617 ia32_emitf(node, "\txorpd %R, %R\n", in1, in0);
1618 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_vfp]) {
1620 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_st]) {
1623 panic("unexpected register class in be_Perm (%+F)", node);
1628 * Emits code for Constant loading.
1630 static void emit_ia32_Const(const ir_node *node)
1632 ia32_emitf(node, "\tmovl %I, %D0\n");
1636 * Emits code to load the TLS base
1638 static void emit_ia32_LdTls(const ir_node *node)
1640 ia32_emitf(node, "\tmovl %%gs:0, %D0\n");
1643 /* helper function for emit_ia32_Minus64Bit */
1644 static void emit_mov(const ir_node* node, const arch_register_t *src, const arch_register_t *dst)
1646 ia32_emitf(node, "\tmovl %R, %R\n", src, dst);
1649 /* helper function for emit_ia32_Minus64Bit */
1650 static void emit_neg(const ir_node* node, const arch_register_t *reg)
1652 ia32_emitf(node, "\tnegl %R\n", reg);
1655 /* helper function for emit_ia32_Minus64Bit */
1656 static void emit_sbb0(const ir_node* node, const arch_register_t *reg)
1658 ia32_emitf(node, "\tsbbl $0, %R\n", reg);
1661 /* helper function for emit_ia32_Minus64Bit */
1662 static void emit_sbb(const ir_node* node, const arch_register_t *src, const arch_register_t *dst)
1664 ia32_emitf(node, "\tsbbl %R, %R\n", src, dst);
1667 /* helper function for emit_ia32_Minus64Bit */
1668 static void emit_xchg(const ir_node* node, const arch_register_t *src, const arch_register_t *dst)
1670 ia32_emitf(node, "\txchgl %R, %R\n", src, dst);
1673 /* helper function for emit_ia32_Minus64Bit */
1674 static void emit_zero(const ir_node* node, const arch_register_t *reg)
1676 ia32_emitf(node, "\txorl %R, %R\n", reg, reg);
1679 static void emit_ia32_Minus64Bit(const ir_node *node)
1681 const arch_register_t *in_lo = get_in_reg(node, 0);
1682 const arch_register_t *in_hi = get_in_reg(node, 1);
1683 const arch_register_t *out_lo = get_out_reg(node, 0);
1684 const arch_register_t *out_hi = get_out_reg(node, 1);
1686 if (out_lo == in_lo) {
1687 if (out_hi != in_hi) {
1688 /* a -> a, b -> d */
1691 /* a -> a, b -> b */
1694 } else if (out_lo == in_hi) {
1695 if (out_hi == in_lo) {
1696 /* a -> b, b -> a */
1697 emit_xchg(node, in_lo, in_hi);
1700 /* a -> b, b -> d */
1701 emit_mov(node, in_hi, out_hi);
1702 emit_mov(node, in_lo, out_lo);
1706 if (out_hi == in_lo) {
1707 /* a -> c, b -> a */
1708 emit_mov(node, in_lo, out_lo);
1710 } else if (out_hi == in_hi) {
1711 /* a -> c, b -> b */
1712 emit_mov(node, in_lo, out_lo);
1715 /* a -> c, b -> d */
1716 emit_mov(node, in_lo, out_lo);
1722 emit_neg( node, out_hi);
1723 emit_neg( node, out_lo);
1724 emit_sbb0(node, out_hi);
1728 emit_zero(node, out_hi);
1729 emit_neg( node, out_lo);
1730 emit_sbb( node, in_hi, out_hi);
1733 static void emit_ia32_GetEIP(const ir_node *node)
1735 ia32_emitf(node, "\tcall %s\n", pic_base_label);
1736 ia32_emitf(NULL, "%s:\n", pic_base_label);
1737 ia32_emitf(node, "\tpopl %D0\n");
1740 static void emit_ia32_ClimbFrame(const ir_node *node)
1742 const ia32_climbframe_attr_t *attr = get_ia32_climbframe_attr_const(node);
1744 ia32_emitf(node, "\tmovl %S0, %D0\n");
1745 ia32_emitf(node, "\tmovl $%u, %S1\n", attr->count);
1746 ia32_emitf(NULL, BLOCK_PREFIX "%ld:\n", get_irn_node_nr(node));
1747 ia32_emitf(node, "\tmovl (%D0), %D0\n");
1748 ia32_emitf(node, "\tdec %S1\n");
1749 ia32_emitf(node, "\tjnz " BLOCK_PREFIX "%ld\n", get_irn_node_nr(node));
1752 static void emit_be_Return(const ir_node *node)
1754 unsigned pop = be_Return_get_pop(node);
1756 if (pop > 0 || be_Return_get_emit_pop(node)) {
1757 ia32_emitf(node, "\tret $%u\n", pop);
1759 ia32_emitf(node, "\tret\n");
1763 static void emit_Nothing(const ir_node *node)
1769 /***********************************************************************************
1772 * _ __ ___ __ _ _ _ __ | |_ _ __ __ _ _ __ ___ _____ _____ _ __| | __
1773 * | '_ ` _ \ / _` | | '_ \ | _| '__/ _` | '_ ` _ \ / _ \ \ /\ / / _ \| '__| |/ /
1774 * | | | | | | (_| | | | | | | | | | | (_| | | | | | | __/\ V V / (_) | | | <
1775 * |_| |_| |_|\__,_|_|_| |_| |_| |_| \__,_|_| |_| |_|\___| \_/\_/ \___/|_| |_|\_\
1777 ***********************************************************************************/
1780 * Enters the emitter functions for handled nodes into the generic
1781 * pointer of an opcode.
1783 static void ia32_register_emitters(void)
1785 #define IA32_EMIT2(a,b) op_ia32_##a->ops.generic = (op_func)emit_ia32_##b
1786 #define IA32_EMIT(a) IA32_EMIT2(a,a)
1787 #define EMIT(a) op_##a->ops.generic = (op_func)emit_##a
1788 #define IGN(a) op_##a->ops.generic = (op_func)emit_Nothing
1789 #define BE_EMIT(a) op_be_##a->ops.generic = (op_func)emit_be_##a
1790 #define BE_IGN(a) op_be_##a->ops.generic = (op_func)emit_Nothing
1792 /* first clear the generic function pointer for all ops */
1793 clear_irp_opcodes_generic_func();
1795 /* register all emitter functions defined in spec */
1796 ia32_register_spec_emitters();
1798 /* other ia32 emitter functions */
1799 IA32_EMIT2(Conv_I2I8Bit, Conv_I2I);
1804 IA32_EMIT(Conv_FP2FP);
1805 IA32_EMIT(Conv_FP2I);
1806 IA32_EMIT(Conv_I2FP);
1807 IA32_EMIT(Conv_I2I);
1814 IA32_EMIT(Minus64Bit);
1815 IA32_EMIT(SwitchJmp);
1816 IA32_EMIT(ClimbFrame);
1818 /* benode emitter */
1841 typedef void (*emit_func_ptr) (const ir_node *);
1844 * Assign and emit an exception label if the current instruction can fail.
1846 static void ia32_assign_exc_label(ir_node *node)
1848 /* assign a new ID to the instruction */
1849 set_ia32_exc_label_id(node, ++exc_label_id);
1851 ia32_emit_exc_label(node);
1853 be_emit_pad_comment();
1854 be_emit_cstring("/* exception to Block ");
1855 ia32_emit_cfop_target(node);
1856 be_emit_cstring(" */\n");
1857 be_emit_write_line();
1861 * Emits code for a node.
1863 static void ia32_emit_node(ir_node *node)
1865 ir_op *op = get_irn_op(node);
1867 DBG((dbg, LEVEL_1, "emitting code for %+F\n", node));
1869 if (is_ia32_irn(node)) {
1870 if (get_ia32_exc_label(node)) {
1871 /* emit the exception label of this instruction */
1872 ia32_assign_exc_label(node);
1874 if (mark_spill_reload) {
1875 if (is_ia32_is_spill(node)) {
1876 ia32_emitf(NULL, "\txchg %ebx, %ebx /* spill mark */\n");
1878 if (is_ia32_is_reload(node)) {
1879 ia32_emitf(NULL, "\txchg %edx, %edx /* reload mark */\n");
1881 if (is_ia32_is_remat(node)) {
1882 ia32_emitf(NULL, "\txchg %ecx, %ecx /* remat mark */\n");
1886 if (op->ops.generic) {
1887 emit_func_ptr func = (emit_func_ptr) op->ops.generic;
1889 be_dbg_set_dbg_info(get_irn_dbg_info(node));
1894 ir_fprintf(stderr, "Error: No emit handler for node %+F (%+G, graph %+F)\n", node, node, current_ir_graph);
1900 * Emits gas alignment directives
1902 static void ia32_emit_alignment(unsigned align, unsigned skip)
1904 ia32_emitf(NULL, "\t.p2align %u,,%u\n", align, skip);
1908 * Emits gas alignment directives for Labels depended on cpu architecture.
1910 static void ia32_emit_align_label(void)
1912 unsigned align = ia32_cg_config.label_alignment;
1913 unsigned maximum_skip = ia32_cg_config.label_alignment_max_skip;
1914 ia32_emit_alignment(align, maximum_skip);
1918 * Test whether a block should be aligned.
1919 * For cpus in the P4/Athlon class it is useful to align jump labels to
1920 * 16 bytes. However we should only do that if the alignment nops before the
1921 * label aren't executed more often than we have jumps to the label.
1923 static int should_align_block(const ir_node *block)
1925 static const double DELTA = .0001;
1926 ir_exec_freq *exec_freq = cg->birg->exec_freq;
1927 ir_node *prev = get_prev_block_sched(block);
1929 double prev_freq = 0; /**< execfreq of the fallthrough block */
1930 double jmp_freq = 0; /**< execfreq of all non-fallthrough blocks */
1933 if (exec_freq == NULL)
1935 if (ia32_cg_config.label_alignment_factor <= 0)
1938 block_freq = get_block_execfreq(exec_freq, block);
1939 if (block_freq < DELTA)
1942 n_cfgpreds = get_Block_n_cfgpreds(block);
1943 for(i = 0; i < n_cfgpreds; ++i) {
1944 const ir_node *pred = get_Block_cfgpred_block(block, i);
1945 double pred_freq = get_block_execfreq(exec_freq, pred);
1948 prev_freq += pred_freq;
1950 jmp_freq += pred_freq;
1954 if (prev_freq < DELTA && !(jmp_freq < DELTA))
1957 jmp_freq /= prev_freq;
1959 return jmp_freq > ia32_cg_config.label_alignment_factor;
1963 * Emit the block header for a block.
1965 * @param block the block
1966 * @param prev_block the previous block
1968 static void ia32_emit_block_header(ir_node *block)
1970 ir_graph *irg = current_ir_graph;
1971 int need_label = block_needs_label(block);
1973 ir_exec_freq *exec_freq = cg->birg->exec_freq;
1975 if (block == get_irg_end_block(irg))
1978 if (ia32_cg_config.label_alignment > 0) {
1979 /* align the current block if:
1980 * a) if should be aligned due to its execution frequency
1981 * b) there is no fall-through here
1983 if (should_align_block(block)) {
1984 ia32_emit_align_label();
1986 /* if the predecessor block has no fall-through,
1987 we can always align the label. */
1989 int has_fallthrough = 0;
1991 for (i = get_Block_n_cfgpreds(block) - 1; i >= 0; --i) {
1992 ir_node *cfg_pred = get_Block_cfgpred(block, i);
1993 if (can_be_fallthrough(cfg_pred)) {
1994 has_fallthrough = 1;
1999 if (!has_fallthrough)
2000 ia32_emit_align_label();
2004 if (need_label || has_Block_label(block)) {
2005 ia32_emit_block_name(block);
2008 be_emit_pad_comment();
2009 be_emit_cstring(" /* ");
2011 be_emit_cstring("\t/* ");
2012 ia32_emit_block_name(block);
2013 be_emit_cstring(": ");
2016 be_emit_cstring("preds:");
2018 /* emit list of pred blocks in comment */
2019 arity = get_irn_arity(block);
2021 be_emit_cstring(" none");
2023 for (i = 0; i < arity; ++i) {
2024 ir_node *predblock = get_Block_cfgpred_block(block, i);
2025 be_emit_irprintf(" %d", get_irn_node_nr(predblock));
2028 if (exec_freq != NULL) {
2029 be_emit_irprintf(", freq: %f",
2030 get_block_execfreq(exec_freq, block));
2032 be_emit_cstring(" */\n");
2033 be_emit_write_line();
2037 * Walks over the nodes in a block connected by scheduling edges
2038 * and emits code for each node.
2040 static void ia32_gen_block(ir_node *block)
2044 ia32_emit_block_header(block);
2046 /* emit the contents of the block */
2047 be_dbg_set_dbg_info(get_irn_dbg_info(block));
2048 sched_foreach(block, node) {
2049 ia32_emit_node(node);
2053 typedef struct exc_entry {
2054 ir_node *exc_instr; /** The instruction that can issue an exception. */
2055 ir_node *block; /** The block to call then. */
2060 * Sets labels for control flow nodes (jump target).
2061 * Links control predecessors to there destination blocks.
2063 static void ia32_gen_labels(ir_node *block, void *data)
2065 exc_entry **exc_list = data;
2069 for (n = get_Block_n_cfgpreds(block) - 1; n >= 0; --n) {
2070 pred = get_Block_cfgpred(block, n);
2071 set_irn_link(pred, block);
2073 pred = skip_Proj(pred);
2074 if (is_ia32_irn(pred) && get_ia32_exc_label(pred)) {
2079 ARR_APP1(exc_entry, *exc_list, e);
2080 set_irn_link(pred, block);
2086 * Compare two exception_entries.
2088 static int cmp_exc_entry(const void *a, const void *b)
2090 const exc_entry *ea = a;
2091 const exc_entry *eb = b;
2093 if (get_ia32_exc_label_id(ea->exc_instr) < get_ia32_exc_label_id(eb->exc_instr))
2099 * Main driver. Emits the code for one routine.
2101 void ia32_gen_routine(ia32_code_gen_t *ia32_cg, ir_graph *irg)
2103 ir_entity *entity = get_irg_entity(irg);
2104 exc_entry *exc_list = NEW_ARR_F(exc_entry, 0);
2109 do_pic = cg->birg->main_env->options->pic;
2111 ia32_register_emitters();
2113 get_unique_label(pic_base_label, sizeof(pic_base_label), ".PIC_BASE");
2115 be_dbg_method_begin(entity, be_abi_get_stack_layout(cg->birg->abi));
2116 be_gas_emit_function_prolog(entity, ia32_cg_config.function_alignment);
2118 /* we use links to point to target blocks */
2119 ir_reserve_resources(irg, IR_RESOURCE_IRN_LINK);
2120 irg_block_walk_graph(irg, ia32_gen_labels, NULL, &exc_list);
2122 /* initialize next block links */
2123 n = ARR_LEN(cg->blk_sched);
2124 for (i = 0; i < n; ++i) {
2125 ir_node *block = cg->blk_sched[i];
2126 ir_node *prev = i > 0 ? cg->blk_sched[i-1] : NULL;
2128 set_irn_link(block, prev);
2131 for (i = 0; i < n; ++i) {
2132 ir_node *block = cg->blk_sched[i];
2134 ia32_gen_block(block);
2137 be_gas_emit_function_epilog(entity);
2138 be_dbg_method_end();
2140 be_emit_write_line();
2142 ir_free_resources(irg, IR_RESOURCE_IRN_LINK);
2144 /* Sort the exception table using the exception label id's.
2145 Those are ascending with ascending addresses. */
2146 qsort(exc_list, ARR_LEN(exc_list), sizeof(exc_list[0]), cmp_exc_entry);
2150 for (i = 0; i < ARR_LEN(exc_list); ++i) {
2151 be_emit_cstring("\t.long ");
2152 ia32_emit_exc_label(exc_list[i].exc_instr);
2154 be_emit_cstring("\t.long ");
2155 ia32_emit_block_name(exc_list[i].block);
2159 DEL_ARR_F(exc_list);
2162 static const lc_opt_table_entry_t ia32_emitter_options[] = {
2163 LC_OPT_ENT_BOOL("mark_spill_reload", "mark spills and reloads with ud opcodes", &mark_spill_reload),
2167 void ia32_init_emitter(void)
2169 lc_opt_entry_t *be_grp;
2170 lc_opt_entry_t *ia32_grp;
2172 be_grp = lc_opt_get_grp(firm_opt_get_root(), "be");
2173 ia32_grp = lc_opt_get_grp(be_grp, "ia32");
2175 lc_opt_add_table(ia32_grp, ia32_emitter_options);
2177 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.emitter");