15 #include "../besched.h"
17 #include "ia32_emitter.h"
18 #include "gen_ia32_emitter.h"
19 #include "ia32_nodes_attr.h"
20 #include "ia32_new_nodes.h"
21 #include "ia32_map_regs.h"
23 #define SNPRINTF_BUF_LEN 128
25 static const arch_env_t *arch_env = NULL;
28 /*************************************************************
30 * (_) | | / _| | | | |
31 * _ __ _ __ _ _ __ | |_| |_ | |__ ___| |_ __ ___ _ __
32 * | '_ \| '__| | '_ \| __| _| | '_ \ / _ \ | '_ \ / _ \ '__|
33 * | |_) | | | | | | | |_| | | | | | __/ | |_) | __/ |
34 * | .__/|_| |_|_| |_|\__|_| |_| |_|\___|_| .__/ \___|_|
37 *************************************************************/
40 * Return node's tarval as string.
42 const char *node_const_to_str(ir_node *n) {
44 tarval *tv = get_ia32_Immop_tarval(n);
47 buf = malloc(SNPRINTF_BUF_LEN);
48 tarval_snprintf(buf, SNPRINTF_BUF_LEN, tv);
51 else if (get_ia32_old_ir(n)) {
52 return get_sc_name(get_ia32_old_ir(n));
59 * Returns node's offset as string.
61 char *node_offset_to_str(ir_node *n) {
63 tarval *tv = get_ia32_am_offs(n);
66 buf = malloc(SNPRINTF_BUF_LEN);
67 tarval_snprintf(buf, SNPRINTF_BUF_LEN, tv);
74 /* We always pass the ir_node which is a pointer. */
75 static int ia32_get_arg_type(const lc_arg_occ_t *occ) {
76 return lc_arg_type_ptr;
81 * Returns the register at in position pos.
83 static const arch_register_t *get_in_reg(ir_node *irn, int pos) {
85 const arch_register_t *reg = NULL;
87 assert(get_irn_arity(irn) > pos && "Invalid IN position");
89 /* The out register of the operator at position pos is the
90 in register we need. */
91 op = get_irn_n(irn, pos);
93 reg = arch_get_irn_register(arch_env, op);
95 assert(reg && "no in register found");
100 * Returns the register at out position pos.
102 static const arch_register_t *get_out_reg(ir_node *irn, int pos) {
104 const arch_register_t *reg = NULL;
106 assert(get_irn_n_edges(irn) > pos && "Invalid OUT position");
108 /* 1st case: irn is not of mode_T, so it has only */
109 /* one OUT register -> good */
110 /* 2nd case: irn is of mode_T -> collect all Projs and ask the */
111 /* Proj with the corresponding projnum for the register */
113 if (get_irn_mode(irn) != mode_T) {
114 reg = arch_get_irn_register(arch_env, irn);
116 else if (is_ia32_irn(irn)) {
117 reg = get_ia32_out_reg(irn, pos);
120 const ir_edge_t *edge;
122 foreach_out_edge(irn, edge) {
123 proj = get_edge_src_irn(edge);
124 assert(is_Proj(proj) && "non-Proj from mode_T node");
125 if (get_Proj_proj(proj) == pos) {
126 reg = arch_get_irn_register(arch_env, proj);
132 assert(reg && "no out register found");
137 * Returns the number of the in register at position pos.
139 int get_ia32_reg_nr(ir_node *irn, int pos, int in_out) {
140 const arch_register_t *reg;
144 reg = get_in_reg(irn, pos);
147 reg = get_out_reg(irn, pos);
150 return arch_register_get_index(reg);
154 * Returns the name of the in register at position pos.
156 const char *get_ia32_reg_name(ir_node *irn, int pos, int in_out) {
157 const arch_register_t *reg;
161 reg = get_in_reg(irn, pos);
164 reg = get_out_reg(irn, pos);
167 return arch_register_get_name(reg);
171 * Get the register name for a node.
173 static int ia32_get_reg_name(lc_appendable_t *app,
174 const lc_arg_occ_t *occ, const lc_arg_value_t *arg)
177 ir_node *X = arg->v_ptr;
178 int nr = occ->width - 1;
181 return lc_arg_append(app, occ, "(null)", 6);
183 if (occ->conversion == 'S') {
184 buf = get_ia32_reg_name(X, nr, 1);
187 buf = get_ia32_reg_name(X, nr, 0);
190 lc_appendable_chadd(app, '%');
191 return lc_arg_append(app, occ, buf, strlen(buf));
195 * Returns the tarval or offset of an ia32 as a string.
197 static int ia32_const_to_str(lc_appendable_t *app,
198 const lc_arg_occ_t *occ, const lc_arg_value_t *arg)
201 ir_node *X = arg->v_ptr;
204 return lc_arg_append(app, occ, "(null)", 6);
206 if (occ->conversion == 'C') {
207 buf = node_const_to_str(X);
210 buf = node_offset_to_str(X);
213 return lc_arg_append(app, occ, buf, strlen(buf));
217 * Determines the SSE suffix depending on the mode.
219 static int ia32_get_mode_suffix(lc_appendable_t *app,
220 const lc_arg_occ_t *occ, const lc_arg_value_t *arg)
222 ir_node *X = arg->v_ptr;
225 return lc_arg_append(app, occ, "(null)", 6);
227 if (get_mode_size_bits(get_irn_mode(X)) == 32)
228 return lc_appendable_chadd(app, 's');
230 return lc_appendable_chadd(app, 'd');
234 * Return the ia32 printf arg environment.
235 * We use the firm environment with some additional handlers.
237 const lc_arg_env_t *ia32_get_arg_env(void) {
238 static lc_arg_env_t *env = NULL;
240 static const lc_arg_handler_t ia32_reg_handler = { ia32_get_arg_type, ia32_get_reg_name };
241 static const lc_arg_handler_t ia32_const_handler = { ia32_get_arg_type, ia32_const_to_str };
242 static const lc_arg_handler_t ia32_mode_handler = { ia32_get_arg_type, ia32_get_mode_suffix };
245 /* extend the firm printer */
246 env = firm_get_arg_env();
249 lc_arg_register(env, "ia32:sreg", 'S', &ia32_reg_handler);
250 lc_arg_register(env, "ia32:dreg", 'D', &ia32_reg_handler);
251 lc_arg_register(env, "ia32:cnst", 'C', &ia32_const_handler);
252 lc_arg_register(env, "ia32:offs", 'O', &ia32_const_handler);
253 lc_arg_register(env, "ia32:mode", 'M', &ia32_mode_handler);
260 * For 2-address code we need to make sure the first src reg is equal to dest reg.
262 void equalize_dest_src(FILE *F, ir_node *n) {
263 if (get_ia32_reg_nr(n, 0, 1) != get_ia32_reg_nr(n, 0, 0)) {
264 if (get_irn_arity(n) > 1 && get_ia32_reg_nr(n, 1, 1) == get_ia32_reg_nr(n, 0, 0)) {
265 if (! is_op_commutative(get_irn_op(n))) {
266 /* we only need to exchange for non-commutative ops */
267 lc_efprintf(ia32_get_arg_env(), F, "\txchg %1S, %2S\t\t\t/* xchg src1 <-> src2 for 2 address code */\n", n, n);
271 lc_efprintf(ia32_get_arg_env(), F, "\tmovl %1S, %1D\t\t\t/* src -> dest for 2 address code */\n", n, n);
277 * Add a number to a prefix. This number will not be used a second time.
279 char *get_unique_label(char *buf, size_t buflen, const char *prefix) {
280 static unsigned long id = 0;
281 snprintf(buf, buflen, "%s%lu", prefix, ++id);
286 /*************************************************
289 * ___ _ __ ___ _| |_ ___ ___ _ __ __| |
290 * / _ \ '_ ` _ \| | __| / __/ _ \| '_ \ / _` |
291 * | __/ | | | | | | |_ | (_| (_) | | | | (_| |
292 * \___|_| |_| |_|_|\__| \___\___/|_| |_|\__,_|
294 *************************************************/
297 * coding of conditions
299 struct cmp2conditon_t {
305 * positive conditions for signed compares
307 static const struct cmp2conditon_t cmp2condition_s[] = {
308 { NULL, pn_Cmp_False }, /* always false */
309 { "e", pn_Cmp_Eq }, /* == */
310 { "l", pn_Cmp_Lt }, /* < */
311 { "le", pn_Cmp_Le }, /* <= */
312 { "g", pn_Cmp_Gt }, /* > */
313 { "ge", pn_Cmp_Ge }, /* >= */
314 { "ne", pn_Cmp_Lg }, /* != */
315 { "ordered", pn_Cmp_Leg }, /* Floating point: ordered */
316 { "unordered", pn_Cmp_Uo }, /* FLoting point: unordered */
317 { "unordered or ==", pn_Cmp_Ue }, /* Floating point: unordered or == */
318 { "unordered or <", pn_Cmp_Ul }, /* Floating point: unordered or < */
319 { "unordered or <=", pn_Cmp_Ule }, /* Floating point: unordered or <= */
320 { "unordered or >", pn_Cmp_Ug }, /* Floating point: unordered or > */
321 { "unordered or >=", pn_Cmp_Uge }, /* Floating point: unordered or >= */
322 { "unordered or !=", pn_Cmp_Ne }, /* Floating point: unordered or != */
323 { NULL, pn_Cmp_True }, /* always true */
327 * positive conditions for unsigned compares
329 static const struct cmp2conditon_t cmp2condition_u[] = {
330 { NULL, pn_Cmp_False }, /* always false */
331 { "e", pn_Cmp_Eq }, /* == */
332 { "b", pn_Cmp_Lt }, /* < */
333 { "be", pn_Cmp_Le }, /* <= */
334 { "a", pn_Cmp_Gt }, /* > */
335 { "ae", pn_Cmp_Ge }, /* >= */
336 { "ne", pn_Cmp_Lg }, /* != */
337 { "ordered", pn_Cmp_Leg }, /* Floating point: ordered */
338 { "unordered", pn_Cmp_Uo }, /* FLoting point: unordered */
339 { "unordered or ==", pn_Cmp_Ue }, /* Floating point: unordered or == */
340 { "unordered or <", pn_Cmp_Ul }, /* Floating point: unordered or < */
341 { "unordered or <=", pn_Cmp_Ule }, /* Floating point: unordered or <= */
342 { "unordered or >", pn_Cmp_Ug }, /* Floating point: unordered or > */
343 { "unordered or >=", pn_Cmp_Uge }, /* Floating point: unordered or >= */
344 { "unordered or !=", pn_Cmp_Ne }, /* Floating point: unordered or != */
345 { NULL, pn_Cmp_True }, /* always true */
349 * returns the condition code
351 static const char *get_cmp_suffix(int cmp_code, int unsigned_cmp)
353 assert(cmp2condition_s[cmp_code].num == cmp_code);
354 assert(cmp2condition_u[cmp_code].num == cmp_code);
356 return unsigned_cmp ? cmp2condition_u[cmp_code & 7].name : cmp2condition_s[cmp_code & 7].name;
360 * Returns the target label for a control flow node.
362 static char *get_cfop_target(const ir_node *irn, char *buf) {
363 ir_node *bl = get_irn_link(irn);
365 snprintf(buf, SNPRINTF_BUF_LEN, "BLOCK_%ld", get_irn_node_nr(bl));
370 * Emits the jump sequence for a conditional jump (cmp + jmp_true + jmp_false)
372 static void finish_CondJmp(FILE *F, ir_node *irn) {
374 const ir_edge_t *edge;
375 char buf[SNPRINTF_BUF_LEN];
377 edge = get_irn_out_edge_first(irn);
378 proj = get_edge_src_irn(edge);
379 assert(is_Proj(proj) && "CondJmp with a non-Proj");
381 if (get_Proj_proj(proj) == 1) {
382 fprintf(F, "\tj%s %s\t\t\t/* cmp(a, b) == TRUE */\n",
383 get_cmp_suffix(get_ia32_pncode(irn), !mode_is_signed(get_irn_mode(get_irn_n(irn, 0)))),
384 get_cfop_target(proj, buf));
387 fprintf(F, "\tjn%s %s\t\t\t/* cmp(a, b) == FALSE */\n",
388 get_cmp_suffix(get_ia32_pncode(irn), !mode_is_signed(get_irn_mode(get_irn_n(irn, 0)))),
389 get_cfop_target(proj, buf));
392 edge = get_irn_out_edge_next(irn, edge);
394 proj = get_edge_src_irn(edge);
395 assert(is_Proj(proj) && "CondJmp with a non-Proj");
396 fprintf(F, "\tjmp %s\t\t\t/* otherwise */\n", get_cfop_target(proj, buf));
401 * Emits code for conditional jump with two variables.
403 static void emit_ia32_CondJmp(ir_node *irn, emit_env_t *env) {
406 lc_efprintf(ia32_get_arg_env(), F, "\tcmp %2S, %1S\t\t\t/* CondJmp(%+F, %+F) */\n", irn, irn,
407 get_irn_n(irn, 0), get_irn_n(irn, 1));
408 finish_CondJmp(F, irn);
412 * Emits code for conditional jump with immediate.
414 void emit_ia32_CondJmp_i(ir_node *irn, emit_env_t *env) {
417 lc_efprintf(ia32_get_arg_env(), F, "\tcmp %C, %1S\t\t\t/* CondJmp_i(%+F) */\n", irn, irn, get_irn_n(irn, 0));
418 finish_CondJmp(F, irn);
423 /*********************************************************
426 * ___ _ __ ___ _| |_ _ _ _ _ __ ___ _ __ ___
427 * / _ \ '_ ` _ \| | __| | | | | | '_ ` _ \| '_ \/ __|
428 * | __/ | | | | | | |_ | | |_| | | | | | | |_) \__ \
429 * \___|_| |_| |_|_|\__| | |\__,_|_| |_| |_| .__/|___/
432 *********************************************************/
434 /* jump table entry (target and corresponding number) */
435 typedef struct _branch_t {
440 /* jump table for switch generation */
441 typedef struct _jmp_tbl_t {
442 ir_node *defProj; /**< default target */
443 int min_value; /**< smallest switch case */
444 int max_value; /**< largest switch case */
445 int num_branches; /**< number of jumps */
446 char *label; /**< label of the jump table */
447 branch_t *branches; /**< jump array */
451 * Compare two variables of type branch_t. Used to sort all switch cases
453 static int ia32_cmp_branch_t(const void *a, const void *b) {
454 branch_t *b1 = (branch_t *)a;
455 branch_t *b2 = (branch_t *)b;
457 if (b1->value <= b2->value)
464 * Emits code for a SwitchJmp (creates a jump table if
465 * possible otherwise a cmp-jmp cascade). Port from
468 void emit_ia32_SwitchJmp(const ir_node *irn, emit_env_t *emit_env) {
469 unsigned long interval;
470 char buf[SNPRINTF_BUF_LEN];
471 int last_value, i, pn, do_jmp_tbl = 1;
474 const ir_edge_t *edge;
475 const lc_arg_env_t *env = ia32_get_arg_env();
476 FILE *F = emit_env->out;
478 /* fill the table structure */
479 tbl.label = malloc(SNPRINTF_BUF_LEN);
480 tbl.label = get_unique_label(tbl.label, SNPRINTF_BUF_LEN, "JMPTBL_");
482 tbl.num_branches = get_irn_n_edges(irn);
483 tbl.branches = calloc(tbl.num_branches, sizeof(tbl.branches[0]));
484 tbl.min_value = INT_MAX;
485 tbl.max_value = INT_MIN;
488 /* go over all proj's and collect them */
489 foreach_out_edge(irn, edge) {
490 proj = get_edge_src_irn(edge);
491 assert(is_Proj(proj) && "Only proj allowed at SwitchJmp");
493 pn = get_Proj_proj(proj);
495 /* create branch entry */
496 tbl.branches[i].target = proj;
497 tbl.branches[i].value = pn;
499 tbl.min_value = pn < tbl.min_value ? pn : tbl.min_value;
500 tbl.max_value = pn > tbl.max_value ? pn : tbl.max_value;
502 /* check for default proj */
503 if (pn == get_ia32_pncode(irn)) {
504 assert(tbl.defProj == NULL && "found two defProjs at SwitchJmp");
511 /* sort the branches by their number */
512 qsort(tbl.branches, tbl.num_branches, sizeof(tbl.branches[0]), ia32_cmp_branch_t);
514 /* two-complement's magic make this work without overflow */
515 interval = tbl.max_value - tbl.min_value;
517 /* check value interval */
518 if (interval > 16 * 1024) {
522 /* check ratio of value interval to number of branches */
523 if ((float)(interval + 1) / (float)tbl.num_branches > 8.0) {
529 if (tbl.min_value != 0) {
530 fprintf(F, "\tcmpl %lu, -%d", interval, tbl.min_value);
531 lc_efprintf(env, F, "(%1S)\t\t/* first switch value is not 0 */\n", irn);
534 fprintf(F, "\tcmpl %lu, ", interval);
535 lc_efprintf(env, F, "%1S\t\t\t/* compare for switch */\n", irn);
538 fprintf(F, "\tja %s\t\t\t/* default jump if out of range */\n", get_cfop_target(tbl.defProj, buf));
540 if (tbl.num_branches > 1) {
543 //fprintf(F, "\tjmp *%s", tbl.label);
544 lc_efprintf(env, F, "\tjmp *%s(,%1S,4)\t\t/* get jump table entry as target */\n", tbl.label, irn);
546 fprintf(F, "\t.section\t.rodata\t\t/* start jump table */\n");
547 fprintf(F, "\t.align 4\n");
549 fprintf(F, "%s:\n", tbl.label);
550 fprintf(F, "\t.long %s\t\t\t/* case %d */\n", get_cfop_target(tbl.branches[0].target, buf), tbl.branches[0].value);
552 last_value = tbl.branches[0].value;
553 for (i = 1; i < tbl.num_branches; ++i) {
554 while (++last_value < tbl.branches[i].value) {
555 fprintf(F, "\t.long %s\t\t/* default case */\n", get_cfop_target(tbl.defProj, buf));
557 fprintf(F, "\t.long %s\t\t\t/* case %d */\n", get_cfop_target(tbl.branches[i].target, buf), last_value);
560 fprintf(F, "\t.text\t\t\t\t/* end of jump table */\n");
563 /* one jump is enough */
564 fprintf(F, "\tjmp %s\t\t/* only one case given */\n", get_cfop_target(tbl.branches[0].target, buf));
567 else { // no jump table
568 for (i = 0; i < tbl.num_branches; ++i) {
569 fprintf(F, "\tcmpl %d, ", tbl.branches[i].value);
570 lc_efprintf(env, F, "%1S", irn);
571 fprintf(F, "\t\t\t/* case %d */\n", tbl.branches[i].value);
572 fprintf(F, "\tje %s\n", get_cfop_target(tbl.branches[i].target, buf));
575 fprintf(F, "\tjmp %s\t\t\t/* default case */\n", get_cfop_target(tbl.defProj, buf));
585 * Emits code for a unconditional jump.
587 void emit_Jmp(ir_node *irn, emit_env_t *env) {
590 char buf[SNPRINTF_BUF_LEN];
591 ir_fprintf(F, "\tjmp %s\t\t\t/* Jmp(%+F) */\n", get_cfop_target(irn, buf), get_irn_link(irn));
596 /****************************
599 * _ __ _ __ ___ _ ___
600 * | '_ \| '__/ _ \| |/ __|
601 * | |_) | | | (_) | |\__ \
602 * | .__/|_| \___/| ||___/
605 ****************************/
608 * Emits code for a proj -> node
610 void emit_Proj(ir_node *irn, emit_env_t *env) {
611 ir_node *pred = get_Proj_pred(irn);
613 if (get_irn_opcode(pred) == iro_Start) {
614 switch(get_Proj_proj(irn)) {
615 case pn_Start_X_initial_exec:
626 /***********************************************************************************
629 * _ __ ___ __ _ _ _ __ | |_ _ __ __ _ _ __ ___ _____ _____ _ __| | __
630 * | '_ ` _ \ / _` | | '_ \ | _| '__/ _` | '_ ` _ \ / _ \ \ /\ / / _ \| '__| |/ /
631 * | | | | | | (_| | | | | | | | | | | (_| | | | | | | __/\ V V / (_) | | | <
632 * |_| |_| |_|\__,_|_|_| |_| |_| |_| \__,_|_| |_| |_|\___| \_/\_/ \___/|_| |_|\_\
634 ***********************************************************************************/
637 * Emits code for a node.
639 void ia32_emit_node(ir_node *irn, void *env) {
640 emit_env_t *emit_env = env;
641 firm_dbg_module_t *mod = emit_env->mod;
642 FILE *F = emit_env->out;
644 DBG((mod, LEVEL_1, "emitting code for %+F\n", irn));
646 #define IA32_EMIT(a) if (is_ia32_##a(irn)) { emit_ia32_##a(irn, emit_env); return; }
647 #define EMIT(a) if (get_irn_opcode(irn) == iro_##a) { emit_##a(irn, emit_env); return; }
649 /* generated int emitter functions */
696 /* generated floating point emitter */
712 /* other emitter functions */
714 IA32_EMIT(CondJmp_i);
715 IA32_EMIT(SwitchJmp);
720 ir_fprintf(F, "\t\t\t\t\t/* %+F */\n", irn);
724 * Walks over the nodes in a block connected by scheduling edges
725 * and emits code for each node.
727 void ia32_gen_block(ir_node *block, void *env) {
730 if (! is_Block(block))
733 fprintf(((emit_env_t *)env)->out, "BLOCK_%ld:\n", get_irn_node_nr(block));
734 sched_foreach(block, irn) {
735 ia32_emit_node(irn, env);
741 * Emits code for function start.
743 void ia32_emit_start(FILE *F, ir_graph *irg) {
744 const char *irg_name = get_entity_name(get_irg_entity(irg));
746 fprintf(F, "\t.text\n");
747 fprintf(F, ".globl %s\n", irg_name);
748 fprintf(F, "\t.type\t%s, @function\n", irg_name);
749 fprintf(F, "%s:\n", irg_name);
753 * Emits code for function end
755 void ia32_emit_end(FILE *F, ir_graph *irg) {
756 const char *irg_name = get_entity_name(get_irg_entity(irg));
758 fprintf(F, "\tret\n");
759 fprintf(F, "\t.size\t%s, .-%s\n\n", irg_name, irg_name);
763 * Sets labels for control flow nodes (jump target)
764 * TODO: Jump optimization
766 void ia32_gen_labels(ir_node *block, void *env) {
768 int n = get_Block_n_cfgpreds(block);
770 for (n--; n >= 0; n--) {
771 pred = get_Block_cfgpred(block, n);
772 set_irn_link(pred, block);
779 void ia32_gen_routine(FILE *F, ir_graph *irg, const arch_env_t *env) {
782 emit_env.mod = firm_dbg_register("ir.be.codegen.ia32");
784 emit_env.arch_env = env;
788 ia32_emit_start(F, irg);
789 irg_block_walk_graph(irg, ia32_gen_labels, NULL, &emit_env);
790 irg_walk_blkwise_graph(irg, NULL, ia32_gen_block, &emit_env);
791 ia32_emit_end(F, irg);