2 * Copyright (C) 1995-2011 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This file implements the ia32 node emitter.
23 * @author Christian Wuerdig, Matthias Braun
26 * Summary table for x86 floatingpoint compares:
33 * pnc_Leg => NP (ordered)
55 #include "iredges_t.h"
59 #include "raw_bitset.h"
63 #include "../besched.h"
64 #include "../benode.h"
66 #include "../be_dbgout.h"
67 #include "../beemitter.h"
68 #include "../begnuas.h"
70 #include "../be_dbgout.h"
72 #include "ia32_emitter.h"
73 #include "ia32_common_transform.h"
74 #include "gen_ia32_emitter.h"
75 #include "gen_ia32_regalloc_if.h"
76 #include "ia32_nodes_attr.h"
77 #include "ia32_new_nodes.h"
78 #include "ia32_architecture.h"
79 #include "bearch_ia32_t.h"
81 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
83 #define SNPRINTF_BUF_LEN 128
85 static const ia32_isa_t *isa;
86 static char pic_base_label[128];
87 static ir_label_t exc_label_id;
88 static int mark_spill_reload = 0;
91 /** Return the next block in Block schedule */
92 static ir_node *get_prev_block_sched(const ir_node *block)
94 return (ir_node*)get_irn_link(block);
97 /** Checks if the current block is a fall-through target. */
98 static int is_fallthrough(const ir_node *cfgpred)
102 if (!is_Proj(cfgpred))
104 pred = get_Proj_pred(cfgpred);
105 if (is_ia32_SwitchJmp(pred))
112 * returns non-zero if the given block needs a label
113 * because of being a jump-target (and not a fall-through)
115 static int block_needs_label(const ir_node *block)
118 int n_cfgpreds = get_Block_n_cfgpreds(block);
120 if (has_Block_entity(block))
123 if (n_cfgpreds == 0) {
125 } else if (n_cfgpreds == 1) {
126 ir_node *cfgpred = get_Block_cfgpred(block, 0);
127 ir_node *cfgpred_block = get_nodes_block(cfgpred);
129 if (get_prev_block_sched(block) == cfgpred_block
130 && is_fallthrough(cfgpred)) {
139 * Returns the register at in position pos.
141 static const arch_register_t *get_in_reg(const ir_node *irn, int pos)
144 const arch_register_t *reg = NULL;
146 assert(get_irn_arity(irn) > pos && "Invalid IN position");
148 /* The out register of the operator at position pos is the
149 in register we need. */
150 op = get_irn_n(irn, pos);
152 reg = arch_get_irn_register(op);
154 assert(reg && "no in register found");
156 if (reg == &ia32_registers[REG_GP_NOREG])
157 panic("trying to emit noreg for %+F input %d", irn, pos);
163 * Returns the register at out position pos.
165 static const arch_register_t *get_out_reg(const ir_node *irn, int pos)
168 const arch_register_t *reg = NULL;
170 /* 1st case: irn is not of mode_T, so it has only */
171 /* one OUT register -> good */
172 /* 2nd case: irn is of mode_T -> collect all Projs and ask the */
173 /* Proj with the corresponding projnum for the register */
175 if (get_irn_mode(irn) != mode_T) {
177 reg = arch_get_irn_register(irn);
178 } else if (is_ia32_irn(irn)) {
179 reg = arch_irn_get_register(irn, pos);
181 const ir_edge_t *edge;
183 foreach_out_edge(irn, edge) {
184 proj = get_edge_src_irn(edge);
185 assert(is_Proj(proj) && "non-Proj from mode_T node");
186 if (get_Proj_proj(proj) == pos) {
187 reg = arch_get_irn_register(proj);
193 assert(reg && "no out register found");
198 * Add a number to a prefix. This number will not be used a second time.
200 static char *get_unique_label(char *buf, size_t buflen, const char *prefix)
202 static unsigned long id = 0;
203 snprintf(buf, buflen, "%s%s%lu", be_gas_get_private_prefix(), prefix, ++id);
208 * Emit the name of the 8bit low register
210 static void emit_8bit_register(const arch_register_t *reg)
212 const char *reg_name = arch_register_get_name(reg);
213 assert(reg->index == REG_GP_EAX || reg->index == REG_GP_EBX
214 || reg->index == REG_GP_ECX || reg->index == REG_GP_EDX);
217 be_emit_char(reg_name[1]); /* get the basic name of the register */
222 * Emit the name of the 8bit high register
224 static void emit_8bit_register_high(const arch_register_t *reg)
226 const char *reg_name = arch_register_get_name(reg);
227 assert(reg->index == REG_GP_EAX || reg->index == REG_GP_EBX
228 || reg->index == REG_GP_ECX || reg->index == REG_GP_EDX);
231 be_emit_char(reg_name[1]); /* get the basic name of the register */
235 static void emit_16bit_register(const arch_register_t *reg)
237 const char *reg_name = arch_register_get_name(reg);
240 be_emit_string(reg_name+1); /* skip the 'e' prefix of the 32bit names */
244 * emit a register, possible shortened by a mode
246 * @param reg the register
247 * @param mode the mode of the register or NULL for full register
249 static void emit_register(const arch_register_t *reg, const ir_mode *mode)
251 const char *reg_name;
254 int size = get_mode_size_bits(mode);
256 case 8: emit_8bit_register(reg); return;
257 case 16: emit_16bit_register(reg); return;
259 assert(mode_is_float(mode) || size == 32);
262 reg_name = arch_register_get_name(reg);
265 be_emit_string(reg_name);
268 void ia32_emit_source_register(const ir_node *node, int pos)
270 const arch_register_t *reg = get_in_reg(node, pos);
272 emit_register(reg, NULL);
275 static void ia32_emit_entity(ir_entity *entity, int no_pic_adjust)
277 be_gas_emit_entity(entity);
279 if (get_entity_owner(entity) == get_tls_type()) {
280 if (get_entity_visibility(entity) == ir_visibility_external) {
281 be_emit_cstring("@INDNTPOFF");
283 be_emit_cstring("@NTPOFF");
287 if (do_pic && !no_pic_adjust) {
289 be_emit_string(pic_base_label);
293 static void emit_ia32_Immediate_no_prefix(const ir_node *node)
295 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(node);
297 if (attr->symconst != NULL) {
300 ia32_emit_entity(attr->symconst, attr->no_pic_adjust);
302 if (attr->symconst == NULL || attr->offset != 0) {
303 if (attr->symconst != NULL) {
304 be_emit_irprintf("%+d", attr->offset);
306 be_emit_irprintf("0x%X", attr->offset);
311 static void emit_ia32_Immediate(const ir_node *node)
314 emit_ia32_Immediate_no_prefix(node);
317 void ia32_emit_8bit_source_register_or_immediate(const ir_node *node, int pos)
319 const arch_register_t *reg;
320 const ir_node *in = get_irn_n(node, pos);
321 if (is_ia32_Immediate(in)) {
322 emit_ia32_Immediate(in);
326 reg = get_in_reg(node, pos);
327 emit_8bit_register(reg);
330 void ia32_emit_8bit_high_source_register(const ir_node *node, int pos)
332 const arch_register_t *reg = get_in_reg(node, pos);
333 emit_8bit_register_high(reg);
336 void ia32_emit_16bit_source_register_or_immediate(const ir_node *node, int pos)
338 const arch_register_t *reg;
339 const ir_node *in = get_irn_n(node, pos);
340 if (is_ia32_Immediate(in)) {
341 emit_ia32_Immediate(in);
345 reg = get_in_reg(node, pos);
346 emit_16bit_register(reg);
349 void ia32_emit_dest_register(const ir_node *node, int pos)
351 const arch_register_t *reg = get_out_reg(node, pos);
353 emit_register(reg, NULL);
356 void ia32_emit_dest_register_size(const ir_node *node, int pos)
358 const arch_register_t *reg = get_out_reg(node, pos);
360 emit_register(reg, get_ia32_ls_mode(node));
363 void ia32_emit_8bit_dest_register(const ir_node *node, int pos)
365 const arch_register_t *reg = get_out_reg(node, pos);
367 emit_register(reg, mode_Bu);
370 void ia32_emit_x87_register(const ir_node *node, int pos)
372 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
376 be_emit_string(attr->x87[pos]->name);
379 static void ia32_emit_mode_suffix_mode(const ir_mode *mode)
381 assert(mode_is_int(mode) || mode_is_reference(mode));
382 switch (get_mode_size_bits(mode)) {
383 case 8: be_emit_char('b'); return;
384 case 16: be_emit_char('w'); return;
385 case 32: be_emit_char('l'); return;
386 /* gas docu says q is the suffix but gcc, objdump and icc use ll
388 case 64: be_emit_cstring("ll"); return;
390 panic("Can't output mode_suffix for %+F", mode);
393 void ia32_emit_mode_suffix(const ir_node *node)
395 ir_mode *mode = get_ia32_ls_mode(node);
399 ia32_emit_mode_suffix_mode(mode);
402 void ia32_emit_x87_mode_suffix(const ir_node *node)
406 /* we only need to emit the mode on address mode */
407 if (get_ia32_op_type(node) == ia32_Normal)
410 mode = get_ia32_ls_mode(node);
411 assert(mode != NULL);
413 if (mode_is_float(mode)) {
414 switch (get_mode_size_bits(mode)) {
415 case 32: be_emit_char('s'); return;
416 case 64: be_emit_char('l'); return;
417 /* long doubles have different sizes due to alignment on different
421 case 128: be_emit_char('t'); return;
424 assert(mode_is_int(mode) || mode_is_reference(mode));
425 switch (get_mode_size_bits(mode)) {
426 case 16: be_emit_char('s'); return;
427 case 32: be_emit_char('l'); return;
428 /* gas docu says q is the suffix but gcc, objdump and icc use ll
430 case 64: be_emit_cstring("ll"); return;
433 panic("Can't output mode_suffix for %+F", mode);
436 static char get_xmm_mode_suffix(ir_mode *mode)
438 assert(mode_is_float(mode));
439 switch (get_mode_size_bits(mode)) {
442 default: panic("Invalid XMM mode");
446 void ia32_emit_xmm_mode_suffix(const ir_node *node)
448 ir_mode *mode = get_ia32_ls_mode(node);
449 assert(mode != NULL);
451 be_emit_char(get_xmm_mode_suffix(mode));
454 void ia32_emit_xmm_mode_suffix_s(const ir_node *node)
456 ir_mode *mode = get_ia32_ls_mode(node);
457 assert(mode != NULL);
458 be_emit_char(get_xmm_mode_suffix(mode));
461 void ia32_emit_extend_suffix(const ir_node *node)
463 ir_mode *mode = get_ia32_ls_mode(node);
464 if (get_mode_size_bits(mode) == 32)
466 be_emit_char(mode_is_signed(mode) ? 's' : 'z');
467 ia32_emit_mode_suffix_mode(mode);
470 void ia32_emit_source_register_or_immediate(const ir_node *node, int pos)
472 ir_node *in = get_irn_n(node, pos);
473 if (is_ia32_Immediate(in)) {
474 emit_ia32_Immediate(in);
476 const ir_mode *mode = get_ia32_ls_mode(node);
477 const arch_register_t *reg = get_in_reg(node, pos);
478 emit_register(reg, mode);
483 * Returns the target block for a control flow node.
485 static ir_node *get_cfop_target_block(const ir_node *irn)
487 assert(get_irn_mode(irn) == mode_X);
488 return (ir_node*)get_irn_link(irn);
492 * Emits the target label for a control flow node.
494 static void ia32_emit_cfop_target(const ir_node *node)
496 ir_node *block = get_cfop_target_block(node);
497 be_gas_emit_block_name(block);
501 * positive conditions for signed compares
503 static const char *const cmp2condition_s[] = {
504 NULL, /* always false */
511 NULL /* always true */
515 * positive conditions for unsigned compares
517 static const char *const cmp2condition_u[] = {
518 NULL, /* always false */
525 NULL /* always true */
529 * Emit the suffix for a compare instruction.
531 static void ia32_emit_cmp_suffix(int pnc)
535 if (pnc == ia32_pn_Cmp_parity) {
540 if (pnc & ia32_pn_Cmp_float || pnc & ia32_pn_Cmp_unsigned) {
541 str = cmp2condition_u[pnc & 7];
543 str = cmp2condition_s[pnc & 7];
549 typedef enum ia32_emit_mod_t {
551 EMIT_RESPECT_LS = 1U << 0,
552 EMIT_ALTERNATE_AM = 1U << 1,
554 EMIT_HIGH_REG = 1U << 3,
555 EMIT_LOW_REG = 1U << 4
557 ENUM_BITSET(ia32_emit_mod_t)
560 * Emits address mode.
562 void ia32_emit_am(const ir_node *node)
564 ir_entity *ent = get_ia32_am_sc(node);
565 int offs = get_ia32_am_offs_int(node);
566 ir_node *base = get_irn_n(node, n_ia32_base);
567 int has_base = !is_ia32_NoReg_GP(base);
568 ir_node *index = get_irn_n(node, n_ia32_index);
569 int has_index = !is_ia32_NoReg_GP(index);
571 /* just to be sure... */
572 assert(!is_ia32_use_frame(node) || get_ia32_frame_ent(node) != NULL);
576 const ia32_attr_t *attr = get_ia32_attr_const(node);
577 if (is_ia32_am_sc_sign(node))
579 ia32_emit_entity(ent, attr->data.am_sc_no_pic_adjust);
582 /* also handle special case if nothing is set */
583 if (offs != 0 || (ent == NULL && !has_base && !has_index)) {
585 be_emit_irprintf("%+d", offs);
587 be_emit_irprintf("%d", offs);
591 if (has_base || has_index) {
596 const arch_register_t *reg = get_in_reg(node, n_ia32_base);
597 emit_register(reg, NULL);
600 /* emit index + scale */
602 const arch_register_t *reg = get_in_reg(node, n_ia32_index);
605 emit_register(reg, NULL);
607 scale = get_ia32_am_scale(node);
609 be_emit_irprintf(",%d", 1 << scale);
617 * fmt parameter output
618 * ---- ---------------------- ---------------------------------------------
620 * %AM <node> address mode of the node
621 * %AR const arch_register_t* address mode of the node or register
622 * %ASx <node> address mode of the node or source register x
623 * %Dx <node> destination register x
624 * %I <node> immediate of the node
625 * %L <node> control flow target of the node
626 * %M <node> mode suffix of the node
627 * %P int condition code
628 * %R const arch_register_t* register
629 * %Sx <node> source register x
630 * %s const char* string
631 * %u unsigned int unsigned int
632 * %d signed int signed int
635 * # modifier for %ASx, %D, %R, and %S uses ls mode of node to alter register width
636 * * modifier does not prefix immediates with $, but AM with *
637 * l modifier for %lu and %ld
638 * > modifier to output high 8bit register (ah, bh)
639 * < modifier to output low 8bit register (al, bl)
641 static void ia32_emitf(const ir_node *node, const char *fmt, ...)
647 const char *start = fmt;
648 ia32_emit_mod_t mod = EMIT_NONE;
650 while (*fmt != '%' && *fmt != '\n' && *fmt != '\0')
653 be_emit_string_len(start, fmt - start);
657 be_emit_finish_line_gas(node);
670 case '*': mod |= EMIT_ALTERNATE_AM; break;
671 case '#': mod |= EMIT_RESPECT_LS; break;
672 case 'l': mod |= EMIT_LONG; break;
673 case '>': mod |= EMIT_HIGH_REG; break;
674 case '<': mod |= EMIT_LOW_REG; break;
691 if (mod & EMIT_ALTERNATE_AM)
697 const arch_register_t *reg = va_arg(ap, const arch_register_t*);
698 if (get_ia32_op_type(node) == ia32_AddrModeS) {
701 if (mod & EMIT_ALTERNATE_AM)
703 emit_register(reg, NULL);
709 if (get_ia32_op_type(node) == ia32_AddrModeS) {
713 assert(get_ia32_op_type(node) == ia32_Normal);
718 default: goto unknown;
725 const arch_register_t *reg;
727 if (*fmt < '0' || '9' <= *fmt)
731 reg = get_out_reg(node, pos);
732 emit_register(reg, mod & EMIT_RESPECT_LS ? get_ia32_ls_mode(node) : NULL);
737 if (!(mod & EMIT_ALTERNATE_AM))
739 emit_ia32_Immediate_no_prefix(node);
743 ia32_emit_cfop_target(node);
747 ia32_emit_mode_suffix_mode(get_ia32_ls_mode(node));
752 int pnc = va_arg(ap, int);
753 ia32_emit_cmp_suffix(pnc);
758 const arch_register_t *reg = va_arg(ap, const arch_register_t*);
759 if (mod & EMIT_HIGH_REG) {
760 emit_8bit_register_high(reg);
761 } else if (mod & EMIT_LOW_REG) {
762 emit_8bit_register(reg);
764 emit_register(reg, mod & EMIT_RESPECT_LS ? get_ia32_ls_mode(node) : NULL);
774 if (*fmt < '0' || '9' <= *fmt)
778 in = get_irn_n(node, pos);
779 if (is_ia32_Immediate(in)) {
780 if (!(mod & EMIT_ALTERNATE_AM))
782 emit_ia32_Immediate_no_prefix(in);
784 const arch_register_t *reg;
786 if (mod & EMIT_ALTERNATE_AM)
788 reg = get_in_reg(node, pos);
789 emit_register(reg, mod & EMIT_RESPECT_LS ? get_ia32_ls_mode(node) : NULL);
795 const char *str = va_arg(ap, const char*);
801 if (mod & EMIT_LONG) {
802 unsigned long num = va_arg(ap, unsigned long);
803 be_emit_irprintf("%lu", num);
805 unsigned num = va_arg(ap, unsigned);
806 be_emit_irprintf("%u", num);
811 if (mod & EMIT_LONG) {
812 long num = va_arg(ap, long);
813 be_emit_irprintf("%ld", num);
815 int num = va_arg(ap, int);
816 be_emit_irprintf("%d", num);
822 panic("unknown format conversion in ia32_emitf()");
830 * Emits registers and/or address mode of a binary operation.
832 void ia32_emit_binop(const ir_node *node)
834 if (is_ia32_Immediate(get_irn_n(node, n_ia32_binary_right))) {
835 ia32_emitf(node, "%#S4, %#AS3");
837 ia32_emitf(node, "%#AS4, %#S3");
842 * Emits registers and/or address mode of a binary operation.
844 void ia32_emit_x87_binop(const ir_node *node)
846 switch (get_ia32_op_type(node)) {
849 const ia32_x87_attr_t *x87_attr = get_ia32_x87_attr_const(node);
850 const arch_register_t *in1 = x87_attr->x87[0];
851 const arch_register_t *in = x87_attr->x87[1];
852 const arch_register_t *out = x87_attr->x87[2];
856 } else if (out == in) {
861 be_emit_string(arch_register_get_name(in));
862 be_emit_cstring(", %");
863 be_emit_string(arch_register_get_name(out));
871 assert(0 && "unsupported op type");
876 * Emits registers and/or address mode of a unary operation.
878 void ia32_emit_unop(const ir_node *node, int pos)
882 ia32_emitf(node, fmt);
885 static void emit_ia32_IMul(const ir_node *node)
887 ir_node *left = get_irn_n(node, n_ia32_IMul_left);
888 const arch_register_t *out_reg = get_out_reg(node, pn_ia32_IMul_res);
890 /* do we need the 3-address form? */
891 if (is_ia32_NoReg_GP(left) ||
892 get_in_reg(node, n_ia32_IMul_left) != out_reg) {
893 ia32_emitf(node, "\timul%M %#S4, %#AS3, %#D0\n");
895 ia32_emitf(node, "\timul%M %#AS4, %#S3\n");
900 * walks up a tree of copies/perms/spills/reloads to find the original value
901 * that is moved around
903 static ir_node *find_original_value(ir_node *node)
905 if (irn_visited(node))
908 mark_irn_visited(node);
909 if (be_is_Copy(node)) {
910 return find_original_value(be_get_Copy_op(node));
911 } else if (be_is_CopyKeep(node)) {
912 return find_original_value(be_get_CopyKeep_op(node));
913 } else if (is_Proj(node)) {
914 ir_node *pred = get_Proj_pred(node);
915 if (be_is_Perm(pred)) {
916 return find_original_value(get_irn_n(pred, get_Proj_proj(node)));
917 } else if (be_is_MemPerm(pred)) {
918 return find_original_value(get_irn_n(pred, get_Proj_proj(node) + 1));
919 } else if (is_ia32_Load(pred)) {
920 return find_original_value(get_irn_n(pred, n_ia32_Load_mem));
924 } else if (is_ia32_Store(node)) {
925 return find_original_value(get_irn_n(node, n_ia32_Store_val));
926 } else if (is_Phi(node)) {
928 arity = get_irn_arity(node);
929 for (i = 0; i < arity; ++i) {
930 ir_node *in = get_irn_n(node, i);
931 ir_node *res = find_original_value(in);
942 static int determine_final_pnc(const ir_node *node, int flags_pos, int pnc)
944 ir_node *flags = get_irn_n(node, flags_pos);
945 const ia32_attr_t *flags_attr;
946 flags = skip_Proj(flags);
948 if (is_ia32_Sahf(flags)) {
949 ir_node *cmp = get_irn_n(flags, n_ia32_Sahf_val);
950 if (!(is_ia32_FucomFnstsw(cmp) || is_ia32_FucompFnstsw(cmp)
951 || is_ia32_FucomppFnstsw(cmp) || is_ia32_FtstFnstsw(cmp))) {
952 inc_irg_visited(current_ir_graph);
953 cmp = find_original_value(cmp);
955 assert(is_ia32_FucomFnstsw(cmp) || is_ia32_FucompFnstsw(cmp)
956 || is_ia32_FucomppFnstsw(cmp) || is_ia32_FtstFnstsw(cmp));
959 flags_attr = get_ia32_attr_const(cmp);
960 if (flags_attr->data.ins_permuted)
961 pnc = get_mirrored_pnc(pnc);
962 pnc |= ia32_pn_Cmp_float;
963 } else if (is_ia32_Ucomi(flags) || is_ia32_Fucomi(flags)
964 || is_ia32_Fucompi(flags)) {
965 flags_attr = get_ia32_attr_const(flags);
967 if (flags_attr->data.ins_permuted)
968 pnc = get_mirrored_pnc(pnc);
969 pnc |= ia32_pn_Cmp_float;
971 flags_attr = get_ia32_attr_const(flags);
973 if (flags_attr->data.ins_permuted)
974 pnc = get_mirrored_pnc(pnc);
975 if (flags_attr->data.cmp_unsigned)
976 pnc |= ia32_pn_Cmp_unsigned;
982 static int ia32_get_negated_pnc(int pnc)
984 ir_mode *mode = pnc & ia32_pn_Cmp_float ? mode_F : mode_Iu;
985 return get_negated_pnc(pnc, mode);
988 void ia32_emit_cmp_suffix_node(const ir_node *node, int flags_pos)
990 int pnc = get_ia32_condcode(node);
991 pnc = determine_final_pnc(node, flags_pos, pnc);
993 ia32_emit_cmp_suffix(pnc);
997 * Emits an exception label for a given node.
999 static void ia32_emit_exc_label(const ir_node *node)
1001 be_emit_string(be_gas_insn_label_prefix());
1002 be_emit_irprintf("%lu", get_ia32_exc_label_id(node));
1006 * Returns the Proj with projection number proj and NOT mode_M
1008 static ir_node *get_proj(const ir_node *node, long proj)
1010 const ir_edge_t *edge;
1013 assert(get_irn_mode(node) == mode_T && "expected mode_T node");
1015 foreach_out_edge(node, edge) {
1016 src = get_edge_src_irn(edge);
1018 assert(is_Proj(src) && "Proj expected");
1019 if (get_irn_mode(src) == mode_M)
1022 if (get_Proj_proj(src) == proj)
1028 static int can_be_fallthrough(const ir_node *node)
1030 ir_node *target_block = get_cfop_target_block(node);
1031 ir_node *block = get_nodes_block(node);
1032 return get_prev_block_sched(target_block) == block;
1036 * Emits the jump sequence for a conditional jump (cmp + jmp_true + jmp_false)
1038 static void emit_ia32_Jcc(const ir_node *node)
1040 int need_parity_label = 0;
1041 const ir_node *proj_true;
1042 const ir_node *proj_false;
1043 int pnc = get_ia32_condcode(node);
1045 pnc = determine_final_pnc(node, 0, pnc);
1047 /* get both Projs */
1048 proj_true = get_proj(node, pn_ia32_Jcc_true);
1049 assert(proj_true && "Jcc without true Proj");
1051 proj_false = get_proj(node, pn_ia32_Jcc_false);
1052 assert(proj_false && "Jcc without false Proj");
1054 if (can_be_fallthrough(proj_true)) {
1055 /* exchange both proj's so the second one can be omitted */
1056 const ir_node *t = proj_true;
1058 proj_true = proj_false;
1060 pnc = ia32_get_negated_pnc(pnc);
1063 if (pnc & ia32_pn_Cmp_float) {
1064 /* Some floating point comparisons require a test of the parity flag,
1065 * which indicates that the result is unordered */
1066 switch (pnc & 0x0f) {
1068 ia32_emitf(proj_true, "\tjp %L\n");
1073 ia32_emitf(proj_true, "\tjnp %L\n");
1079 /* we need a local label if the false proj is a fallthrough
1080 * as the falseblock might have no label emitted then */
1081 if (can_be_fallthrough(proj_false)) {
1082 need_parity_label = 1;
1083 ia32_emitf(proj_false, "\tjp 1f\n");
1085 ia32_emitf(proj_false, "\tjp %L\n");
1092 ia32_emitf(proj_true, "\tjp %L\n");
1100 ia32_emitf(proj_true, "\tj%P %L\n", pnc);
1103 if (need_parity_label) {
1104 ia32_emitf(NULL, "1:\n");
1107 /* the second Proj might be a fallthrough */
1108 if (can_be_fallthrough(proj_false)) {
1109 ia32_emitf(proj_false, "\t/* fallthrough to %L */\n");
1111 ia32_emitf(proj_false, "\tjmp %L\n");
1116 * Emits an ia32 Setcc. This is mostly easy but some floating point compares
1119 static void emit_ia32_Setcc(const ir_node *node)
1121 const arch_register_t *dreg = get_out_reg(node, pn_ia32_Setcc_res);
1123 int pnc = get_ia32_condcode(node);
1124 pnc = determine_final_pnc(node, n_ia32_Setcc_eflags, pnc);
1125 if (pnc & ia32_pn_Cmp_float) {
1126 switch (pnc & 0x0f) {
1128 ia32_emitf(node, "\tsetp %#R\n", dreg);
1132 ia32_emitf(node, "\tsetnp %#R\n", dreg);
1138 ia32_emitf(node, "\tset%P %<R\n", pnc, dreg);
1139 ia32_emitf(node, "\tsetnp %>R\n", dreg);
1140 ia32_emitf(node, "\tandb %>R, %<R\n", dreg, dreg);
1146 ia32_emitf(node, "\tset%P %<R\n", pnc, dreg);
1147 ia32_emitf(node, "\tsetp %>R\n", dreg);
1148 ia32_emitf(node, "\torb %>R, %<R\n", dreg, dreg);
1155 ia32_emitf(node, "\tset%P %#R\n", pnc, dreg);
1158 static void emit_ia32_CMovcc(const ir_node *node)
1160 const ia32_attr_t *attr = get_ia32_attr_const(node);
1161 const arch_register_t *out = arch_irn_get_register(node, pn_ia32_res);
1162 int pnc = get_ia32_condcode(node);
1163 const arch_register_t *in_true;
1164 const arch_register_t *in_false;
1166 pnc = determine_final_pnc(node, n_ia32_CMovcc_eflags, pnc);
1167 /* although you can't set ins_permuted in the constructor it might still
1168 * be set by memory operand folding
1169 * Permuting inputs of a cmov means the condition is negated!
1171 if (attr->data.ins_permuted)
1172 pnc = ia32_get_negated_pnc(pnc);
1174 in_true = arch_get_irn_register(get_irn_n(node, n_ia32_CMovcc_val_true));
1175 in_false = arch_get_irn_register(get_irn_n(node, n_ia32_CMovcc_val_false));
1177 /* should be same constraint fullfilled? */
1178 if (out == in_false) {
1179 /* yes -> nothing to do */
1180 } else if (out == in_true) {
1181 const arch_register_t *tmp;
1183 assert(get_ia32_op_type(node) == ia32_Normal);
1185 pnc = ia32_get_negated_pnc(pnc);
1192 ia32_emitf(node, "\tmovl %R, %R\n", in_false, out);
1195 /* TODO: handling of Nans isn't correct yet */
1196 if (pnc & ia32_pn_Cmp_float) {
1197 switch (pnc & 0x0f) {
1206 panic("CMov with floatingpoint compare/parity not supported yet");
1210 ia32_emitf(node, "\tcmov%P %#AR, %#R\n", pnc, in_true, out);
1214 /* jump table entry (target and corresponding number) */
1215 typedef struct branch_t {
1220 /* jump table for switch generation */
1221 typedef struct jmp_tbl_t {
1222 ir_node *defProj; /**< default target */
1223 long min_value; /**< smallest switch case */
1224 long max_value; /**< largest switch case */
1225 long num_branches; /**< number of jumps */
1226 char label[SNPRINTF_BUF_LEN]; /**< label of the jump table */
1227 branch_t *branches; /**< jump array */
1231 * Compare two variables of type branch_t. Used to sort all switch cases
1233 static int ia32_cmp_branch_t(const void *a, const void *b)
1235 branch_t *b1 = (branch_t *)a;
1236 branch_t *b2 = (branch_t *)b;
1238 if (b1->value <= b2->value)
1244 static void generate_jump_table(jmp_tbl_t *tbl, const ir_node *node)
1250 const ir_edge_t *edge;
1252 /* fill the table structure */
1253 get_unique_label(tbl->label, SNPRINTF_BUF_LEN, "TBL_");
1254 tbl->defProj = NULL;
1255 tbl->num_branches = get_irn_n_edges(node) - 1;
1256 tbl->branches = XMALLOCNZ(branch_t, tbl->num_branches);
1257 tbl->min_value = LONG_MAX;
1258 tbl->max_value = LONG_MIN;
1260 default_pn = get_ia32_condcode(node);
1262 /* go over all proj's and collect them */
1263 foreach_out_edge(node, edge) {
1264 proj = get_edge_src_irn(edge);
1265 assert(is_Proj(proj) && "Only proj allowed at SwitchJmp");
1267 pnc = get_Proj_proj(proj);
1269 /* check for default proj */
1270 if (pnc == default_pn) {
1271 assert(tbl->defProj == NULL && "found two default Projs at SwitchJmp");
1272 tbl->defProj = proj;
1274 tbl->min_value = pnc < tbl->min_value ? pnc : tbl->min_value;
1275 tbl->max_value = pnc > tbl->max_value ? pnc : tbl->max_value;
1277 /* create branch entry */
1278 tbl->branches[i].target = proj;
1279 tbl->branches[i].value = pnc;
1284 assert(i == tbl->num_branches);
1286 /* sort the branches by their number */
1287 qsort(tbl->branches, tbl->num_branches, sizeof(tbl->branches[0]), ia32_cmp_branch_t);
1291 * Emits code for a SwitchJmp (creates a jump table if
1292 * possible otherwise a cmp-jmp cascade). Port from
1295 static void emit_ia32_SwitchJmp(const ir_node *node)
1297 unsigned long interval;
1301 /* fill the table structure */
1302 generate_jump_table(&tbl, node);
1304 /* two-complement's magic make this work without overflow */
1305 interval = tbl.max_value - tbl.min_value;
1307 /* emit the table */
1308 ia32_emitf(node, "\tcmpl $%u, %S0\n", interval);
1309 ia32_emitf(tbl.defProj, "\tja %L\n");
1311 if (tbl.num_branches > 1) {
1313 ia32_emitf(node, "\tjmp *%s(,%S0,4)\n", tbl.label);
1315 be_gas_emit_switch_section(GAS_SECTION_RODATA);
1316 ia32_emitf(NULL, "\t.align 4\n");
1317 ia32_emitf(NULL, "%s:\n", tbl.label);
1319 last_value = tbl.branches[0].value;
1320 for (i = 0; i != tbl.num_branches; ++i) {
1321 while (last_value != tbl.branches[i].value) {
1322 ia32_emitf(tbl.defProj, ".long %L\n");
1325 ia32_emitf(tbl.branches[i].target, ".long %L\n");
1328 be_gas_emit_switch_section(GAS_SECTION_TEXT);
1330 /* one jump is enough */
1331 ia32_emitf(tbl.branches[0].target, "\tjmp %L\n");
1338 * Emits code for a unconditional jump.
1340 static void emit_ia32_Jmp(const ir_node *node)
1344 /* for now, the code works for scheduled and non-schedules blocks */
1345 block = get_nodes_block(node);
1347 /* we have a block schedule */
1348 if (can_be_fallthrough(node)) {
1349 ia32_emitf(node, "\t/* fallthrough to %L */\n");
1351 ia32_emitf(node, "\tjmp %L\n");
1356 * Emit an inline assembler operand.
1358 * @param node the ia32_ASM node
1359 * @param s points to the operand (a %c)
1361 * @return pointer to the first char in s NOT in the current operand
1363 static const char* emit_asm_operand(const ir_node *node, const char *s)
1365 const ia32_attr_t *ia32_attr = get_ia32_attr_const(node);
1366 const ia32_asm_attr_t *attr = CONST_CAST_IA32_ATTR(ia32_asm_attr_t,
1368 const arch_register_t *reg;
1369 const ia32_asm_reg_t *asm_regs = attr->register_map;
1370 const ia32_asm_reg_t *asm_reg;
1379 /* parse modifiers */
1382 ir_fprintf(stderr, "Warning: asm text (%+F) ends with %%\n", node);
1407 "Warning: asm text (%+F) contains unknown modifier '%c' for asm op\n",
1414 if (sscanf(s, "%d%n", &num, &p) != 1) {
1415 ir_fprintf(stderr, "Warning: Couldn't parse assembler operand (%+F)\n",
1422 if (num < 0 || ARR_LEN(asm_regs) <= (size_t)num) {
1424 "Error: Custom assembler references invalid input/output (%+F)\n",
1428 asm_reg = & asm_regs[num];
1429 assert(asm_reg->valid);
1432 if (asm_reg->use_input == 0) {
1433 reg = get_out_reg(node, asm_reg->inout_pos);
1435 ir_node *pred = get_irn_n(node, asm_reg->inout_pos);
1437 /* might be an immediate value */
1438 if (is_ia32_Immediate(pred)) {
1439 emit_ia32_Immediate(pred);
1442 reg = get_in_reg(node, asm_reg->inout_pos);
1446 "Warning: no register assigned for %d asm op (%+F)\n",
1451 if (asm_reg->memory) {
1456 if (modifier != 0) {
1459 emit_8bit_register(reg);
1462 emit_8bit_register_high(reg);
1465 emit_16bit_register(reg);
1468 panic("Invalid asm op modifier");
1471 emit_register(reg, asm_reg->mode);
1474 if (asm_reg->memory) {
1482 * Emits code for an ASM pseudo op.
1484 static void emit_ia32_Asm(const ir_node *node)
1486 const void *gen_attr = get_irn_generic_attr_const(node);
1487 const ia32_asm_attr_t *attr
1488 = CONST_CAST_IA32_ATTR(ia32_asm_attr_t, gen_attr);
1489 ident *asm_text = attr->asm_text;
1490 const char *s = get_id_str(asm_text);
1492 ia32_emitf(node, "#APP\t\n");
1499 s = emit_asm_operand(node, s);
1505 ia32_emitf(NULL, "\n#NO_APP\n");
1510 * Emit movsb/w instructions to make mov count divideable by 4
1512 static void emit_CopyB_prolog(unsigned size)
1515 ia32_emitf(NULL, "\tmovsb\n");
1517 ia32_emitf(NULL, "\tmovsw\n");
1521 * Emit rep movsd instruction for memcopy.
1523 static void emit_ia32_CopyB(const ir_node *node)
1525 unsigned size = get_ia32_copyb_size(node);
1527 emit_CopyB_prolog(size);
1528 ia32_emitf(node, "\trep movsd\n");
1532 * Emits unrolled memcopy.
1534 static void emit_ia32_CopyB_i(const ir_node *node)
1536 unsigned size = get_ia32_copyb_size(node);
1538 emit_CopyB_prolog(size);
1542 ia32_emitf(NULL, "\tmovsd\n");
1548 * Emit code for conversions (I, FP), (FP, I) and (FP, FP).
1550 static void emit_ia32_Conv_with_FP(const ir_node *node, const char* conv_f,
1553 ir_mode *ls_mode = get_ia32_ls_mode(node);
1554 int ls_bits = get_mode_size_bits(ls_mode);
1555 const char *conv = ls_bits == 32 ? conv_f : conv_d;
1557 ia32_emitf(node, "\tcvt%s %AS3, %D0\n", conv);
1560 static void emit_ia32_Conv_I2FP(const ir_node *node)
1562 emit_ia32_Conv_with_FP(node, "si2ss", "si2sd");
1565 static void emit_ia32_Conv_FP2I(const ir_node *node)
1567 emit_ia32_Conv_with_FP(node, "ss2si", "sd2si");
1570 static void emit_ia32_Conv_FP2FP(const ir_node *node)
1572 emit_ia32_Conv_with_FP(node, "sd2ss", "ss2sd");
1576 * Emits code for an Int conversion.
1578 static void emit_ia32_Conv_I2I(const ir_node *node)
1580 ir_mode *smaller_mode = get_ia32_ls_mode(node);
1581 int signed_mode = mode_is_signed(smaller_mode);
1582 const char *sign_suffix;
1584 assert(!mode_is_float(smaller_mode));
1586 sign_suffix = signed_mode ? "s" : "z";
1587 ia32_emitf(node, "\tmov%s%Ml %#AS3, %D0\n", sign_suffix);
1593 static void emit_ia32_Call(const ir_node *node)
1595 /* Special case: Call must not have its immediates prefixed by $, instead
1596 * address mode is prefixed by *. */
1597 ia32_emitf(node, "\tcall %*AS3\n");
1602 * Emits code to increase stack pointer.
1604 static void emit_be_IncSP(const ir_node *node)
1606 int offs = be_get_IncSP_offset(node);
1612 ia32_emitf(node, "\tsubl $%u, %D0\n", offs);
1614 ia32_emitf(node, "\taddl $%u, %D0\n", -offs);
1619 * Emits code for Copy/CopyKeep.
1621 static void Copy_emitter(const ir_node *node, const ir_node *op)
1623 const arch_register_t *in = arch_get_irn_register(op);
1624 const arch_register_t *out = arch_get_irn_register(node);
1629 /* copies of vf nodes aren't real... */
1630 if (arch_register_get_class(in) == &ia32_reg_classes[CLASS_ia32_vfp])
1633 if (get_irn_mode(node) == mode_E) {
1634 ia32_emitf(node, "\tmovsd %R, %R\n", in, out);
1636 ia32_emitf(node, "\tmovl %R, %R\n", in, out);
1640 static void emit_be_Copy(const ir_node *node)
1642 Copy_emitter(node, be_get_Copy_op(node));
1645 static void emit_be_CopyKeep(const ir_node *node)
1647 Copy_emitter(node, be_get_CopyKeep_op(node));
1651 * Emits code for exchange.
1653 static void emit_be_Perm(const ir_node *node)
1655 const arch_register_t *in0, *in1;
1656 const arch_register_class_t *cls0, *cls1;
1658 in0 = arch_get_irn_register(get_irn_n(node, 0));
1659 in1 = arch_get_irn_register(get_irn_n(node, 1));
1661 cls0 = arch_register_get_class(in0);
1662 cls1 = arch_register_get_class(in1);
1664 assert(cls0 == cls1 && "Register class mismatch at Perm");
1666 if (cls0 == &ia32_reg_classes[CLASS_ia32_gp]) {
1667 ia32_emitf(node, "\txchg %R, %R\n", in1, in0);
1668 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_xmm]) {
1669 ia32_emitf(NULL, "\txorpd %R, %R\n", in1, in0);
1670 ia32_emitf(NULL, "\txorpd %R, %R\n", in0, in1);
1671 ia32_emitf(node, "\txorpd %R, %R\n", in1, in0);
1672 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_vfp]) {
1674 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_st]) {
1677 panic("unexpected register class in be_Perm (%+F)", node);
1682 * Emits code for Constant loading.
1684 static void emit_ia32_Const(const ir_node *node)
1686 ia32_emitf(node, "\tmovl %I, %D0\n");
1690 * Emits code to load the TLS base
1692 static void emit_ia32_LdTls(const ir_node *node)
1694 ia32_emitf(node, "\tmovl %%gs:0, %D0\n");
1697 /* helper function for emit_ia32_Minus64Bit */
1698 static void emit_mov(const ir_node* node, const arch_register_t *src, const arch_register_t *dst)
1700 ia32_emitf(node, "\tmovl %R, %R\n", src, dst);
1703 /* helper function for emit_ia32_Minus64Bit */
1704 static void emit_neg(const ir_node* node, const arch_register_t *reg)
1706 ia32_emitf(node, "\tnegl %R\n", reg);
1709 /* helper function for emit_ia32_Minus64Bit */
1710 static void emit_sbb0(const ir_node* node, const arch_register_t *reg)
1712 ia32_emitf(node, "\tsbbl $0, %R\n", reg);
1715 /* helper function for emit_ia32_Minus64Bit */
1716 static void emit_sbb(const ir_node* node, const arch_register_t *src, const arch_register_t *dst)
1718 ia32_emitf(node, "\tsbbl %R, %R\n", src, dst);
1721 /* helper function for emit_ia32_Minus64Bit */
1722 static void emit_xchg(const ir_node* node, const arch_register_t *src, const arch_register_t *dst)
1724 ia32_emitf(node, "\txchgl %R, %R\n", src, dst);
1727 /* helper function for emit_ia32_Minus64Bit */
1728 static void emit_zero(const ir_node* node, const arch_register_t *reg)
1730 ia32_emitf(node, "\txorl %R, %R\n", reg, reg);
1733 static void emit_ia32_Minus64Bit(const ir_node *node)
1735 const arch_register_t *in_lo = get_in_reg(node, 0);
1736 const arch_register_t *in_hi = get_in_reg(node, 1);
1737 const arch_register_t *out_lo = get_out_reg(node, 0);
1738 const arch_register_t *out_hi = get_out_reg(node, 1);
1740 if (out_lo == in_lo) {
1741 if (out_hi != in_hi) {
1742 /* a -> a, b -> d */
1745 /* a -> a, b -> b */
1748 } else if (out_lo == in_hi) {
1749 if (out_hi == in_lo) {
1750 /* a -> b, b -> a */
1751 emit_xchg(node, in_lo, in_hi);
1754 /* a -> b, b -> d */
1755 emit_mov(node, in_hi, out_hi);
1756 emit_mov(node, in_lo, out_lo);
1760 if (out_hi == in_lo) {
1761 /* a -> c, b -> a */
1762 emit_mov(node, in_lo, out_lo);
1764 } else if (out_hi == in_hi) {
1765 /* a -> c, b -> b */
1766 emit_mov(node, in_lo, out_lo);
1769 /* a -> c, b -> d */
1770 emit_mov(node, in_lo, out_lo);
1776 emit_neg( node, out_hi);
1777 emit_neg( node, out_lo);
1778 emit_sbb0(node, out_hi);
1782 emit_zero(node, out_hi);
1783 emit_neg( node, out_lo);
1784 emit_sbb( node, in_hi, out_hi);
1787 static void emit_ia32_GetEIP(const ir_node *node)
1789 ia32_emitf(node, "\tcall %s\n", pic_base_label);
1790 ia32_emitf(NULL, "%s:\n", pic_base_label);
1791 ia32_emitf(node, "\tpopl %D0\n");
1794 static void emit_ia32_ClimbFrame(const ir_node *node)
1796 const ia32_climbframe_attr_t *attr = get_ia32_climbframe_attr_const(node);
1798 ia32_emitf(node, "\tmovl %S0, %D0\n");
1799 ia32_emitf(node, "\tmovl $%u, %S1\n", attr->count);
1800 be_gas_emit_block_name(node);
1801 be_emit_cstring(":\n");
1802 be_emit_write_line();
1803 ia32_emitf(node, "\tmovl (%D0), %D0\n");
1804 ia32_emitf(node, "\tdec %S1\n");
1805 be_emit_cstring("\tjnz ");
1806 be_gas_emit_block_name(node);
1807 be_emit_finish_line_gas(node);
1810 static void emit_be_Return(const ir_node *node)
1812 unsigned pop = be_Return_get_pop(node);
1814 if (pop > 0 || be_Return_get_emit_pop(node)) {
1815 ia32_emitf(node, "\tret $%u\n", pop);
1817 ia32_emitf(node, "\tret\n");
1821 static void emit_Nothing(const ir_node *node)
1828 * Enters the emitter functions for handled nodes into the generic
1829 * pointer of an opcode.
1831 static void ia32_register_emitters(void)
1833 #define IA32_EMIT2(a,b) op_ia32_##a->ops.generic = (op_func)emit_ia32_##b
1834 #define IA32_EMIT(a) IA32_EMIT2(a,a)
1835 #define EMIT(a) op_##a->ops.generic = (op_func)emit_##a
1836 #define IGN(a) op_##a->ops.generic = (op_func)emit_Nothing
1837 #define BE_EMIT(a) op_be_##a->ops.generic = (op_func)emit_be_##a
1838 #define BE_IGN(a) op_be_##a->ops.generic = (op_func)emit_Nothing
1840 /* first clear the generic function pointer for all ops */
1841 clear_irp_opcodes_generic_func();
1843 /* register all emitter functions defined in spec */
1844 ia32_register_spec_emitters();
1846 /* other ia32 emitter functions */
1847 IA32_EMIT2(Conv_I2I8Bit, Conv_I2I);
1852 IA32_EMIT(Conv_FP2FP);
1853 IA32_EMIT(Conv_FP2I);
1854 IA32_EMIT(Conv_I2FP);
1855 IA32_EMIT(Conv_I2I);
1863 IA32_EMIT(Minus64Bit);
1864 IA32_EMIT(SwitchJmp);
1865 IA32_EMIT(ClimbFrame);
1868 /* benode emitter */
1889 typedef void (*emit_func_ptr) (const ir_node *);
1892 * Assign and emit an exception label if the current instruction can fail.
1894 static void ia32_assign_exc_label(ir_node *node)
1896 /* assign a new ID to the instruction */
1897 set_ia32_exc_label_id(node, ++exc_label_id);
1899 ia32_emit_exc_label(node);
1901 be_emit_pad_comment();
1902 be_emit_cstring("/* exception to Block ");
1903 ia32_emit_cfop_target(node);
1904 be_emit_cstring(" */\n");
1905 be_emit_write_line();
1909 * Emits code for a node.
1911 static void ia32_emit_node(ir_node *node)
1913 ir_op *op = get_irn_op(node);
1915 DBG((dbg, LEVEL_1, "emitting code for %+F\n", node));
1917 if (is_ia32_irn(node)) {
1918 if (get_ia32_exc_label(node)) {
1919 /* emit the exception label of this instruction */
1920 ia32_assign_exc_label(node);
1922 if (mark_spill_reload) {
1923 if (is_ia32_is_spill(node)) {
1924 ia32_emitf(NULL, "\txchg %ebx, %ebx /* spill mark */\n");
1926 if (is_ia32_is_reload(node)) {
1927 ia32_emitf(NULL, "\txchg %edx, %edx /* reload mark */\n");
1929 if (is_ia32_is_remat(node)) {
1930 ia32_emitf(NULL, "\txchg %ecx, %ecx /* remat mark */\n");
1934 if (op->ops.generic) {
1935 emit_func_ptr func = (emit_func_ptr) op->ops.generic;
1937 be_dbg_set_dbg_info(get_irn_dbg_info(node));
1942 ir_fprintf(stderr, "Error: No emit handler for node %+F (%+G, graph %+F)\n", node, node, current_ir_graph);
1948 * Emits gas alignment directives
1950 static void ia32_emit_alignment(unsigned align, unsigned skip)
1952 ia32_emitf(NULL, "\t.p2align %u,,%u\n", align, skip);
1956 * Emits gas alignment directives for Labels depended on cpu architecture.
1958 static void ia32_emit_align_label(void)
1960 unsigned align = ia32_cg_config.label_alignment;
1961 unsigned maximum_skip = ia32_cg_config.label_alignment_max_skip;
1962 ia32_emit_alignment(align, maximum_skip);
1966 * Test whether a block should be aligned.
1967 * For cpus in the P4/Athlon class it is useful to align jump labels to
1968 * 16 bytes. However we should only do that if the alignment nops before the
1969 * label aren't executed more often than we have jumps to the label.
1971 static int should_align_block(const ir_node *block)
1973 static const double DELTA = .0001;
1974 ir_graph *irg = get_irn_irg(block);
1975 ir_exec_freq *exec_freq = be_get_irg_exec_freq(irg);
1976 ir_node *prev = get_prev_block_sched(block);
1978 double prev_freq = 0; /**< execfreq of the fallthrough block */
1979 double jmp_freq = 0; /**< execfreq of all non-fallthrough blocks */
1982 if (exec_freq == NULL)
1984 if (ia32_cg_config.label_alignment_factor <= 0)
1987 block_freq = get_block_execfreq(exec_freq, block);
1988 if (block_freq < DELTA)
1991 n_cfgpreds = get_Block_n_cfgpreds(block);
1992 for (i = 0; i < n_cfgpreds; ++i) {
1993 const ir_node *pred = get_Block_cfgpred_block(block, i);
1994 double pred_freq = get_block_execfreq(exec_freq, pred);
1997 prev_freq += pred_freq;
1999 jmp_freq += pred_freq;
2003 if (prev_freq < DELTA && !(jmp_freq < DELTA))
2006 jmp_freq /= prev_freq;
2008 return jmp_freq > ia32_cg_config.label_alignment_factor;
2012 * Emit the block header for a block.
2014 * @param block the block
2015 * @param prev_block the previous block
2017 static void ia32_emit_block_header(ir_node *block)
2019 ir_graph *irg = current_ir_graph;
2020 int need_label = block_needs_label(block);
2022 ir_exec_freq *exec_freq = be_get_irg_exec_freq(irg);
2024 if (block == get_irg_end_block(irg))
2027 if (ia32_cg_config.label_alignment > 0) {
2028 /* align the current block if:
2029 * a) if should be aligned due to its execution frequency
2030 * b) there is no fall-through here
2032 if (should_align_block(block)) {
2033 ia32_emit_align_label();
2035 /* if the predecessor block has no fall-through,
2036 we can always align the label. */
2038 int has_fallthrough = 0;
2040 for (i = get_Block_n_cfgpreds(block) - 1; i >= 0; --i) {
2041 ir_node *cfg_pred = get_Block_cfgpred(block, i);
2042 if (can_be_fallthrough(cfg_pred)) {
2043 has_fallthrough = 1;
2048 if (!has_fallthrough)
2049 ia32_emit_align_label();
2054 be_gas_emit_block_name(block);
2057 be_emit_pad_comment();
2058 be_emit_cstring(" /* ");
2060 be_emit_cstring("\t/* ");
2061 be_gas_emit_block_name(block);
2062 be_emit_cstring(": ");
2065 be_emit_cstring("preds:");
2067 /* emit list of pred blocks in comment */
2068 arity = get_irn_arity(block);
2070 be_emit_cstring(" none");
2072 for (i = 0; i < arity; ++i) {
2073 ir_node *predblock = get_Block_cfgpred_block(block, i);
2074 be_emit_irprintf(" %d", get_irn_node_nr(predblock));
2077 if (exec_freq != NULL) {
2078 be_emit_irprintf(", freq: %f",
2079 get_block_execfreq(exec_freq, block));
2081 be_emit_cstring(" */\n");
2082 be_emit_write_line();
2086 * Walks over the nodes in a block connected by scheduling edges
2087 * and emits code for each node.
2089 static void ia32_gen_block(ir_node *block)
2093 ia32_emit_block_header(block);
2095 /* emit the contents of the block */
2096 be_dbg_set_dbg_info(get_irn_dbg_info(block));
2097 sched_foreach(block, node) {
2098 ia32_emit_node(node);
2102 typedef struct exc_entry {
2103 ir_node *exc_instr; /** The instruction that can issue an exception. */
2104 ir_node *block; /** The block to call then. */
2109 * Sets labels for control flow nodes (jump target).
2110 * Links control predecessors to there destination blocks.
2112 static void ia32_gen_labels(ir_node *block, void *data)
2114 exc_entry **exc_list = (exc_entry**)data;
2118 for (n = get_Block_n_cfgpreds(block) - 1; n >= 0; --n) {
2119 pred = get_Block_cfgpred(block, n);
2120 set_irn_link(pred, block);
2122 pred = skip_Proj(pred);
2123 if (is_ia32_irn(pred) && get_ia32_exc_label(pred)) {
2128 ARR_APP1(exc_entry, *exc_list, e);
2129 set_irn_link(pred, block);
2135 * Compare two exception_entries.
2137 static int cmp_exc_entry(const void *a, const void *b)
2139 const exc_entry *ea = (const exc_entry*)a;
2140 const exc_entry *eb = (const exc_entry*)b;
2142 if (get_ia32_exc_label_id(ea->exc_instr) < get_ia32_exc_label_id(eb->exc_instr))
2148 * Main driver. Emits the code for one routine.
2150 void ia32_gen_routine(ir_graph *irg)
2152 ir_entity *entity = get_irg_entity(irg);
2153 exc_entry *exc_list = NEW_ARR_F(exc_entry, 0);
2154 const arch_env_t *arch_env = be_get_irg_arch_env(irg);
2155 ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
2156 ir_node **blk_sched = irg_data->blk_sched;
2159 isa = (ia32_isa_t*) arch_env;
2160 do_pic = be_get_irg_options(irg)->pic;
2162 be_gas_elf_type_char = '@';
2164 ia32_register_emitters();
2166 get_unique_label(pic_base_label, sizeof(pic_base_label), "PIC_BASE");
2168 be_dbg_method_begin(entity);
2169 be_gas_emit_function_prolog(entity, ia32_cg_config.function_alignment);
2171 /* we use links to point to target blocks */
2172 ir_reserve_resources(irg, IR_RESOURCE_IRN_LINK);
2173 irg_block_walk_graph(irg, ia32_gen_labels, NULL, &exc_list);
2175 /* initialize next block links */
2176 n = ARR_LEN(blk_sched);
2177 for (i = 0; i < n; ++i) {
2178 ir_node *block = blk_sched[i];
2179 ir_node *prev = i > 0 ? blk_sched[i-1] : NULL;
2181 set_irn_link(block, prev);
2184 for (i = 0; i < n; ++i) {
2185 ir_node *block = blk_sched[i];
2187 ia32_gen_block(block);
2190 be_gas_emit_function_epilog(entity);
2191 be_dbg_method_end();
2193 be_emit_write_line();
2195 ir_free_resources(irg, IR_RESOURCE_IRN_LINK);
2197 /* Sort the exception table using the exception label id's.
2198 Those are ascending with ascending addresses. */
2199 qsort(exc_list, ARR_LEN(exc_list), sizeof(exc_list[0]), cmp_exc_entry);
2203 for (i = 0; i < ARR_LEN(exc_list); ++i) {
2204 be_emit_cstring("\t.long ");
2205 ia32_emit_exc_label(exc_list[i].exc_instr);
2207 be_emit_cstring("\t.long ");
2208 be_gas_emit_block_name(exc_list[i].block);
2212 DEL_ARR_F(exc_list);
2215 static const lc_opt_table_entry_t ia32_emitter_options[] = {
2216 LC_OPT_ENT_BOOL("mark_spill_reload", "mark spills and reloads with ud opcodes", &mark_spill_reload),
2220 /* ==== Experimental binary emitter ==== */
2222 static unsigned char reg_gp_map[N_ia32_gp_REGS];
2223 //static unsigned char reg_mmx_map[N_ia32_mmx_REGS];
2224 //static unsigned char reg_sse_map[N_ia32_xmm_REGS];
2225 static unsigned char pnc_map_signed[8];
2226 static unsigned char pnc_map_unsigned[8];
2228 static void build_reg_map(void)
2230 reg_gp_map[REG_GP_EAX] = 0x0;
2231 reg_gp_map[REG_GP_ECX] = 0x1;
2232 reg_gp_map[REG_GP_EDX] = 0x2;
2233 reg_gp_map[REG_GP_EBX] = 0x3;
2234 reg_gp_map[REG_GP_ESP] = 0x4;
2235 reg_gp_map[REG_GP_EBP] = 0x5;
2236 reg_gp_map[REG_GP_ESI] = 0x6;
2237 reg_gp_map[REG_GP_EDI] = 0x7;
2239 pnc_map_signed[pn_Cmp_Eq] = 0x04;
2240 pnc_map_signed[pn_Cmp_Lt] = 0x0C;
2241 pnc_map_signed[pn_Cmp_Le] = 0x0E;
2242 pnc_map_signed[pn_Cmp_Gt] = 0x0F;
2243 pnc_map_signed[pn_Cmp_Ge] = 0x0D;
2244 pnc_map_signed[pn_Cmp_Lg] = 0x05;
2246 pnc_map_unsigned[pn_Cmp_Eq] = 0x04;
2247 pnc_map_unsigned[pn_Cmp_Lt] = 0x02;
2248 pnc_map_unsigned[pn_Cmp_Le] = 0x06;
2249 pnc_map_unsigned[pn_Cmp_Gt] = 0x07;
2250 pnc_map_unsigned[pn_Cmp_Ge] = 0x03;
2251 pnc_map_unsigned[pn_Cmp_Lg] = 0x05;
2254 /** Returns the encoding for a pnc field. */
2255 static unsigned char pnc2cc(int pnc)
2258 if (pnc == ia32_pn_Cmp_parity) {
2260 } else if (pnc & ia32_pn_Cmp_float || pnc & ia32_pn_Cmp_unsigned) {
2261 cc = pnc_map_unsigned[pnc & 0x07];
2263 cc = pnc_map_signed[pnc & 0x07];
2269 /** Sign extension bit values for binops */
2271 UNSIGNED_IMM = 0, /**< unsigned immediate */
2272 SIGNEXT_IMM = 2, /**< sign extended immediate */
2275 /** The mod encoding of the ModR/M */
2277 MOD_IND = 0x00, /**< [reg1] */
2278 MOD_IND_BYTE_OFS = 0x40, /**< [reg1 + byte ofs] */
2279 MOD_IND_WORD_OFS = 0x80, /**< [reg1 + word ofs] */
2280 MOD_REG = 0xC0 /**< reg1 */
2283 /** create R/M encoding for ModR/M */
2284 #define ENC_RM(x) (x)
2285 /** create REG encoding for ModR/M */
2286 #define ENC_REG(x) ((x) << 3)
2288 /** create encoding for a SIB byte */
2289 #define ENC_SIB(scale, index, base) ((scale) << 6 | (index) << 3 | (base))
2291 /* Node: The following routines are supposed to append bytes, words, dwords
2292 to the output stream.
2293 Currently the implementation is stupid in that it still creates output
2294 for an "assembler" in the form of .byte, .long
2295 We will change this when enough infrastructure is there to create complete
2296 machine code in memory/object files */
2298 static void bemit8(const unsigned char byte)
2300 be_emit_irprintf("\t.byte 0x%x\n", byte);
2301 be_emit_write_line();
2304 static void bemit16(const unsigned short u16)
2306 be_emit_irprintf("\t.word 0x%x\n", u16);
2307 be_emit_write_line();
2310 static void bemit32(const unsigned u32)
2312 be_emit_irprintf("\t.long 0x%x\n", u32);
2313 be_emit_write_line();
2317 * Emit address of an entity. If @p is_relative is true then a relative
2318 * offset from behind the address to the entity is created.
2320 static void bemit_entity(ir_entity *entity, bool entity_sign, int offset,
2323 if (entity == NULL) {
2328 /* the final version should remember the position in the bytestream
2329 and patch it with the correct address at linktime... */
2330 be_emit_cstring("\t.long ");
2333 be_gas_emit_entity(entity);
2335 if (get_entity_owner(entity) == get_tls_type()) {
2336 if (get_entity_visibility(entity) == ir_visibility_external) {
2337 be_emit_cstring("@INDNTPOFF");
2339 be_emit_cstring("@NTPOFF");
2344 be_emit_cstring("-.");
2349 be_emit_irprintf("%+d", offset);
2352 be_emit_write_line();
2355 static void bemit_jmp_destination(const ir_node *dest_block)
2357 be_emit_cstring("\t.long ");
2358 be_gas_emit_block_name(dest_block);
2359 be_emit_cstring(" - . - 4\n");
2360 be_emit_write_line();
2363 /* end emit routines, all emitters following here should only use the functions
2366 typedef enum reg_modifier {
2371 /** Create a ModR/M byte for src1,src2 registers */
2372 static void bemit_modrr(const arch_register_t *src1,
2373 const arch_register_t *src2)
2375 unsigned char modrm = MOD_REG;
2376 modrm |= ENC_RM(reg_gp_map[src1->index]);
2377 modrm |= ENC_REG(reg_gp_map[src2->index]);
2381 /** Create a ModR/M8 byte for src1,src2 registers */
2382 static void bemit_modrr8(reg_modifier_t high_part1, const arch_register_t *src1,
2383 reg_modifier_t high_part2, const arch_register_t *src2)
2385 unsigned char modrm = MOD_REG;
2386 modrm |= ENC_RM(reg_gp_map[src1->index] + (high_part1 == REG_HIGH ? 4 : 0));
2387 modrm |= ENC_REG(reg_gp_map[src2->index] + (high_part2 == REG_HIGH ? 4 : 0));
2391 /** Create a ModR/M byte for one register and extension */
2392 static void bemit_modru(const arch_register_t *reg, unsigned ext)
2394 unsigned char modrm = MOD_REG;
2396 modrm |= ENC_RM(reg_gp_map[reg->index]);
2397 modrm |= ENC_REG(ext);
2401 /** Create a ModR/M8 byte for one register */
2402 static void bemit_modrm8(reg_modifier_t high_part, const arch_register_t *reg)
2404 unsigned char modrm = MOD_REG;
2405 assert(reg_gp_map[reg->index] < 4);
2406 modrm |= ENC_RM(reg_gp_map[reg->index] + (high_part == REG_HIGH ? 4 : 0));
2412 * Calculate the size of an signed immediate in bytes.
2414 * @param offset an offset
2416 static unsigned get_signed_imm_size(int offset)
2418 if (-128 <= offset && offset < 128) {
2420 } else if (-32768 <= offset && offset < 32768) {
2428 * Emit an address mode.
2430 * @param reg content of the reg field: either a register index or an opcode extension
2431 * @param node the node
2433 static void bemit_mod_am(unsigned reg, const ir_node *node)
2435 ir_entity *ent = get_ia32_am_sc(node);
2436 int offs = get_ia32_am_offs_int(node);
2437 ir_node *base = get_irn_n(node, n_ia32_base);
2438 int has_base = !is_ia32_NoReg_GP(base);
2439 ir_node *index = get_irn_n(node, n_ia32_index);
2440 int has_index = !is_ia32_NoReg_GP(index);
2443 unsigned emitoffs = 0;
2444 bool emitsib = false;
2447 /* set the mod part depending on displacement */
2449 modrm |= MOD_IND_WORD_OFS;
2451 } else if (offs == 0) {
2454 } else if (-128 <= offs && offs < 128) {
2455 modrm |= MOD_IND_BYTE_OFS;
2458 modrm |= MOD_IND_WORD_OFS;
2463 const arch_register_t *base_reg = arch_get_irn_register(base);
2464 base_enc = reg_gp_map[base_reg->index];
2466 /* Use the EBP encoding + MOD_IND if NO base register. There is
2467 * always a 32bit offset present in this case. */
2473 /* Determine if we need a SIB byte. */
2475 const arch_register_t *reg_index = arch_get_irn_register(index);
2476 int scale = get_ia32_am_scale(node);
2478 /* R/M set to ESP means SIB in 32bit mode. */
2479 modrm |= ENC_RM(0x04);
2480 sib = ENC_SIB(scale, reg_gp_map[reg_index->index], base_enc);
2482 } else if (base_enc == 0x04) {
2483 /* for the above reason we are forced to emit a SIB when base is ESP.
2484 * Only the base is used, index must be ESP too, which means no index.
2486 modrm |= ENC_RM(0x04);
2487 sib = ENC_SIB(0, 0x04, 0x04);
2490 modrm |= ENC_RM(base_enc);
2493 /* We are forced to emit an 8bit offset as EBP base without offset is a
2494 * special case for SIB without base register. */
2495 if (base_enc == 0x05 && emitoffs == 0) {
2496 modrm |= MOD_IND_BYTE_OFS;
2500 modrm |= ENC_REG(reg);
2506 /* emit displacement */
2507 if (emitoffs == 8) {
2508 bemit8((unsigned) offs);
2509 } else if (emitoffs == 32) {
2510 bemit_entity(ent, is_ia32_am_sc_sign(node), offs, false);
2515 * Emit a binop with a immediate operand.
2517 * @param node the node to emit
2518 * @param opcode_eax the opcode for the op eax, imm variant
2519 * @param opcode the opcode for the reg, imm variant
2520 * @param ruval the opcode extension for opcode
2522 static void bemit_binop_with_imm(
2523 const ir_node *node,
2524 unsigned char opcode_ax,
2525 unsigned char opcode, unsigned char ruval)
2527 /* Use in-reg, because some instructions (cmp, test) have no out-reg. */
2528 const ir_node *op = get_irn_n(node, n_ia32_binary_right);
2529 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(op);
2532 /* Some instructions (test) have no short form with 32bit value + 8bit
2534 if (attr->symconst != NULL || opcode & SIGNEXT_IMM) {
2537 /* check for sign extension */
2538 size = get_signed_imm_size(attr->offset);
2543 bemit8(opcode | SIGNEXT_IMM);
2544 /* cmp has this special mode */
2545 if (get_ia32_op_type(node) == ia32_AddrModeS) {
2546 bemit_mod_am(ruval, node);
2548 const arch_register_t *reg = get_in_reg(node, n_ia32_binary_left);
2549 bemit_modru(reg, ruval);
2551 bemit8((unsigned char)attr->offset);
2555 /* check for eax variant: this variant is shorter for 32bit immediates only */
2556 if (get_ia32_op_type(node) == ia32_AddrModeS) {
2558 bemit_mod_am(ruval, node);
2560 const arch_register_t *reg = get_in_reg(node, n_ia32_binary_left);
2561 if (reg->index == REG_GP_EAX) {
2565 bemit_modru(reg, ruval);
2568 bemit_entity(attr->symconst, attr->sc_sign, attr->offset, false);
2571 panic("invalid imm size?!?");
2577 static void bemit_binop_2(const ir_node *node, unsigned code)
2579 const arch_register_t *out = get_in_reg(node, n_ia32_binary_left);
2581 if (get_ia32_op_type(node) == ia32_Normal) {
2582 const arch_register_t *op2 = get_in_reg(node, n_ia32_binary_right);
2583 bemit_modrr(op2, out);
2585 bemit_mod_am(reg_gp_map[out->index], node);
2592 static void bemit_binop(const ir_node *node, const unsigned char opcodes[4])
2594 ir_node *right = get_irn_n(node, n_ia32_binary_right);
2595 if (is_ia32_Immediate(right)) {
2596 bemit_binop_with_imm(node, opcodes[1], opcodes[2], opcodes[3]);
2598 bemit_binop_2(node, opcodes[0]);
2605 static void bemit_unop(const ir_node *node, unsigned char code, unsigned char ext, int input)
2608 if (get_ia32_op_type(node) == ia32_Normal) {
2609 const arch_register_t *in = get_in_reg(node, input);
2610 bemit_modru(in, ext);
2612 bemit_mod_am(ext, node);
2616 static void bemit_unop_reg(const ir_node *node, unsigned char code, int input)
2618 const arch_register_t *out = get_out_reg(node, 0);
2619 bemit_unop(node, code, reg_gp_map[out->index], input);
2622 static void bemit_unop_mem(const ir_node *node, unsigned char code, unsigned char ext)
2624 unsigned size = get_mode_size_bits(get_ia32_ls_mode(node));
2627 bemit8(size == 8 ? code : code + 1);
2628 bemit_mod_am(ext, node);
2631 static void bemit_immediate(const ir_node *node, bool relative)
2633 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(node);
2634 bemit_entity(attr->symconst, attr->sc_sign, attr->offset, relative);
2637 static void bemit_copy(const ir_node *copy)
2639 const arch_register_t *in = get_in_reg(copy, 0);
2640 const arch_register_t *out = get_out_reg(copy, 0);
2644 /* copies of vf nodes aren't real... */
2645 if (arch_register_get_class(in) == &ia32_reg_classes[CLASS_ia32_vfp])
2648 if (get_irn_mode(copy) == mode_E) {
2651 assert(arch_register_get_class(in) == &ia32_reg_classes[CLASS_ia32_gp]);
2653 bemit_modrr(in, out);
2657 static void bemit_perm(const ir_node *node)
2659 const arch_register_t *in0 = arch_get_irn_register(get_irn_n(node, 0));
2660 const arch_register_t *in1 = arch_get_irn_register(get_irn_n(node, 1));
2661 const arch_register_class_t *cls0 = arch_register_get_class(in0);
2663 assert(cls0 == arch_register_get_class(in1) && "Register class mismatch at Perm");
2665 if (cls0 == &ia32_reg_classes[CLASS_ia32_gp]) {
2666 if (in0->index == REG_GP_EAX) {
2667 bemit8(0x90 + reg_gp_map[in1->index]);
2668 } else if (in1->index == REG_GP_EAX) {
2669 bemit8(0x90 + reg_gp_map[in0->index]);
2672 bemit_modrr(in0, in1);
2674 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_xmm]) {
2675 panic("unimplemented"); // TODO implement
2676 //ia32_emitf(NULL, "\txorpd %R, %R\n", in1, in0);
2677 //ia32_emitf(NULL, "\txorpd %R, %R\n", in0, in1);
2678 //ia32_emitf(node, "\txorpd %R, %R\n", in1, in0);
2679 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_vfp]) {
2681 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_st]) {
2684 panic("unexpected register class in be_Perm (%+F)", node);
2688 static void bemit_xor0(const ir_node *node)
2690 const arch_register_t *out = get_out_reg(node, 0);
2692 bemit_modrr(out, out);
2695 static void bemit_mov_const(const ir_node *node)
2697 const arch_register_t *out = get_out_reg(node, 0);
2698 bemit8(0xB8 + reg_gp_map[out->index]);
2699 bemit_immediate(node, false);
2703 * Creates a function for a Binop with 3 possible encodings.
2705 #define BINOP(op, op0, op1, op2, op2_ext) \
2706 static void bemit_ ## op(const ir_node *node) { \
2707 static const unsigned char op ## _codes[] = {op0, op1, op2, op2_ext}; \
2708 bemit_binop(node, op ## _codes); \
2711 /* insn def eax,imm imm */
2712 BINOP(add, 0x03, 0x05, 0x81, 0)
2713 BINOP(or, 0x0B, 0x0D, 0x81, 1)
2714 BINOP(adc, 0x13, 0x15, 0x81, 2)
2715 BINOP(sbb, 0x1B, 0x1D, 0x81, 3)
2716 BINOP(and, 0x23, 0x25, 0x81, 4)
2717 BINOP(sub, 0x2B, 0x2D, 0x81, 5)
2718 BINOP(xor, 0x33, 0x35, 0x81, 6)
2719 BINOP(test, 0x85, 0xA9, 0xF7, 0)
2721 #define BINOPMEM(op, ext) \
2722 static void bemit_##op(const ir_node *node) \
2725 unsigned size = get_mode_size_bits(get_ia32_ls_mode(node)); \
2728 val = get_irn_n(node, n_ia32_unary_op); \
2729 if (is_ia32_Immediate(val)) { \
2730 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(val); \
2731 int offset = attr->offset; \
2732 if (attr->symconst == NULL && get_signed_imm_size(offset) == 1) { \
2734 bemit_mod_am(ext, node); \
2738 bemit_mod_am(ext, node); \
2742 bemit_entity(attr->symconst, attr->sc_sign, offset, false); \
2746 bemit8(ext << 3 | 1); \
2747 bemit_mod_am(reg_gp_map[get_out_reg(val, 0)->index], node); \
2751 static void bemit_##op##8bit(const ir_node *node) \
2753 ir_node *val = get_irn_n(node, n_ia32_unary_op); \
2754 if (is_ia32_Immediate(val)) { \
2756 bemit_mod_am(ext, node); \
2757 bemit8(get_ia32_immediate_attr_const(val)->offset); \
2760 bemit_mod_am(reg_gp_map[get_out_reg(val, 0)->index], node); \
2772 * Creates a function for an Unop with code /ext encoding.
2774 #define UNOP(op, code, ext, input) \
2775 static void bemit_ ## op(const ir_node *node) { \
2776 bemit_unop(node, code, ext, input); \
2779 UNOP(not, 0xF7, 2, n_ia32_Not_val)
2780 UNOP(neg, 0xF7, 3, n_ia32_Neg_val)
2781 UNOP(mul, 0xF7, 4, n_ia32_Mul_right)
2782 UNOP(imul1op, 0xF7, 5, n_ia32_IMul1OP_right)
2783 UNOP(div, 0xF7, 6, n_ia32_Div_divisor)
2784 UNOP(idiv, 0xF7, 7, n_ia32_IDiv_divisor)
2786 /* TODO: am support for IJmp */
2787 UNOP(ijmp, 0xFF, 4, n_ia32_IJmp_target)
2789 #define SHIFT(op, ext) \
2790 static void bemit_##op(const ir_node *node) \
2792 const arch_register_t *out = get_out_reg(node, 0); \
2793 ir_node *count = get_irn_n(node, 1); \
2794 if (is_ia32_Immediate(count)) { \
2795 int offset = get_ia32_immediate_attr_const(count)->offset; \
2796 if (offset == 1) { \
2798 bemit_modru(out, ext); \
2801 bemit_modru(out, ext); \
2806 bemit_modru(out, ext); \
2810 static void bemit_##op##mem(const ir_node *node) \
2813 unsigned size = get_mode_size_bits(get_ia32_ls_mode(node)); \
2816 count = get_irn_n(node, 1); \
2817 if (is_ia32_Immediate(count)) { \
2818 int offset = get_ia32_immediate_attr_const(count)->offset; \
2819 if (offset == 1) { \
2820 bemit8(size == 8 ? 0xD0 : 0xD1); \
2821 bemit_mod_am(ext, node); \
2823 bemit8(size == 8 ? 0xC0 : 0xC1); \
2824 bemit_mod_am(ext, node); \
2828 bemit8(size == 8 ? 0xD2 : 0xD3); \
2829 bemit_mod_am(ext, node); \
2839 static void bemit_shld(const ir_node *node)
2841 const arch_register_t *in = get_in_reg(node, n_ia32_ShlD_val_low);
2842 const arch_register_t *out = get_out_reg(node, pn_ia32_ShlD_res);
2843 ir_node *count = get_irn_n(node, n_ia32_ShlD_count);
2845 if (is_ia32_Immediate(count)) {
2847 bemit_modrr(out, in);
2848 bemit8(get_ia32_immediate_attr_const(count)->offset);
2851 bemit_modrr(out, in);
2855 static void bemit_shrd(const ir_node *node)
2857 const arch_register_t *in = get_in_reg(node, n_ia32_ShrD_val_low);
2858 const arch_register_t *out = get_out_reg(node, pn_ia32_ShrD_res);
2859 ir_node *count = get_irn_n(node, n_ia32_ShrD_count);
2861 if (is_ia32_Immediate(count)) {
2863 bemit_modrr(out, in);
2864 bemit8(get_ia32_immediate_attr_const(count)->offset);
2867 bemit_modrr(out, in);
2872 * binary emitter for setcc.
2874 static void bemit_setcc(const ir_node *node)
2876 const arch_register_t *dreg = get_out_reg(node, pn_ia32_Setcc_res);
2878 int pnc = get_ia32_condcode(node);
2879 pnc = determine_final_pnc(node, n_ia32_Setcc_eflags, pnc);
2880 if (pnc & ia32_pn_Cmp_float) {
2881 switch (pnc & 0x0f) {
2886 bemit_modrm8(REG_LOW, dreg);
2893 bemit_modrm8(REG_LOW, dreg);
2901 bemit8(0x90 | pnc2cc(pnc));
2902 bemit_modrm8(REG_LOW, dreg);
2907 bemit_modrm8(REG_HIGH, dreg);
2909 /* andb %>dreg, %<dreg */
2911 bemit_modrr8(REG_LOW, dreg, REG_HIGH, dreg);
2919 bemit8(0x90 | pnc2cc(pnc));
2920 bemit_modrm8(REG_LOW, dreg);
2925 bemit_modrm8(REG_HIGH, dreg);
2927 /* orb %>dreg, %<dreg */
2929 bemit_modrr8(REG_LOW, dreg, REG_HIGH, dreg);
2938 bemit8(0x90 | pnc2cc(pnc));
2939 bemit_modrm8(REG_LOW, dreg);
2942 static void bemit_cmovcc(const ir_node *node)
2944 const ia32_attr_t *attr = get_ia32_attr_const(node);
2945 int ins_permuted = attr->data.ins_permuted;
2946 const arch_register_t *out = arch_irn_get_register(node, pn_ia32_res);
2947 int pnc = get_ia32_condcode(node);
2948 const arch_register_t *in_true;
2949 const arch_register_t *in_false;
2951 pnc = determine_final_pnc(node, n_ia32_CMovcc_eflags, pnc);
2953 in_true = arch_get_irn_register(get_irn_n(node, n_ia32_CMovcc_val_true));
2954 in_false = arch_get_irn_register(get_irn_n(node, n_ia32_CMovcc_val_false));
2956 /* should be same constraint fullfilled? */
2957 if (out == in_false) {
2958 /* yes -> nothing to do */
2959 } else if (out == in_true) {
2960 assert(get_ia32_op_type(node) == ia32_Normal);
2961 ins_permuted = !ins_permuted;
2965 bemit8(0x8B); // mov %in_false, %out
2966 bemit_modrr(in_false, out);
2970 pnc = ia32_get_negated_pnc(pnc);
2972 /* TODO: handling of Nans isn't correct yet */
2975 bemit8(0x40 | pnc2cc(pnc));
2976 if (get_ia32_op_type(node) == ia32_Normal) {
2977 bemit_modrr(in_true, out);
2979 bemit_mod_am(reg_gp_map[out->index], node);
2983 static void bemit_cmp(const ir_node *node)
2985 unsigned ls_size = get_mode_size_bits(get_ia32_ls_mode(node));
2991 right = get_irn_n(node, n_ia32_binary_right);
2992 if (is_ia32_Immediate(right)) {
2993 /* Use in-reg, because some instructions (cmp, test) have no out-reg. */
2994 const ir_node *op = get_irn_n(node, n_ia32_binary_right);
2995 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(op);
2998 if (attr->symconst != NULL) {
3001 /* check for sign extension */
3002 size = get_signed_imm_size(attr->offset);
3007 bemit8(0x81 | SIGNEXT_IMM);
3008 /* cmp has this special mode */
3009 if (get_ia32_op_type(node) == ia32_AddrModeS) {
3010 bemit_mod_am(7, node);
3012 const arch_register_t *reg = get_in_reg(node, n_ia32_binary_left);
3013 bemit_modru(reg, 7);
3015 bemit8((unsigned char)attr->offset);
3019 /* check for eax variant: this variant is shorter for 32bit immediates only */
3020 if (get_ia32_op_type(node) == ia32_AddrModeS) {
3022 bemit_mod_am(7, node);
3024 const arch_register_t *reg = get_in_reg(node, n_ia32_binary_left);
3025 if (reg->index == REG_GP_EAX) {
3029 bemit_modru(reg, 7);
3032 if (ls_size == 16) {
3033 bemit16(attr->offset);
3035 bemit_entity(attr->symconst, attr->sc_sign, attr->offset, false);
3039 panic("invalid imm size?!?");
3041 const arch_register_t *out = get_in_reg(node, n_ia32_binary_left);
3043 if (get_ia32_op_type(node) == ia32_Normal) {
3044 const arch_register_t *op2 = get_in_reg(node, n_ia32_binary_right);
3045 bemit_modrr(op2, out);
3047 bemit_mod_am(reg_gp_map[out->index], node);
3052 static void bemit_cmp8bit(const ir_node *node)
3054 ir_node *right = get_irn_n(node, n_ia32_binary_right);
3055 if (is_ia32_Immediate(right)) {
3056 if (get_ia32_op_type(node) == ia32_Normal) {
3057 const arch_register_t *out = get_in_reg(node, n_ia32_Cmp_left);
3058 if (out->index == REG_GP_EAX) {
3062 bemit_modru(out, 7);
3066 bemit_mod_am(7, node);
3068 bemit8(get_ia32_immediate_attr_const(right)->offset);
3070 const arch_register_t *out = get_in_reg(node, n_ia32_Cmp_left);
3072 if (get_ia32_op_type(node) == ia32_Normal) {
3073 const arch_register_t *in = get_in_reg(node, n_ia32_Cmp_right);
3074 bemit_modrr(out, in);
3076 bemit_mod_am(reg_gp_map[out->index], node);
3081 static void bemit_test8bit(const ir_node *node)
3083 ir_node *right = get_irn_n(node, n_ia32_Test8Bit_right);
3084 if (is_ia32_Immediate(right)) {
3085 if (get_ia32_op_type(node) == ia32_Normal) {
3086 const arch_register_t *out = get_in_reg(node, n_ia32_Test8Bit_left);
3087 if (out->index == REG_GP_EAX) {
3091 bemit_modru(out, 0);
3095 bemit_mod_am(0, node);
3097 bemit8(get_ia32_immediate_attr_const(right)->offset);
3099 const arch_register_t *out = get_in_reg(node, n_ia32_Test8Bit_left);
3101 if (get_ia32_op_type(node) == ia32_Normal) {
3102 const arch_register_t *in = get_in_reg(node, n_ia32_Test8Bit_right);
3103 bemit_modrr(out, in);
3105 bemit_mod_am(reg_gp_map[out->index], node);
3110 static void bemit_imul(const ir_node *node)
3112 ir_node *right = get_irn_n(node, n_ia32_IMul_right);
3113 /* Do we need the immediate form? */
3114 if (is_ia32_Immediate(right)) {
3115 int imm = get_ia32_immediate_attr_const(right)->offset;
3116 if (get_signed_imm_size(imm) == 1) {
3117 bemit_unop_reg(node, 0x6B, n_ia32_IMul_left);
3120 bemit_unop_reg(node, 0x69, n_ia32_IMul_left);
3125 bemit_unop_reg(node, 0xAF, n_ia32_IMul_right);
3129 static void bemit_dec(const ir_node *node)
3131 const arch_register_t *out = get_out_reg(node, pn_ia32_Dec_res);
3132 bemit8(0x48 + reg_gp_map[out->index]);
3135 static void bemit_inc(const ir_node *node)
3137 const arch_register_t *out = get_out_reg(node, pn_ia32_Inc_res);
3138 bemit8(0x40 + reg_gp_map[out->index]);
3141 #define UNOPMEM(op, code, ext) \
3142 static void bemit_##op(const ir_node *node) \
3144 bemit_unop_mem(node, code, ext); \
3147 UNOPMEM(notmem, 0xF6, 2)
3148 UNOPMEM(negmem, 0xF6, 3)
3149 UNOPMEM(incmem, 0xFE, 0)
3150 UNOPMEM(decmem, 0xFE, 1)
3152 static void bemit_ldtls(const ir_node *node)
3154 const arch_register_t *out = get_out_reg(node, 0);
3156 bemit8(0x65); // gs:
3157 if (out->index == REG_GP_EAX) {
3158 bemit8(0xA1); // movl 0, %eax
3160 bemit8(0x8B); // movl 0, %reg
3161 bemit8(MOD_IND | ENC_REG(reg_gp_map[out->index]) | ENC_RM(0x05));
3169 static void bemit_lea(const ir_node *node)
3171 const arch_register_t *out = get_out_reg(node, 0);
3173 bemit_mod_am(reg_gp_map[out->index], node);
3176 /* helper function for bemit_minus64bit */
3177 static void bemit_helper_mov(const arch_register_t *src, const arch_register_t *dst)
3179 bemit8(0x8B); // movl %src, %dst
3180 bemit_modrr(src, dst);
3183 /* helper function for bemit_minus64bit */
3184 static void bemit_helper_neg(const arch_register_t *reg)
3186 bemit8(0xF7); // negl %reg
3187 bemit_modru(reg, 3);
3190 /* helper function for bemit_minus64bit */
3191 static void bemit_helper_sbb0(const arch_register_t *reg)
3193 bemit8(0x83); // sbbl $0, %reg
3194 bemit_modru(reg, 3);
3198 /* helper function for bemit_minus64bit */
3199 static void bemit_helper_sbb(const arch_register_t *src, const arch_register_t *dst)
3201 bemit8(0x1B); // sbbl %src, %dst
3202 bemit_modrr(src, dst);
3205 /* helper function for bemit_minus64bit */
3206 static void bemit_helper_xchg(const arch_register_t *src, const arch_register_t *dst)
3208 if (src->index == REG_GP_EAX) {
3209 bemit8(0x90 + reg_gp_map[dst->index]); // xchgl %eax, %dst
3210 } else if (dst->index == REG_GP_EAX) {
3211 bemit8(0x90 + reg_gp_map[src->index]); // xchgl %src, %eax
3213 bemit8(0x87); // xchgl %src, %dst
3214 bemit_modrr(src, dst);
3218 /* helper function for bemit_minus64bit */
3219 static void bemit_helper_zero(const arch_register_t *reg)
3221 bemit8(0x33); // xorl %reg, %reg
3222 bemit_modrr(reg, reg);
3225 static void bemit_minus64bit(const ir_node *node)
3227 const arch_register_t *in_lo = get_in_reg(node, 0);
3228 const arch_register_t *in_hi = get_in_reg(node, 1);
3229 const arch_register_t *out_lo = get_out_reg(node, 0);
3230 const arch_register_t *out_hi = get_out_reg(node, 1);
3232 if (out_lo == in_lo) {
3233 if (out_hi != in_hi) {
3234 /* a -> a, b -> d */
3237 /* a -> a, b -> b */
3240 } else if (out_lo == in_hi) {
3241 if (out_hi == in_lo) {
3242 /* a -> b, b -> a */
3243 bemit_helper_xchg(in_lo, in_hi);
3246 /* a -> b, b -> d */
3247 bemit_helper_mov(in_hi, out_hi);
3248 bemit_helper_mov(in_lo, out_lo);
3252 if (out_hi == in_lo) {
3253 /* a -> c, b -> a */
3254 bemit_helper_mov(in_lo, out_lo);
3256 } else if (out_hi == in_hi) {
3257 /* a -> c, b -> b */
3258 bemit_helper_mov(in_lo, out_lo);
3261 /* a -> c, b -> d */
3262 bemit_helper_mov(in_lo, out_lo);
3268 bemit_helper_neg( out_hi);
3269 bemit_helper_neg( out_lo);
3270 bemit_helper_sbb0(out_hi);
3274 bemit_helper_zero(out_hi);
3275 bemit_helper_neg( out_lo);
3276 bemit_helper_sbb( in_hi, out_hi);
3280 * Emit a single opcode.
3282 #define EMIT_SINGLEOP(op, code) \
3283 static void bemit_ ## op(const ir_node *node) { \
3288 //EMIT_SINGLEOP(daa, 0x27)
3289 //EMIT_SINGLEOP(das, 0x2F)
3290 //EMIT_SINGLEOP(aaa, 0x37)
3291 //EMIT_SINGLEOP(aas, 0x3F)
3292 //EMIT_SINGLEOP(nop, 0x90)
3293 EMIT_SINGLEOP(cwtl, 0x98)
3294 EMIT_SINGLEOP(cltd, 0x99)
3295 //EMIT_SINGLEOP(fwait, 0x9B)
3296 EMIT_SINGLEOP(sahf, 0x9E)
3297 //EMIT_SINGLEOP(popf, 0x9D)
3298 EMIT_SINGLEOP(leave, 0xC9)
3299 EMIT_SINGLEOP(int3, 0xCC)
3300 //EMIT_SINGLEOP(iret, 0xCF)
3301 //EMIT_SINGLEOP(xlat, 0xD7)
3302 //EMIT_SINGLEOP(lock, 0xF0)
3303 EMIT_SINGLEOP(rep, 0xF3)
3304 //EMIT_SINGLEOP(halt, 0xF4)
3305 EMIT_SINGLEOP(cmc, 0xF5)
3306 EMIT_SINGLEOP(stc, 0xF9)
3307 //EMIT_SINGLEOP(cli, 0xFA)
3308 //EMIT_SINGLEOP(sti, 0xFB)
3309 //EMIT_SINGLEOP(std, 0xFD)
3312 * Emits a MOV out, [MEM].
3314 static void bemit_load(const ir_node *node)
3316 const arch_register_t *out = get_out_reg(node, 0);
3318 if (out->index == REG_GP_EAX) {
3319 ir_node *base = get_irn_n(node, n_ia32_base);
3320 int has_base = !is_ia32_NoReg_GP(base);
3321 ir_node *index = get_irn_n(node, n_ia32_index);
3322 int has_index = !is_ia32_NoReg_GP(index);
3323 if (!has_base && !has_index) {
3324 ir_entity *ent = get_ia32_am_sc(node);
3325 int offs = get_ia32_am_offs_int(node);
3326 /* load from constant address to EAX can be encoded
3329 bemit_entity(ent, 0, offs, false);
3334 bemit_mod_am(reg_gp_map[out->index], node);
3338 * Emits a MOV [mem], in.
3340 static void bemit_store(const ir_node *node)
3342 const ir_node *value = get_irn_n(node, n_ia32_Store_val);
3343 unsigned size = get_mode_size_bits(get_ia32_ls_mode(node));
3345 if (is_ia32_Immediate(value)) {
3348 bemit_mod_am(0, node);
3349 bemit8(get_ia32_immediate_attr_const(value)->offset);
3350 } else if (size == 16) {
3353 bemit_mod_am(0, node);
3354 bemit16(get_ia32_immediate_attr_const(value)->offset);
3357 bemit_mod_am(0, node);
3358 bemit_immediate(value, false);
3361 const arch_register_t *in = get_in_reg(node, n_ia32_Store_val);
3363 if (in->index == REG_GP_EAX) {
3364 ir_node *base = get_irn_n(node, n_ia32_base);
3365 int has_base = !is_ia32_NoReg_GP(base);
3366 ir_node *index = get_irn_n(node, n_ia32_index);
3367 int has_index = !is_ia32_NoReg_GP(index);
3368 if (!has_base && !has_index) {
3369 ir_entity *ent = get_ia32_am_sc(node);
3370 int offs = get_ia32_am_offs_int(node);
3371 /* store to constant address from EAX can be encoded as
3372 * 0xA2/0xA3 [offset]*/
3380 bemit_entity(ent, 0, offs, false);
3392 bemit_mod_am(reg_gp_map[in->index], node);
3396 static void bemit_conv_i2i(const ir_node *node)
3398 ir_mode *smaller_mode = get_ia32_ls_mode(node);
3407 if (mode_is_signed(smaller_mode)) opcode |= 0x08;
3408 if (get_mode_size_bits(smaller_mode) == 16) opcode |= 0x01;
3409 bemit_unop_reg(node, opcode, n_ia32_Conv_I2I_val);
3415 static void bemit_push(const ir_node *node)
3417 const ir_node *value = get_irn_n(node, n_ia32_Push_val);
3419 if (is_ia32_Immediate(value)) {
3420 const ia32_immediate_attr_t *attr
3421 = get_ia32_immediate_attr_const(value);
3422 unsigned size = get_signed_imm_size(attr->offset);
3428 bemit8((unsigned char)attr->offset);
3433 bemit_immediate(value, false);
3436 } else if (is_ia32_NoReg_GP(value)) {
3438 bemit_mod_am(6, node);
3440 const arch_register_t *reg = get_in_reg(node, n_ia32_Push_val);
3441 bemit8(0x50 + reg_gp_map[reg->index]);
3448 static void bemit_pop(const ir_node *node)
3450 const arch_register_t *reg = get_out_reg(node, pn_ia32_Pop_res);
3451 bemit8(0x58 + reg_gp_map[reg->index]);
3454 static void bemit_popmem(const ir_node *node)
3457 bemit_mod_am(0, node);
3460 static void bemit_call(const ir_node *node)
3462 ir_node *proc = get_irn_n(node, n_ia32_Call_addr);
3464 if (is_ia32_Immediate(proc)) {
3466 bemit_immediate(proc, true);
3468 bemit_unop(node, 0xFF, 2, n_ia32_Call_addr);
3472 static void bemit_jmp(const ir_node *dest_block)
3475 bemit_jmp_destination(dest_block);
3478 static void bemit_jump(const ir_node *node)
3480 if (can_be_fallthrough(node))
3483 bemit_jmp(get_cfop_target_block(node));
3486 static void bemit_jcc(int pnc, const ir_node *dest_block)
3488 unsigned char cc = pnc2cc(pnc);
3491 bemit_jmp_destination(dest_block);
3494 static void bemit_jp(bool odd, const ir_node *dest_block)
3498 bemit_jmp_destination(dest_block);
3501 static void bemit_ia32_jcc(const ir_node *node)
3503 int pnc = get_ia32_condcode(node);
3504 const ir_node *proj_true;
3505 const ir_node *proj_false;
3506 const ir_node *dest_true;
3507 const ir_node *dest_false;
3508 const ir_node *block;
3510 pnc = determine_final_pnc(node, 0, pnc);
3512 /* get both Projs */
3513 proj_true = get_proj(node, pn_ia32_Jcc_true);
3514 assert(proj_true && "Jcc without true Proj");
3516 proj_false = get_proj(node, pn_ia32_Jcc_false);
3517 assert(proj_false && "Jcc without false Proj");
3519 block = get_nodes_block(node);
3521 if (can_be_fallthrough(proj_true)) {
3522 /* exchange both proj's so the second one can be omitted */
3523 const ir_node *t = proj_true;
3525 proj_true = proj_false;
3527 pnc = ia32_get_negated_pnc(pnc);
3530 dest_true = get_cfop_target_block(proj_true);
3531 dest_false = get_cfop_target_block(proj_false);
3533 if (pnc & ia32_pn_Cmp_float) {
3534 /* Some floating point comparisons require a test of the parity flag,
3535 * which indicates that the result is unordered */
3538 bemit_jp(false, dest_true);
3543 bemit_jp(true, dest_true);
3549 /* we need a local label if the false proj is a fallthrough
3550 * as the falseblock might have no label emitted then */
3551 if (can_be_fallthrough(proj_false)) {
3553 bemit8(0x06); // jp + 6
3555 bemit_jp(false, dest_false);
3562 bemit_jp(false, dest_true);
3570 bemit_jcc(pnc, dest_true);
3573 /* the second Proj might be a fallthrough */
3574 if (can_be_fallthrough(proj_false)) {
3575 /* it's a fallthrough */
3577 bemit_jmp(dest_false);
3581 static void bemit_switchjmp(const ir_node *node)
3583 unsigned long interval;
3587 const arch_register_t *in;
3589 /* fill the table structure */
3590 generate_jump_table(&tbl, node);
3592 /* two-complement's magic make this work without overflow */
3593 interval = tbl.max_value - tbl.min_value;
3595 in = get_in_reg(node, 0);
3596 /* emit the table */
3597 if (get_signed_imm_size(interval) == 1) {
3598 bemit8(0x83); // cmpl $imm8, %in
3602 bemit8(0x81); // cmpl $imm32, %in
3606 bemit8(0x0F); // ja tbl.defProj
3608 ia32_emitf(tbl.defProj, ".long %L - . - 4\n");
3610 if (tbl.num_branches > 1) {
3612 bemit8(0xFF); // jmp *tbl.label(,%in,4)
3613 bemit8(MOD_IND | ENC_REG(4) | ENC_RM(0x04));
3614 bemit8(ENC_SIB(2, reg_gp_map[in->index], 0x05));
3615 be_emit_irprintf("\t.long %s\n", tbl.label);
3617 be_gas_emit_switch_section(GAS_SECTION_RODATA);
3618 be_emit_cstring(".align 4\n");
3619 be_emit_irprintf("%s:\n", tbl.label);
3621 last_value = tbl.branches[0].value;
3622 for (i = 0; i != tbl.num_branches; ++i) {
3623 while (last_value != tbl.branches[i].value) {
3624 ia32_emitf(tbl.defProj, ".long %L\n");
3627 ia32_emitf(tbl.branches[i].target, ".long %L\n");
3630 be_gas_emit_switch_section(GAS_SECTION_TEXT);
3632 /* one jump is enough */
3633 panic("switch only has one case");
3634 //ia32_emitf(tbl.branches[0].target, "\tjmp %L\n");
3637 be_emit_write_line();
3645 static void bemit_return(const ir_node *node)
3647 unsigned pop = be_Return_get_pop(node);
3648 if (pop > 0 || be_Return_get_emit_pop(node)) {
3650 assert(pop <= 0xffff);
3657 static void bemit_subsp(const ir_node *node)
3659 const arch_register_t *out;
3662 /* mov %esp, %out */
3664 out = get_out_reg(node, 1);
3665 bemit8(MOD_REG | ENC_REG(reg_gp_map[out->index]) | ENC_RM(0x04));
3668 static void bemit_incsp(const ir_node *node)
3671 const arch_register_t *reg;
3675 offs = be_get_IncSP_offset(node);
3686 size = get_signed_imm_size(offs);
3687 bemit8(size == 1 ? 0x83 : 0x81);
3689 reg = get_out_reg(node, 0);
3690 bemit_modru(reg, ext);
3699 static void bemit_copybi(const ir_node *node)
3701 unsigned size = get_ia32_copyb_size(node);
3703 bemit8(0xA4); // movsb
3706 bemit8(0xA5); // movsw
3710 bemit8(0xA5); // movsl
3714 static void bemit_fbinop(const ir_node *node, unsigned code, unsigned code_to)
3716 if (get_ia32_op_type(node) == ia32_Normal) {
3717 const ia32_x87_attr_t *x87_attr = get_ia32_x87_attr_const(node);
3718 const arch_register_t *in1 = x87_attr->x87[0];
3719 const arch_register_t *in = x87_attr->x87[1];
3720 const arch_register_t *out = x87_attr->x87[2];
3724 } else if (out == in) {
3728 if (out->index == 0) {
3730 bemit8(MOD_REG | ENC_REG(code) | ENC_RM(in->index));
3733 bemit8(MOD_REG | ENC_REG(code_to) | ENC_RM(out->index));
3736 if (get_mode_size_bits(get_ia32_ls_mode(node)) == 32) {
3741 bemit_mod_am(code, node);
3745 static void bemit_fbinopp(const ir_node *node, unsigned const code)
3747 const ia32_x87_attr_t *x87_attr = get_ia32_x87_attr_const(node);
3748 const arch_register_t *out = x87_attr->x87[2];
3750 bemit8(code + out->index);
3753 static void bemit_fabs(const ir_node *node)
3761 static void bemit_fadd(const ir_node *node)
3763 bemit_fbinop(node, 0, 0);
3766 static void bemit_faddp(const ir_node *node)
3768 bemit_fbinopp(node, 0xC0);
3771 static void bemit_fchs(const ir_node *node)
3779 static void bemit_fdiv(const ir_node *node)
3781 bemit_fbinop(node, 6, 7);
3784 static void bemit_fdivp(const ir_node *node)
3786 bemit_fbinopp(node, 0xF8);
3789 static void bemit_fdivr(const ir_node *node)
3791 bemit_fbinop(node, 7, 6);
3794 static void bemit_fdivrp(const ir_node *node)
3796 bemit_fbinopp(node, 0xF0);
3799 static void bemit_fild(const ir_node *node)
3801 switch (get_mode_size_bits(get_ia32_ls_mode(node))) {
3803 bemit8(0xDF); // filds
3804 bemit_mod_am(0, node);
3808 bemit8(0xDB); // fildl
3809 bemit_mod_am(0, node);
3813 bemit8(0xDF); // fildll
3814 bemit_mod_am(5, node);
3818 panic("invalid mode size");
3822 static void bemit_fist(const ir_node *node)
3824 switch (get_mode_size_bits(get_ia32_ls_mode(node))) {
3826 bemit8(0xDF); // fists
3830 bemit8(0xDB); // fistl
3834 panic("invalid mode size");
3836 bemit_mod_am(2, node);
3839 static void bemit_fistp(const ir_node *node)
3841 switch (get_mode_size_bits(get_ia32_ls_mode(node))) {
3843 bemit8(0xDF); // fistps
3844 bemit_mod_am(3, node);
3848 bemit8(0xDB); // fistpl
3849 bemit_mod_am(3, node);
3853 bemit8(0xDF); // fistpll
3854 bemit_mod_am(7, node);
3858 panic("invalid mode size");
3862 static void bemit_fld(const ir_node *node)
3864 switch (get_mode_size_bits(get_ia32_ls_mode(node))) {
3866 bemit8(0xD9); // flds
3867 bemit_mod_am(0, node);
3871 bemit8(0xDD); // fldl
3872 bemit_mod_am(0, node);
3877 bemit8(0xDB); // fldt
3878 bemit_mod_am(5, node);
3882 panic("invalid mode size");
3886 static void bemit_fld1(const ir_node *node)
3890 bemit8(0xE8); // fld1
3893 static void bemit_fldcw(const ir_node *node)
3895 bemit8(0xD9); // fldcw
3896 bemit_mod_am(5, node);
3899 static void bemit_fldz(const ir_node *node)
3903 bemit8(0xEE); // fldz
3906 static void bemit_fmul(const ir_node *node)
3908 bemit_fbinop(node, 1, 1);
3911 static void bemit_fmulp(const ir_node *node)
3913 bemit_fbinopp(node, 0xC8);
3916 static void bemit_fpop(const ir_node *node)
3918 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
3920 bemit8(0xD8 + attr->x87[0]->index);
3923 static void bemit_fpush(const ir_node *node)
3925 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
3927 bemit8(0xC0 + attr->x87[0]->index);
3930 static void bemit_fpushcopy(const ir_node *node)
3932 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
3934 bemit8(0xC0 + attr->x87[0]->index);
3937 static void bemit_fst(const ir_node *node)
3939 switch (get_mode_size_bits(get_ia32_ls_mode(node))) {
3941 bemit8(0xD9); // fsts
3945 bemit8(0xDD); // fstl
3949 panic("invalid mode size");
3951 bemit_mod_am(2, node);
3954 static void bemit_fstp(const ir_node *node)
3956 switch (get_mode_size_bits(get_ia32_ls_mode(node))) {
3958 bemit8(0xD9); // fstps
3959 bemit_mod_am(3, node);
3963 bemit8(0xDD); // fstpl
3964 bemit_mod_am(3, node);
3969 bemit8(0xDB); // fstpt
3970 bemit_mod_am(7, node);
3974 panic("invalid mode size");
3978 static void bemit_fsub(const ir_node *node)
3980 bemit_fbinop(node, 4, 5);
3983 static void bemit_fsubp(const ir_node *node)
3985 bemit_fbinopp(node, 0xE8);
3988 static void bemit_fsubr(const ir_node *node)
3990 bemit_fbinop(node, 5, 4);
3993 static void bemit_fsubrp(const ir_node *node)
3995 bemit_fbinopp(node, 0xE0);
3998 static void bemit_fnstcw(const ir_node *node)
4000 bemit8(0xD9); // fnstcw
4001 bemit_mod_am(7, node);
4004 static void bemit_fnstsw(void)
4006 bemit8(0xDF); // fnstsw %ax
4010 static void bemit_ftstfnstsw(const ir_node *node)
4014 bemit8(0xD9); // ftst
4019 static void bemit_fucomi(const ir_node *node)
4021 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
4022 bemit8(0xDB); // fucomi
4023 bemit8(0xE8 + attr->x87[1]->index);
4026 static void bemit_fucomip(const ir_node *node)
4028 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
4029 bemit8(0xDF); // fucomip
4030 bemit8(0xE8 + attr->x87[1]->index);
4033 static void bemit_fucomfnstsw(const ir_node *node)
4035 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
4036 bemit8(0xDD); // fucom
4037 bemit8(0xE0 + attr->x87[1]->index);
4041 static void bemit_fucompfnstsw(const ir_node *node)
4043 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
4044 bemit8(0xDD); // fucomp
4045 bemit8(0xE8 + attr->x87[1]->index);
4049 static void bemit_fucomppfnstsw(const ir_node *node)
4053 bemit8(0xDA); // fucompp
4058 static void bemit_fxch(const ir_node *node)
4060 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
4062 bemit8(0xC8 + attr->x87[0]->index);
4066 * The type of a emitter function.
4068 typedef void (*emit_func) (const ir_node *);
4071 * Set a node emitter. Make it a bit more type safe.
4073 static void register_emitter(ir_op *op, emit_func func)
4075 op->ops.generic = (op_func) func;
4078 static void ia32_register_binary_emitters(void)
4080 /* first clear the generic function pointer for all ops */
4081 clear_irp_opcodes_generic_func();
4083 /* benode emitter */
4084 register_emitter(op_be_Copy, bemit_copy);
4085 register_emitter(op_be_CopyKeep, bemit_copy);
4086 register_emitter(op_be_IncSP, bemit_incsp);
4087 register_emitter(op_be_Perm, bemit_perm);
4088 register_emitter(op_be_Return, bemit_return);
4089 register_emitter(op_ia32_Adc, bemit_adc);
4090 register_emitter(op_ia32_Add, bemit_add);
4091 register_emitter(op_ia32_AddMem, bemit_addmem);
4092 register_emitter(op_ia32_AddMem8Bit, bemit_addmem8bit);
4093 register_emitter(op_ia32_And, bemit_and);
4094 register_emitter(op_ia32_AndMem, bemit_andmem);
4095 register_emitter(op_ia32_AndMem8Bit, bemit_andmem8bit);
4096 register_emitter(op_ia32_Breakpoint, bemit_int3);
4097 register_emitter(op_ia32_CMovcc, bemit_cmovcc);
4098 register_emitter(op_ia32_Call, bemit_call);
4099 register_emitter(op_ia32_Cltd, bemit_cltd);
4100 register_emitter(op_ia32_Cmc, bemit_cmc);
4101 register_emitter(op_ia32_Cmp, bemit_cmp);
4102 register_emitter(op_ia32_Cmp8Bit, bemit_cmp8bit);
4103 register_emitter(op_ia32_Const, bemit_mov_const);
4104 register_emitter(op_ia32_Conv_I2I, bemit_conv_i2i);
4105 register_emitter(op_ia32_Conv_I2I8Bit, bemit_conv_i2i);
4106 register_emitter(op_ia32_CopyB_i, bemit_copybi);
4107 register_emitter(op_ia32_Cwtl, bemit_cwtl);
4108 register_emitter(op_ia32_Dec, bemit_dec);
4109 register_emitter(op_ia32_DecMem, bemit_decmem);
4110 register_emitter(op_ia32_Div, bemit_div);
4111 register_emitter(op_ia32_FldCW, bemit_fldcw);
4112 register_emitter(op_ia32_FnstCW, bemit_fnstcw);
4113 register_emitter(op_ia32_FtstFnstsw, bemit_ftstfnstsw);
4114 register_emitter(op_ia32_FucomFnstsw, bemit_fucomfnstsw);
4115 register_emitter(op_ia32_Fucomi, bemit_fucomi);
4116 register_emitter(op_ia32_FucompFnstsw, bemit_fucompfnstsw);
4117 register_emitter(op_ia32_Fucompi, bemit_fucomip);
4118 register_emitter(op_ia32_FucomppFnstsw, bemit_fucomppfnstsw);
4119 register_emitter(op_ia32_IDiv, bemit_idiv);
4120 register_emitter(op_ia32_IJmp, bemit_ijmp);
4121 register_emitter(op_ia32_IMul, bemit_imul);
4122 register_emitter(op_ia32_IMul1OP, bemit_imul1op);
4123 register_emitter(op_ia32_Inc, bemit_inc);
4124 register_emitter(op_ia32_IncMem, bemit_incmem);
4125 register_emitter(op_ia32_Jcc, bemit_ia32_jcc);
4126 register_emitter(op_ia32_Jmp, bemit_jump);
4127 register_emitter(op_ia32_LdTls, bemit_ldtls);
4128 register_emitter(op_ia32_Lea, bemit_lea);
4129 register_emitter(op_ia32_Leave, bemit_leave);
4130 register_emitter(op_ia32_Load, bemit_load);
4131 register_emitter(op_ia32_Minus64Bit, bemit_minus64bit);
4132 register_emitter(op_ia32_Mul, bemit_mul);
4133 register_emitter(op_ia32_Neg, bemit_neg);
4134 register_emitter(op_ia32_NegMem, bemit_negmem);
4135 register_emitter(op_ia32_Not, bemit_not);
4136 register_emitter(op_ia32_NotMem, bemit_notmem);
4137 register_emitter(op_ia32_Or, bemit_or);
4138 register_emitter(op_ia32_OrMem, bemit_ormem);
4139 register_emitter(op_ia32_OrMem8Bit, bemit_ormem8bit);
4140 register_emitter(op_ia32_Pop, bemit_pop);
4141 register_emitter(op_ia32_PopEbp, bemit_pop);
4142 register_emitter(op_ia32_PopMem, bemit_popmem);
4143 register_emitter(op_ia32_Push, bemit_push);
4144 register_emitter(op_ia32_RepPrefix, bemit_rep);
4145 register_emitter(op_ia32_Rol, bemit_rol);
4146 register_emitter(op_ia32_RolMem, bemit_rolmem);
4147 register_emitter(op_ia32_Ror, bemit_ror);
4148 register_emitter(op_ia32_RorMem, bemit_rormem);
4149 register_emitter(op_ia32_Sahf, bemit_sahf);
4150 register_emitter(op_ia32_Sar, bemit_sar);
4151 register_emitter(op_ia32_SarMem, bemit_sarmem);
4152 register_emitter(op_ia32_Sbb, bemit_sbb);
4153 register_emitter(op_ia32_Setcc, bemit_setcc);
4154 register_emitter(op_ia32_Shl, bemit_shl);
4155 register_emitter(op_ia32_ShlD, bemit_shld);
4156 register_emitter(op_ia32_ShlMem, bemit_shlmem);
4157 register_emitter(op_ia32_Shr, bemit_shr);
4158 register_emitter(op_ia32_ShrD, bemit_shrd);
4159 register_emitter(op_ia32_ShrMem, bemit_shrmem);
4160 register_emitter(op_ia32_Stc, bemit_stc);
4161 register_emitter(op_ia32_Store, bemit_store);
4162 register_emitter(op_ia32_Store8Bit, bemit_store);
4163 register_emitter(op_ia32_Sub, bemit_sub);
4164 register_emitter(op_ia32_SubMem, bemit_submem);
4165 register_emitter(op_ia32_SubMem8Bit, bemit_submem8bit);
4166 register_emitter(op_ia32_SubSP, bemit_subsp);
4167 register_emitter(op_ia32_SwitchJmp, bemit_switchjmp);
4168 register_emitter(op_ia32_Test, bemit_test);
4169 register_emitter(op_ia32_Test8Bit, bemit_test8bit);
4170 register_emitter(op_ia32_Xor, bemit_xor);
4171 register_emitter(op_ia32_Xor0, bemit_xor0);
4172 register_emitter(op_ia32_XorMem, bemit_xormem);
4173 register_emitter(op_ia32_XorMem8Bit, bemit_xormem8bit);
4174 register_emitter(op_ia32_fabs, bemit_fabs);
4175 register_emitter(op_ia32_fadd, bemit_fadd);
4176 register_emitter(op_ia32_faddp, bemit_faddp);
4177 register_emitter(op_ia32_fchs, bemit_fchs);
4178 register_emitter(op_ia32_fdiv, bemit_fdiv);
4179 register_emitter(op_ia32_fdivp, bemit_fdivp);
4180 register_emitter(op_ia32_fdivr, bemit_fdivr);
4181 register_emitter(op_ia32_fdivrp, bemit_fdivrp);
4182 register_emitter(op_ia32_fild, bemit_fild);
4183 register_emitter(op_ia32_fist, bemit_fist);
4184 register_emitter(op_ia32_fistp, bemit_fistp);
4185 register_emitter(op_ia32_fld, bemit_fld);
4186 register_emitter(op_ia32_fld1, bemit_fld1);
4187 register_emitter(op_ia32_fldz, bemit_fldz);
4188 register_emitter(op_ia32_fmul, bemit_fmul);
4189 register_emitter(op_ia32_fmulp, bemit_fmulp);
4190 register_emitter(op_ia32_fpop, bemit_fpop);
4191 register_emitter(op_ia32_fpush, bemit_fpush);
4192 register_emitter(op_ia32_fpushCopy, bemit_fpushcopy);
4193 register_emitter(op_ia32_fst, bemit_fst);
4194 register_emitter(op_ia32_fstp, bemit_fstp);
4195 register_emitter(op_ia32_fsub, bemit_fsub);
4196 register_emitter(op_ia32_fsubp, bemit_fsubp);
4197 register_emitter(op_ia32_fsubr, bemit_fsubr);
4198 register_emitter(op_ia32_fsubrp, bemit_fsubrp);
4199 register_emitter(op_ia32_fxch, bemit_fxch);
4201 /* ignore the following nodes */
4202 register_emitter(op_ia32_ProduceVal, emit_Nothing);
4203 register_emitter(op_be_Barrier, emit_Nothing);
4204 register_emitter(op_be_Keep, emit_Nothing);
4205 register_emitter(op_be_Start, emit_Nothing);
4206 register_emitter(op_Phi, emit_Nothing);
4207 register_emitter(op_Start, emit_Nothing);
4210 static void gen_binary_block(ir_node *block)
4214 ia32_emit_block_header(block);
4216 /* emit the contents of the block */
4217 sched_foreach(block, node) {
4218 ia32_emit_node(node);
4222 void ia32_gen_binary_routine(ir_graph *irg)
4224 ir_entity *entity = get_irg_entity(irg);
4225 const arch_env_t *arch_env = be_get_irg_arch_env(irg);
4226 ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
4227 ir_node **blk_sched = irg_data->blk_sched;
4230 isa = (ia32_isa_t*) arch_env;
4232 ia32_register_binary_emitters();
4234 be_gas_emit_function_prolog(entity, ia32_cg_config.function_alignment);
4236 /* we use links to point to target blocks */
4237 ir_reserve_resources(irg, IR_RESOURCE_IRN_LINK);
4238 irg_block_walk_graph(irg, ia32_gen_labels, NULL, NULL);
4240 /* initialize next block links */
4241 n = ARR_LEN(blk_sched);
4242 for (i = 0; i < n; ++i) {
4243 ir_node *block = blk_sched[i];
4244 ir_node *prev = i > 0 ? blk_sched[i-1] : NULL;
4246 set_irn_link(block, prev);
4249 for (i = 0; i < n; ++i) {
4250 ir_node *block = blk_sched[i];
4251 gen_binary_block(block);
4254 be_gas_emit_function_epilog(entity);
4255 be_dbg_method_end();
4257 be_emit_write_line();
4259 ir_free_resources(irg, IR_RESOURCE_IRN_LINK);
4263 void ia32_init_emitter(void)
4265 lc_opt_entry_t *be_grp;
4266 lc_opt_entry_t *ia32_grp;
4268 be_grp = lc_opt_get_grp(firm_opt_get_root(), "be");
4269 ia32_grp = lc_opt_get_grp(be_grp, "ia32");
4271 lc_opt_add_table(ia32_grp, ia32_emitter_options);
4275 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.emitter");