2 * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This file implements the ia32 node emitter.
23 * @author Christian Wuerdig, Matthias Braun
41 #include "iredges_t.h"
44 #include "raw_bitset.h"
47 #include "../besched_t.h"
48 #include "../benode_t.h"
50 #include "../be_dbgout.h"
51 #include "../beemitter.h"
52 #include "../begnuas.h"
53 #include "../beirg_t.h"
55 #include "ia32_emitter.h"
56 #include "gen_ia32_emitter.h"
57 #include "gen_ia32_regalloc_if.h"
58 #include "ia32_nodes_attr.h"
59 #include "ia32_new_nodes.h"
60 #include "ia32_map_regs.h"
61 #include "ia32_architecture.h"
62 #include "bearch_ia32_t.h"
64 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
66 #define BLOCK_PREFIX ".L"
68 #define SNPRINTF_BUF_LEN 128
70 static const arch_env_t *arch_env;
71 static const ia32_isa_t *isa;
72 static ia32_code_gen_t *cg;
75 * Returns the register at in position pos.
77 static const arch_register_t *get_in_reg(const ir_node *irn, int pos)
80 const arch_register_t *reg = NULL;
82 assert(get_irn_arity(irn) > pos && "Invalid IN position");
84 /* The out register of the operator at position pos is the
85 in register we need. */
86 op = get_irn_n(irn, pos);
88 reg = arch_get_irn_register(arch_env, op);
90 assert(reg && "no in register found");
92 if(reg == &ia32_gp_regs[REG_GP_NOREG])
93 panic("trying to emit noreg for %+F input %d", irn, pos);
95 /* in case of unknown register: just return a valid register */
96 if (reg == &ia32_gp_regs[REG_GP_UKNWN]) {
97 const arch_register_req_t *req;
99 /* ask for the requirements */
100 req = arch_get_register_req(arch_env, irn, pos);
102 if (arch_register_req_is(req, limited)) {
103 /* in case of limited requirements: get the first allowed register */
104 unsigned idx = rbitset_next(req->limited, 0, 1);
105 reg = arch_register_for_index(req->cls, idx);
107 /* otherwise get first register in class */
108 reg = arch_register_for_index(req->cls, 0);
116 * Returns the register at out position pos.
118 static const arch_register_t *get_out_reg(const ir_node *irn, int pos)
121 const arch_register_t *reg = NULL;
123 /* 1st case: irn is not of mode_T, so it has only */
124 /* one OUT register -> good */
125 /* 2nd case: irn is of mode_T -> collect all Projs and ask the */
126 /* Proj with the corresponding projnum for the register */
128 if (get_irn_mode(irn) != mode_T) {
130 reg = arch_get_irn_register(arch_env, irn);
131 } else if (is_ia32_irn(irn)) {
132 reg = get_ia32_out_reg(irn, pos);
134 const ir_edge_t *edge;
136 foreach_out_edge(irn, edge) {
137 proj = get_edge_src_irn(edge);
138 assert(is_Proj(proj) && "non-Proj from mode_T node");
139 if (get_Proj_proj(proj) == pos) {
140 reg = arch_get_irn_register(arch_env, proj);
146 assert(reg && "no out register found");
151 * Add a number to a prefix. This number will not be used a second time.
153 static char *get_unique_label(char *buf, size_t buflen, const char *prefix)
155 static unsigned long id = 0;
156 snprintf(buf, buflen, "%s%lu", prefix, ++id);
160 /*************************************************************
162 * (_) | | / _| | | | |
163 * _ __ _ __ _ _ __ | |_| |_ | |__ ___| |_ __ ___ _ __
164 * | '_ \| '__| | '_ \| __| _| | '_ \ / _ \ | '_ \ / _ \ '__|
165 * | |_) | | | | | | | |_| | | | | | __/ | |_) | __/ |
166 * | .__/|_| |_|_| |_|\__|_| |_| |_|\___|_| .__/ \___|_|
169 *************************************************************/
171 static void emit_8bit_register(const arch_register_t *reg)
173 const char *reg_name = arch_register_get_name(reg);
176 be_emit_char(reg_name[1]);
180 static void emit_16bit_register(const arch_register_t *reg)
182 const char *reg_name = ia32_get_mapped_reg_name(isa->regs_16bit, reg);
185 be_emit_string(reg_name);
188 static void emit_register(const arch_register_t *reg, const ir_mode *mode)
190 const char *reg_name;
193 int size = get_mode_size_bits(mode);
195 emit_8bit_register(reg);
197 } else if(size == 16) {
198 emit_16bit_register(reg);
201 assert(mode_is_float(mode) || size == 32);
205 reg_name = arch_register_get_name(reg);
208 be_emit_string(reg_name);
211 void ia32_emit_source_register(const ir_node *node, int pos)
213 const arch_register_t *reg = get_in_reg(node, pos);
215 emit_register(reg, NULL);
218 static void emit_ia32_Immediate(const ir_node *node);
220 void ia32_emit_8bit_source_register_or_immediate(const ir_node *node, int pos)
222 const arch_register_t *reg;
223 ir_node *in = get_irn_n(node, pos);
224 if(is_ia32_Immediate(in)) {
225 emit_ia32_Immediate(in);
229 reg = get_in_reg(node, pos);
230 emit_8bit_register(reg);
233 void ia32_emit_dest_register(const ir_node *node, int pos)
235 const arch_register_t *reg = get_out_reg(node, pos);
237 emit_register(reg, NULL);
240 void ia32_emit_8bit_dest_register(const ir_node *node, int pos)
242 const arch_register_t *reg = get_out_reg(node, pos);
244 emit_register(reg, mode_Bu);
247 void ia32_emit_x87_register(const ir_node *node, int pos)
249 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
253 be_emit_string(attr->x87[pos]->name);
256 static void ia32_emit_mode_suffix_mode(const ir_mode *mode)
258 if(mode_is_float(mode)) {
259 switch(get_mode_size_bits(mode)) {
260 case 32: be_emit_char('s'); return;
261 case 64: be_emit_char('l'); return;
263 case 96: be_emit_char('t'); return;
266 assert(mode_is_int(mode) || mode_is_reference(mode));
267 switch(get_mode_size_bits(mode)) {
268 case 64: be_emit_cstring("ll"); return;
269 /* gas docu says q is the suffix but gcc, objdump and icc use
271 case 32: be_emit_char('l'); return;
272 case 16: be_emit_char('w'); return;
273 case 8: be_emit_char('b'); return;
276 panic("Can't output mode_suffix for %+F\n", mode);
279 void ia32_emit_mode_suffix(const ir_node *node)
281 ir_mode *mode = get_ia32_ls_mode(node);
285 ia32_emit_mode_suffix_mode(mode);
288 void ia32_emit_x87_mode_suffix(const ir_node *node)
290 ir_mode *mode = get_ia32_ls_mode(node);
291 assert(mode != NULL);
292 /* we only need to emit the mode on address mode */
293 if(get_ia32_op_type(node) != ia32_Normal)
294 ia32_emit_mode_suffix_mode(mode);
298 char get_xmm_mode_suffix(ir_mode *mode)
300 assert(mode_is_float(mode));
301 switch(get_mode_size_bits(mode)) {
312 void ia32_emit_xmm_mode_suffix(const ir_node *node)
314 ir_mode *mode = get_ia32_ls_mode(node);
315 assert(mode != NULL);
317 be_emit_char(get_xmm_mode_suffix(mode));
320 void ia32_emit_xmm_mode_suffix_s(const ir_node *node)
322 ir_mode *mode = get_ia32_ls_mode(node);
323 assert(mode != NULL);
324 be_emit_char(get_xmm_mode_suffix(mode));
327 void ia32_emit_extend_suffix(const ir_mode *mode)
329 if(get_mode_size_bits(mode) == 32)
331 if(mode_is_signed(mode)) {
339 void ia32_emit_function_object(const char *name)
341 switch (be_gas_flavour) {
342 case GAS_FLAVOUR_NORMAL:
343 be_emit_cstring("\t.type\t");
344 be_emit_string(name);
345 be_emit_cstring(", @function\n");
346 be_emit_write_line();
348 case GAS_FLAVOUR_MINGW:
349 be_emit_cstring("\t.def\t");
350 be_emit_string(name);
351 be_emit_cstring(";\t.scl\t2;\t.type\t32;\t.endef\n");
352 be_emit_write_line();
354 case GAS_FLAVOUR_YASM:
362 void ia32_emit_function_size(const char *name)
364 switch (be_gas_flavour) {
365 case GAS_FLAVOUR_NORMAL:
366 be_emit_cstring("\t.size\t");
367 be_emit_string(name);
368 be_emit_cstring(", .-");
369 be_emit_string(name);
371 be_emit_write_line();
373 case GAS_FLAVOUR_MINGW:
374 case GAS_FLAVOUR_YASM:
382 void ia32_emit_source_register_or_immediate(const ir_node *node, int pos)
384 ir_node *in = get_irn_n(node, pos);
385 if(is_ia32_Immediate(in)) {
386 emit_ia32_Immediate(in);
388 const ir_mode *mode = get_ia32_ls_mode(node);
389 const arch_register_t *reg = get_in_reg(node, pos);
390 emit_register(reg, mode);
395 * Emits registers and/or address mode of a binary operation.
397 void ia32_emit_binop(const ir_node *node) {
398 const ir_node *right_op = get_irn_n(node, n_ia32_binary_right);
399 const ir_mode *mode = get_ia32_ls_mode(node);
400 const arch_register_t *reg_left;
402 switch(get_ia32_op_type(node)) {
404 reg_left = get_in_reg(node, n_ia32_binary_left);
405 if(is_ia32_Immediate(right_op)) {
406 emit_ia32_Immediate(right_op);
407 be_emit_cstring(", ");
408 emit_register(reg_left, mode);
411 const arch_register_t *reg_right
412 = get_in_reg(node, n_ia32_binary_right);
413 emit_register(reg_right, mode);
414 be_emit_cstring(", ");
415 emit_register(reg_left, mode);
419 if(is_ia32_Immediate(right_op)) {
420 emit_ia32_Immediate(right_op);
421 be_emit_cstring(", ");
424 reg_left = get_in_reg(node, n_ia32_binary_left);
426 be_emit_cstring(", ");
427 emit_register(reg_left, mode);
431 panic("DestMode can't be output by %%binop anymore");
434 assert(0 && "unsupported op type");
439 * Emits registers and/or address mode of a binary operation.
441 void ia32_emit_x87_binop(const ir_node *node) {
442 switch(get_ia32_op_type(node)) {
445 const ia32_x87_attr_t *x87_attr = get_ia32_x87_attr_const(node);
446 const arch_register_t *in1 = x87_attr->x87[0];
447 const arch_register_t *in2 = x87_attr->x87[1];
448 const arch_register_t *out = x87_attr->x87[2];
449 const arch_register_t *in;
451 in = out ? ((out == in2) ? in1 : in2) : in2;
452 out = out ? out : in1;
455 be_emit_string(arch_register_get_name(in));
456 be_emit_cstring(", %");
457 be_emit_string(arch_register_get_name(out));
465 assert(0 && "unsupported op type");
469 void ia32_emit_am_or_dest_register(const ir_node *node,
471 if(get_ia32_op_type(node) == ia32_Normal) {
472 ia32_emit_dest_register(node, pos);
474 assert(get_ia32_op_type(node) == ia32_AddrModeD);
480 * Emits registers and/or address mode of a unary operation.
482 void ia32_emit_unop(const ir_node *node, int pos) {
485 switch(get_ia32_op_type(node)) {
487 op = get_irn_n(node, pos);
488 if (is_ia32_Immediate(op)) {
489 emit_ia32_Immediate(op);
491 ia32_emit_source_register(node, pos);
499 assert(0 && "unsupported op type");
503 static void ia32_emit_entity(ir_entity *entity)
507 set_entity_backend_marked(entity, 1);
508 id = get_entity_ld_ident(entity);
511 if(get_entity_owner(entity) == get_tls_type()) {
512 if (get_entity_visibility(entity) == visibility_external_allocated) {
513 be_emit_cstring("@INDNTPOFF");
515 be_emit_cstring("@NTPOFF");
521 * Emits address mode.
523 void ia32_emit_am(const ir_node *node) {
524 ir_entity *ent = get_ia32_am_sc(node);
525 int offs = get_ia32_am_offs_int(node);
526 ir_node *base = get_irn_n(node, 0);
527 int has_base = !is_ia32_NoReg_GP(base);
528 ir_node *index = get_irn_n(node, 1);
529 int has_index = !is_ia32_NoReg_GP(index);
531 /* just to be sure... */
532 assert(!is_ia32_use_frame(node) || get_ia32_frame_ent(node) != NULL);
536 if (is_ia32_am_sc_sign(node))
538 ia32_emit_entity(ent);
543 be_emit_irprintf("%+d", offs);
545 be_emit_irprintf("%d", offs);
549 if (has_base || has_index) {
554 const arch_register_t *reg = get_in_reg(node, n_ia32_base);
555 emit_register(reg, NULL);
558 /* emit index + scale */
560 const arch_register_t *reg = get_in_reg(node, n_ia32_index);
563 emit_register(reg, NULL);
565 scale = get_ia32_am_scale(node);
567 be_emit_irprintf(",%d", 1 << get_ia32_am_scale(node));
573 /* special case if nothing is set */
574 if(ent == NULL && offs == 0 && !has_base && !has_index) {
579 static void emit_ia32_IMul(const ir_node *node)
581 ir_node *left = get_irn_n(node, n_ia32_IMul_left);
582 const arch_register_t *out_reg = get_out_reg(node, pn_ia32_IMul_res);
584 be_emit_cstring("\timul");
585 ia32_emit_mode_suffix(node);
588 ia32_emit_binop(node);
590 /* do we need the 3-address form? */
591 if(is_ia32_NoReg_GP(left) ||
592 get_in_reg(node, n_ia32_IMul_left) != out_reg) {
593 be_emit_cstring(", ");
594 emit_register(out_reg, get_ia32_ls_mode(node));
596 be_emit_finish_line_gas(node);
599 /*************************************************
602 * ___ _ __ ___ _| |_ ___ ___ _ __ __| |
603 * / _ \ '_ ` _ \| | __| / __/ _ \| '_ \ / _` |
604 * | __/ | | | | | | |_ | (_| (_) | | | | (_| |
605 * \___|_| |_| |_|_|\__| \___\___/|_| |_|\__,_|
607 *************************************************/
610 #define IA32_DO_EMIT(irn) ia32_fprintf_format(F, irn, cmd_buf, cmnt_buf)
613 * coding of conditions
615 struct cmp2conditon_t {
621 * positive conditions for signed compares
623 static const struct cmp2conditon_t cmp2condition_s[] = {
624 { NULL, pn_Cmp_False }, /* always false */
625 { "e", pn_Cmp_Eq }, /* == */
626 { "l", pn_Cmp_Lt }, /* < */
627 { "le", pn_Cmp_Le }, /* <= */
628 { "g", pn_Cmp_Gt }, /* > */
629 { "ge", pn_Cmp_Ge }, /* >= */
630 { "ne", pn_Cmp_Lg }, /* != */
631 { NULL, pn_Cmp_Leg}, /* always true */
635 * positive conditions for unsigned compares
637 static const struct cmp2conditon_t cmp2condition_u[] = {
638 { NULL, pn_Cmp_False }, /* always false */
639 { "e", pn_Cmp_Eq }, /* == */
640 { "b", pn_Cmp_Lt }, /* < */
641 { "be", pn_Cmp_Le }, /* <= */
642 { "a", pn_Cmp_Gt }, /* > */
643 { "ae", pn_Cmp_Ge }, /* >= */
644 { "ne", pn_Cmp_Lg }, /* != */
645 { NULL, pn_Cmp_Leg }, /* always true */
649 ia32_pn_Cmp_unsigned = 0x1000,
650 ia32_pn_Cmp_float = 0x2000,
654 * walks up a tree of copies/perms/spills/reloads to find the original value
655 * that is moved around
657 static ir_node *find_original_value(ir_node *node)
659 inc_irg_visited(current_ir_graph);
661 mark_irn_visited(node);
662 if(be_is_Copy(node)) {
663 node = be_get_Copy_op(node);
664 } else if(be_is_CopyKeep(node)) {
665 node = be_get_CopyKeep_op(node);
666 } else if(is_Proj(node)) {
667 ir_node *pred = get_Proj_pred(node);
668 if(be_is_Perm(pred)) {
669 node = get_irn_n(pred, get_Proj_proj(node));
670 } else if(be_is_MemPerm(pred)) {
671 node = get_irn_n(pred, get_Proj_proj(node) + 1);
672 } else if(is_ia32_Load(pred)) {
673 node = get_irn_n(pred, n_ia32_Load_mem);
677 } else if(is_ia32_Store(node)) {
678 node = get_irn_n(node, n_ia32_Store_val);
679 } else if(is_Phi(node)) {
681 arity = get_irn_arity(node);
682 for(i = 0; i < arity; ++i) {
683 ir_node *in = get_irn_n(node, i);
696 static int determine_final_pnc(const ir_node *node, int flags_pos,
699 ir_node *flags = get_irn_n(node, flags_pos);
700 const ia32_attr_t *flags_attr;
701 flags = skip_Proj(flags);
703 if(is_ia32_Sahf(flags)) {
704 ir_node *cmp = get_irn_n(flags, n_ia32_Sahf_val);
705 if(!(is_ia32_FucomFnstsw(cmp) || is_ia32_FucompFnstsw(cmp)
706 || is_ia32_FucomppFnstsw(cmp) || is_ia32_FtstFnstsw(cmp))) {
707 cmp = find_original_value(cmp);
708 assert(is_ia32_FucomFnstsw(cmp) || is_ia32_FucompFnstsw(cmp)
709 || is_ia32_FucomppFnstsw(cmp) || is_ia32_FtstFnstsw(cmp));
712 flags_attr = get_ia32_attr_const(cmp);
713 if(flags_attr->data.ins_permuted)
714 pnc = get_mirrored_pnc(pnc);
715 pnc |= ia32_pn_Cmp_float;
716 } else if(is_ia32_Ucomi(flags) || is_ia32_Fucomi(flags)
717 || is_ia32_Fucompi(flags)) {
718 flags_attr = get_ia32_attr_const(flags);
720 if(flags_attr->data.ins_permuted)
721 pnc = get_mirrored_pnc(pnc);
722 pnc |= ia32_pn_Cmp_float;
725 assert(is_ia32_Cmp(flags) || is_ia32_Test(flags)
726 || is_ia32_Cmp8Bit(flags) || is_ia32_Test8Bit(flags));
728 flags_attr = get_ia32_attr_const(flags);
730 if(flags_attr->data.ins_permuted)
731 pnc = get_mirrored_pnc(pnc);
732 if(flags_attr->data.cmp_unsigned)
733 pnc |= ia32_pn_Cmp_unsigned;
739 static void ia32_emit_cmp_suffix(int pnc)
743 if((pnc & ia32_pn_Cmp_float) || (pnc & ia32_pn_Cmp_unsigned)) {
745 assert(cmp2condition_u[pnc].num == pnc);
746 str = cmp2condition_u[pnc].name;
749 assert(cmp2condition_s[pnc].num == pnc);
750 str = cmp2condition_s[pnc].name;
756 void ia32_emit_cmp_suffix_node(const ir_node *node,
759 const ia32_attr_t *attr = get_ia32_attr_const(node);
761 pn_Cmp pnc = get_ia32_condcode(node);
763 pnc = determine_final_pnc(node, flags_pos, pnc);
764 if(attr->data.ins_permuted) {
765 if(pnc & ia32_pn_Cmp_float) {
766 pnc = get_negated_pnc(pnc, mode_F);
768 pnc = get_negated_pnc(pnc, mode_Iu);
772 ia32_emit_cmp_suffix(pnc);
776 * Returns the target block for a control flow node.
779 ir_node *get_cfop_target_block(const ir_node *irn) {
780 return get_irn_link(irn);
784 * Emits a block label for the given block.
787 void ia32_emit_block_name(const ir_node *block)
789 if (has_Block_label(block)) {
790 be_emit_string(be_gas_label_prefix());
791 be_emit_irprintf("%u", (unsigned)get_Block_label(block));
793 be_emit_cstring(BLOCK_PREFIX);
794 be_emit_irprintf("%d", get_irn_node_nr(block));
799 * Emits the target label for a control flow node.
801 static void ia32_emit_cfop_target(const ir_node *node)
803 ir_node *block = get_cfop_target_block(node);
805 ia32_emit_block_name(block);
808 /** Return the next block in Block schedule */
809 static ir_node *next_blk_sched(const ir_node *block)
811 return get_irn_link(block);
815 * Returns the Proj with projection number proj and NOT mode_M
817 static ir_node *get_proj(const ir_node *node, long proj) {
818 const ir_edge_t *edge;
821 assert(get_irn_mode(node) == mode_T && "expected mode_T node");
823 foreach_out_edge(node, edge) {
824 src = get_edge_src_irn(edge);
826 assert(is_Proj(src) && "Proj expected");
827 if (get_irn_mode(src) == mode_M)
830 if (get_Proj_proj(src) == proj)
837 * Emits the jump sequence for a conditional jump (cmp + jmp_true + jmp_false)
839 static void emit_ia32_Jcc(const ir_node *node)
841 const ir_node *proj_true;
842 const ir_node *proj_false;
843 const ir_node *block;
844 const ir_node *next_block;
845 pn_Cmp pnc = get_ia32_condcode(node);
847 pnc = determine_final_pnc(node, 0, pnc);
850 proj_true = get_proj(node, pn_ia32_Jcc_true);
851 assert(proj_true && "Jcc without true Proj");
853 proj_false = get_proj(node, pn_ia32_Jcc_false);
854 assert(proj_false && "Jcc without false Proj");
856 block = get_nodes_block(node);
857 next_block = next_blk_sched(block);
859 if (get_cfop_target_block(proj_true) == next_block) {
860 /* exchange both proj's so the second one can be omitted */
861 const ir_node *t = proj_true;
863 proj_true = proj_false;
865 if(pnc & ia32_pn_Cmp_float) {
866 pnc = get_negated_pnc(pnc, mode_F);
868 pnc = get_negated_pnc(pnc, mode_Iu);
872 if (pnc & ia32_pn_Cmp_float) {
873 /* Some floating point comparisons require a test of the parity flag,
874 * which indicates that the result is unordered */
877 be_emit_cstring("\tjp ");
878 ia32_emit_cfop_target(proj_true);
879 be_emit_finish_line_gas(proj_true);
883 be_emit_cstring("\tjnp ");
884 ia32_emit_cfop_target(proj_true);
885 be_emit_finish_line_gas(proj_true);
891 be_emit_cstring("\tjp ");
892 ia32_emit_cfop_target(proj_false);
893 be_emit_finish_line_gas(proj_false);
899 be_emit_cstring("\tjp ");
900 ia32_emit_cfop_target(proj_true);
901 be_emit_finish_line_gas(proj_true);
909 be_emit_cstring("\tj");
910 ia32_emit_cmp_suffix(pnc);
912 ia32_emit_cfop_target(proj_true);
913 be_emit_finish_line_gas(proj_true);
916 /* the second Proj might be a fallthrough */
917 if (get_cfop_target_block(proj_false) != next_block) {
918 be_emit_cstring("\tjmp ");
919 ia32_emit_cfop_target(proj_false);
920 be_emit_finish_line_gas(proj_false);
922 be_emit_cstring("\t/* fallthrough to ");
923 ia32_emit_cfop_target(proj_false);
924 be_emit_cstring(" */");
925 be_emit_finish_line_gas(proj_false);
929 static void emit_ia32_CMov(const ir_node *node)
931 const ia32_attr_t *attr = get_ia32_attr_const(node);
932 int ins_permuted = attr->data.ins_permuted;
933 const arch_register_t *out = arch_get_irn_register(arch_env, node);
934 pn_Cmp pnc = get_ia32_condcode(node);
935 const arch_register_t *in_true;
936 const arch_register_t *in_false;
938 pnc = determine_final_pnc(node, n_ia32_CMov_eflags, pnc);
940 in_true = arch_get_irn_register(arch_env,
941 get_irn_n(node, n_ia32_CMov_val_true));
942 in_false = arch_get_irn_register(arch_env,
943 get_irn_n(node, n_ia32_CMov_val_false));
945 /* should be same constraint fullfilled? */
946 if(out == in_false) {
947 /* yes -> nothing to do */
948 } else if(out == in_true) {
949 const arch_register_t *tmp;
951 assert(get_ia32_op_type(node) == ia32_Normal);
953 ins_permuted = !ins_permuted;
960 be_emit_cstring("\tmovl ");
961 emit_register(in_false, NULL);
962 be_emit_cstring(", ");
963 emit_register(out, NULL);
964 be_emit_finish_line_gas(node);
968 if(pnc & ia32_pn_Cmp_float) {
969 pnc = get_negated_pnc(pnc, mode_F);
971 pnc = get_negated_pnc(pnc, mode_Iu);
975 /* TODO: handling of Nans isn't correct yet */
977 be_emit_cstring("\tcmov");
978 ia32_emit_cmp_suffix(pnc);
980 if(get_ia32_op_type(node) == ia32_AddrModeS) {
983 emit_register(in_true, get_ia32_ls_mode(node));
985 be_emit_cstring(", ");
986 emit_register(out, get_ia32_ls_mode(node));
987 be_emit_finish_line_gas(node);
990 /*********************************************************
993 * ___ _ __ ___ _| |_ _ _ _ _ __ ___ _ __ ___
994 * / _ \ '_ ` _ \| | __| | | | | | '_ ` _ \| '_ \/ __|
995 * | __/ | | | | | | |_ | | |_| | | | | | | |_) \__ \
996 * \___|_| |_| |_|_|\__| | |\__,_|_| |_| |_| .__/|___/
999 *********************************************************/
1001 /* jump table entry (target and corresponding number) */
1002 typedef struct _branch_t {
1007 /* jump table for switch generation */
1008 typedef struct _jmp_tbl_t {
1009 ir_node *defProj; /**< default target */
1010 long min_value; /**< smallest switch case */
1011 long max_value; /**< largest switch case */
1012 long num_branches; /**< number of jumps */
1013 char *label; /**< label of the jump table */
1014 branch_t *branches; /**< jump array */
1018 * Compare two variables of type branch_t. Used to sort all switch cases
1021 int ia32_cmp_branch_t(const void *a, const void *b) {
1022 branch_t *b1 = (branch_t *)a;
1023 branch_t *b2 = (branch_t *)b;
1025 if (b1->value <= b2->value)
1032 * Emits code for a SwitchJmp (creates a jump table if
1033 * possible otherwise a cmp-jmp cascade). Port from
1036 static void emit_ia32_SwitchJmp(const ir_node *node)
1038 unsigned long interval;
1044 const ir_edge_t *edge;
1046 /* fill the table structure */
1047 tbl.label = xmalloc(SNPRINTF_BUF_LEN);
1048 tbl.label = get_unique_label(tbl.label, SNPRINTF_BUF_LEN, ".TBL_");
1050 tbl.num_branches = get_irn_n_edges(node) - 1;
1051 tbl.branches = xcalloc(tbl.num_branches, sizeof(tbl.branches[0]));
1052 tbl.min_value = INT_MAX;
1053 tbl.max_value = INT_MIN;
1055 default_pn = get_ia32_condcode(node);
1057 /* go over all proj's and collect them */
1058 foreach_out_edge(node, edge) {
1059 proj = get_edge_src_irn(edge);
1060 assert(is_Proj(proj) && "Only proj allowed at SwitchJmp");
1062 pnc = get_Proj_proj(proj);
1064 /* check for default proj */
1065 if (pnc == default_pn) {
1066 assert(tbl.defProj == NULL && "found two default Projs at SwitchJmp");
1069 tbl.min_value = pnc < tbl.min_value ? pnc : tbl.min_value;
1070 tbl.max_value = pnc > tbl.max_value ? pnc : tbl.max_value;
1072 /* create branch entry */
1073 tbl.branches[i].target = proj;
1074 tbl.branches[i].value = pnc;
1079 assert(i == tbl.num_branches);
1081 /* sort the branches by their number */
1082 qsort(tbl.branches, tbl.num_branches, sizeof(tbl.branches[0]), ia32_cmp_branch_t);
1084 /* two-complement's magic make this work without overflow */
1085 interval = tbl.max_value - tbl.min_value;
1087 /* emit the table */
1088 be_emit_cstring("\tcmpl $");
1089 be_emit_irprintf("%u, ", interval);
1090 ia32_emit_source_register(node, 0);
1091 be_emit_finish_line_gas(node);
1093 be_emit_cstring("\tja ");
1094 ia32_emit_cfop_target(tbl.defProj);
1095 be_emit_finish_line_gas(node);
1097 if (tbl.num_branches > 1) {
1099 be_emit_cstring("\tjmp *");
1100 be_emit_string(tbl.label);
1101 be_emit_cstring("(,");
1102 ia32_emit_source_register(node, 0);
1103 be_emit_cstring(",4)");
1104 be_emit_finish_line_gas(node);
1106 be_gas_emit_switch_section(GAS_SECTION_RODATA);
1107 be_emit_cstring("\t.align 4\n");
1108 be_emit_write_line();
1110 be_emit_string(tbl.label);
1111 be_emit_cstring(":\n");
1112 be_emit_write_line();
1114 be_emit_cstring(".long ");
1115 ia32_emit_cfop_target(tbl.branches[0].target);
1116 be_emit_finish_line_gas(NULL);
1118 last_value = tbl.branches[0].value;
1119 for (i = 1; i < tbl.num_branches; ++i) {
1120 while (++last_value < tbl.branches[i].value) {
1121 be_emit_cstring(".long ");
1122 ia32_emit_cfop_target(tbl.defProj);
1123 be_emit_finish_line_gas(NULL);
1125 be_emit_cstring(".long ");
1126 ia32_emit_cfop_target(tbl.branches[i].target);
1127 be_emit_finish_line_gas(NULL);
1129 be_gas_emit_switch_section(GAS_SECTION_TEXT);
1131 /* one jump is enough */
1132 be_emit_cstring("\tjmp ");
1133 ia32_emit_cfop_target(tbl.branches[0].target);
1134 be_emit_finish_line_gas(node);
1144 * Emits code for a unconditional jump.
1146 static void emit_Jmp(const ir_node *node)
1148 ir_node *block, *next_block;
1150 /* for now, the code works for scheduled and non-schedules blocks */
1151 block = get_nodes_block(node);
1153 /* we have a block schedule */
1154 next_block = next_blk_sched(block);
1155 if (get_cfop_target_block(node) != next_block) {
1156 be_emit_cstring("\tjmp ");
1157 ia32_emit_cfop_target(node);
1159 be_emit_cstring("\t/* fallthrough to ");
1160 ia32_emit_cfop_target(node);
1161 be_emit_cstring(" */");
1163 be_emit_finish_line_gas(node);
1166 static void emit_ia32_Immediate(const ir_node *node)
1168 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(node);
1171 if(attr->symconst != NULL) {
1174 ia32_emit_entity(attr->symconst);
1176 if(attr->symconst == NULL || attr->offset != 0) {
1177 if(attr->symconst != NULL) {
1178 be_emit_irprintf("%+d", attr->offset);
1180 be_emit_irprintf("0x%X", attr->offset);
1186 * Emit an inline assembler operand.
1188 * @param node the ia32_ASM node
1189 * @param s points to the operand (a %c)
1191 * @return pointer to the first char in s NOT in the current operand
1193 static const char* emit_asm_operand(const ir_node *node, const char *s)
1195 const ia32_attr_t *ia32_attr = get_ia32_attr_const(node);
1196 const ia32_asm_attr_t *attr = CONST_CAST_IA32_ATTR(ia32_asm_attr_t,
1198 const arch_register_t *reg;
1199 const ia32_asm_reg_t *asm_regs = attr->register_map;
1200 const ia32_asm_reg_t *asm_reg;
1201 const char *reg_name;
1210 /* parse modifiers */
1213 ir_fprintf(stderr, "Warning: asm text (%+F) ends with %\n", node);
1237 ir_fprintf(stderr, "Warning: asm text (%+F) contains unknown modifier "
1238 "'%c' for asm op\n", node, c);
1244 sscanf(s, "%d%n", &num, &p);
1246 ir_fprintf(stderr, "Warning: Couldn't parse assembler operand (%+F)\n",
1253 if(num < 0 || num >= ARR_LEN(asm_regs)) {
1254 ir_fprintf(stderr, "Error: Custom assembler references invalid "
1255 "input/output (%+F)\n", node);
1258 asm_reg = & asm_regs[num];
1259 assert(asm_reg->valid);
1262 if(asm_reg->use_input == 0) {
1263 reg = get_out_reg(node, asm_reg->inout_pos);
1265 ir_node *pred = get_irn_n(node, asm_reg->inout_pos);
1267 /* might be an immediate value */
1268 if(is_ia32_Immediate(pred)) {
1269 emit_ia32_Immediate(pred);
1272 reg = get_in_reg(node, asm_reg->inout_pos);
1275 ir_fprintf(stderr, "Warning: no register assigned for %d asm op "
1276 "(%+F)\n", num, node);
1280 if(asm_reg->memory) {
1289 reg_name = ia32_get_mapped_reg_name(isa->regs_8bit, reg);
1292 reg_name = ia32_get_mapped_reg_name(isa->regs_8bit_high, reg);
1295 reg_name = ia32_get_mapped_reg_name(isa->regs_16bit, reg);
1298 panic("Invalid asm op modifier");
1300 be_emit_string(reg_name);
1302 emit_register(reg, asm_reg->mode);
1305 if(asm_reg->memory) {
1313 * Emits code for an ASM pseudo op.
1315 static void emit_ia32_Asm(const ir_node *node)
1317 const void *gen_attr = get_irn_generic_attr_const(node);
1318 const ia32_asm_attr_t *attr
1319 = CONST_CAST_IA32_ATTR(ia32_asm_attr_t, gen_attr);
1320 ident *asm_text = attr->asm_text;
1321 const char *s = get_id_str(asm_text);
1323 be_emit_cstring("# Begin ASM \t");
1324 be_emit_finish_line_gas(node);
1331 s = emit_asm_operand(node, s);
1340 be_emit_write_line();
1342 be_emit_cstring("# End ASM\n");
1343 be_emit_write_line();
1346 /**********************************
1349 * | | ___ _ __ _ _| |_) |
1350 * | | / _ \| '_ \| | | | _ <
1351 * | |___| (_) | |_) | |_| | |_) |
1352 * \_____\___/| .__/ \__, |____/
1355 **********************************/
1358 * Emit movsb/w instructions to make mov count divideable by 4
1360 static void emit_CopyB_prolog(unsigned size) {
1361 be_emit_cstring("\tcld");
1362 be_emit_finish_line_gas(NULL);
1366 be_emit_cstring("\tmovsb");
1367 be_emit_finish_line_gas(NULL);
1370 be_emit_cstring("\tmovsw");
1371 be_emit_finish_line_gas(NULL);
1374 be_emit_cstring("\tmovsb");
1375 be_emit_finish_line_gas(NULL);
1376 be_emit_cstring("\tmovsw");
1377 be_emit_finish_line_gas(NULL);
1383 * Emit rep movsd instruction for memcopy.
1385 static void emit_ia32_CopyB(const ir_node *node)
1387 unsigned size = get_ia32_copyb_size(node);
1389 emit_CopyB_prolog(size);
1391 be_emit_cstring("\trep movsd");
1392 be_emit_finish_line_gas(node);
1396 * Emits unrolled memcopy.
1398 static void emit_ia32_CopyB_i(const ir_node *node)
1400 unsigned size = get_ia32_copyb_size(node);
1402 emit_CopyB_prolog(size & 0x3);
1406 be_emit_cstring("\tmovsd");
1407 be_emit_finish_line_gas(NULL);
1413 /***************************
1417 * | | / _ \| '_ \ \ / /
1418 * | |___| (_) | | | \ V /
1419 * \_____\___/|_| |_|\_/
1421 ***************************/
1424 * Emit code for conversions (I, FP), (FP, I) and (FP, FP).
1426 static void emit_ia32_Conv_with_FP(const ir_node *node)
1428 ir_mode *ls_mode = get_ia32_ls_mode(node);
1429 int ls_bits = get_mode_size_bits(ls_mode);
1431 be_emit_cstring("\tcvt");
1433 if(is_ia32_Conv_I2FP(node)) {
1435 be_emit_cstring("si2ss");
1437 be_emit_cstring("si2sd");
1439 } else if(is_ia32_Conv_FP2I(node)) {
1441 be_emit_cstring("ss2si");
1443 be_emit_cstring("sd2si");
1446 assert(is_ia32_Conv_FP2FP(node));
1448 be_emit_cstring("sd2ss");
1450 be_emit_cstring("ss2sd");
1455 switch(get_ia32_op_type(node)) {
1457 ia32_emit_source_register(node, n_ia32_unary_op);
1459 case ia32_AddrModeS:
1463 assert(0 && "unsupported op type for Conv");
1465 be_emit_cstring(", ");
1466 ia32_emit_dest_register(node, 0);
1467 be_emit_finish_line_gas(node);
1470 static void emit_ia32_Conv_I2FP(const ir_node *node)
1472 emit_ia32_Conv_with_FP(node);
1475 static void emit_ia32_Conv_FP2I(const ir_node *node)
1477 emit_ia32_Conv_with_FP(node);
1480 static void emit_ia32_Conv_FP2FP(const ir_node *node)
1482 emit_ia32_Conv_with_FP(node);
1486 * Emits code for an Int conversion.
1488 static void emit_ia32_Conv_I2I(const ir_node *node)
1490 const char *sign_suffix;
1491 ir_mode *smaller_mode = get_ia32_ls_mode(node);
1492 int smaller_bits = get_mode_size_bits(smaller_mode);
1494 const arch_register_t *in_reg, *out_reg;
1496 assert(!mode_is_float(smaller_mode));
1497 assert(smaller_bits == 8 || smaller_bits == 16 || smaller_bits == 32);
1499 signed_mode = mode_is_signed(smaller_mode);
1500 if(smaller_bits == 32) {
1501 // this should not happen as it's no convert
1505 sign_suffix = signed_mode ? "s" : "z";
1508 out_reg = get_out_reg(node, 0);
1510 switch(get_ia32_op_type(node)) {
1512 in_reg = get_in_reg(node, n_ia32_unary_op);
1514 if (in_reg == &ia32_gp_regs[REG_EAX] &&
1515 out_reg == &ia32_gp_regs[REG_EAX] &&
1519 /* argument and result are both in EAX and */
1520 /* signedness is ok: -> use the smaller cwtl opcode */
1521 be_emit_cstring("\tcwtl");
1523 be_emit_cstring("\tmov");
1524 be_emit_string(sign_suffix);
1525 ia32_emit_mode_suffix_mode(smaller_mode);
1526 be_emit_cstring("l ");
1527 emit_register(in_reg, smaller_mode);
1528 be_emit_cstring(", ");
1529 emit_register(out_reg, NULL);
1532 case ia32_AddrModeS: {
1533 be_emit_cstring("\tmov");
1534 be_emit_string(sign_suffix);
1535 ia32_emit_mode_suffix_mode(smaller_mode);
1536 be_emit_cstring("l ");
1538 be_emit_cstring(", ");
1539 emit_register(out_reg, NULL);
1543 assert(0 && "unsupported op type for Conv");
1545 be_emit_finish_line_gas(node);
1549 /*******************************************
1552 * | |__ ___ _ __ ___ __| | ___ ___
1553 * | '_ \ / _ \ '_ \ / _ \ / _` |/ _ \/ __|
1554 * | |_) | __/ | | | (_) | (_| | __/\__ \
1555 * |_.__/ \___|_| |_|\___/ \__,_|\___||___/
1557 *******************************************/
1560 * Emits a backend call
1562 static void emit_be_Call(const ir_node *node)
1564 ir_entity *ent = be_Call_get_entity(node);
1566 be_emit_cstring("\tcall ");
1568 ia32_emit_entity(ent);
1570 const arch_register_t *reg = get_in_reg(node, be_pos_Call_ptr);
1572 emit_register(reg, NULL);
1574 be_emit_finish_line_gas(node);
1578 * Emits code to increase stack pointer.
1580 static void emit_be_IncSP(const ir_node *node)
1582 int offs = be_get_IncSP_offset(node);
1583 const arch_register_t *reg = arch_get_irn_register(arch_env, node);
1589 be_emit_cstring("\tsubl $");
1590 be_emit_irprintf("%u, ", offs);
1591 emit_register(reg, NULL);
1593 be_emit_cstring("\taddl $");
1594 be_emit_irprintf("%u, ", -offs);
1595 emit_register(reg, NULL);
1597 be_emit_finish_line_gas(node);
1601 * Emits code for Copy/CopyKeep.
1603 static void Copy_emitter(const ir_node *node, const ir_node *op)
1605 const arch_register_t *in = arch_get_irn_register(arch_env, op);
1606 const arch_register_t *out = arch_get_irn_register(arch_env, node);
1612 if(is_unknown_reg(in))
1614 /* copies of vf nodes aren't real... */
1615 if(arch_register_get_class(in) == &ia32_reg_classes[CLASS_ia32_vfp])
1618 mode = get_irn_mode(node);
1619 if (mode == mode_E) {
1620 be_emit_cstring("\tmovsd ");
1621 emit_register(in, NULL);
1622 be_emit_cstring(", ");
1623 emit_register(out, NULL);
1625 be_emit_cstring("\tmovl ");
1626 emit_register(in, NULL);
1627 be_emit_cstring(", ");
1628 emit_register(out, NULL);
1630 be_emit_finish_line_gas(node);
1633 static void emit_be_Copy(const ir_node *node)
1635 Copy_emitter(node, be_get_Copy_op(node));
1638 static void emit_be_CopyKeep(const ir_node *node)
1640 Copy_emitter(node, be_get_CopyKeep_op(node));
1644 * Emits code for exchange.
1646 static void emit_be_Perm(const ir_node *node)
1648 const arch_register_t *in0, *in1;
1649 const arch_register_class_t *cls0, *cls1;
1651 in0 = arch_get_irn_register(arch_env, get_irn_n(node, 0));
1652 in1 = arch_get_irn_register(arch_env, get_irn_n(node, 1));
1654 cls0 = arch_register_get_class(in0);
1655 cls1 = arch_register_get_class(in1);
1657 assert(cls0 == cls1 && "Register class mismatch at Perm");
1659 if (cls0 == &ia32_reg_classes[CLASS_ia32_gp]) {
1660 be_emit_cstring("\txchg ");
1661 emit_register(in1, NULL);
1662 be_emit_cstring(", ");
1663 emit_register(in0, NULL);
1664 be_emit_finish_line_gas(node);
1665 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_xmm]) {
1666 be_emit_cstring("\txorpd ");
1667 emit_register(in1, NULL);
1668 be_emit_cstring(", ");
1669 emit_register(in0, NULL);
1670 be_emit_finish_line_gas(NULL);
1672 be_emit_cstring("\txorpd ");
1673 emit_register(in0, NULL);
1674 be_emit_cstring(", ");
1675 emit_register(in1, NULL);
1676 be_emit_finish_line_gas(NULL);
1678 be_emit_cstring("\txorpd ");
1679 emit_register(in1, NULL);
1680 be_emit_cstring(", ");
1681 emit_register(in0, NULL);
1682 be_emit_finish_line_gas(node);
1683 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_vfp]) {
1685 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_st]) {
1688 panic("unexpected register class in be_Perm (%+F)\n", node);
1693 * Emits code for Constant loading.
1695 static void emit_ia32_Const(const ir_node *node)
1697 be_emit_cstring("\tmovl ");
1698 emit_ia32_Immediate(node);
1699 be_emit_cstring(", ");
1700 ia32_emit_dest_register(node, 0);
1702 be_emit_finish_line_gas(node);
1706 * Emits code to load the TLS base
1708 static void emit_ia32_LdTls(const ir_node *node)
1710 be_emit_cstring("\tmovl %gs:0, ");
1711 ia32_emit_dest_register(node, 0);
1712 be_emit_finish_line_gas(node);
1715 /* helper function for emit_ia32_Minus64Bit */
1716 static void emit_mov(const ir_node* node, const arch_register_t *src, const arch_register_t *dst)
1718 be_emit_cstring("\tmovl ");
1719 emit_register(src, NULL);
1720 be_emit_cstring(", ");
1721 emit_register(dst, NULL);
1722 be_emit_finish_line_gas(node);
1725 /* helper function for emit_ia32_Minus64Bit */
1726 static void emit_neg(const ir_node* node, const arch_register_t *reg)
1728 be_emit_cstring("\tnegl ");
1729 emit_register(reg, NULL);
1730 be_emit_finish_line_gas(node);
1733 /* helper function for emit_ia32_Minus64Bit */
1734 static void emit_sbb0(const ir_node* node, const arch_register_t *reg)
1736 be_emit_cstring("\tsbbl $0, ");
1737 emit_register(reg, NULL);
1738 be_emit_finish_line_gas(node);
1741 /* helper function for emit_ia32_Minus64Bit */
1742 static void emit_sbb(const ir_node* node, const arch_register_t *src, const arch_register_t *dst)
1744 be_emit_cstring("\tsbbl ");
1745 emit_register(src, NULL);
1746 be_emit_cstring(", ");
1747 emit_register(dst, NULL);
1748 be_emit_finish_line_gas(node);
1751 /* helper function for emit_ia32_Minus64Bit */
1752 static void emit_xchg(const ir_node* node, const arch_register_t *src, const arch_register_t *dst)
1754 be_emit_cstring("\txchgl ");
1755 emit_register(src, NULL);
1756 be_emit_cstring(", ");
1757 emit_register(dst, NULL);
1758 be_emit_finish_line_gas(node);
1761 /* helper function for emit_ia32_Minus64Bit */
1762 static void emit_zero(const ir_node* node, const arch_register_t *reg)
1764 be_emit_cstring("\txorl ");
1765 emit_register(reg, NULL);
1766 be_emit_cstring(", ");
1767 emit_register(reg, NULL);
1768 be_emit_finish_line_gas(node);
1771 static void emit_ia32_Minus64Bit(const ir_node *node)
1773 const arch_register_t *in_lo = get_in_reg(node, 0);
1774 const arch_register_t *in_hi = get_in_reg(node, 1);
1775 const arch_register_t *out_lo = get_out_reg(node, 0);
1776 const arch_register_t *out_hi = get_out_reg(node, 1);
1778 if (out_lo == in_lo) {
1779 if (out_hi != in_hi) {
1780 /* a -> a, b -> d */
1783 /* a -> a, b -> b */
1786 } else if (out_lo == in_hi) {
1787 if (out_hi == in_lo) {
1788 /* a -> b, b -> a */
1789 emit_xchg(node, in_lo, in_hi);
1792 /* a -> b, b -> d */
1793 emit_mov(node, in_hi, out_hi);
1794 emit_mov(node, in_lo, out_lo);
1798 if (out_hi == in_lo) {
1799 /* a -> c, b -> a */
1800 emit_mov(node, in_lo, out_lo);
1802 } else if (out_hi == in_hi) {
1803 /* a -> c, b -> b */
1804 emit_mov(node, in_lo, out_lo);
1807 /* a -> c, b -> d */
1808 emit_mov(node, in_lo, out_lo);
1814 emit_neg( node, out_hi);
1815 emit_neg( node, out_lo);
1816 emit_sbb0(node, out_hi);
1820 emit_zero(node, out_hi);
1821 emit_neg( node, out_lo);
1822 emit_sbb( node, in_hi, out_hi);
1825 static void emit_be_Return(const ir_node *node)
1828 be_emit_cstring("\tret");
1830 pop = be_Return_get_pop(node);
1832 be_emit_irprintf(" $%d", pop);
1834 be_emit_finish_line_gas(node);
1837 static void emit_Nothing(const ir_node *node)
1843 /***********************************************************************************
1846 * _ __ ___ __ _ _ _ __ | |_ _ __ __ _ _ __ ___ _____ _____ _ __| | __
1847 * | '_ ` _ \ / _` | | '_ \ | _| '__/ _` | '_ ` _ \ / _ \ \ /\ / / _ \| '__| |/ /
1848 * | | | | | | (_| | | | | | | | | | | (_| | | | | | | __/\ V V / (_) | | | <
1849 * |_| |_| |_|\__,_|_|_| |_| |_| |_| \__,_|_| |_| |_|\___| \_/\_/ \___/|_| |_|\_\
1851 ***********************************************************************************/
1854 * Enters the emitter functions for handled nodes into the generic
1855 * pointer of an opcode.
1858 void ia32_register_emitters(void) {
1860 #define IA32_EMIT2(a,b) op_ia32_##a->ops.generic = (op_func)emit_ia32_##b
1861 #define IA32_EMIT(a) IA32_EMIT2(a,a)
1862 #define EMIT(a) op_##a->ops.generic = (op_func)emit_##a
1863 #define IGN(a) op_##a->ops.generic = (op_func)emit_Nothing
1864 #define BE_EMIT(a) op_be_##a->ops.generic = (op_func)emit_be_##a
1865 #define BE_IGN(a) op_be_##a->ops.generic = (op_func)emit_Nothing
1867 /* first clear the generic function pointer for all ops */
1868 clear_irp_opcodes_generic_func();
1870 /* register all emitter functions defined in spec */
1871 ia32_register_spec_emitters();
1873 /* other ia32 emitter functions */
1877 IA32_EMIT(SwitchJmp);
1880 IA32_EMIT(Conv_I2FP);
1881 IA32_EMIT(Conv_FP2I);
1882 IA32_EMIT(Conv_FP2FP);
1883 IA32_EMIT(Conv_I2I);
1884 IA32_EMIT2(Conv_I2I8Bit, Conv_I2I);
1887 IA32_EMIT(Minus64Bit);
1890 /* benode emitter */
1915 static const char *last_name = NULL;
1916 static unsigned last_line = -1;
1917 static unsigned num = -1;
1920 * Emit the debug support for node node.
1922 static void ia32_emit_dbg(const ir_node *node)
1924 dbg_info *db = get_irn_dbg_info(node);
1926 const char *fname = ir_retrieve_dbg_info(db, &lineno);
1928 if (! cg->birg->main_env->options->stabs_debug_support)
1932 if (last_name != fname) {
1934 be_dbg_include_begin(cg->birg->main_env->db_handle, fname);
1937 if (last_line != lineno) {
1940 snprintf(name, sizeof(name), ".LM%u", ++num);
1942 be_dbg_line(cg->birg->main_env->db_handle, lineno, name);
1943 be_emit_string(name);
1944 be_emit_cstring(":\n");
1945 be_emit_write_line();
1950 typedef void (*emit_func_ptr) (const ir_node *);
1953 * Emits code for a node.
1955 static void ia32_emit_node(const ir_node *node)
1957 ir_op *op = get_irn_op(node);
1959 DBG((dbg, LEVEL_1, "emitting code for %+F\n", node));
1961 if (op->ops.generic) {
1962 emit_func_ptr func = (emit_func_ptr) op->ops.generic;
1963 ia32_emit_dbg(node);
1967 ir_fprintf(stderr, "Error: No emit handler for node %+F (%+G, graph %+F)\n", node, node, current_ir_graph);
1973 * Emits gas alignment directives
1975 static void ia32_emit_alignment(unsigned align, unsigned skip)
1977 be_emit_cstring("\t.p2align ");
1978 be_emit_irprintf("%u,,%u\n", align, skip);
1979 be_emit_write_line();
1983 * Emits gas alignment directives for Functions depended on cpu architecture.
1985 static void ia32_emit_align_func(void)
1987 unsigned align = ia32_cg_config.function_alignment;
1988 unsigned maximum_skip = (1 << align) - 1;
1990 ia32_emit_alignment(align, maximum_skip);
1994 * Emits gas alignment directives for Labels depended on cpu architecture.
1996 static void ia32_emit_align_label(void)
1998 unsigned align = ia32_cg_config.label_alignment;
1999 unsigned maximum_skip = (1 << align) - 1;
2000 ia32_emit_alignment(align, maximum_skip);
2004 * Test wether a block should be aligned.
2005 * For cpus in the P4/Athlon class it is useful to align jump labels to
2006 * 16 bytes. However we should only do that if the alignment nops before the
2007 * label aren't executed more often than we have jumps to the label.
2009 static int should_align_block(ir_node *block, ir_node *prev)
2011 static const double DELTA = .0001;
2012 ir_exec_freq *exec_freq = cg->birg->exec_freq;
2014 double prev_freq = 0; /**< execfreq of the fallthrough block */
2015 double jmp_freq = 0; /**< execfreq of all non-fallthrough blocks */
2018 if(exec_freq == NULL)
2020 if(ia32_cg_config.label_alignment_factor <= 0)
2023 block_freq = get_block_execfreq(exec_freq, block);
2024 if(block_freq < DELTA)
2027 n_cfgpreds = get_Block_n_cfgpreds(block);
2028 for(i = 0; i < n_cfgpreds; ++i) {
2029 ir_node *pred = get_Block_cfgpred_block(block, i);
2030 double pred_freq = get_block_execfreq(exec_freq, pred);
2033 prev_freq += pred_freq;
2035 jmp_freq += pred_freq;
2039 if(prev_freq < DELTA && !(jmp_freq < DELTA))
2042 jmp_freq /= prev_freq;
2044 return jmp_freq > ia32_cg_config.label_alignment_factor;
2047 static void ia32_emit_block_header(ir_node *block, ir_node *prev)
2052 ir_exec_freq *exec_freq = cg->birg->exec_freq;
2054 n_cfgpreds = get_Block_n_cfgpreds(block);
2055 need_label = (n_cfgpreds != 0);
2057 if (should_align_block(block, prev)) {
2059 ia32_emit_align_label();
2063 ia32_emit_block_name(block);
2066 be_emit_pad_comment();
2067 be_emit_cstring(" /* preds:");
2069 /* emit list of pred blocks in comment */
2070 arity = get_irn_arity(block);
2071 for (i = 0; i < arity; ++i) {
2072 ir_node *predblock = get_Block_cfgpred_block(block, i);
2073 be_emit_irprintf(" %d", get_irn_node_nr(predblock));
2076 be_emit_cstring("\t/* ");
2077 ia32_emit_block_name(block);
2078 be_emit_cstring(": ");
2080 if (exec_freq != NULL) {
2081 be_emit_irprintf(" freq: %f",
2082 get_block_execfreq(exec_freq, block));
2084 be_emit_cstring(" */\n");
2085 be_emit_write_line();
2089 * Walks over the nodes in a block connected by scheduling edges
2090 * and emits code for each node.
2092 static void ia32_gen_block(ir_node *block, ir_node *last_block)
2094 const ir_node *node;
2096 ia32_emit_block_header(block, last_block);
2098 /* emit the contents of the block */
2099 ia32_emit_dbg(block);
2100 sched_foreach(block, node) {
2101 ia32_emit_node(node);
2106 * Emits code for function start.
2108 static void ia32_emit_func_prolog(ir_graph *irg)
2110 ir_entity *irg_ent = get_irg_entity(irg);
2111 const char *irg_name = get_entity_ld_name(irg_ent);
2112 const be_irg_t *birg = cg->birg;
2114 /* write the begin line (used by scripts processing the assembler... */
2115 be_emit_write_line();
2116 be_emit_cstring("# -- Begin ");
2117 be_emit_string(irg_name);
2119 be_emit_write_line();
2121 be_gas_emit_switch_section(GAS_SECTION_TEXT);
2122 be_dbg_method_begin(birg->main_env->db_handle, irg_ent, be_abi_get_stack_layout(birg->abi));
2123 ia32_emit_align_func();
2124 if (get_entity_visibility(irg_ent) == visibility_external_visible) {
2125 be_emit_cstring(".global ");
2126 be_emit_string(irg_name);
2128 be_emit_write_line();
2130 ia32_emit_function_object(irg_name);
2131 be_emit_string(irg_name);
2132 be_emit_cstring(":\n");
2133 be_emit_write_line();
2137 * Emits code for function end
2139 static void ia32_emit_func_epilog(ir_graph *irg)
2141 const char *irg_name = get_entity_ld_name(get_irg_entity(irg));
2142 const be_irg_t *birg = cg->birg;
2144 ia32_emit_function_size(irg_name);
2145 be_dbg_method_end(birg->main_env->db_handle);
2147 be_emit_cstring("# -- End ");
2148 be_emit_string(irg_name);
2150 be_emit_write_line();
2153 be_emit_write_line();
2158 * Sets labels for control flow nodes (jump target)
2160 static void ia32_gen_labels(ir_node *block, void *data)
2163 int n = get_Block_n_cfgpreds(block);
2166 for (n--; n >= 0; n--) {
2167 pred = get_Block_cfgpred(block, n);
2168 set_irn_link(pred, block);
2173 * Emit an exception label if the current instruction can fail.
2175 void ia32_emit_exc_label(const ir_node *node)
2177 if (get_ia32_exc_label(node)) {
2178 be_emit_irprintf(".EXL%u\n", 0);
2179 be_emit_write_line();
2184 * Main driver. Emits the code for one routine.
2186 void ia32_gen_routine(ia32_code_gen_t *ia32_cg, ir_graph *irg)
2189 ir_node *last_block = NULL;
2193 isa = (const ia32_isa_t*) cg->arch_env->isa;
2194 arch_env = cg->arch_env;
2196 ia32_register_emitters();
2198 ia32_emit_func_prolog(irg);
2199 irg_block_walk_graph(irg, ia32_gen_labels, NULL, NULL);
2201 n = ARR_LEN(cg->blk_sched);
2202 for (i = 0; i < n;) {
2205 block = cg->blk_sched[i];
2207 next_bl = i < n ? cg->blk_sched[i] : NULL;
2209 /* set here the link. the emitter expects to find the next block here */
2210 set_irn_link(block, next_bl);
2211 ia32_gen_block(block, last_block);
2215 ia32_emit_func_epilog(irg);
2218 void ia32_init_emitter(void)
2220 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.emitter");