2 * Copyright (C) 1995-2011 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This file implements the ia32 node emitter.
23 * @author Christian Wuerdig, Matthias Braun
25 * Summary table for x86 floatingpoint compares:
26 * (remember effect of unordered on x86: ZF=1, PF=1, CF=1)
34 * pnc_Leg => NP (ordered)
56 #include "iredges_t.h"
60 #include "raw_bitset.h"
69 #include "beemitter.h"
73 #include "ia32_emitter.h"
74 #include "ia32_common_transform.h"
75 #include "gen_ia32_emitter.h"
76 #include "gen_ia32_regalloc_if.h"
77 #include "ia32_nodes_attr.h"
78 #include "ia32_new_nodes.h"
79 #include "ia32_architecture.h"
80 #include "bearch_ia32_t.h"
82 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
84 static const ia32_isa_t *isa;
85 static char pic_base_label[128];
86 static ir_label_t exc_label_id;
87 static int mark_spill_reload = 0;
90 static bool sp_relative;
91 static int frame_type_size;
92 static int callframe_offset;
94 /** Return the next block in Block schedule */
95 static ir_node *get_prev_block_sched(const ir_node *block)
97 return (ir_node*)get_irn_link(block);
100 /** Checks if the current block is a fall-through target. */
101 static int is_fallthrough(const ir_node *cfgpred)
105 if (!is_Proj(cfgpred))
107 pred = get_Proj_pred(cfgpred);
108 if (is_ia32_SwitchJmp(pred))
115 * returns non-zero if the given block needs a label
116 * because of being a jump-target (and not a fall-through)
118 static int block_needs_label(const ir_node *block)
121 int n_cfgpreds = get_Block_n_cfgpreds(block);
123 if (get_Block_entity(block) != NULL)
126 if (n_cfgpreds == 0) {
128 } else if (n_cfgpreds == 1) {
129 ir_node *cfgpred = get_Block_cfgpred(block, 0);
130 ir_node *cfgpred_block = get_nodes_block(cfgpred);
132 if (get_prev_block_sched(block) == cfgpred_block
133 && is_fallthrough(cfgpred)) {
142 * Add a number to a prefix. This number will not be used a second time.
144 static char *get_unique_label(char *buf, size_t buflen, const char *prefix)
146 static unsigned long id = 0;
147 snprintf(buf, buflen, "%s%s%lu", be_gas_get_private_prefix(), prefix, ++id);
152 * Emit the name of the 8bit low register
154 static void emit_8bit_register(const arch_register_t *reg)
156 const char *reg_name = arch_register_get_name(reg);
157 assert(reg->index == REG_GP_EAX || reg->index == REG_GP_EBX
158 || reg->index == REG_GP_ECX || reg->index == REG_GP_EDX);
161 be_emit_char(reg_name[1]); /* get the basic name of the register */
166 * Emit the name of the 8bit high register
168 static void emit_8bit_register_high(const arch_register_t *reg)
170 const char *reg_name = arch_register_get_name(reg);
171 assert(reg->index == REG_GP_EAX || reg->index == REG_GP_EBX
172 || reg->index == REG_GP_ECX || reg->index == REG_GP_EDX);
175 be_emit_char(reg_name[1]); /* get the basic name of the register */
179 static void emit_16bit_register(const arch_register_t *reg)
181 const char *reg_name = arch_register_get_name(reg);
184 be_emit_string(reg_name+1); /* skip the 'e' prefix of the 32bit names */
188 * emit a register, possible shortened by a mode
190 * @param reg the register
191 * @param mode the mode of the register or NULL for full register
193 static void emit_register(const arch_register_t *reg, const ir_mode *mode)
195 const char *reg_name;
198 int size = get_mode_size_bits(mode);
200 case 8: emit_8bit_register(reg); return;
201 case 16: emit_16bit_register(reg); return;
203 assert(mode_is_float(mode) || size == 32);
206 reg_name = arch_register_get_name(reg);
209 be_emit_string(reg_name);
212 static void ia32_emit_entity(ir_entity *entity, int no_pic_adjust)
214 be_gas_emit_entity(entity);
216 if (get_entity_owner(entity) == get_tls_type()) {
217 if (!entity_has_definition(entity)) {
218 be_emit_cstring("@INDNTPOFF");
220 be_emit_cstring("@NTPOFF");
224 if (do_pic && !no_pic_adjust) {
226 be_emit_string(pic_base_label);
230 static void emit_ia32_Immediate_no_prefix(const ir_node *node)
232 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(node);
234 if (attr->symconst != NULL) {
237 ia32_emit_entity(attr->symconst, attr->no_pic_adjust);
239 if (attr->symconst == NULL || attr->offset != 0) {
240 if (attr->symconst != NULL) {
241 be_emit_irprintf("%+d", attr->offset);
243 be_emit_irprintf("0x%X", attr->offset);
248 static void emit_ia32_Immediate(const ir_node *node)
251 emit_ia32_Immediate_no_prefix(node);
254 static void ia32_emit_mode_suffix_mode(const ir_mode *mode)
256 assert(mode_is_int(mode) || mode_is_reference(mode));
257 switch (get_mode_size_bits(mode)) {
258 case 8: be_emit_char('b'); return;
259 case 16: be_emit_char('w'); return;
260 case 32: be_emit_char('l'); return;
261 /* gas docu says q is the suffix but gcc, objdump and icc use ll
263 case 64: be_emit_cstring("ll"); return;
265 panic("Can't output mode_suffix for %+F", mode);
268 static void ia32_emit_x87_mode_suffix(ir_node const *const node)
272 /* we only need to emit the mode on address mode */
273 if (get_ia32_op_type(node) == ia32_Normal)
276 mode = get_ia32_ls_mode(node);
277 assert(mode != NULL);
279 if (mode_is_float(mode)) {
280 switch (get_mode_size_bits(mode)) {
281 case 32: be_emit_char('s'); return;
282 case 64: be_emit_char('l'); return;
283 /* long doubles have different sizes due to alignment on different
287 case 128: be_emit_char('t'); return;
290 assert(mode_is_int(mode) || mode_is_reference(mode));
291 switch (get_mode_size_bits(mode)) {
292 case 16: be_emit_char('s'); return;
293 case 32: be_emit_char('l'); return;
294 /* gas docu says q is the suffix but gcc, objdump and icc use ll
296 case 64: be_emit_cstring("ll"); return;
299 panic("Can't output mode_suffix for %+F", mode);
302 static char get_xmm_mode_suffix(ir_mode *mode)
304 assert(mode_is_float(mode));
305 switch (get_mode_size_bits(mode)) {
308 default: panic("Invalid XMM mode");
312 static void ia32_emit_xmm_mode_suffix(ir_node const *const node)
314 ir_mode *mode = get_ia32_ls_mode(node);
315 assert(mode != NULL);
316 be_emit_char(get_xmm_mode_suffix(mode));
320 * Returns the target block for a control flow node.
322 static ir_node *get_cfop_target_block(const ir_node *irn)
324 assert(get_irn_mode(irn) == mode_X);
325 return (ir_node*)get_irn_link(irn);
329 * Emits the target label for a control flow node.
331 static void ia32_emit_cfop_target(const ir_node *node)
333 ir_node *block = get_cfop_target_block(node);
334 be_gas_emit_block_name(block);
338 * Emit the suffix for a compare instruction.
340 static void ia32_emit_condition_code(ia32_condition_code_t cc)
343 case ia32_cc_overflow: be_emit_cstring("o"); return;
344 case ia32_cc_not_overflow: be_emit_cstring("no"); return;
345 case ia32_cc_float_below:
346 case ia32_cc_float_unordered_below:
347 case ia32_cc_below: be_emit_cstring("b"); return;
348 case ia32_cc_float_above_equal:
349 case ia32_cc_float_unordered_above_equal:
350 case ia32_cc_above_equal: be_emit_cstring("ae"); return;
351 case ia32_cc_float_equal:
352 case ia32_cc_equal: be_emit_cstring("e"); return;
353 case ia32_cc_float_not_equal:
354 case ia32_cc_not_equal: be_emit_cstring("ne"); return;
355 case ia32_cc_float_below_equal:
356 case ia32_cc_float_unordered_below_equal:
357 case ia32_cc_below_equal: be_emit_cstring("be"); return;
358 case ia32_cc_float_above:
359 case ia32_cc_float_unordered_above:
360 case ia32_cc_above: be_emit_cstring("a"); return;
361 case ia32_cc_sign: be_emit_cstring("s"); return;
362 case ia32_cc_not_sign: be_emit_cstring("ns"); return;
363 case ia32_cc_parity: be_emit_cstring("p"); return;
364 case ia32_cc_not_parity: be_emit_cstring("np"); return;
365 case ia32_cc_less: be_emit_cstring("l"); return;
366 case ia32_cc_greater_equal: be_emit_cstring("ge"); return;
367 case ia32_cc_less_equal: be_emit_cstring("le"); return;
368 case ia32_cc_greater: be_emit_cstring("g"); return;
369 case ia32_cc_float_parity_cases:
370 case ia32_cc_additional_float_cases:
373 panic("Invalid ia32 condition code");
376 typedef enum ia32_emit_mod_t {
378 EMIT_RESPECT_LS = 1U << 0,
379 EMIT_ALTERNATE_AM = 1U << 1,
381 EMIT_HIGH_REG = 1U << 3,
382 EMIT_LOW_REG = 1U << 4,
383 EMIT_16BIT_REG = 1U << 5
385 ENUM_BITSET(ia32_emit_mod_t)
388 * Emits address mode.
390 static void ia32_emit_am(ir_node const *const node)
392 ir_entity *ent = get_ia32_am_sc(node);
393 int offs = get_ia32_am_offs_int(node);
394 ir_node *base = get_irn_n(node, n_ia32_base);
395 int has_base = !is_ia32_NoReg_GP(base);
396 ir_node *idx = get_irn_n(node, n_ia32_index);
397 int has_index = !is_ia32_NoReg_GP(idx);
399 /* just to be sure... */
400 assert(!is_ia32_use_frame(node) || get_ia32_frame_ent(node) != NULL);
402 if (get_ia32_am_tls_segment(node))
403 be_emit_cstring("%gs:");
407 const ia32_attr_t *attr = get_ia32_attr_const(node);
408 if (is_ia32_am_sc_sign(node))
410 ia32_emit_entity(ent, attr->data.am_sc_no_pic_adjust);
413 /* also handle special case if nothing is set */
414 if (offs != 0 || (ent == NULL && !has_base && !has_index)) {
416 be_emit_irprintf("%+d", offs);
418 be_emit_irprintf("%d", offs);
422 if (has_base || has_index) {
427 const arch_register_t *reg = arch_get_irn_register_in(node, n_ia32_base);
428 emit_register(reg, NULL);
431 /* emit index + scale */
433 const arch_register_t *reg = arch_get_irn_register_in(node, n_ia32_index);
436 emit_register(reg, NULL);
438 scale = get_ia32_am_scale(node);
440 be_emit_irprintf(",%d", 1 << scale);
447 static ia32_condition_code_t determine_final_cc(ir_node const *node, int flags_pos, ia32_condition_code_t cc);
449 void ia32_emitf(ir_node const *const node, char const *fmt, ...)
456 const char *start = fmt;
457 ia32_emit_mod_t mod = EMIT_NONE;
459 while (*fmt != '%' && *fmt != '\n' && *fmt != '\0')
462 be_emit_string_len(start, fmt - start);
467 be_emit_write_line();
481 case '*': mod |= EMIT_ALTERNATE_AM; break;
482 case '#': mod |= EMIT_RESPECT_LS; break;
483 case 'l': mod |= EMIT_LONG; break;
484 case '>': mod |= EMIT_HIGH_REG; break;
485 case '<': mod |= EMIT_LOW_REG; break;
486 case '^': mod |= EMIT_16BIT_REG; break;
495 arch_register_t const *reg;
505 if (get_ia32_op_type(node) == ia32_AddrModeS) {
508 assert(get_ia32_op_type(node) == ia32_Normal);
509 ia32_x87_attr_t const *const x87_attr = get_ia32_x87_attr_const(node);
510 arch_register_t const *const out = x87_attr->x87[2];
511 arch_register_t const * in = x87_attr->x87[1];
513 in = x87_attr->x87[0];
514 be_emit_irprintf("%%%s, %%%s", arch_register_get_name(in), arch_register_get_name(out));
520 if (mod & EMIT_ALTERNATE_AM)
526 reg = va_arg(ap, const arch_register_t*);
527 if (get_ia32_op_type(node) == ia32_AddrModeS) {
534 if (get_ia32_op_type(node) == ia32_AddrModeS) {
538 assert(get_ia32_op_type(node) == ia32_Normal);
542 default: goto unknown;
548 imm = get_irn_n(node, n_ia32_binary_right);
549 if (is_ia32_Immediate(imm)) {
550 emit_ia32_Immediate(imm);
551 be_emit_cstring(", ");
552 if (get_ia32_op_type(node) == ia32_AddrModeS) {
555 assert(get_ia32_op_type(node) == ia32_Normal);
556 reg = arch_get_irn_register_in(node, n_ia32_binary_left);
557 emit_register(reg, get_ia32_ls_mode(node));
560 if (get_ia32_op_type(node) == ia32_AddrModeS) {
563 assert(get_ia32_op_type(node) == ia32_Normal);
564 reg = arch_get_irn_register_in(node, n_ia32_binary_right);
565 emit_register(reg, get_ia32_ls_mode(node));
567 be_emit_cstring(", ");
568 reg = arch_get_irn_register_in(node, n_ia32_binary_left);
569 emit_register(reg, get_ia32_ls_mode(node));
574 if (*fmt < '0' || '9' < *fmt)
576 reg = arch_get_irn_register_out(node, *fmt++ - '0');
582 ia32_emit_x87_mode_suffix(node);
583 } else if (*fmt == 'P') {
585 ia32_x87_attr_t const *const attr = get_ia32_x87_attr_const(node);
588 } else if (*fmt == 'R') {
590 /* NOTE: Work around a gas quirk for non-commutative operations if the
591 * destination register is not %st0. In this case r/non-r is swapped.
592 * %st0 = %st0 - %st1 -> fsub %st1, %st0 (as expected)
593 * %st0 = %st1 - %st0 -> fsubr %st1, %st0 (as expected)
594 * %st1 = %st0 - %st1 -> fsub %st0, %st1 (expected: fsubr)
595 * %st1 = %st1 - %st0 -> fsubr %st0, %st1 (expected: fsub)
596 * In fact this corresponds to the encoding of the instruction:
597 * - The r suffix selects whether %st0 is on the left (no r) or on the
598 * right (r) side of the executed operation.
599 * - The placement of %st0 selects whether the result is written to
600 * %st0 (right) or the other register (left).
601 * This results in testing whether the left operand register is %st0
602 * instead of the expected test whether the output register equals the
603 * left operand register. */
604 ia32_x87_attr_t const *const attr = get_ia32_x87_attr_const(node);
605 if (get_ia32_op_type(node) == ia32_Normal ?
606 attr->x87[0] != &ia32_registers[REG_ST0] :
607 attr->attr.data.ins_permuted)
609 } else if (*fmt == 'X') {
611 ia32_emit_xmm_mode_suffix(node);
612 } else if ('0' <= *fmt && *fmt <= '2') {
613 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
615 be_emit_string(attr->x87[*fmt++ - '0']->name);
624 if (!(mod & EMIT_ALTERNATE_AM))
626 emit_ia32_Immediate_no_prefix(imm);
630 ia32_emit_cfop_target(node);
634 ir_mode *mode = get_ia32_ls_mode(node);
637 if (mod & EMIT_RESPECT_LS) {
638 if (get_mode_size_bits(mode) == 32)
640 be_emit_char(mode_is_signed(mode) ? 's' : 'z');
642 ia32_emit_mode_suffix_mode(mode);
647 ia32_condition_code_t cc;
650 cc = (ia32_condition_code_t)va_arg(ap, int);
651 } else if ('0' <= *fmt && *fmt <= '9') {
652 cc = get_ia32_condcode(node);
653 cc = determine_final_cc(node, *fmt - '0', cc);
658 ia32_emit_condition_code(cc);
663 reg = va_arg(ap, const arch_register_t*);
665 if (mod & EMIT_ALTERNATE_AM)
667 if (mod & EMIT_HIGH_REG) {
668 emit_8bit_register_high(reg);
669 } else if (mod & EMIT_LOW_REG) {
670 emit_8bit_register(reg);
671 } else if (mod & EMIT_16BIT_REG) {
672 emit_16bit_register(reg);
674 emit_register(reg, mod & EMIT_RESPECT_LS ? get_ia32_ls_mode(node) : NULL);
682 if (*fmt < '0' || '9' < *fmt)
686 imm = get_irn_n(node, pos);
687 if (is_ia32_Immediate(imm)) {
690 reg = arch_get_irn_register_in(node, pos);
696 const char *str = va_arg(ap, const char*);
702 if (mod & EMIT_LONG) {
703 unsigned long num = va_arg(ap, unsigned long);
704 be_emit_irprintf("%lu", num);
706 unsigned num = va_arg(ap, unsigned);
707 be_emit_irprintf("%u", num);
712 if (mod & EMIT_LONG) {
713 long num = va_arg(ap, long);
714 be_emit_irprintf("%ld", num);
716 int num = va_arg(ap, int);
717 be_emit_irprintf("%d", num);
723 panic("unknown format conversion");
727 be_emit_finish_line_gas(node);
731 static void emit_ia32_IMul(const ir_node *node)
733 ir_node *left = get_irn_n(node, n_ia32_IMul_left);
734 const arch_register_t *out_reg = arch_get_irn_register_out(node, pn_ia32_IMul_res);
736 /* do we need the 3-address form? */
737 if (is_ia32_NoReg_GP(left) ||
738 arch_get_irn_register_in(node, n_ia32_IMul_left) != out_reg) {
739 ia32_emitf(node, "imul%M %#S4, %#AS3, %#D0");
741 ia32_emitf(node, "imul%M %#AS4, %#S3");
746 * walks up a tree of copies/perms/spills/reloads to find the original value
747 * that is moved around
749 static ir_node *find_original_value(ir_node *node)
751 if (irn_visited(node))
754 mark_irn_visited(node);
755 if (be_is_Copy(node)) {
756 return find_original_value(be_get_Copy_op(node));
757 } else if (be_is_CopyKeep(node)) {
758 return find_original_value(be_get_CopyKeep_op(node));
759 } else if (is_Proj(node)) {
760 ir_node *pred = get_Proj_pred(node);
761 if (be_is_Perm(pred)) {
762 return find_original_value(get_irn_n(pred, get_Proj_proj(node)));
763 } else if (be_is_MemPerm(pred)) {
764 return find_original_value(get_irn_n(pred, get_Proj_proj(node) + 1));
765 } else if (is_ia32_Load(pred)) {
766 return find_original_value(get_irn_n(pred, n_ia32_Load_mem));
767 } else if (is_ia32_Store(pred)) {
768 return find_original_value(get_irn_n(pred, n_ia32_Store_val));
772 } else if (is_Phi(node)) {
774 arity = get_irn_arity(node);
775 for (i = 0; i < arity; ++i) {
776 ir_node *in = get_irn_n(node, i);
777 ir_node *res = find_original_value(in);
788 static ia32_condition_code_t determine_final_cc(const ir_node *node,
789 int flags_pos, ia32_condition_code_t cc)
791 ir_node *flags = get_irn_n(node, flags_pos);
792 const ia32_attr_t *flags_attr;
793 flags = skip_Proj(flags);
795 if (is_ia32_Sahf(flags)) {
796 ir_node *cmp = get_irn_n(flags, n_ia32_Sahf_val);
797 if (!(is_ia32_FucomFnstsw(cmp) || is_ia32_FucompFnstsw(cmp)
798 || is_ia32_FucomppFnstsw(cmp) || is_ia32_FtstFnstsw(cmp))) {
799 inc_irg_visited(current_ir_graph);
800 cmp = find_original_value(cmp);
802 assert(is_ia32_FucomFnstsw(cmp) || is_ia32_FucompFnstsw(cmp)
803 || is_ia32_FucomppFnstsw(cmp) || is_ia32_FtstFnstsw(cmp));
806 flags_attr = get_ia32_attr_const(cmp);
808 flags_attr = get_ia32_attr_const(flags);
811 if (flags_attr->data.ins_permuted)
812 cc = ia32_invert_condition_code(cc);
817 * Emits an exception label for a given node.
819 static void ia32_emit_exc_label(const ir_node *node)
821 be_emit_string(be_gas_insn_label_prefix());
822 be_emit_irprintf("%lu", get_ia32_exc_label_id(node));
826 * Returns the Proj with projection number proj and NOT mode_M
828 static ir_node *get_proj(const ir_node *node, long proj)
832 assert(get_irn_mode(node) == mode_T && "expected mode_T node");
834 foreach_out_edge(node, edge) {
835 src = get_edge_src_irn(edge);
837 assert(is_Proj(src) && "Proj expected");
838 if (get_irn_mode(src) == mode_M)
841 if (get_Proj_proj(src) == proj)
847 static int can_be_fallthrough(const ir_node *node)
849 ir_node *target_block = get_cfop_target_block(node);
850 ir_node *block = get_nodes_block(node);
851 return get_prev_block_sched(target_block) == block;
855 * Emits the jump sequence for a conditional jump (cmp + jmp_true + jmp_false)
857 static void emit_ia32_Jcc(const ir_node *node)
859 int need_parity_label = 0;
860 ia32_condition_code_t cc = get_ia32_condcode(node);
861 const ir_node *proj_true;
862 const ir_node *proj_false;
864 cc = determine_final_cc(node, 0, cc);
867 proj_true = get_proj(node, pn_ia32_Jcc_true);
868 assert(proj_true && "Jcc without true Proj");
870 proj_false = get_proj(node, pn_ia32_Jcc_false);
871 assert(proj_false && "Jcc without false Proj");
873 if (can_be_fallthrough(proj_true)) {
874 /* exchange both proj's so the second one can be omitted */
875 const ir_node *t = proj_true;
877 proj_true = proj_false;
879 cc = ia32_negate_condition_code(cc);
882 if (cc & ia32_cc_float_parity_cases) {
883 /* Some floating point comparisons require a test of the parity flag,
884 * which indicates that the result is unordered */
885 if (cc & ia32_cc_negated) {
886 ia32_emitf(proj_true, "jp %L");
888 /* we need a local label if the false proj is a fallthrough
889 * as the falseblock might have no label emitted then */
890 if (can_be_fallthrough(proj_false)) {
891 need_parity_label = 1;
892 ia32_emitf(proj_false, "jp 1f");
894 ia32_emitf(proj_false, "jp %L");
898 ia32_emitf(proj_true, "j%PX %L", (int)cc);
899 if (need_parity_label) {
900 be_emit_cstring("1:\n");
901 be_emit_write_line();
904 /* the second Proj might be a fallthrough */
905 if (can_be_fallthrough(proj_false)) {
906 if (be_options.verbose_asm)
907 ia32_emitf(proj_false, "/* fallthrough to %L */");
909 ia32_emitf(proj_false, "jmp %L");
914 * Emits an ia32 Setcc. This is mostly easy but some floating point compares
917 static void emit_ia32_Setcc(const ir_node *node)
919 const arch_register_t *dreg = arch_get_irn_register_out(node, pn_ia32_Setcc_res);
921 ia32_condition_code_t cc = get_ia32_condcode(node);
922 cc = determine_final_cc(node, n_ia32_Setcc_eflags, cc);
923 if (cc & ia32_cc_float_parity_cases) {
924 if (cc & ia32_cc_negated) {
925 ia32_emitf(node, "set%PX %<R", (int)cc, dreg);
926 ia32_emitf(node, "setp %>R", dreg);
927 ia32_emitf(node, "orb %>R, %<R", dreg, dreg);
929 ia32_emitf(node, "set%PX %<R", (int)cc, dreg);
930 ia32_emitf(node, "setnp %>R", dreg);
931 ia32_emitf(node, "andb %>R, %<R", dreg, dreg);
934 ia32_emitf(node, "set%PX %#R", (int)cc, dreg);
938 static void emit_ia32_CMovcc(const ir_node *node)
940 const ia32_attr_t *attr = get_ia32_attr_const(node);
941 const arch_register_t *out = arch_get_irn_register_out(node, pn_ia32_res);
942 ia32_condition_code_t cc = get_ia32_condcode(node);
943 const arch_register_t *in_true;
944 const arch_register_t *in_false;
946 cc = determine_final_cc(node, n_ia32_CMovcc_eflags, cc);
947 /* although you can't set ins_permuted in the constructor it might still
948 * be set by memory operand folding
949 * Permuting inputs of a cmov means the condition is negated!
951 if (attr->data.ins_permuted)
952 cc = ia32_negate_condition_code(cc);
954 in_true = arch_get_irn_register(get_irn_n(node, n_ia32_CMovcc_val_true));
955 in_false = arch_get_irn_register(get_irn_n(node, n_ia32_CMovcc_val_false));
957 /* should be same constraint fullfilled? */
958 if (out == in_false) {
959 /* yes -> nothing to do */
960 } else if (out == in_true) {
961 const arch_register_t *tmp;
963 assert(get_ia32_op_type(node) == ia32_Normal);
965 cc = ia32_negate_condition_code(cc);
972 ia32_emitf(node, "movl %R, %R", in_false, out);
975 if (cc & ia32_cc_float_parity_cases) {
976 panic("CMov with floatingpoint compare/parity not supported yet");
979 ia32_emitf(node, "cmov%PX %#AR, %#R", (int)cc, in_true, out);
983 * Emits code for a SwitchJmp
985 static void emit_ia32_SwitchJmp(const ir_node *node)
987 ir_entity *jump_table = get_ia32_am_sc(node);
988 const ir_switch_table *table = get_ia32_switch_table(node);
990 ia32_emitf(node, "jmp %*AM");
991 be_emit_jump_table(node, table, jump_table, get_cfop_target_block);
995 * Emits code for a unconditional jump.
997 static void emit_ia32_Jmp(const ir_node *node)
999 /* we have a block schedule */
1000 if (can_be_fallthrough(node)) {
1001 if (be_options.verbose_asm)
1002 ia32_emitf(node, "/* fallthrough to %L */");
1004 ia32_emitf(node, "jmp %L");
1009 * Emit an inline assembler operand.
1011 * @param node the ia32_ASM node
1012 * @param s points to the operand (a %c)
1014 * @return pointer to the first char in s NOT in the current operand
1016 static const char* emit_asm_operand(const ir_node *node, const char *s)
1018 const ia32_attr_t *ia32_attr = get_ia32_attr_const(node);
1019 const ia32_asm_attr_t *attr = CONST_CAST_IA32_ATTR(ia32_asm_attr_t,
1021 const arch_register_t *reg;
1022 const ia32_asm_reg_t *asm_regs = attr->register_map;
1023 const ia32_asm_reg_t *asm_reg;
1032 /* parse modifiers */
1035 ir_fprintf(stderr, "Warning: asm text (%+F) ends with %%\n", node);
1060 "Warning: asm text (%+F) contains unknown modifier '%c' for asm op\n",
1067 if (sscanf(s, "%d%n", &num, &p) != 1) {
1068 ir_fprintf(stderr, "Warning: Couldn't parse assembler operand (%+F)\n",
1075 if (num < 0 || ARR_LEN(asm_regs) <= (size_t)num) {
1077 "Error: Custom assembler references invalid input/output (%+F)\n",
1081 asm_reg = & asm_regs[num];
1082 assert(asm_reg->valid);
1085 if (asm_reg->use_input == 0) {
1086 reg = arch_get_irn_register_out(node, asm_reg->inout_pos);
1088 ir_node *pred = get_irn_n(node, asm_reg->inout_pos);
1090 /* might be an immediate value */
1091 if (is_ia32_Immediate(pred)) {
1092 emit_ia32_Immediate(pred);
1095 reg = arch_get_irn_register_in(node, asm_reg->inout_pos);
1099 "Warning: no register assigned for %d asm op (%+F)\n",
1104 if (asm_reg->memory) {
1109 if (modifier != 0) {
1112 emit_8bit_register(reg);
1115 emit_8bit_register_high(reg);
1118 emit_16bit_register(reg);
1121 panic("Invalid asm op modifier");
1124 emit_register(reg, asm_reg->memory ? mode_Iu : asm_reg->mode);
1127 if (asm_reg->memory) {
1135 * Emits code for an ASM pseudo op.
1137 static void emit_ia32_Asm(const ir_node *node)
1139 const void *gen_attr = get_irn_generic_attr_const(node);
1140 const ia32_asm_attr_t *attr
1141 = CONST_CAST_IA32_ATTR(ia32_asm_attr_t, gen_attr);
1142 ident *asm_text = attr->asm_text;
1143 const char *s = get_id_str(asm_text);
1145 be_emit_cstring("#APP\n");
1146 be_emit_write_line();
1153 s = emit_asm_operand(node, s);
1159 be_emit_cstring("\n#NO_APP\n");
1160 be_emit_write_line();
1165 * Emit movsb/w instructions to make mov count divideable by 4
1167 static void emit_CopyB_prolog(unsigned size)
1170 ia32_emitf(NULL, "movsb");
1172 ia32_emitf(NULL, "movsw");
1176 * Emit rep movsd instruction for memcopy.
1178 static void emit_ia32_CopyB(const ir_node *node)
1180 unsigned size = get_ia32_copyb_size(node);
1182 emit_CopyB_prolog(size);
1183 ia32_emitf(node, "rep movsd");
1187 * Emits unrolled memcopy.
1189 static void emit_ia32_CopyB_i(const ir_node *node)
1191 unsigned size = get_ia32_copyb_size(node);
1193 emit_CopyB_prolog(size);
1197 ia32_emitf(NULL, "movsd");
1203 * Emit code for conversions (I, FP), (FP, I) and (FP, FP).
1205 static void emit_ia32_Conv_with_FP(const ir_node *node, const char* conv_f,
1208 ir_mode *ls_mode = get_ia32_ls_mode(node);
1209 int ls_bits = get_mode_size_bits(ls_mode);
1210 const char *conv = ls_bits == 32 ? conv_f : conv_d;
1212 ia32_emitf(node, "cvt%s %AS3, %D0", conv);
1215 static void emit_ia32_Conv_I2FP(const ir_node *node)
1217 emit_ia32_Conv_with_FP(node, "si2ss", "si2sd");
1220 static void emit_ia32_Conv_FP2I(const ir_node *node)
1222 emit_ia32_Conv_with_FP(node, "ss2si", "sd2si");
1225 static void emit_ia32_Conv_FP2FP(const ir_node *node)
1227 emit_ia32_Conv_with_FP(node, "sd2ss", "ss2sd");
1231 * Emits code to increase stack pointer.
1233 static void emit_be_IncSP(const ir_node *node)
1235 int offs = be_get_IncSP_offset(node);
1241 ia32_emitf(node, "subl $%u, %D0", offs);
1243 ia32_emitf(node, "addl $%u, %D0", -offs);
1248 * Emits code for Copy/CopyKeep.
1250 static void Copy_emitter(const ir_node *node, const ir_node *op)
1252 const arch_register_t *in = arch_get_irn_register(op);
1253 const arch_register_t *out = arch_get_irn_register(node);
1258 /* copies of vf nodes aren't real... */
1259 if (arch_register_get_class(in) == &ia32_reg_classes[CLASS_ia32_vfp])
1262 ia32_emitf(node, "movl %R, %R", in, out);
1265 static void emit_be_Copy(const ir_node *node)
1267 Copy_emitter(node, be_get_Copy_op(node));
1270 static void emit_be_CopyKeep(const ir_node *node)
1272 Copy_emitter(node, be_get_CopyKeep_op(node));
1276 * Emits code for exchange.
1278 static void emit_be_Perm(const ir_node *node)
1280 const arch_register_t *in0, *in1;
1281 const arch_register_class_t *cls0, *cls1;
1283 in0 = arch_get_irn_register(get_irn_n(node, 0));
1284 in1 = arch_get_irn_register(get_irn_n(node, 1));
1286 cls0 = arch_register_get_class(in0);
1287 cls1 = arch_register_get_class(in1);
1289 assert(cls0 == cls1 && "Register class mismatch at Perm");
1291 if (cls0 == &ia32_reg_classes[CLASS_ia32_gp]) {
1292 ia32_emitf(node, "xchg %R, %R", in1, in0);
1293 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_xmm]) {
1294 ia32_emitf(NULL, "xorpd %R, %R", in1, in0);
1295 ia32_emitf(NULL, "xorpd %R, %R", in0, in1);
1296 ia32_emitf(node, "xorpd %R, %R", in1, in0);
1297 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_vfp]) {
1299 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_st]) {
1302 panic("unexpected register class in be_Perm (%+F)", node);
1306 /* helper function for emit_ia32_Minus64Bit */
1307 static void emit_mov(const ir_node* node, const arch_register_t *src, const arch_register_t *dst)
1309 ia32_emitf(node, "movl %R, %R", src, dst);
1312 /* helper function for emit_ia32_Minus64Bit */
1313 static void emit_neg(const ir_node* node, const arch_register_t *reg)
1315 ia32_emitf(node, "negl %R", reg);
1318 /* helper function for emit_ia32_Minus64Bit */
1319 static void emit_sbb0(const ir_node* node, const arch_register_t *reg)
1321 ia32_emitf(node, "sbbl $0, %R", reg);
1324 /* helper function for emit_ia32_Minus64Bit */
1325 static void emit_sbb(const ir_node* node, const arch_register_t *src, const arch_register_t *dst)
1327 ia32_emitf(node, "sbbl %R, %R", src, dst);
1330 /* helper function for emit_ia32_Minus64Bit */
1331 static void emit_xchg(const ir_node* node, const arch_register_t *src, const arch_register_t *dst)
1333 ia32_emitf(node, "xchgl %R, %R", src, dst);
1336 /* helper function for emit_ia32_Minus64Bit */
1337 static void emit_zero(const ir_node* node, const arch_register_t *reg)
1339 ia32_emitf(node, "xorl %R, %R", reg, reg);
1342 static void emit_ia32_Minus64Bit(const ir_node *node)
1344 const arch_register_t *in_lo = arch_get_irn_register_in(node, 0);
1345 const arch_register_t *in_hi = arch_get_irn_register_in(node, 1);
1346 const arch_register_t *out_lo = arch_get_irn_register_out(node, 0);
1347 const arch_register_t *out_hi = arch_get_irn_register_out(node, 1);
1349 if (out_lo == in_lo) {
1350 if (out_hi != in_hi) {
1351 /* a -> a, b -> d */
1354 /* a -> a, b -> b */
1357 } else if (out_lo == in_hi) {
1358 if (out_hi == in_lo) {
1359 /* a -> b, b -> a */
1360 emit_xchg(node, in_lo, in_hi);
1363 /* a -> b, b -> d */
1364 emit_mov(node, in_hi, out_hi);
1365 emit_mov(node, in_lo, out_lo);
1369 if (out_hi == in_lo) {
1370 /* a -> c, b -> a */
1371 emit_mov(node, in_lo, out_lo);
1373 } else if (out_hi == in_hi) {
1374 /* a -> c, b -> b */
1375 emit_mov(node, in_lo, out_lo);
1378 /* a -> c, b -> d */
1379 emit_mov(node, in_lo, out_lo);
1385 emit_neg( node, out_hi);
1386 emit_neg( node, out_lo);
1387 emit_sbb0(node, out_hi);
1391 emit_zero(node, out_hi);
1392 emit_neg( node, out_lo);
1393 emit_sbb( node, in_hi, out_hi);
1396 static void emit_ia32_GetEIP(const ir_node *node)
1398 ia32_emitf(node, "call %s", pic_base_label);
1399 be_emit_irprintf("%s:\n", pic_base_label);
1400 be_emit_write_line();
1401 ia32_emitf(node, "popl %D0");
1404 static void emit_ia32_ClimbFrame(const ir_node *node)
1406 const ia32_climbframe_attr_t *attr = get_ia32_climbframe_attr_const(node);
1408 ia32_emitf(node, "movl %S0, %D0");
1409 ia32_emitf(node, "movl $%u, %S1", attr->count);
1410 be_gas_emit_block_name(node);
1411 be_emit_cstring(":\n");
1412 be_emit_write_line();
1413 ia32_emitf(node, "movl (%D0), %D0");
1414 ia32_emitf(node, "dec %S1");
1415 be_emit_cstring("\tjnz ");
1416 be_gas_emit_block_name(node);
1417 be_emit_finish_line_gas(node);
1420 static void emit_be_Return(const ir_node *node)
1422 unsigned pop = be_Return_get_pop(node);
1424 if (pop > 0 || be_Return_get_emit_pop(node)) {
1425 ia32_emitf(node, "ret $%u", pop);
1427 ia32_emitf(node, "ret");
1431 static void emit_Nothing(const ir_node *node)
1438 * Enters the emitter functions for handled nodes into the generic
1439 * pointer of an opcode.
1441 static void ia32_register_emitters(void)
1443 #define IA32_EMIT(a) op_ia32_##a->ops.generic = (op_func)emit_ia32_##a
1444 #define EMIT(a) op_##a->ops.generic = (op_func)emit_##a
1445 #define IGN(a) op_##a->ops.generic = (op_func)emit_Nothing
1446 #define BE_EMIT(a) op_be_##a->ops.generic = (op_func)emit_be_##a
1447 #define BE_IGN(a) op_be_##a->ops.generic = (op_func)emit_Nothing
1449 /* first clear the generic function pointer for all ops */
1450 ir_clear_opcodes_generic_func();
1452 /* register all emitter functions defined in spec */
1453 ia32_register_spec_emitters();
1455 /* other ia32 emitter functions */
1458 IA32_EMIT(Conv_FP2FP);
1459 IA32_EMIT(Conv_FP2I);
1460 IA32_EMIT(Conv_I2FP);
1467 IA32_EMIT(Minus64Bit);
1468 IA32_EMIT(SwitchJmp);
1469 IA32_EMIT(ClimbFrame);
1472 /* benode emitter */
1491 typedef void (*emit_func_ptr) (const ir_node *);
1494 * Assign and emit an exception label if the current instruction can fail.
1496 static void ia32_assign_exc_label(ir_node *node)
1498 /* assign a new ID to the instruction */
1499 set_ia32_exc_label_id(node, ++exc_label_id);
1501 ia32_emit_exc_label(node);
1503 be_emit_pad_comment();
1504 be_emit_cstring("/* exception to Block ");
1505 ia32_emit_cfop_target(node);
1506 be_emit_cstring(" */\n");
1507 be_emit_write_line();
1511 * Emits code for a node.
1513 static void ia32_emit_node(ir_node *node)
1515 ir_op *op = get_irn_op(node);
1517 DBG((dbg, LEVEL_1, "emitting code for %+F\n", node));
1519 if (is_ia32_irn(node)) {
1520 if (get_ia32_exc_label(node)) {
1521 /* emit the exception label of this instruction */
1522 ia32_assign_exc_label(node);
1524 if (mark_spill_reload) {
1525 if (is_ia32_is_spill(node)) {
1526 ia32_emitf(NULL, "xchg %ebx, %ebx /* spill mark */");
1528 if (is_ia32_is_reload(node)) {
1529 ia32_emitf(NULL, "xchg %edx, %edx /* reload mark */");
1531 if (is_ia32_is_remat(node)) {
1532 ia32_emitf(NULL, "xchg %ecx, %ecx /* remat mark */");
1536 if (op->ops.generic) {
1537 emit_func_ptr func = (emit_func_ptr) op->ops.generic;
1539 be_dwarf_location(get_irn_dbg_info(node));
1544 ir_fprintf(stderr, "Error: No emit handler for node %+F (%+G, graph %+F)\n", node, node, current_ir_graph);
1549 int sp_change = arch_get_sp_bias(node);
1550 if (sp_change != 0) {
1551 assert(sp_change != SP_BIAS_RESET);
1552 callframe_offset += sp_change;
1553 be_dwarf_callframe_offset(callframe_offset);
1559 * Emits gas alignment directives
1561 static void ia32_emit_alignment(unsigned align, unsigned skip)
1563 ia32_emitf(NULL, ".p2align %u,,%u", align, skip);
1567 * Emits gas alignment directives for Labels depended on cpu architecture.
1569 static void ia32_emit_align_label(void)
1571 unsigned align = ia32_cg_config.label_alignment;
1572 unsigned maximum_skip = ia32_cg_config.label_alignment_max_skip;
1573 ia32_emit_alignment(align, maximum_skip);
1577 * Test whether a block should be aligned.
1578 * For cpus in the P4/Athlon class it is useful to align jump labels to
1579 * 16 bytes. However we should only do that if the alignment nops before the
1580 * label aren't executed more often than we have jumps to the label.
1582 static int should_align_block(const ir_node *block)
1584 static const double DELTA = .0001;
1585 ir_node *prev = get_prev_block_sched(block);
1586 double prev_freq = 0; /**< execfreq of the fallthrough block */
1587 double jmp_freq = 0; /**< execfreq of all non-fallthrough blocks */
1591 if (ia32_cg_config.label_alignment_factor <= 0)
1594 block_freq = get_block_execfreq(block);
1595 if (block_freq < DELTA)
1598 n_cfgpreds = get_Block_n_cfgpreds(block);
1599 for (i = 0; i < n_cfgpreds; ++i) {
1600 const ir_node *pred = get_Block_cfgpred_block(block, i);
1601 double pred_freq = get_block_execfreq(pred);
1604 prev_freq += pred_freq;
1606 jmp_freq += pred_freq;
1610 if (prev_freq < DELTA && !(jmp_freq < DELTA))
1613 jmp_freq /= prev_freq;
1615 return jmp_freq > ia32_cg_config.label_alignment_factor;
1619 * Emit the block header for a block.
1621 * @param block the block
1622 * @param prev_block the previous block
1624 static void ia32_emit_block_header(ir_node *block)
1626 ir_graph *irg = current_ir_graph;
1627 int need_label = block_needs_label(block);
1629 if (block == get_irg_end_block(irg))
1632 if (ia32_cg_config.label_alignment > 0) {
1633 /* align the current block if:
1634 * a) if should be aligned due to its execution frequency
1635 * b) there is no fall-through here
1637 if (should_align_block(block)) {
1638 ia32_emit_align_label();
1640 /* if the predecessor block has no fall-through,
1641 we can always align the label. */
1643 int has_fallthrough = 0;
1645 for (i = get_Block_n_cfgpreds(block) - 1; i >= 0; --i) {
1646 ir_node *cfg_pred = get_Block_cfgpred(block, i);
1647 if (can_be_fallthrough(cfg_pred)) {
1648 has_fallthrough = 1;
1653 if (!has_fallthrough)
1654 ia32_emit_align_label();
1658 be_gas_begin_block(block, need_label);
1662 * Walks over the nodes in a block connected by scheduling edges
1663 * and emits code for each node.
1665 static void ia32_gen_block(ir_node *block)
1667 ia32_emit_block_header(block);
1670 ir_graph *irg = get_irn_irg(block);
1671 callframe_offset = 4; /* 4 bytes for the return address */
1672 /* ESP guessing, TODO perform a real ESP simulation */
1673 if (block != get_irg_start_block(irg)) {
1674 callframe_offset += frame_type_size;
1676 be_dwarf_callframe_offset(callframe_offset);
1679 /* emit the contents of the block */
1680 be_dwarf_location(get_irn_dbg_info(block));
1681 sched_foreach(block, node) {
1682 ia32_emit_node(node);
1686 typedef struct exc_entry {
1687 ir_node *exc_instr; /** The instruction that can issue an exception. */
1688 ir_node *block; /** The block to call then. */
1693 * Sets labels for control flow nodes (jump target).
1694 * Links control predecessors to there destination blocks.
1696 static void ia32_gen_labels(ir_node *block, void *data)
1698 exc_entry **exc_list = (exc_entry**)data;
1702 for (n = get_Block_n_cfgpreds(block) - 1; n >= 0; --n) {
1703 pred = get_Block_cfgpred(block, n);
1704 set_irn_link(pred, block);
1706 pred = skip_Proj(pred);
1707 if (is_ia32_irn(pred) && get_ia32_exc_label(pred)) {
1712 ARR_APP1(exc_entry, *exc_list, e);
1713 set_irn_link(pred, block);
1719 * Compare two exception_entries.
1721 static int cmp_exc_entry(const void *a, const void *b)
1723 const exc_entry *ea = (const exc_entry*)a;
1724 const exc_entry *eb = (const exc_entry*)b;
1726 if (get_ia32_exc_label_id(ea->exc_instr) < get_ia32_exc_label_id(eb->exc_instr))
1731 static parameter_dbg_info_t *construct_parameter_infos(ir_graph *irg)
1733 ir_entity *entity = get_irg_entity(irg);
1734 ir_type *type = get_entity_type(entity);
1735 size_t n_params = get_method_n_params(type);
1736 be_stack_layout_t *layout = be_get_irg_stack_layout(irg);
1737 ir_type *arg_type = layout->arg_type;
1738 size_t n_members = get_compound_n_members(arg_type);
1739 parameter_dbg_info_t *infos = XMALLOCNZ(parameter_dbg_info_t, n_params);
1742 for (i = 0; i < n_members; ++i) {
1743 ir_entity *member = get_compound_member(arg_type, i);
1745 if (!is_parameter_entity(member))
1747 param = get_entity_parameter_number(member);
1748 if (param == IR_VA_START_PARAMETER_NUMBER)
1750 assert(infos[param].entity == NULL && infos[param].reg == NULL);
1751 infos[param].reg = NULL;
1752 infos[param].entity = member;
1759 * Main driver. Emits the code for one routine.
1761 void ia32_gen_routine(ir_graph *irg)
1763 ir_entity *entity = get_irg_entity(irg);
1764 exc_entry *exc_list = NEW_ARR_F(exc_entry, 0);
1765 const arch_env_t *arch_env = be_get_irg_arch_env(irg);
1766 ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
1767 ir_node **blk_sched = irg_data->blk_sched;
1768 be_stack_layout_t *layout = be_get_irg_stack_layout(irg);
1769 parameter_dbg_info_t *infos;
1772 isa = (ia32_isa_t*) arch_env;
1773 do_pic = be_options.pic;
1775 be_gas_elf_type_char = '@';
1777 ia32_register_emitters();
1779 get_unique_label(pic_base_label, sizeof(pic_base_label), "PIC_BASE");
1781 infos = construct_parameter_infos(irg);
1782 be_gas_emit_function_prolog(entity, ia32_cg_config.function_alignment,
1786 sp_relative = layout->sp_relative;
1787 if (layout->sp_relative) {
1788 ir_type *frame_type = get_irg_frame_type(irg);
1789 frame_type_size = get_type_size_bytes(frame_type);
1790 be_dwarf_callframe_register(&ia32_registers[REG_ESP]);
1792 /* well not entirely correct here, we should emit this after the
1793 * "movl esp, ebp" */
1794 be_dwarf_callframe_register(&ia32_registers[REG_EBP]);
1795 /* TODO: do not hardcode the following */
1796 be_dwarf_callframe_offset(8);
1797 be_dwarf_callframe_spilloffset(&ia32_registers[REG_EBP], -8);
1800 /* we use links to point to target blocks */
1801 ir_reserve_resources(irg, IR_RESOURCE_IRN_LINK);
1802 irg_block_walk_graph(irg, ia32_gen_labels, NULL, &exc_list);
1804 /* initialize next block links */
1805 n = ARR_LEN(blk_sched);
1806 for (i = 0; i < n; ++i) {
1807 ir_node *block = blk_sched[i];
1808 ir_node *prev = i > 0 ? blk_sched[i-1] : NULL;
1810 set_irn_link(block, prev);
1813 for (i = 0; i < n; ++i) {
1814 ir_node *block = blk_sched[i];
1816 ia32_gen_block(block);
1819 be_gas_emit_function_epilog(entity);
1821 ir_free_resources(irg, IR_RESOURCE_IRN_LINK);
1823 /* Sort the exception table using the exception label id's.
1824 Those are ascending with ascending addresses. */
1825 qsort(exc_list, ARR_LEN(exc_list), sizeof(exc_list[0]), cmp_exc_entry);
1829 for (e = 0; e < ARR_LEN(exc_list); ++e) {
1830 be_emit_cstring("\t.long ");
1831 ia32_emit_exc_label(exc_list[e].exc_instr);
1833 be_emit_cstring("\t.long ");
1834 be_gas_emit_block_name(exc_list[e].block);
1838 DEL_ARR_F(exc_list);
1841 static const lc_opt_table_entry_t ia32_emitter_options[] = {
1842 LC_OPT_ENT_BOOL("mark_spill_reload", "mark spills and reloads with ud opcodes", &mark_spill_reload),
1846 /* ==== Experimental binary emitter ==== */
1848 static unsigned char reg_gp_map[N_ia32_gp_REGS];
1849 //static unsigned char reg_mmx_map[N_ia32_mmx_REGS];
1850 //static unsigned char reg_sse_map[N_ia32_xmm_REGS];
1852 static void build_reg_map(void)
1854 reg_gp_map[REG_GP_EAX] = 0x0;
1855 reg_gp_map[REG_GP_ECX] = 0x1;
1856 reg_gp_map[REG_GP_EDX] = 0x2;
1857 reg_gp_map[REG_GP_EBX] = 0x3;
1858 reg_gp_map[REG_GP_ESP] = 0x4;
1859 reg_gp_map[REG_GP_EBP] = 0x5;
1860 reg_gp_map[REG_GP_ESI] = 0x6;
1861 reg_gp_map[REG_GP_EDI] = 0x7;
1864 /** Returns the encoding for a pnc field. */
1865 static unsigned char pnc2cc(ia32_condition_code_t cc)
1870 /** Sign extension bit values for binops */
1872 UNSIGNED_IMM = 0, /**< unsigned immediate */
1873 SIGNEXT_IMM = 2, /**< sign extended immediate */
1876 /** The mod encoding of the ModR/M */
1878 MOD_IND = 0x00, /**< [reg1] */
1879 MOD_IND_BYTE_OFS = 0x40, /**< [reg1 + byte ofs] */
1880 MOD_IND_WORD_OFS = 0x80, /**< [reg1 + word ofs] */
1881 MOD_REG = 0xC0 /**< reg1 */
1884 /** create R/M encoding for ModR/M */
1885 #define ENC_RM(x) (x)
1886 /** create REG encoding for ModR/M */
1887 #define ENC_REG(x) ((x) << 3)
1889 /** create encoding for a SIB byte */
1890 #define ENC_SIB(scale, index, base) ((scale) << 6 | (index) << 3 | (base))
1892 /* Node: The following routines are supposed to append bytes, words, dwords
1893 to the output stream.
1894 Currently the implementation is stupid in that it still creates output
1895 for an "assembler" in the form of .byte, .long
1896 We will change this when enough infrastructure is there to create complete
1897 machine code in memory/object files */
1899 static void bemit8(const unsigned char byte)
1901 be_emit_irprintf("\t.byte 0x%x\n", byte);
1902 be_emit_write_line();
1905 static void bemit16(const unsigned short u16)
1907 be_emit_irprintf("\t.word 0x%x\n", u16);
1908 be_emit_write_line();
1911 static void bemit32(const unsigned u32)
1913 be_emit_irprintf("\t.long 0x%x\n", u32);
1914 be_emit_write_line();
1918 * Emit address of an entity. If @p is_relative is true then a relative
1919 * offset from behind the address to the entity is created.
1921 static void bemit_entity(ir_entity *entity, bool entity_sign, int offset,
1924 if (entity == NULL) {
1929 /* the final version should remember the position in the bytestream
1930 and patch it with the correct address at linktime... */
1931 be_emit_cstring("\t.long ");
1934 be_gas_emit_entity(entity);
1936 if (get_entity_owner(entity) == get_tls_type()) {
1937 if (!entity_has_definition(entity)) {
1938 be_emit_cstring("@INDNTPOFF");
1940 be_emit_cstring("@NTPOFF");
1945 be_emit_cstring("-.");
1950 be_emit_irprintf("%+d", offset);
1953 be_emit_write_line();
1956 static void bemit_jmp_destination(const ir_node *dest_block)
1958 be_emit_cstring("\t.long ");
1959 be_gas_emit_block_name(dest_block);
1960 be_emit_cstring(" - . - 4\n");
1961 be_emit_write_line();
1964 /* end emit routines, all emitters following here should only use the functions
1967 typedef enum reg_modifier {
1972 /** Create a ModR/M byte for src1,src2 registers */
1973 static void bemit_modrr(const arch_register_t *src1,
1974 const arch_register_t *src2)
1976 unsigned char modrm = MOD_REG;
1977 modrm |= ENC_RM(reg_gp_map[src1->index]);
1978 modrm |= ENC_REG(reg_gp_map[src2->index]);
1982 /** Create a ModR/M8 byte for src1,src2 registers */
1983 static void bemit_modrr8(reg_modifier_t high_part1, const arch_register_t *src1,
1984 reg_modifier_t high_part2, const arch_register_t *src2)
1986 unsigned char modrm = MOD_REG;
1987 modrm |= ENC_RM(reg_gp_map[src1->index] + (high_part1 == REG_HIGH ? 4 : 0));
1988 modrm |= ENC_REG(reg_gp_map[src2->index] + (high_part2 == REG_HIGH ? 4 : 0));
1992 /** Create a ModR/M byte for one register and extension */
1993 static void bemit_modru(const arch_register_t *reg, unsigned ext)
1995 unsigned char modrm = MOD_REG;
1997 modrm |= ENC_RM(reg_gp_map[reg->index]);
1998 modrm |= ENC_REG(ext);
2002 /** Create a ModR/M8 byte for one register */
2003 static void bemit_modrm8(reg_modifier_t high_part, const arch_register_t *reg)
2005 unsigned char modrm = MOD_REG;
2006 assert(reg_gp_map[reg->index] < 4);
2007 modrm |= ENC_RM(reg_gp_map[reg->index] + (high_part == REG_HIGH ? 4 : 0));
2013 * Calculate the size of an signed immediate in bytes.
2015 * @param offset an offset
2017 static unsigned get_signed_imm_size(int offset)
2019 if (-128 <= offset && offset < 128) {
2021 } else if (-32768 <= offset && offset < 32768) {
2029 * Emit an address mode.
2031 * @param reg content of the reg field: either a register index or an opcode extension
2032 * @param node the node
2034 static void bemit_mod_am(unsigned reg, const ir_node *node)
2036 ir_entity *ent = get_ia32_am_sc(node);
2037 int offs = get_ia32_am_offs_int(node);
2038 ir_node *base = get_irn_n(node, n_ia32_base);
2039 int has_base = !is_ia32_NoReg_GP(base);
2040 ir_node *idx = get_irn_n(node, n_ia32_index);
2041 int has_index = !is_ia32_NoReg_GP(idx);
2044 unsigned emitoffs = 0;
2045 bool emitsib = false;
2048 /* set the mod part depending on displacement */
2050 modrm |= MOD_IND_WORD_OFS;
2052 } else if (offs == 0) {
2055 } else if (-128 <= offs && offs < 128) {
2056 modrm |= MOD_IND_BYTE_OFS;
2059 modrm |= MOD_IND_WORD_OFS;
2064 const arch_register_t *base_reg = arch_get_irn_register(base);
2065 base_enc = reg_gp_map[base_reg->index];
2067 /* Use the EBP encoding + MOD_IND if NO base register. There is
2068 * always a 32bit offset present in this case. */
2074 /* Determine if we need a SIB byte. */
2076 const arch_register_t *reg_index = arch_get_irn_register(idx);
2077 int scale = get_ia32_am_scale(node);
2079 /* R/M set to ESP means SIB in 32bit mode. */
2080 modrm |= ENC_RM(0x04);
2081 sib = ENC_SIB(scale, reg_gp_map[reg_index->index], base_enc);
2083 } else if (base_enc == 0x04) {
2084 /* for the above reason we are forced to emit a SIB when base is ESP.
2085 * Only the base is used, index must be ESP too, which means no index.
2087 modrm |= ENC_RM(0x04);
2088 sib = ENC_SIB(0, 0x04, 0x04);
2091 modrm |= ENC_RM(base_enc);
2094 /* We are forced to emit an 8bit offset as EBP base without offset is a
2095 * special case for SIB without base register. */
2096 if (base_enc == 0x05 && emitoffs == 0) {
2097 modrm |= MOD_IND_BYTE_OFS;
2101 modrm |= ENC_REG(reg);
2107 /* emit displacement */
2108 if (emitoffs == 8) {
2109 bemit8((unsigned) offs);
2110 } else if (emitoffs == 32) {
2111 bemit_entity(ent, is_ia32_am_sc_sign(node), offs, false);
2116 * Emit a binop with a immediate operand.
2118 * @param node the node to emit
2119 * @param opcode_eax the opcode for the op eax, imm variant
2120 * @param opcode the opcode for the reg, imm variant
2121 * @param ruval the opcode extension for opcode
2123 static void bemit_binop_with_imm(
2124 const ir_node *node,
2125 unsigned char opcode_ax,
2126 unsigned char opcode, unsigned char ruval)
2128 /* Use in-reg, because some instructions (cmp, test) have no out-reg. */
2129 const ir_node *op = get_irn_n(node, n_ia32_binary_right);
2130 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(op);
2133 /* Some instructions (test) have no short form with 32bit value + 8bit
2135 if (attr->symconst != NULL || opcode & SIGNEXT_IMM) {
2138 /* check for sign extension */
2139 size = get_signed_imm_size(attr->offset);
2144 bemit8(opcode | SIGNEXT_IMM);
2145 /* cmp has this special mode */
2146 if (get_ia32_op_type(node) == ia32_AddrModeS) {
2147 bemit_mod_am(ruval, node);
2149 const arch_register_t *reg = arch_get_irn_register_in(node, n_ia32_binary_left);
2150 bemit_modru(reg, ruval);
2152 bemit8((unsigned char)attr->offset);
2156 /* check for eax variant: this variant is shorter for 32bit immediates only */
2157 if (get_ia32_op_type(node) == ia32_AddrModeS) {
2159 bemit_mod_am(ruval, node);
2161 const arch_register_t *reg = arch_get_irn_register_in(node, n_ia32_binary_left);
2162 if (reg->index == REG_GP_EAX) {
2166 bemit_modru(reg, ruval);
2169 bemit_entity(attr->symconst, attr->sc_sign, attr->offset, false);
2172 panic("invalid imm size?!?");
2178 static void bemit_binop_2(const ir_node *node, unsigned code)
2180 const arch_register_t *out = arch_get_irn_register_in(node, n_ia32_binary_left);
2182 if (get_ia32_op_type(node) == ia32_Normal) {
2183 const arch_register_t *op2 = arch_get_irn_register_in(node, n_ia32_binary_right);
2184 bemit_modrr(op2, out);
2186 bemit_mod_am(reg_gp_map[out->index], node);
2193 static void bemit_binop(const ir_node *node, const unsigned char opcodes[4])
2195 ir_node *right = get_irn_n(node, n_ia32_binary_right);
2196 if (is_ia32_Immediate(right)) {
2197 bemit_binop_with_imm(node, opcodes[1], opcodes[2], opcodes[3]);
2199 bemit_binop_2(node, opcodes[0]);
2206 static void bemit_unop(const ir_node *node, unsigned char code, unsigned char ext, int input)
2209 if (get_ia32_op_type(node) == ia32_Normal) {
2210 const arch_register_t *in = arch_get_irn_register_in(node, input);
2211 bemit_modru(in, ext);
2213 bemit_mod_am(ext, node);
2217 static void bemit_unop_reg(const ir_node *node, unsigned char code, int input)
2219 const arch_register_t *out = arch_get_irn_register_out(node, 0);
2220 bemit_unop(node, code, reg_gp_map[out->index], input);
2223 static void bemit_unop_mem(const ir_node *node, unsigned char code, unsigned char ext)
2225 unsigned size = get_mode_size_bits(get_ia32_ls_mode(node));
2228 bemit8(size == 8 ? code : code + 1);
2229 bemit_mod_am(ext, node);
2232 static void bemit_0f_unop_reg(ir_node const *const node, unsigned char const code, int const input)
2235 bemit_unop_reg(node, code, input);
2238 static void bemit_immediate(const ir_node *node, bool relative)
2240 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(node);
2241 bemit_entity(attr->symconst, attr->sc_sign, attr->offset, relative);
2244 static void bemit_copy(const ir_node *copy)
2246 const arch_register_t *in = arch_get_irn_register_in(copy, 0);
2247 const arch_register_t *out = arch_get_irn_register_out(copy, 0);
2251 /* copies of vf nodes aren't real... */
2252 if (arch_register_get_class(in) == &ia32_reg_classes[CLASS_ia32_vfp])
2255 assert(arch_register_get_class(in) == &ia32_reg_classes[CLASS_ia32_gp]);
2257 bemit_modrr(in, out);
2260 static void bemit_perm(const ir_node *node)
2262 const arch_register_t *in0 = arch_get_irn_register(get_irn_n(node, 0));
2263 const arch_register_t *in1 = arch_get_irn_register(get_irn_n(node, 1));
2264 const arch_register_class_t *cls0 = arch_register_get_class(in0);
2266 assert(cls0 == arch_register_get_class(in1) && "Register class mismatch at Perm");
2268 if (cls0 == &ia32_reg_classes[CLASS_ia32_gp]) {
2269 if (in0->index == REG_GP_EAX) {
2270 bemit8(0x90 + reg_gp_map[in1->index]);
2271 } else if (in1->index == REG_GP_EAX) {
2272 bemit8(0x90 + reg_gp_map[in0->index]);
2275 bemit_modrr(in0, in1);
2277 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_xmm]) {
2278 panic("unimplemented"); // TODO implement
2279 //ia32_emitf(NULL, "xorpd %R, %R", in1, in0);
2280 //ia32_emitf(NULL, "xorpd %R, %R", in0, in1);
2281 //ia32_emitf(node, "xorpd %R, %R", in1, in0);
2282 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_vfp]) {
2284 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_st]) {
2287 panic("unexpected register class in be_Perm (%+F)", node);
2291 static void bemit_xor0(const ir_node *node)
2293 const arch_register_t *out = arch_get_irn_register_out(node, 0);
2295 bemit_modrr(out, out);
2298 static void bemit_mov_const(const ir_node *node)
2300 const arch_register_t *out = arch_get_irn_register_out(node, 0);
2301 bemit8(0xB8 + reg_gp_map[out->index]);
2302 bemit_immediate(node, false);
2306 * Creates a function for a Binop with 3 possible encodings.
2308 #define BINOP(op, op0, op1, op2, op2_ext) \
2309 static void bemit_ ## op(const ir_node *node) { \
2310 static const unsigned char op ## _codes[] = {op0, op1, op2, op2_ext}; \
2311 bemit_binop(node, op ## _codes); \
2314 /* insn def eax,imm imm */
2315 BINOP(add, 0x03, 0x05, 0x81, 0)
2316 BINOP(or, 0x0B, 0x0D, 0x81, 1)
2317 BINOP(adc, 0x13, 0x15, 0x81, 2)
2318 BINOP(sbb, 0x1B, 0x1D, 0x81, 3)
2319 BINOP(and, 0x23, 0x25, 0x81, 4)
2320 BINOP(sub, 0x2B, 0x2D, 0x81, 5)
2321 BINOP(xor, 0x33, 0x35, 0x81, 6)
2322 BINOP(test, 0x85, 0xA9, 0xF7, 0)
2324 #define BINOPMEM(op, ext) \
2325 static void bemit_##op(const ir_node *node) \
2328 unsigned size = get_mode_size_bits(get_ia32_ls_mode(node)); \
2331 val = get_irn_n(node, n_ia32_unary_op); \
2332 if (is_ia32_Immediate(val)) { \
2333 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(val); \
2334 int offset = attr->offset; \
2335 if (attr->symconst == NULL && get_signed_imm_size(offset) == 1) { \
2337 bemit_mod_am(ext, node); \
2341 bemit_mod_am(ext, node); \
2345 bemit_entity(attr->symconst, attr->sc_sign, offset, false); \
2349 bemit8(ext << 3 | 1); \
2350 bemit_mod_am(reg_gp_map[arch_get_irn_register(val)->index], node); \
2354 static void bemit_##op##8bit(const ir_node *node) \
2356 ir_node *val = get_irn_n(node, n_ia32_unary_op); \
2357 if (is_ia32_Immediate(val)) { \
2359 bemit_mod_am(ext, node); \
2360 bemit8(get_ia32_immediate_attr_const(val)->offset); \
2363 bemit_mod_am(reg_gp_map[arch_get_irn_register(val)->index], node); \
2375 * Creates a function for an Unop with code /ext encoding.
2377 #define UNOP(op, code, ext, input) \
2378 static void bemit_ ## op(const ir_node *node) { \
2379 bemit_unop(node, code, ext, input); \
2382 UNOP(not, 0xF7, 2, n_ia32_Not_val)
2383 UNOP(neg, 0xF7, 3, n_ia32_Neg_val)
2384 UNOP(mul, 0xF7, 4, n_ia32_Mul_right)
2385 UNOP(imul1op, 0xF7, 5, n_ia32_IMul1OP_right)
2386 UNOP(div, 0xF7, 6, n_ia32_Div_divisor)
2387 UNOP(idiv, 0xF7, 7, n_ia32_IDiv_divisor)
2389 /* TODO: am support for IJmp */
2390 UNOP(ijmp, 0xFF, 4, n_ia32_IJmp_target)
2392 #define SHIFT(op, ext) \
2393 static void bemit_##op(const ir_node *node) \
2395 const arch_register_t *out = arch_get_irn_register_out(node, 0); \
2396 ir_node *count = get_irn_n(node, 1); \
2397 if (is_ia32_Immediate(count)) { \
2398 int offset = get_ia32_immediate_attr_const(count)->offset; \
2399 if (offset == 1) { \
2401 bemit_modru(out, ext); \
2404 bemit_modru(out, ext); \
2409 bemit_modru(out, ext); \
2413 static void bemit_##op##mem(const ir_node *node) \
2416 unsigned size = get_mode_size_bits(get_ia32_ls_mode(node)); \
2419 count = get_irn_n(node, 1); \
2420 if (is_ia32_Immediate(count)) { \
2421 int offset = get_ia32_immediate_attr_const(count)->offset; \
2422 if (offset == 1) { \
2423 bemit8(size == 8 ? 0xD0 : 0xD1); \
2424 bemit_mod_am(ext, node); \
2426 bemit8(size == 8 ? 0xC0 : 0xC1); \
2427 bemit_mod_am(ext, node); \
2431 bemit8(size == 8 ? 0xD2 : 0xD3); \
2432 bemit_mod_am(ext, node); \
2442 static void bemit_shld(const ir_node *node)
2444 const arch_register_t *in = arch_get_irn_register_in(node, n_ia32_ShlD_val_low);
2445 const arch_register_t *out = arch_get_irn_register_out(node, pn_ia32_ShlD_res);
2446 ir_node *count = get_irn_n(node, n_ia32_ShlD_count);
2448 if (is_ia32_Immediate(count)) {
2450 bemit_modrr(out, in);
2451 bemit8(get_ia32_immediate_attr_const(count)->offset);
2454 bemit_modrr(out, in);
2458 static void bemit_shrd(const ir_node *node)
2460 const arch_register_t *in = arch_get_irn_register_in(node, n_ia32_ShrD_val_low);
2461 const arch_register_t *out = arch_get_irn_register_out(node, pn_ia32_ShrD_res);
2462 ir_node *count = get_irn_n(node, n_ia32_ShrD_count);
2464 if (is_ia32_Immediate(count)) {
2466 bemit_modrr(out, in);
2467 bemit8(get_ia32_immediate_attr_const(count)->offset);
2470 bemit_modrr(out, in);
2474 static void bemit_sbb0(ir_node const *const node)
2476 arch_register_t const *const out = arch_get_irn_register_out(node, pn_ia32_Sbb0_res);
2477 unsigned char const reg = reg_gp_map[out->index];
2479 bemit8(MOD_REG | ENC_REG(reg) | ENC_RM(reg));
2483 * binary emitter for setcc.
2485 static void bemit_setcc(const ir_node *node)
2487 const arch_register_t *dreg = arch_get_irn_register_out(node, pn_ia32_Setcc_res);
2489 ia32_condition_code_t cc = get_ia32_condcode(node);
2490 cc = determine_final_cc(node, n_ia32_Setcc_eflags, cc);
2491 if (cc & ia32_cc_float_parity_cases) {
2492 if (cc & ia32_cc_negated) {
2495 bemit8(0x90 | pnc2cc(cc));
2496 bemit_modrm8(REG_LOW, dreg);
2501 bemit_modrm8(REG_HIGH, dreg);
2503 /* orb %>dreg, %<dreg */
2505 bemit_modrr8(REG_LOW, dreg, REG_HIGH, dreg);
2509 bemit8(0x90 | pnc2cc(cc));
2510 bemit_modrm8(REG_LOW, dreg);
2515 bemit_modrm8(REG_HIGH, dreg);
2517 /* andb %>dreg, %<dreg */
2519 bemit_modrr8(REG_LOW, dreg, REG_HIGH, dreg);
2524 bemit8(0x90 | pnc2cc(cc));
2525 bemit_modrm8(REG_LOW, dreg);
2529 static void bemit_bsf(ir_node const *const node)
2531 bemit_0f_unop_reg(node, 0xBC, n_ia32_Bsf_operand);
2534 static void bemit_bsr(ir_node const *const node)
2536 bemit_0f_unop_reg(node, 0xBD, n_ia32_Bsr_operand);
2539 static void bemit_bswap(ir_node const *const node)
2542 bemit_modru(arch_get_irn_register_out(node, pn_ia32_Bswap_res), 1);
2545 static void bemit_bt(ir_node const *const node)
2548 arch_register_t const *const lreg = arch_get_irn_register_in(node, n_ia32_Bt_left);
2549 ir_node const *const right = get_irn_n(node, n_ia32_Bt_right);
2550 if (is_ia32_Immediate(right)) {
2551 ia32_immediate_attr_t const *const attr = get_ia32_immediate_attr_const(right);
2552 int const offset = attr->offset;
2553 assert(!attr->symconst);
2554 assert(get_signed_imm_size(offset) == 1);
2556 bemit_modru(lreg, 4);
2560 bemit_modrr(lreg, arch_get_irn_register(right));
2564 static void bemit_cmovcc(const ir_node *node)
2566 const ia32_attr_t *attr = get_ia32_attr_const(node);
2567 int ins_permuted = attr->data.ins_permuted;
2568 const arch_register_t *out = arch_get_irn_register_out(node, pn_ia32_res);
2569 ia32_condition_code_t cc = get_ia32_condcode(node);
2570 const arch_register_t *in_true;
2571 const arch_register_t *in_false;
2573 cc = determine_final_cc(node, n_ia32_CMovcc_eflags, cc);
2575 in_true = arch_get_irn_register(get_irn_n(node, n_ia32_CMovcc_val_true));
2576 in_false = arch_get_irn_register(get_irn_n(node, n_ia32_CMovcc_val_false));
2578 /* should be same constraint fullfilled? */
2579 if (out == in_false) {
2580 /* yes -> nothing to do */
2581 } else if (out == in_true) {
2582 assert(get_ia32_op_type(node) == ia32_Normal);
2583 ins_permuted = !ins_permuted;
2587 bemit8(0x8B); // mov %in_false, %out
2588 bemit_modrr(in_false, out);
2592 cc = ia32_negate_condition_code(cc);
2594 if (cc & ia32_cc_float_parity_cases)
2595 panic("cmov can't handle parity float cases");
2598 bemit8(0x40 | pnc2cc(cc));
2599 if (get_ia32_op_type(node) == ia32_Normal) {
2600 bemit_modrr(in_true, out);
2602 bemit_mod_am(reg_gp_map[out->index], node);
2606 static void bemit_cmp(const ir_node *node)
2608 unsigned ls_size = get_mode_size_bits(get_ia32_ls_mode(node));
2614 right = get_irn_n(node, n_ia32_binary_right);
2615 if (is_ia32_Immediate(right)) {
2616 /* Use in-reg, because some instructions (cmp, test) have no out-reg. */
2617 const ir_node *op = get_irn_n(node, n_ia32_binary_right);
2618 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(op);
2621 if (attr->symconst != NULL) {
2624 /* check for sign extension */
2625 size = get_signed_imm_size(attr->offset);
2630 bemit8(0x81 | SIGNEXT_IMM);
2631 /* cmp has this special mode */
2632 if (get_ia32_op_type(node) == ia32_AddrModeS) {
2633 bemit_mod_am(7, node);
2635 const arch_register_t *reg = arch_get_irn_register_in(node, n_ia32_binary_left);
2636 bemit_modru(reg, 7);
2638 bemit8((unsigned char)attr->offset);
2642 /* check for eax variant: this variant is shorter for 32bit immediates only */
2643 if (get_ia32_op_type(node) == ia32_AddrModeS) {
2645 bemit_mod_am(7, node);
2647 const arch_register_t *reg = arch_get_irn_register_in(node, n_ia32_binary_left);
2648 if (reg->index == REG_GP_EAX) {
2652 bemit_modru(reg, 7);
2655 if (ls_size == 16) {
2656 bemit16(attr->offset);
2658 bemit_entity(attr->symconst, attr->sc_sign, attr->offset, false);
2662 panic("invalid imm size?!?");
2664 const arch_register_t *out = arch_get_irn_register_in(node, n_ia32_binary_left);
2666 if (get_ia32_op_type(node) == ia32_Normal) {
2667 const arch_register_t *op2 = arch_get_irn_register_in(node, n_ia32_binary_right);
2668 bemit_modrr(op2, out);
2670 bemit_mod_am(reg_gp_map[out->index], node);
2675 static void bemit_cmp8bit(const ir_node *node)
2677 ir_node *right = get_irn_n(node, n_ia32_binary_right);
2678 if (is_ia32_Immediate(right)) {
2679 if (get_ia32_op_type(node) == ia32_Normal) {
2680 const arch_register_t *out = arch_get_irn_register_in(node, n_ia32_Cmp_left);
2681 if (out->index == REG_GP_EAX) {
2685 bemit_modru(out, 7);
2689 bemit_mod_am(7, node);
2691 bemit8(get_ia32_immediate_attr_const(right)->offset);
2693 const arch_register_t *out = arch_get_irn_register_in(node, n_ia32_Cmp_left);
2695 if (get_ia32_op_type(node) == ia32_Normal) {
2696 const arch_register_t *in = arch_get_irn_register_in(node, n_ia32_Cmp_right);
2697 bemit_modrr(out, in);
2699 bemit_mod_am(reg_gp_map[out->index], node);
2704 static void bemit_test8bit(const ir_node *node)
2706 ir_node *right = get_irn_n(node, n_ia32_Test8Bit_right);
2707 if (is_ia32_Immediate(right)) {
2708 if (get_ia32_op_type(node) == ia32_Normal) {
2709 const arch_register_t *out = arch_get_irn_register_in(node, n_ia32_Test8Bit_left);
2710 if (out->index == REG_GP_EAX) {
2714 bemit_modru(out, 0);
2718 bemit_mod_am(0, node);
2720 bemit8(get_ia32_immediate_attr_const(right)->offset);
2722 const arch_register_t *out = arch_get_irn_register_in(node, n_ia32_Test8Bit_left);
2724 if (get_ia32_op_type(node) == ia32_Normal) {
2725 const arch_register_t *in = arch_get_irn_register_in(node, n_ia32_Test8Bit_right);
2726 bemit_modrr(out, in);
2728 bemit_mod_am(reg_gp_map[out->index], node);
2733 static void bemit_imul(const ir_node *node)
2735 ir_node *right = get_irn_n(node, n_ia32_IMul_right);
2736 /* Do we need the immediate form? */
2737 if (is_ia32_Immediate(right)) {
2738 int imm = get_ia32_immediate_attr_const(right)->offset;
2739 if (get_signed_imm_size(imm) == 1) {
2740 bemit_unop_reg(node, 0x6B, n_ia32_IMul_left);
2743 bemit_unop_reg(node, 0x69, n_ia32_IMul_left);
2747 bemit_0f_unop_reg(node, 0xAF, n_ia32_IMul_right);
2751 static void bemit_dec(const ir_node *node)
2753 const arch_register_t *out = arch_get_irn_register_out(node, pn_ia32_Dec_res);
2754 bemit8(0x48 + reg_gp_map[out->index]);
2757 static void bemit_inc(const ir_node *node)
2759 const arch_register_t *out = arch_get_irn_register_out(node, pn_ia32_Inc_res);
2760 bemit8(0x40 + reg_gp_map[out->index]);
2763 #define UNOPMEM(op, code, ext) \
2764 static void bemit_##op(const ir_node *node) \
2766 bemit_unop_mem(node, code, ext); \
2769 UNOPMEM(notmem, 0xF6, 2)
2770 UNOPMEM(negmem, 0xF6, 3)
2771 UNOPMEM(incmem, 0xFE, 0)
2772 UNOPMEM(decmem, 0xFE, 1)
2774 static void bemit_ldtls(const ir_node *node)
2776 const arch_register_t *out = arch_get_irn_register_out(node, 0);
2778 bemit8(0x65); // gs:
2779 if (out->index == REG_GP_EAX) {
2780 bemit8(0xA1); // movl 0, %eax
2782 bemit8(0x8B); // movl 0, %reg
2783 bemit8(MOD_IND | ENC_REG(reg_gp_map[out->index]) | ENC_RM(0x05));
2791 static void bemit_lea(const ir_node *node)
2793 const arch_register_t *out = arch_get_irn_register_out(node, 0);
2795 bemit_mod_am(reg_gp_map[out->index], node);
2798 /* helper function for bemit_minus64bit */
2799 static void bemit_helper_mov(const arch_register_t *src, const arch_register_t *dst)
2801 bemit8(0x8B); // movl %src, %dst
2802 bemit_modrr(src, dst);
2805 /* helper function for bemit_minus64bit */
2806 static void bemit_helper_neg(const arch_register_t *reg)
2808 bemit8(0xF7); // negl %reg
2809 bemit_modru(reg, 3);
2812 /* helper function for bemit_minus64bit */
2813 static void bemit_helper_sbb0(const arch_register_t *reg)
2815 bemit8(0x83); // sbbl $0, %reg
2816 bemit_modru(reg, 3);
2820 /* helper function for bemit_minus64bit */
2821 static void bemit_helper_sbb(const arch_register_t *src, const arch_register_t *dst)
2823 bemit8(0x1B); // sbbl %src, %dst
2824 bemit_modrr(src, dst);
2827 /* helper function for bemit_minus64bit */
2828 static void bemit_helper_xchg(const arch_register_t *src, const arch_register_t *dst)
2830 if (src->index == REG_GP_EAX) {
2831 bemit8(0x90 + reg_gp_map[dst->index]); // xchgl %eax, %dst
2832 } else if (dst->index == REG_GP_EAX) {
2833 bemit8(0x90 + reg_gp_map[src->index]); // xchgl %src, %eax
2835 bemit8(0x87); // xchgl %src, %dst
2836 bemit_modrr(src, dst);
2840 /* helper function for bemit_minus64bit */
2841 static void bemit_helper_zero(const arch_register_t *reg)
2843 bemit8(0x33); // xorl %reg, %reg
2844 bemit_modrr(reg, reg);
2847 static void bemit_minus64bit(const ir_node *node)
2849 const arch_register_t *in_lo = arch_get_irn_register_in(node, 0);
2850 const arch_register_t *in_hi = arch_get_irn_register_in(node, 1);
2851 const arch_register_t *out_lo = arch_get_irn_register_out(node, 0);
2852 const arch_register_t *out_hi = arch_get_irn_register_out(node, 1);
2854 if (out_lo == in_lo) {
2855 if (out_hi != in_hi) {
2856 /* a -> a, b -> d */
2859 /* a -> a, b -> b */
2862 } else if (out_lo == in_hi) {
2863 if (out_hi == in_lo) {
2864 /* a -> b, b -> a */
2865 bemit_helper_xchg(in_lo, in_hi);
2868 /* a -> b, b -> d */
2869 bemit_helper_mov(in_hi, out_hi);
2870 bemit_helper_mov(in_lo, out_lo);
2874 if (out_hi == in_lo) {
2875 /* a -> c, b -> a */
2876 bemit_helper_mov(in_lo, out_lo);
2878 } else if (out_hi == in_hi) {
2879 /* a -> c, b -> b */
2880 bemit_helper_mov(in_lo, out_lo);
2883 /* a -> c, b -> d */
2884 bemit_helper_mov(in_lo, out_lo);
2890 bemit_helper_neg( out_hi);
2891 bemit_helper_neg( out_lo);
2892 bemit_helper_sbb0(out_hi);
2896 bemit_helper_zero(out_hi);
2897 bemit_helper_neg( out_lo);
2898 bemit_helper_sbb( in_hi, out_hi);
2902 * Emit a single opcode.
2904 #define EMIT_SINGLEOP(op, code) \
2905 static void bemit_ ## op(const ir_node *node) { \
2910 //EMIT_SINGLEOP(daa, 0x27)
2911 //EMIT_SINGLEOP(das, 0x2F)
2912 //EMIT_SINGLEOP(aaa, 0x37)
2913 //EMIT_SINGLEOP(aas, 0x3F)
2914 //EMIT_SINGLEOP(nop, 0x90)
2915 EMIT_SINGLEOP(cwtl, 0x98)
2916 EMIT_SINGLEOP(cltd, 0x99)
2917 //EMIT_SINGLEOP(fwait, 0x9B)
2918 EMIT_SINGLEOP(sahf, 0x9E)
2919 //EMIT_SINGLEOP(popf, 0x9D)
2920 EMIT_SINGLEOP(leave, 0xC9)
2921 EMIT_SINGLEOP(int3, 0xCC)
2922 //EMIT_SINGLEOP(iret, 0xCF)
2923 //EMIT_SINGLEOP(xlat, 0xD7)
2924 //EMIT_SINGLEOP(lock, 0xF0)
2925 EMIT_SINGLEOP(rep, 0xF3)
2926 //EMIT_SINGLEOP(halt, 0xF4)
2927 EMIT_SINGLEOP(cmc, 0xF5)
2928 EMIT_SINGLEOP(stc, 0xF9)
2929 //EMIT_SINGLEOP(cli, 0xFA)
2930 //EMIT_SINGLEOP(sti, 0xFB)
2931 //EMIT_SINGLEOP(std, 0xFD)
2934 * Emits a MOV out, [MEM].
2936 static void bemit_load(const ir_node *node)
2938 const arch_register_t *out = arch_get_irn_register_out(node, 0);
2940 if (out->index == REG_GP_EAX) {
2941 ir_node *base = get_irn_n(node, n_ia32_base);
2942 int has_base = !is_ia32_NoReg_GP(base);
2943 ir_node *idx = get_irn_n(node, n_ia32_index);
2944 int has_index = !is_ia32_NoReg_GP(idx);
2945 if (!has_base && !has_index) {
2946 ir_entity *ent = get_ia32_am_sc(node);
2947 int offs = get_ia32_am_offs_int(node);
2948 /* load from constant address to EAX can be encoded
2951 bemit_entity(ent, 0, offs, false);
2956 bemit_mod_am(reg_gp_map[out->index], node);
2960 * Emits a MOV [mem], in.
2962 static void bemit_store(const ir_node *node)
2964 const ir_node *value = get_irn_n(node, n_ia32_Store_val);
2965 unsigned size = get_mode_size_bits(get_ia32_ls_mode(node));
2967 if (is_ia32_Immediate(value)) {
2970 bemit_mod_am(0, node);
2971 bemit8(get_ia32_immediate_attr_const(value)->offset);
2972 } else if (size == 16) {
2975 bemit_mod_am(0, node);
2976 bemit16(get_ia32_immediate_attr_const(value)->offset);
2979 bemit_mod_am(0, node);
2980 bemit_immediate(value, false);
2983 const arch_register_t *in = arch_get_irn_register_in(node, n_ia32_Store_val);
2985 if (in->index == REG_GP_EAX) {
2986 ir_node *base = get_irn_n(node, n_ia32_base);
2987 int has_base = !is_ia32_NoReg_GP(base);
2988 ir_node *idx = get_irn_n(node, n_ia32_index);
2989 int has_index = !is_ia32_NoReg_GP(idx);
2990 if (!has_base && !has_index) {
2991 ir_entity *ent = get_ia32_am_sc(node);
2992 int offs = get_ia32_am_offs_int(node);
2993 /* store to constant address from EAX can be encoded as
2994 * 0xA2/0xA3 [offset]*/
3002 bemit_entity(ent, 0, offs, false);
3014 bemit_mod_am(reg_gp_map[in->index], node);
3018 static void bemit_conv_i2i(const ir_node *node)
3023 ir_mode *const smaller_mode = get_ia32_ls_mode(node);
3024 unsigned opcode = 0xB6;
3025 if (mode_is_signed(smaller_mode)) opcode |= 0x08;
3026 if (get_mode_size_bits(smaller_mode) == 16) opcode |= 0x01;
3027 bemit_0f_unop_reg(node, opcode, n_ia32_Conv_I2I_val);
3030 static void bemit_popcnt(ir_node const *const node)
3033 bemit_0f_unop_reg(node, 0xB8, n_ia32_Popcnt_operand);
3039 static void bemit_push(const ir_node *node)
3041 const ir_node *value = get_irn_n(node, n_ia32_Push_val);
3043 if (is_ia32_Immediate(value)) {
3044 const ia32_immediate_attr_t *attr
3045 = get_ia32_immediate_attr_const(value);
3046 unsigned size = get_signed_imm_size(attr->offset);
3052 bemit8((unsigned char)attr->offset);
3057 bemit_immediate(value, false);
3060 } else if (is_ia32_NoReg_GP(value)) {
3062 bemit_mod_am(6, node);
3064 const arch_register_t *reg = arch_get_irn_register_in(node, n_ia32_Push_val);
3065 bemit8(0x50 + reg_gp_map[reg->index]);
3072 static void bemit_pop(const ir_node *node)
3074 const arch_register_t *reg = arch_get_irn_register_out(node, pn_ia32_Pop_res);
3075 bemit8(0x58 + reg_gp_map[reg->index]);
3078 static void bemit_popmem(const ir_node *node)
3081 bemit_mod_am(0, node);
3084 static void bemit_call(const ir_node *node)
3086 ir_node *proc = get_irn_n(node, n_ia32_Call_addr);
3088 if (is_ia32_Immediate(proc)) {
3090 bemit_immediate(proc, true);
3092 bemit_unop(node, 0xFF, 2, n_ia32_Call_addr);
3096 static void bemit_jmp(const ir_node *dest_block)
3099 bemit_jmp_destination(dest_block);
3102 static void bemit_jump(const ir_node *node)
3104 if (can_be_fallthrough(node))
3107 bemit_jmp(get_cfop_target_block(node));
3110 static void bemit_jcc(ia32_condition_code_t pnc, const ir_node *dest_block)
3112 unsigned char cc = pnc2cc(pnc);
3115 bemit_jmp_destination(dest_block);
3118 static void bemit_jp(bool odd, const ir_node *dest_block)
3122 bemit_jmp_destination(dest_block);
3125 static void bemit_ia32_jcc(const ir_node *node)
3127 ia32_condition_code_t cc = get_ia32_condcode(node);
3128 const ir_node *proj_true;
3129 const ir_node *proj_false;
3130 const ir_node *dest_true;
3131 const ir_node *dest_false;
3133 cc = determine_final_cc(node, 0, cc);
3135 /* get both Projs */
3136 proj_true = get_proj(node, pn_ia32_Jcc_true);
3137 assert(proj_true && "Jcc without true Proj");
3139 proj_false = get_proj(node, pn_ia32_Jcc_false);
3140 assert(proj_false && "Jcc without false Proj");
3142 if (can_be_fallthrough(proj_true)) {
3143 /* exchange both proj's so the second one can be omitted */
3144 const ir_node *t = proj_true;
3146 proj_true = proj_false;
3148 cc = ia32_negate_condition_code(cc);
3151 dest_true = get_cfop_target_block(proj_true);
3152 dest_false = get_cfop_target_block(proj_false);
3154 if (cc & ia32_cc_float_parity_cases) {
3155 /* Some floating point comparisons require a test of the parity flag,
3156 * which indicates that the result is unordered */
3157 if (cc & ia32_cc_negated) {
3158 bemit_jp(false, dest_true);
3160 /* we need a local label if the false proj is a fallthrough
3161 * as the falseblock might have no label emitted then */
3162 if (can_be_fallthrough(proj_false)) {
3164 bemit8(0x06); // jp + 6
3166 bemit_jp(false, dest_false);
3170 bemit_jcc(cc, dest_true);
3172 /* the second Proj might be a fallthrough */
3173 if (can_be_fallthrough(proj_false)) {
3174 /* it's a fallthrough */
3176 bemit_jmp(dest_false);
3180 static void bemit_switchjmp(const ir_node *node)
3182 ir_entity *jump_table = get_ia32_am_sc(node);
3183 const ir_switch_table *table = get_ia32_switch_table(node);
3185 bemit8(0xFF); // jmp *tbl.label(,%in,4)
3186 bemit_mod_am(0x05, node);
3188 be_emit_jump_table(node, table, jump_table, get_cfop_target_block);
3194 static void bemit_return(const ir_node *node)
3196 unsigned pop = be_Return_get_pop(node);
3197 if (pop > 0 || be_Return_get_emit_pop(node)) {
3199 assert(pop <= 0xffff);
3206 static void bemit_subsp(const ir_node *node)
3208 const arch_register_t *out;
3211 /* mov %esp, %out */
3213 out = arch_get_irn_register_out(node, 1);
3214 bemit8(MOD_REG | ENC_REG(reg_gp_map[out->index]) | ENC_RM(0x04));
3217 static void bemit_incsp(const ir_node *node)
3220 const arch_register_t *reg;
3224 offs = be_get_IncSP_offset(node);
3235 size = get_signed_imm_size(offs);
3236 bemit8(size == 1 ? 0x83 : 0x81);
3238 reg = arch_get_irn_register_out(node, 0);
3239 bemit_modru(reg, ext);
3248 static void bemit_copybi(const ir_node *node)
3250 unsigned size = get_ia32_copyb_size(node);
3252 bemit8(0xA4); // movsb
3255 bemit8(0xA5); // movsw
3259 bemit8(0xA5); // movsl
3263 static void bemit_fbinop(ir_node const *const node, unsigned const op_fwd, unsigned const op_rev)
3265 ia32_x87_attr_t const *const attr = get_ia32_x87_attr_const(node);
3266 arch_register_t const *const st0 = &ia32_registers[REG_ST0];
3267 if (get_ia32_op_type(node) == ia32_Normal) {
3268 arch_register_t const *const out = attr->x87[2];
3269 assert(out == attr->x87[0] || out == attr->x87[1]);
3270 assert(!attr->attr.data.ins_permuted);
3272 unsigned char op0 = 0xD8;
3273 if (out != st0) op0 |= 0x04;
3274 if (attr->pop) op0 |= 0x02;
3277 unsigned op = op_rev;
3278 arch_register_t const *reg = attr->x87[0];
3283 bemit8(MOD_REG | ENC_REG(op) | ENC_RM(reg->index));
3285 assert(attr->x87[2] == st0);
3288 unsigned const size = get_mode_size_bits(get_ia32_ls_mode(node));
3289 bemit8(size == 32 ? 0xD8 : 0xDC);
3290 bemit_mod_am(attr->attr.data.ins_permuted ? op_rev : op_fwd, node);
3294 static void bemit_fop_reg(ir_node const *const node, unsigned char const op0, unsigned char const op1)
3297 bemit8(op1 + get_ia32_x87_attr_const(node)->x87[0]->index);
3300 static void bemit_fabs(const ir_node *node)
3308 static void bemit_fadd(const ir_node *node)
3310 bemit_fbinop(node, 0, 0);
3313 static void bemit_fchs(const ir_node *node)
3321 static void bemit_fdiv(const ir_node *node)
3323 bemit_fbinop(node, 6, 7);
3326 static void bemit_ffreep(ir_node const *const node)
3328 bemit_fop_reg(node, 0xDF, 0xC0);
3331 static void bemit_fild(const ir_node *node)
3333 switch (get_mode_size_bits(get_ia32_ls_mode(node))) {
3335 bemit8(0xDF); // filds
3336 bemit_mod_am(0, node);
3340 bemit8(0xDB); // fildl
3341 bemit_mod_am(0, node);
3345 bemit8(0xDF); // fildll
3346 bemit_mod_am(5, node);
3350 panic("invalid mode size");
3354 static void bemit_fist(const ir_node *node)
3356 switch (get_mode_size_bits(get_ia32_ls_mode(node))) {
3358 bemit8(0xDF); // fists
3362 bemit8(0xDB); // fistl
3366 panic("invalid mode size");
3368 bemit_mod_am(2, node);
3371 static void bemit_fistp(const ir_node *node)
3373 switch (get_mode_size_bits(get_ia32_ls_mode(node))) {
3375 bemit8(0xDF); // fistps
3376 bemit_mod_am(3, node);
3380 bemit8(0xDB); // fistpl
3381 bemit_mod_am(3, node);
3385 bemit8(0xDF); // fistpll
3386 bemit_mod_am(7, node);
3390 panic("invalid mode size");
3394 static void bemit_fisttp(ir_node const *const node)
3396 switch (get_mode_size_bits(get_ia32_ls_mode(node))) {
3397 case 16: bemit8(0xDF); break; // fisttps
3398 case 32: bemit8(0xDB); break; // fisttpl
3399 case 64: bemit8(0xDD); break; // fisttpll
3400 default: panic("Invalid mode size");
3402 bemit_mod_am(1, node);
3405 static void bemit_fld(const ir_node *node)
3407 switch (get_mode_size_bits(get_ia32_ls_mode(node))) {
3409 bemit8(0xD9); // flds
3410 bemit_mod_am(0, node);
3414 bemit8(0xDD); // fldl
3415 bemit_mod_am(0, node);
3420 bemit8(0xDB); // fldt
3421 bemit_mod_am(5, node);
3425 panic("invalid mode size");
3429 static void bemit_fld1(const ir_node *node)
3433 bemit8(0xE8); // fld1
3436 static void bemit_fldcw(const ir_node *node)
3438 bemit8(0xD9); // fldcw
3439 bemit_mod_am(5, node);
3442 static void bemit_fldz(const ir_node *node)
3446 bemit8(0xEE); // fldz
3449 static void bemit_fmul(const ir_node *node)
3451 bemit_fbinop(node, 1, 1);
3454 static void bemit_fpop(const ir_node *node)
3456 bemit_fop_reg(node, 0xDD, 0xD8);
3459 static void bemit_fpush(const ir_node *node)
3461 bemit_fop_reg(node, 0xD9, 0xC0);
3464 static void bemit_fpushcopy(const ir_node *node)
3466 bemit_fop_reg(node, 0xD9, 0xC0);
3469 static void bemit_fst(const ir_node *node)
3471 switch (get_mode_size_bits(get_ia32_ls_mode(node))) {
3473 bemit8(0xD9); // fsts
3477 bemit8(0xDD); // fstl
3481 panic("invalid mode size");
3483 bemit_mod_am(2, node);
3486 static void bemit_fstp(const ir_node *node)
3488 switch (get_mode_size_bits(get_ia32_ls_mode(node))) {
3490 bemit8(0xD9); // fstps
3491 bemit_mod_am(3, node);
3495 bemit8(0xDD); // fstpl
3496 bemit_mod_am(3, node);
3501 bemit8(0xDB); // fstpt
3502 bemit_mod_am(7, node);
3506 panic("invalid mode size");
3510 static void bemit_fsub(const ir_node *node)
3512 bemit_fbinop(node, 4, 5);
3515 static void bemit_fnstcw(const ir_node *node)
3517 bemit8(0xD9); // fnstcw
3518 bemit_mod_am(7, node);
3521 static void bemit_fnstsw(void)
3523 bemit8(0xDF); // fnstsw %ax
3527 static void bemit_ftstfnstsw(const ir_node *node)
3531 bemit8(0xD9); // ftst
3536 static void bemit_fucomi(const ir_node *node)
3538 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
3539 bemit8(0xDB); // fucomi
3540 bemit8(0xE8 + attr->x87[1]->index);
3543 static void bemit_fucomip(const ir_node *node)
3545 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
3546 bemit8(0xDF); // fucomip
3547 bemit8(0xE8 + attr->x87[1]->index);
3550 static void bemit_fucomfnstsw(const ir_node *node)
3552 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
3553 bemit8(0xDD); // fucom
3554 bemit8(0xE0 + attr->x87[1]->index);
3558 static void bemit_fucompfnstsw(const ir_node *node)
3560 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
3561 bemit8(0xDD); // fucomp
3562 bemit8(0xE8 + attr->x87[1]->index);
3566 static void bemit_fucomppfnstsw(const ir_node *node)
3570 bemit8(0xDA); // fucompp
3575 static void bemit_fxch(const ir_node *node)
3577 bemit_fop_reg(node, 0xD9, 0xC8);
3581 * The type of a emitter function.
3583 typedef void (*emit_func) (const ir_node *);
3586 * Set a node emitter. Make it a bit more type safe.
3588 static void register_emitter(ir_op *op, emit_func func)
3590 op->ops.generic = (op_func) func;
3593 static void ia32_register_binary_emitters(void)
3595 /* first clear the generic function pointer for all ops */
3596 ir_clear_opcodes_generic_func();
3598 /* benode emitter */
3599 register_emitter(op_be_Copy, bemit_copy);
3600 register_emitter(op_be_CopyKeep, bemit_copy);
3601 register_emitter(op_be_IncSP, bemit_incsp);
3602 register_emitter(op_be_Perm, bemit_perm);
3603 register_emitter(op_be_Return, bemit_return);
3604 register_emitter(op_ia32_Adc, bemit_adc);
3605 register_emitter(op_ia32_Add, bemit_add);
3606 register_emitter(op_ia32_AddMem, bemit_addmem);
3607 register_emitter(op_ia32_AddMem8Bit, bemit_addmem8bit);
3608 register_emitter(op_ia32_And, bemit_and);
3609 register_emitter(op_ia32_AndMem, bemit_andmem);
3610 register_emitter(op_ia32_AndMem8Bit, bemit_andmem8bit);
3611 register_emitter(op_ia32_Asm, emit_ia32_Asm); // TODO implement binary emitter
3612 register_emitter(op_ia32_Breakpoint, bemit_int3);
3613 register_emitter(op_ia32_Bsf, bemit_bsf);
3614 register_emitter(op_ia32_Bsr, bemit_bsr);
3615 register_emitter(op_ia32_Bswap, bemit_bswap);
3616 register_emitter(op_ia32_Bt, bemit_bt);
3617 register_emitter(op_ia32_CMovcc, bemit_cmovcc);
3618 register_emitter(op_ia32_Call, bemit_call);
3619 register_emitter(op_ia32_Cltd, bemit_cltd);
3620 register_emitter(op_ia32_Cmc, bemit_cmc);
3621 register_emitter(op_ia32_Cmp, bemit_cmp);
3622 register_emitter(op_ia32_Cmp8Bit, bemit_cmp8bit);
3623 register_emitter(op_ia32_Const, bemit_mov_const);
3624 register_emitter(op_ia32_Conv_I2I, bemit_conv_i2i);
3625 register_emitter(op_ia32_Conv_I2I8Bit, bemit_conv_i2i);
3626 register_emitter(op_ia32_CopyB_i, bemit_copybi);
3627 register_emitter(op_ia32_Cwtl, bemit_cwtl);
3628 register_emitter(op_ia32_Dec, bemit_dec);
3629 register_emitter(op_ia32_DecMem, bemit_decmem);
3630 register_emitter(op_ia32_Div, bemit_div);
3631 register_emitter(op_ia32_FldCW, bemit_fldcw);
3632 register_emitter(op_ia32_FnstCW, bemit_fnstcw);
3633 register_emitter(op_ia32_FtstFnstsw, bemit_ftstfnstsw);
3634 register_emitter(op_ia32_FucomFnstsw, bemit_fucomfnstsw);
3635 register_emitter(op_ia32_Fucomi, bemit_fucomi);
3636 register_emitter(op_ia32_FucompFnstsw, bemit_fucompfnstsw);
3637 register_emitter(op_ia32_Fucompi, bemit_fucomip);
3638 register_emitter(op_ia32_FucomppFnstsw, bemit_fucomppfnstsw);
3639 register_emitter(op_ia32_IDiv, bemit_idiv);
3640 register_emitter(op_ia32_IJmp, bemit_ijmp);
3641 register_emitter(op_ia32_IMul, bemit_imul);
3642 register_emitter(op_ia32_IMul1OP, bemit_imul1op);
3643 register_emitter(op_ia32_Inc, bemit_inc);
3644 register_emitter(op_ia32_IncMem, bemit_incmem);
3645 register_emitter(op_ia32_Jcc, bemit_ia32_jcc);
3646 register_emitter(op_ia32_Jmp, bemit_jump);
3647 register_emitter(op_ia32_LdTls, bemit_ldtls);
3648 register_emitter(op_ia32_Lea, bemit_lea);
3649 register_emitter(op_ia32_Leave, bemit_leave);
3650 register_emitter(op_ia32_Load, bemit_load);
3651 register_emitter(op_ia32_Minus64Bit, bemit_minus64bit);
3652 register_emitter(op_ia32_Mul, bemit_mul);
3653 register_emitter(op_ia32_Neg, bemit_neg);
3654 register_emitter(op_ia32_NegMem, bemit_negmem);
3655 register_emitter(op_ia32_Not, bemit_not);
3656 register_emitter(op_ia32_NotMem, bemit_notmem);
3657 register_emitter(op_ia32_Or, bemit_or);
3658 register_emitter(op_ia32_OrMem, bemit_ormem);
3659 register_emitter(op_ia32_OrMem8Bit, bemit_ormem8bit);
3660 register_emitter(op_ia32_Pop, bemit_pop);
3661 register_emitter(op_ia32_PopEbp, bemit_pop);
3662 register_emitter(op_ia32_PopMem, bemit_popmem);
3663 register_emitter(op_ia32_Popcnt, bemit_popcnt);
3664 register_emitter(op_ia32_Push, bemit_push);
3665 register_emitter(op_ia32_RepPrefix, bemit_rep);
3666 register_emitter(op_ia32_Rol, bemit_rol);
3667 register_emitter(op_ia32_RolMem, bemit_rolmem);
3668 register_emitter(op_ia32_Ror, bemit_ror);
3669 register_emitter(op_ia32_RorMem, bemit_rormem);
3670 register_emitter(op_ia32_Sahf, bemit_sahf);
3671 register_emitter(op_ia32_Sar, bemit_sar);
3672 register_emitter(op_ia32_SarMem, bemit_sarmem);
3673 register_emitter(op_ia32_Sbb, bemit_sbb);
3674 register_emitter(op_ia32_Sbb0, bemit_sbb0);
3675 register_emitter(op_ia32_Setcc, bemit_setcc);
3676 register_emitter(op_ia32_Shl, bemit_shl);
3677 register_emitter(op_ia32_ShlD, bemit_shld);
3678 register_emitter(op_ia32_ShlMem, bemit_shlmem);
3679 register_emitter(op_ia32_Shr, bemit_shr);
3680 register_emitter(op_ia32_ShrD, bemit_shrd);
3681 register_emitter(op_ia32_ShrMem, bemit_shrmem);
3682 register_emitter(op_ia32_Stc, bemit_stc);
3683 register_emitter(op_ia32_Store, bemit_store);
3684 register_emitter(op_ia32_Store8Bit, bemit_store);
3685 register_emitter(op_ia32_Sub, bemit_sub);
3686 register_emitter(op_ia32_SubMem, bemit_submem);
3687 register_emitter(op_ia32_SubMem8Bit, bemit_submem8bit);
3688 register_emitter(op_ia32_SubSP, bemit_subsp);
3689 register_emitter(op_ia32_SwitchJmp, bemit_switchjmp);
3690 register_emitter(op_ia32_Test, bemit_test);
3691 register_emitter(op_ia32_Test8Bit, bemit_test8bit);
3692 register_emitter(op_ia32_Xor, bemit_xor);
3693 register_emitter(op_ia32_Xor0, bemit_xor0);
3694 register_emitter(op_ia32_XorMem, bemit_xormem);
3695 register_emitter(op_ia32_XorMem8Bit, bemit_xormem8bit);
3696 register_emitter(op_ia32_fabs, bemit_fabs);
3697 register_emitter(op_ia32_fadd, bemit_fadd);
3698 register_emitter(op_ia32_fchs, bemit_fchs);
3699 register_emitter(op_ia32_fdiv, bemit_fdiv);
3700 register_emitter(op_ia32_ffreep, bemit_ffreep);
3701 register_emitter(op_ia32_fild, bemit_fild);
3702 register_emitter(op_ia32_fist, bemit_fist);
3703 register_emitter(op_ia32_fistp, bemit_fistp);
3704 register_emitter(op_ia32_fisttp, bemit_fisttp);
3705 register_emitter(op_ia32_fld, bemit_fld);
3706 register_emitter(op_ia32_fld1, bemit_fld1);
3707 register_emitter(op_ia32_fldz, bemit_fldz);
3708 register_emitter(op_ia32_fmul, bemit_fmul);
3709 register_emitter(op_ia32_fpop, bemit_fpop);
3710 register_emitter(op_ia32_fpush, bemit_fpush);
3711 register_emitter(op_ia32_fpushCopy, bemit_fpushcopy);
3712 register_emitter(op_ia32_fst, bemit_fst);
3713 register_emitter(op_ia32_fstp, bemit_fstp);
3714 register_emitter(op_ia32_fsub, bemit_fsub);
3715 register_emitter(op_ia32_fxch, bemit_fxch);
3717 /* ignore the following nodes */
3718 register_emitter(op_ia32_ProduceVal, emit_Nothing);
3719 register_emitter(op_ia32_Unknown, emit_Nothing);
3720 register_emitter(op_be_Keep, emit_Nothing);
3721 register_emitter(op_be_Start, emit_Nothing);
3722 register_emitter(op_Phi, emit_Nothing);
3723 register_emitter(op_Start, emit_Nothing);
3726 static void gen_binary_block(ir_node *block)
3728 ia32_emit_block_header(block);
3730 /* emit the contents of the block */
3731 sched_foreach(block, node) {
3732 ia32_emit_node(node);
3736 void ia32_gen_binary_routine(ir_graph *irg)
3738 ir_entity *entity = get_irg_entity(irg);
3739 const arch_env_t *arch_env = be_get_irg_arch_env(irg);
3740 ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
3741 ir_node **blk_sched = irg_data->blk_sched;
3743 parameter_dbg_info_t *infos;
3745 isa = (ia32_isa_t*) arch_env;
3747 ia32_register_binary_emitters();
3749 infos = construct_parameter_infos(irg);
3750 be_gas_emit_function_prolog(entity, ia32_cg_config.function_alignment,
3754 /* we use links to point to target blocks */
3755 ir_reserve_resources(irg, IR_RESOURCE_IRN_LINK);
3756 irg_block_walk_graph(irg, ia32_gen_labels, NULL, NULL);
3758 /* initialize next block links */
3759 n = ARR_LEN(blk_sched);
3760 for (i = 0; i < n; ++i) {
3761 ir_node *block = blk_sched[i];
3762 ir_node *prev = i > 0 ? blk_sched[i-1] : NULL;
3764 set_irn_link(block, prev);
3767 for (i = 0; i < n; ++i) {
3768 ir_node *block = blk_sched[i];
3769 gen_binary_block(block);
3772 be_gas_emit_function_epilog(entity);
3774 ir_free_resources(irg, IR_RESOURCE_IRN_LINK);
3778 void ia32_init_emitter(void)
3780 lc_opt_entry_t *be_grp;
3781 lc_opt_entry_t *ia32_grp;
3783 be_grp = lc_opt_get_grp(firm_opt_get_root(), "be");
3784 ia32_grp = lc_opt_get_grp(be_grp, "ia32");
3786 lc_opt_add_table(ia32_grp, ia32_emitter_options);
3790 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.emitter");