2 * Copyright (C) 1995-2011 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This file implements the ia32 node emitter.
23 * @author Christian Wuerdig, Matthias Braun
26 * Summary table for x86 floatingpoint compares:
27 * (remember effect of unordered on x86: ZF=1, PF=1, CF=1)
35 * pnc_Leg => NP (ordered)
57 #include "iredges_t.h"
61 #include "raw_bitset.h"
65 #include "../besched.h"
66 #include "../benode.h"
68 #include "../be_dbgout.h"
69 #include "../beemitter.h"
70 #include "../begnuas.h"
72 #include "../be_dbgout.h"
74 #include "ia32_emitter.h"
75 #include "ia32_common_transform.h"
76 #include "gen_ia32_emitter.h"
77 #include "gen_ia32_regalloc_if.h"
78 #include "ia32_nodes_attr.h"
79 #include "ia32_new_nodes.h"
80 #include "ia32_architecture.h"
81 #include "bearch_ia32_t.h"
83 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
85 #define SNPRINTF_BUF_LEN 128
87 static const ia32_isa_t *isa;
88 static char pic_base_label[128];
89 static ir_label_t exc_label_id;
90 static int mark_spill_reload = 0;
93 /** Return the next block in Block schedule */
94 static ir_node *get_prev_block_sched(const ir_node *block)
96 return (ir_node*)get_irn_link(block);
99 /** Checks if the current block is a fall-through target. */
100 static int is_fallthrough(const ir_node *cfgpred)
104 if (!is_Proj(cfgpred))
106 pred = get_Proj_pred(cfgpred);
107 if (is_ia32_SwitchJmp(pred))
114 * returns non-zero if the given block needs a label
115 * because of being a jump-target (and not a fall-through)
117 static int block_needs_label(const ir_node *block)
120 int n_cfgpreds = get_Block_n_cfgpreds(block);
122 if (has_Block_entity(block))
125 if (n_cfgpreds == 0) {
127 } else if (n_cfgpreds == 1) {
128 ir_node *cfgpred = get_Block_cfgpred(block, 0);
129 ir_node *cfgpred_block = get_nodes_block(cfgpred);
131 if (get_prev_block_sched(block) == cfgpred_block
132 && is_fallthrough(cfgpred)) {
141 * Returns the register at in position pos.
143 static const arch_register_t *get_in_reg(const ir_node *irn, int pos)
146 const arch_register_t *reg = NULL;
148 assert(get_irn_arity(irn) > pos && "Invalid IN position");
150 /* The out register of the operator at position pos is the
151 in register we need. */
152 op = get_irn_n(irn, pos);
154 reg = arch_get_irn_register(op);
156 assert(reg && "no in register found");
158 if (reg == &ia32_registers[REG_GP_NOREG])
159 panic("trying to emit noreg for %+F input %d", irn, pos);
165 * Returns the register at out position pos.
167 static const arch_register_t *get_out_reg(const ir_node *irn, int pos)
170 const arch_register_t *reg = NULL;
172 /* 1st case: irn is not of mode_T, so it has only */
173 /* one OUT register -> good */
174 /* 2nd case: irn is of mode_T -> collect all Projs and ask the */
175 /* Proj with the corresponding projnum for the register */
177 if (get_irn_mode(irn) != mode_T) {
179 reg = arch_get_irn_register(irn);
180 } else if (is_ia32_irn(irn)) {
181 reg = arch_irn_get_register(irn, pos);
183 const ir_edge_t *edge;
185 foreach_out_edge(irn, edge) {
186 proj = get_edge_src_irn(edge);
187 assert(is_Proj(proj) && "non-Proj from mode_T node");
188 if (get_Proj_proj(proj) == pos) {
189 reg = arch_get_irn_register(proj);
195 assert(reg && "no out register found");
200 * Add a number to a prefix. This number will not be used a second time.
202 static char *get_unique_label(char *buf, size_t buflen, const char *prefix)
204 static unsigned long id = 0;
205 snprintf(buf, buflen, "%s%s%lu", be_gas_get_private_prefix(), prefix, ++id);
210 * Emit the name of the 8bit low register
212 static void emit_8bit_register(const arch_register_t *reg)
214 const char *reg_name = arch_register_get_name(reg);
215 assert(reg->index == REG_GP_EAX || reg->index == REG_GP_EBX
216 || reg->index == REG_GP_ECX || reg->index == REG_GP_EDX);
219 be_emit_char(reg_name[1]); /* get the basic name of the register */
224 * Emit the name of the 8bit high register
226 static void emit_8bit_register_high(const arch_register_t *reg)
228 const char *reg_name = arch_register_get_name(reg);
229 assert(reg->index == REG_GP_EAX || reg->index == REG_GP_EBX
230 || reg->index == REG_GP_ECX || reg->index == REG_GP_EDX);
233 be_emit_char(reg_name[1]); /* get the basic name of the register */
237 static void emit_16bit_register(const arch_register_t *reg)
239 const char *reg_name = arch_register_get_name(reg);
242 be_emit_string(reg_name+1); /* skip the 'e' prefix of the 32bit names */
246 * emit a register, possible shortened by a mode
248 * @param reg the register
249 * @param mode the mode of the register or NULL for full register
251 static void emit_register(const arch_register_t *reg, const ir_mode *mode)
253 const char *reg_name;
256 int size = get_mode_size_bits(mode);
258 case 8: emit_8bit_register(reg); return;
259 case 16: emit_16bit_register(reg); return;
261 assert(mode_is_float(mode) || size == 32);
264 reg_name = arch_register_get_name(reg);
267 be_emit_string(reg_name);
270 void ia32_emit_source_register(const ir_node *node, int pos)
272 const arch_register_t *reg = get_in_reg(node, pos);
274 emit_register(reg, NULL);
277 static void ia32_emit_entity(ir_entity *entity, int no_pic_adjust)
279 be_gas_emit_entity(entity);
281 if (get_entity_owner(entity) == get_tls_type()) {
282 if (get_entity_visibility(entity) == ir_visibility_external) {
283 be_emit_cstring("@INDNTPOFF");
285 be_emit_cstring("@NTPOFF");
289 if (do_pic && !no_pic_adjust) {
291 be_emit_string(pic_base_label);
295 static void emit_ia32_Immediate_no_prefix(const ir_node *node)
297 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(node);
299 if (attr->symconst != NULL) {
302 ia32_emit_entity(attr->symconst, attr->no_pic_adjust);
304 if (attr->symconst == NULL || attr->offset != 0) {
305 if (attr->symconst != NULL) {
306 be_emit_irprintf("%+d", attr->offset);
308 be_emit_irprintf("0x%X", attr->offset);
313 static void emit_ia32_Immediate(const ir_node *node)
316 emit_ia32_Immediate_no_prefix(node);
319 void ia32_emit_8bit_source_register_or_immediate(const ir_node *node, int pos)
321 const arch_register_t *reg;
322 const ir_node *in = get_irn_n(node, pos);
323 if (is_ia32_Immediate(in)) {
324 emit_ia32_Immediate(in);
328 reg = get_in_reg(node, pos);
329 emit_8bit_register(reg);
332 void ia32_emit_8bit_high_source_register(const ir_node *node, int pos)
334 const arch_register_t *reg = get_in_reg(node, pos);
335 emit_8bit_register_high(reg);
338 void ia32_emit_16bit_source_register_or_immediate(const ir_node *node, int pos)
340 const arch_register_t *reg;
341 const ir_node *in = get_irn_n(node, pos);
342 if (is_ia32_Immediate(in)) {
343 emit_ia32_Immediate(in);
347 reg = get_in_reg(node, pos);
348 emit_16bit_register(reg);
351 void ia32_emit_dest_register(const ir_node *node, int pos)
353 const arch_register_t *reg = get_out_reg(node, pos);
355 emit_register(reg, NULL);
358 void ia32_emit_dest_register_size(const ir_node *node, int pos)
360 const arch_register_t *reg = get_out_reg(node, pos);
362 emit_register(reg, get_ia32_ls_mode(node));
365 void ia32_emit_8bit_dest_register(const ir_node *node, int pos)
367 const arch_register_t *reg = get_out_reg(node, pos);
369 emit_register(reg, mode_Bu);
372 void ia32_emit_x87_register(const ir_node *node, int pos)
374 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
378 be_emit_string(attr->x87[pos]->name);
381 static void ia32_emit_mode_suffix_mode(const ir_mode *mode)
383 assert(mode_is_int(mode) || mode_is_reference(mode));
384 switch (get_mode_size_bits(mode)) {
385 case 8: be_emit_char('b'); return;
386 case 16: be_emit_char('w'); return;
387 case 32: be_emit_char('l'); return;
388 /* gas docu says q is the suffix but gcc, objdump and icc use ll
390 case 64: be_emit_cstring("ll"); return;
392 panic("Can't output mode_suffix for %+F", mode);
395 void ia32_emit_mode_suffix(const ir_node *node)
397 ir_mode *mode = get_ia32_ls_mode(node);
401 ia32_emit_mode_suffix_mode(mode);
404 void ia32_emit_x87_mode_suffix(const ir_node *node)
408 /* we only need to emit the mode on address mode */
409 if (get_ia32_op_type(node) == ia32_Normal)
412 mode = get_ia32_ls_mode(node);
413 assert(mode != NULL);
415 if (mode_is_float(mode)) {
416 switch (get_mode_size_bits(mode)) {
417 case 32: be_emit_char('s'); return;
418 case 64: be_emit_char('l'); return;
419 /* long doubles have different sizes due to alignment on different
423 case 128: be_emit_char('t'); return;
426 assert(mode_is_int(mode) || mode_is_reference(mode));
427 switch (get_mode_size_bits(mode)) {
428 case 16: be_emit_char('s'); return;
429 case 32: be_emit_char('l'); return;
430 /* gas docu says q is the suffix but gcc, objdump and icc use ll
432 case 64: be_emit_cstring("ll"); return;
435 panic("Can't output mode_suffix for %+F", mode);
438 static char get_xmm_mode_suffix(ir_mode *mode)
440 assert(mode_is_float(mode));
441 switch (get_mode_size_bits(mode)) {
444 default: panic("Invalid XMM mode");
448 void ia32_emit_xmm_mode_suffix(const ir_node *node)
450 ir_mode *mode = get_ia32_ls_mode(node);
451 assert(mode != NULL);
453 be_emit_char(get_xmm_mode_suffix(mode));
456 void ia32_emit_xmm_mode_suffix_s(const ir_node *node)
458 ir_mode *mode = get_ia32_ls_mode(node);
459 assert(mode != NULL);
460 be_emit_char(get_xmm_mode_suffix(mode));
463 void ia32_emit_extend_suffix(const ir_node *node)
465 ir_mode *mode = get_ia32_ls_mode(node);
466 if (get_mode_size_bits(mode) == 32)
468 be_emit_char(mode_is_signed(mode) ? 's' : 'z');
469 ia32_emit_mode_suffix_mode(mode);
472 void ia32_emit_source_register_or_immediate(const ir_node *node, int pos)
474 ir_node *in = get_irn_n(node, pos);
475 if (is_ia32_Immediate(in)) {
476 emit_ia32_Immediate(in);
478 const ir_mode *mode = get_ia32_ls_mode(node);
479 const arch_register_t *reg = get_in_reg(node, pos);
480 emit_register(reg, mode);
485 * Returns the target block for a control flow node.
487 static ir_node *get_cfop_target_block(const ir_node *irn)
489 assert(get_irn_mode(irn) == mode_X);
490 return (ir_node*)get_irn_link(irn);
494 * Emits the target label for a control flow node.
496 static void ia32_emit_cfop_target(const ir_node *node)
498 ir_node *block = get_cfop_target_block(node);
499 be_gas_emit_block_name(block);
503 * Emit the suffix for a compare instruction.
505 static void ia32_emit_condition_code(ia32_condition_code_t cc)
508 case ia32_cc_overflow: be_emit_cstring("o"); return;
509 case ia32_cc_not_overflow: be_emit_cstring("no"); return;
510 case ia32_cc_float_below:
511 case ia32_cc_float_unordered_below:
512 case ia32_cc_below: be_emit_cstring("b"); return;
513 case ia32_cc_float_above_equal:
514 case ia32_cc_float_unordered_above_equal:
515 case ia32_cc_above_equal: be_emit_cstring("ae"); return;
516 case ia32_cc_float_equal:
517 case ia32_cc_equal: be_emit_cstring("e"); return;
518 case ia32_cc_float_not_equal:
519 case ia32_cc_not_equal: be_emit_cstring("ne"); return;
520 case ia32_cc_float_below_equal:
521 case ia32_cc_float_unordered_below_equal:
522 case ia32_cc_below_equal: be_emit_cstring("be"); return;
523 case ia32_cc_float_above:
524 case ia32_cc_float_unordered_above:
525 case ia32_cc_above: be_emit_cstring("a"); return;
526 case ia32_cc_sign: be_emit_cstring("s"); return;
527 case ia32_cc_not_sign: be_emit_cstring("ns"); return;
528 case ia32_cc_parity: be_emit_cstring("p"); return;
529 case ia32_cc_not_parity: be_emit_cstring("np"); return;
530 case ia32_cc_less: be_emit_cstring("l"); return;
531 case ia32_cc_greater_equal: be_emit_cstring("ge"); return;
532 case ia32_cc_less_equal: be_emit_cstring("le"); return;
533 case ia32_cc_greater: be_emit_cstring("g"); return;
534 case ia32_cc_float_parity_cases:
535 case ia32_cc_additional_float_cases:
538 panic("Invalid ia32 condition code");
541 typedef enum ia32_emit_mod_t {
543 EMIT_RESPECT_LS = 1U << 0,
544 EMIT_ALTERNATE_AM = 1U << 1,
546 EMIT_HIGH_REG = 1U << 3,
547 EMIT_LOW_REG = 1U << 4
549 ENUM_BITSET(ia32_emit_mod_t)
552 * Emits address mode.
554 void ia32_emit_am(const ir_node *node)
556 ir_entity *ent = get_ia32_am_sc(node);
557 int offs = get_ia32_am_offs_int(node);
558 ir_node *base = get_irn_n(node, n_ia32_base);
559 int has_base = !is_ia32_NoReg_GP(base);
560 ir_node *index = get_irn_n(node, n_ia32_index);
561 int has_index = !is_ia32_NoReg_GP(index);
563 /* just to be sure... */
564 assert(!is_ia32_use_frame(node) || get_ia32_frame_ent(node) != NULL);
566 if (get_ia32_am_tls_segment(node))
567 be_emit_cstring("%gs:");
571 const ia32_attr_t *attr = get_ia32_attr_const(node);
572 if (is_ia32_am_sc_sign(node))
574 ia32_emit_entity(ent, attr->data.am_sc_no_pic_adjust);
577 /* also handle special case if nothing is set */
578 if (offs != 0 || (ent == NULL && !has_base && !has_index)) {
580 be_emit_irprintf("%+d", offs);
582 be_emit_irprintf("%d", offs);
586 if (has_base || has_index) {
591 const arch_register_t *reg = get_in_reg(node, n_ia32_base);
592 emit_register(reg, NULL);
595 /* emit index + scale */
597 const arch_register_t *reg = get_in_reg(node, n_ia32_index);
600 emit_register(reg, NULL);
602 scale = get_ia32_am_scale(node);
604 be_emit_irprintf(",%d", 1 << scale);
612 * fmt parameter output
613 * ---- ---------------------- ---------------------------------------------
615 * %AM <node> address mode of the node
616 * %AR const arch_register_t* address mode of the node or register
617 * %ASx <node> address mode of the node or source register x
618 * %Dx <node> destination register x
619 * %I <node> immediate of the node
620 * %L <node> control flow target of the node
621 * %M <node> mode suffix of the node
622 * %P int condition code
623 * %R const arch_register_t* register
624 * %Sx <node> source register x
625 * %s const char* string
626 * %u unsigned int unsigned int
627 * %d signed int signed int
630 * # modifier for %ASx, %D, %R, and %S uses ls mode of node to alter register width
631 * * modifier does not prefix immediates with $, but AM with *
632 * l modifier for %lu and %ld
633 * > modifier to output high 8bit register (ah, bh)
634 * < modifier to output low 8bit register (al, bl)
636 static void ia32_emitf(const ir_node *node, const char *fmt, ...)
642 const char *start = fmt;
643 ia32_emit_mod_t mod = EMIT_NONE;
645 while (*fmt != '%' && *fmt != '\n' && *fmt != '\0')
648 be_emit_string_len(start, fmt - start);
652 be_emit_finish_line_gas(node);
665 case '*': mod |= EMIT_ALTERNATE_AM; break;
666 case '#': mod |= EMIT_RESPECT_LS; break;
667 case 'l': mod |= EMIT_LONG; break;
668 case '>': mod |= EMIT_HIGH_REG; break;
669 case '<': mod |= EMIT_LOW_REG; break;
686 if (mod & EMIT_ALTERNATE_AM)
692 const arch_register_t *reg = va_arg(ap, const arch_register_t*);
693 if (get_ia32_op_type(node) == ia32_AddrModeS) {
696 if (mod & EMIT_ALTERNATE_AM)
698 emit_register(reg, NULL);
704 if (get_ia32_op_type(node) == ia32_AddrModeS) {
708 assert(get_ia32_op_type(node) == ia32_Normal);
713 default: goto unknown;
720 const arch_register_t *reg;
722 if (*fmt < '0' || '9' <= *fmt)
726 reg = get_out_reg(node, pos);
727 emit_register(reg, mod & EMIT_RESPECT_LS ? get_ia32_ls_mode(node) : NULL);
732 if (!(mod & EMIT_ALTERNATE_AM))
734 emit_ia32_Immediate_no_prefix(node);
738 ia32_emit_cfop_target(node);
742 ia32_emit_mode_suffix_mode(get_ia32_ls_mode(node));
747 ia32_condition_code_t cc = va_arg(ap, ia32_condition_code_t);
748 ia32_emit_condition_code(cc);
753 const arch_register_t *reg = va_arg(ap, const arch_register_t*);
754 if (mod & EMIT_HIGH_REG) {
755 emit_8bit_register_high(reg);
756 } else if (mod & EMIT_LOW_REG) {
757 emit_8bit_register(reg);
759 emit_register(reg, mod & EMIT_RESPECT_LS ? get_ia32_ls_mode(node) : NULL);
769 if (*fmt < '0' || '9' <= *fmt)
773 in = get_irn_n(node, pos);
774 if (is_ia32_Immediate(in)) {
775 if (!(mod & EMIT_ALTERNATE_AM))
777 emit_ia32_Immediate_no_prefix(in);
779 const arch_register_t *reg;
781 if (mod & EMIT_ALTERNATE_AM)
783 reg = get_in_reg(node, pos);
784 emit_register(reg, mod & EMIT_RESPECT_LS ? get_ia32_ls_mode(node) : NULL);
790 const char *str = va_arg(ap, const char*);
796 if (mod & EMIT_LONG) {
797 unsigned long num = va_arg(ap, unsigned long);
798 be_emit_irprintf("%lu", num);
800 unsigned num = va_arg(ap, unsigned);
801 be_emit_irprintf("%u", num);
806 if (mod & EMIT_LONG) {
807 long num = va_arg(ap, long);
808 be_emit_irprintf("%ld", num);
810 int num = va_arg(ap, int);
811 be_emit_irprintf("%d", num);
817 panic("unknown format conversion in ia32_emitf()");
825 * Emits registers and/or address mode of a binary operation.
827 void ia32_emit_binop(const ir_node *node)
829 if (is_ia32_Immediate(get_irn_n(node, n_ia32_binary_right))) {
830 ia32_emitf(node, "%#S4, %#AS3");
832 ia32_emitf(node, "%#AS4, %#S3");
837 * Emits registers and/or address mode of a binary operation.
839 void ia32_emit_x87_binop(const ir_node *node)
841 switch (get_ia32_op_type(node)) {
844 const ia32_x87_attr_t *x87_attr = get_ia32_x87_attr_const(node);
845 const arch_register_t *in1 = x87_attr->x87[0];
846 const arch_register_t *in = x87_attr->x87[1];
847 const arch_register_t *out = x87_attr->x87[2];
851 } else if (out == in) {
856 be_emit_string(arch_register_get_name(in));
857 be_emit_cstring(", %");
858 be_emit_string(arch_register_get_name(out));
866 assert(0 && "unsupported op type");
871 * Emits registers and/or address mode of a unary operation.
873 void ia32_emit_unop(const ir_node *node, int pos)
877 ia32_emitf(node, fmt);
880 static void emit_ia32_IMul(const ir_node *node)
882 ir_node *left = get_irn_n(node, n_ia32_IMul_left);
883 const arch_register_t *out_reg = get_out_reg(node, pn_ia32_IMul_res);
885 /* do we need the 3-address form? */
886 if (is_ia32_NoReg_GP(left) ||
887 get_in_reg(node, n_ia32_IMul_left) != out_reg) {
888 ia32_emitf(node, "\timul%M %#S4, %#AS3, %#D0\n");
890 ia32_emitf(node, "\timul%M %#AS4, %#S3\n");
895 * walks up a tree of copies/perms/spills/reloads to find the original value
896 * that is moved around
898 static ir_node *find_original_value(ir_node *node)
900 if (irn_visited(node))
903 mark_irn_visited(node);
904 if (be_is_Copy(node)) {
905 return find_original_value(be_get_Copy_op(node));
906 } else if (be_is_CopyKeep(node)) {
907 return find_original_value(be_get_CopyKeep_op(node));
908 } else if (is_Proj(node)) {
909 ir_node *pred = get_Proj_pred(node);
910 if (be_is_Perm(pred)) {
911 return find_original_value(get_irn_n(pred, get_Proj_proj(node)));
912 } else if (be_is_MemPerm(pred)) {
913 return find_original_value(get_irn_n(pred, get_Proj_proj(node) + 1));
914 } else if (is_ia32_Load(pred)) {
915 return find_original_value(get_irn_n(pred, n_ia32_Load_mem));
919 } else if (is_ia32_Store(node)) {
920 return find_original_value(get_irn_n(node, n_ia32_Store_val));
921 } else if (is_Phi(node)) {
923 arity = get_irn_arity(node);
924 for (i = 0; i < arity; ++i) {
925 ir_node *in = get_irn_n(node, i);
926 ir_node *res = find_original_value(in);
937 static int determine_final_cc(const ir_node *node, int flags_pos, int cc)
939 ir_node *flags = get_irn_n(node, flags_pos);
940 const ia32_attr_t *flags_attr;
941 flags = skip_Proj(flags);
943 if (is_ia32_Sahf(flags)) {
944 ir_node *cmp = get_irn_n(flags, n_ia32_Sahf_val);
945 if (!(is_ia32_FucomFnstsw(cmp) || is_ia32_FucompFnstsw(cmp)
946 || is_ia32_FucomppFnstsw(cmp) || is_ia32_FtstFnstsw(cmp))) {
947 inc_irg_visited(current_ir_graph);
948 cmp = find_original_value(cmp);
950 assert(is_ia32_FucomFnstsw(cmp) || is_ia32_FucompFnstsw(cmp)
951 || is_ia32_FucomppFnstsw(cmp) || is_ia32_FtstFnstsw(cmp));
954 flags_attr = get_ia32_attr_const(cmp);
956 flags_attr = get_ia32_attr_const(flags);
959 if (flags_attr->data.ins_permuted)
960 cc = ia32_invert_condition_code(cc);
964 void ia32_emit_cmp_suffix_node(const ir_node *node, int flags_pos)
966 ia32_condition_code_t cc = get_ia32_condcode(node);
967 cc = determine_final_cc(node, flags_pos, cc);
969 ia32_emit_condition_code(cc);
973 * Emits an exception label for a given node.
975 static void ia32_emit_exc_label(const ir_node *node)
977 be_emit_string(be_gas_insn_label_prefix());
978 be_emit_irprintf("%lu", get_ia32_exc_label_id(node));
982 * Returns the Proj with projection number proj and NOT mode_M
984 static ir_node *get_proj(const ir_node *node, long proj)
986 const ir_edge_t *edge;
989 assert(get_irn_mode(node) == mode_T && "expected mode_T node");
991 foreach_out_edge(node, edge) {
992 src = get_edge_src_irn(edge);
994 assert(is_Proj(src) && "Proj expected");
995 if (get_irn_mode(src) == mode_M)
998 if (get_Proj_proj(src) == proj)
1004 static int can_be_fallthrough(const ir_node *node)
1006 ir_node *target_block = get_cfop_target_block(node);
1007 ir_node *block = get_nodes_block(node);
1008 return get_prev_block_sched(target_block) == block;
1012 * Emits the jump sequence for a conditional jump (cmp + jmp_true + jmp_false)
1014 static void emit_ia32_Jcc(const ir_node *node)
1016 int need_parity_label = 0;
1017 ia32_condition_code_t cc = get_ia32_condcode(node);
1018 const ir_node *proj_true;
1019 const ir_node *proj_false;
1021 cc = determine_final_cc(node, 0, cc);
1023 /* get both Projs */
1024 proj_true = get_proj(node, pn_ia32_Jcc_true);
1025 assert(proj_true && "Jcc without true Proj");
1027 proj_false = get_proj(node, pn_ia32_Jcc_false);
1028 assert(proj_false && "Jcc without false Proj");
1030 if (can_be_fallthrough(proj_true)) {
1031 /* exchange both proj's so the second one can be omitted */
1032 const ir_node *t = proj_true;
1034 proj_true = proj_false;
1036 cc = ia32_negate_condition_code(cc);
1039 if (cc & ia32_cc_float_parity_cases) {
1040 /* Some floating point comparisons require a test of the parity flag,
1041 * which indicates that the result is unordered */
1042 if (cc & ia32_cc_negated) {
1043 ia32_emitf(proj_true, "\tjp %L\n");
1045 /* we need a local label if the false proj is a fallthrough
1046 * as the falseblock might have no label emitted then */
1047 if (can_be_fallthrough(proj_false)) {
1048 need_parity_label = 1;
1049 ia32_emitf(proj_false, "\tjp 1f\n");
1051 ia32_emitf(proj_false, "\tjp %L\n");
1055 ia32_emitf(proj_true, "\tj%P %L\n", cc);
1056 if (need_parity_label) {
1057 ia32_emitf(NULL, "1:\n");
1060 /* the second Proj might be a fallthrough */
1061 if (can_be_fallthrough(proj_false)) {
1062 ia32_emitf(proj_false, "\t/* fallthrough to %L */\n");
1064 ia32_emitf(proj_false, "\tjmp %L\n");
1069 * Emits an ia32 Setcc. This is mostly easy but some floating point compares
1072 static void emit_ia32_Setcc(const ir_node *node)
1074 const arch_register_t *dreg = get_out_reg(node, pn_ia32_Setcc_res);
1076 ia32_condition_code_t cc = get_ia32_condcode(node);
1077 cc = determine_final_cc(node, n_ia32_Setcc_eflags, cc);
1078 if (cc & ia32_cc_float_parity_cases) {
1079 if (cc & ia32_cc_negated) {
1080 ia32_emitf(node, "\tset%P %<R\n", cc, dreg);
1081 ia32_emitf(node, "\tsetp %>R\n", dreg);
1082 ia32_emitf(node, "\torb %>R, %<R\n", dreg, dreg);
1084 ia32_emitf(node, "\tset%P %<R\n", cc, dreg);
1085 ia32_emitf(node, "\tsetnp %>R\n", dreg);
1086 ia32_emitf(node, "\tandb %>R, %<R\n", dreg, dreg);
1089 ia32_emitf(node, "\tset%P %#R\n", cc, dreg);
1093 static void emit_ia32_CMovcc(const ir_node *node)
1095 const ia32_attr_t *attr = get_ia32_attr_const(node);
1096 const arch_register_t *out = arch_irn_get_register(node, pn_ia32_res);
1097 ia32_condition_code_t cc = get_ia32_condcode(node);
1098 const arch_register_t *in_true;
1099 const arch_register_t *in_false;
1101 cc = determine_final_cc(node, n_ia32_CMovcc_eflags, cc);
1102 /* although you can't set ins_permuted in the constructor it might still
1103 * be set by memory operand folding
1104 * Permuting inputs of a cmov means the condition is negated!
1106 if (attr->data.ins_permuted)
1107 cc = ia32_negate_condition_code(cc);
1109 in_true = arch_get_irn_register(get_irn_n(node, n_ia32_CMovcc_val_true));
1110 in_false = arch_get_irn_register(get_irn_n(node, n_ia32_CMovcc_val_false));
1112 /* should be same constraint fullfilled? */
1113 if (out == in_false) {
1114 /* yes -> nothing to do */
1115 } else if (out == in_true) {
1116 const arch_register_t *tmp;
1118 assert(get_ia32_op_type(node) == ia32_Normal);
1120 cc = ia32_negate_condition_code(cc);
1127 ia32_emitf(node, "\tmovl %R, %R\n", in_false, out);
1130 if (cc & ia32_cc_float_parity_cases) {
1131 panic("CMov with floatingpoint compare/parity not supported yet");
1134 ia32_emitf(node, "\tcmov%P %#AR, %#R\n", cc, in_true, out);
1138 /* jump table entry (target and corresponding number) */
1139 typedef struct branch_t {
1144 /* jump table for switch generation */
1145 typedef struct jmp_tbl_t {
1146 ir_node *defProj; /**< default target */
1147 long min_value; /**< smallest switch case */
1148 long max_value; /**< largest switch case */
1149 long num_branches; /**< number of jumps */
1150 char label[SNPRINTF_BUF_LEN]; /**< label of the jump table */
1151 branch_t *branches; /**< jump array */
1155 * Compare two variables of type branch_t. Used to sort all switch cases
1157 static int ia32_cmp_branch_t(const void *a, const void *b)
1159 branch_t *b1 = (branch_t *)a;
1160 branch_t *b2 = (branch_t *)b;
1162 if (b1->value <= b2->value)
1168 static void generate_jump_table(jmp_tbl_t *tbl, const ir_node *node)
1171 long default_pn = get_ia32_default_pn(node);
1173 const ir_edge_t *edge;
1175 /* fill the table structure */
1176 get_unique_label(tbl->label, SNPRINTF_BUF_LEN, "TBL_");
1177 tbl->defProj = NULL;
1178 tbl->num_branches = get_irn_n_edges(node) - 1;
1179 tbl->branches = XMALLOCNZ(branch_t, tbl->num_branches);
1180 tbl->min_value = LONG_MAX;
1181 tbl->max_value = LONG_MIN;
1184 /* go over all proj's and collect them */
1185 foreach_out_edge(node, edge) {
1187 proj = get_edge_src_irn(edge);
1188 assert(is_Proj(proj) && "Only proj allowed at SwitchJmp");
1190 pn = get_Proj_proj(proj);
1192 /* check for default proj */
1193 if (pn == default_pn) {
1194 assert(tbl->defProj == NULL && "found two default Projs at SwitchJmp");
1195 tbl->defProj = proj;
1197 tbl->min_value = pn < tbl->min_value ? pn : tbl->min_value;
1198 tbl->max_value = pn > tbl->max_value ? pn : tbl->max_value;
1200 /* create branch entry */
1201 tbl->branches[i].target = proj;
1202 tbl->branches[i].value = pn;
1207 assert(i == tbl->num_branches);
1209 /* sort the branches by their number */
1210 qsort(tbl->branches, tbl->num_branches, sizeof(tbl->branches[0]), ia32_cmp_branch_t);
1214 * Emits code for a SwitchJmp (creates a jump table if
1215 * possible otherwise a cmp-jmp cascade). Port from
1218 static void emit_ia32_SwitchJmp(const ir_node *node)
1220 unsigned long interval;
1224 /* fill the table structure */
1225 generate_jump_table(&tbl, node);
1227 /* two-complement's magic make this work without overflow */
1228 interval = tbl.max_value - tbl.min_value;
1230 /* emit the table */
1231 ia32_emitf(node, "\tcmpl $%u, %S0\n", interval);
1232 ia32_emitf(tbl.defProj, "\tja %L\n");
1234 if (tbl.num_branches > 1) {
1236 ia32_emitf(node, "\tjmp *%s(,%S0,4)\n", tbl.label);
1238 be_gas_emit_switch_section(GAS_SECTION_RODATA);
1239 ia32_emitf(NULL, "\t.align 4\n");
1240 ia32_emitf(NULL, "%s:\n", tbl.label);
1242 last_value = tbl.branches[0].value;
1243 for (i = 0; i != tbl.num_branches; ++i) {
1244 while (last_value != tbl.branches[i].value) {
1245 ia32_emitf(tbl.defProj, ".long %L\n");
1248 ia32_emitf(tbl.branches[i].target, ".long %L\n");
1251 be_gas_emit_switch_section(GAS_SECTION_TEXT);
1253 /* one jump is enough */
1254 ia32_emitf(tbl.branches[0].target, "\tjmp %L\n");
1261 * Emits code for a unconditional jump.
1263 static void emit_ia32_Jmp(const ir_node *node)
1267 /* for now, the code works for scheduled and non-schedules blocks */
1268 block = get_nodes_block(node);
1270 /* we have a block schedule */
1271 if (can_be_fallthrough(node)) {
1272 ia32_emitf(node, "\t/* fallthrough to %L */\n");
1274 ia32_emitf(node, "\tjmp %L\n");
1279 * Emit an inline assembler operand.
1281 * @param node the ia32_ASM node
1282 * @param s points to the operand (a %c)
1284 * @return pointer to the first char in s NOT in the current operand
1286 static const char* emit_asm_operand(const ir_node *node, const char *s)
1288 const ia32_attr_t *ia32_attr = get_ia32_attr_const(node);
1289 const ia32_asm_attr_t *attr = CONST_CAST_IA32_ATTR(ia32_asm_attr_t,
1291 const arch_register_t *reg;
1292 const ia32_asm_reg_t *asm_regs = attr->register_map;
1293 const ia32_asm_reg_t *asm_reg;
1302 /* parse modifiers */
1305 ir_fprintf(stderr, "Warning: asm text (%+F) ends with %%\n", node);
1330 "Warning: asm text (%+F) contains unknown modifier '%c' for asm op\n",
1337 if (sscanf(s, "%d%n", &num, &p) != 1) {
1338 ir_fprintf(stderr, "Warning: Couldn't parse assembler operand (%+F)\n",
1345 if (num < 0 || ARR_LEN(asm_regs) <= (size_t)num) {
1347 "Error: Custom assembler references invalid input/output (%+F)\n",
1351 asm_reg = & asm_regs[num];
1352 assert(asm_reg->valid);
1355 if (asm_reg->use_input == 0) {
1356 reg = get_out_reg(node, asm_reg->inout_pos);
1358 ir_node *pred = get_irn_n(node, asm_reg->inout_pos);
1360 /* might be an immediate value */
1361 if (is_ia32_Immediate(pred)) {
1362 emit_ia32_Immediate(pred);
1365 reg = get_in_reg(node, asm_reg->inout_pos);
1369 "Warning: no register assigned for %d asm op (%+F)\n",
1374 if (asm_reg->memory) {
1379 if (modifier != 0) {
1382 emit_8bit_register(reg);
1385 emit_8bit_register_high(reg);
1388 emit_16bit_register(reg);
1391 panic("Invalid asm op modifier");
1394 emit_register(reg, asm_reg->mode);
1397 if (asm_reg->memory) {
1405 * Emits code for an ASM pseudo op.
1407 static void emit_ia32_Asm(const ir_node *node)
1409 const void *gen_attr = get_irn_generic_attr_const(node);
1410 const ia32_asm_attr_t *attr
1411 = CONST_CAST_IA32_ATTR(ia32_asm_attr_t, gen_attr);
1412 ident *asm_text = attr->asm_text;
1413 const char *s = get_id_str(asm_text);
1415 ia32_emitf(node, "#APP\t\n");
1422 s = emit_asm_operand(node, s);
1428 ia32_emitf(NULL, "\n#NO_APP\n");
1433 * Emit movsb/w instructions to make mov count divideable by 4
1435 static void emit_CopyB_prolog(unsigned size)
1438 ia32_emitf(NULL, "\tmovsb\n");
1440 ia32_emitf(NULL, "\tmovsw\n");
1444 * Emit rep movsd instruction for memcopy.
1446 static void emit_ia32_CopyB(const ir_node *node)
1448 unsigned size = get_ia32_copyb_size(node);
1450 emit_CopyB_prolog(size);
1451 ia32_emitf(node, "\trep movsd\n");
1455 * Emits unrolled memcopy.
1457 static void emit_ia32_CopyB_i(const ir_node *node)
1459 unsigned size = get_ia32_copyb_size(node);
1461 emit_CopyB_prolog(size);
1465 ia32_emitf(NULL, "\tmovsd\n");
1471 * Emit code for conversions (I, FP), (FP, I) and (FP, FP).
1473 static void emit_ia32_Conv_with_FP(const ir_node *node, const char* conv_f,
1476 ir_mode *ls_mode = get_ia32_ls_mode(node);
1477 int ls_bits = get_mode_size_bits(ls_mode);
1478 const char *conv = ls_bits == 32 ? conv_f : conv_d;
1480 ia32_emitf(node, "\tcvt%s %AS3, %D0\n", conv);
1483 static void emit_ia32_Conv_I2FP(const ir_node *node)
1485 emit_ia32_Conv_with_FP(node, "si2ss", "si2sd");
1488 static void emit_ia32_Conv_FP2I(const ir_node *node)
1490 emit_ia32_Conv_with_FP(node, "ss2si", "sd2si");
1493 static void emit_ia32_Conv_FP2FP(const ir_node *node)
1495 emit_ia32_Conv_with_FP(node, "sd2ss", "ss2sd");
1499 * Emits code for an Int conversion.
1501 static void emit_ia32_Conv_I2I(const ir_node *node)
1503 ir_mode *smaller_mode = get_ia32_ls_mode(node);
1504 int signed_mode = mode_is_signed(smaller_mode);
1505 const char *sign_suffix;
1507 assert(!mode_is_float(smaller_mode));
1509 sign_suffix = signed_mode ? "s" : "z";
1510 ia32_emitf(node, "\tmov%s%Ml %#AS3, %D0\n", sign_suffix);
1516 static void emit_ia32_Call(const ir_node *node)
1518 /* Special case: Call must not have its immediates prefixed by $, instead
1519 * address mode is prefixed by *. */
1520 ia32_emitf(node, "\tcall %*AS3\n");
1525 * Emits code to increase stack pointer.
1527 static void emit_be_IncSP(const ir_node *node)
1529 int offs = be_get_IncSP_offset(node);
1535 ia32_emitf(node, "\tsubl $%u, %D0\n", offs);
1537 ia32_emitf(node, "\taddl $%u, %D0\n", -offs);
1542 * Emits code for Copy/CopyKeep.
1544 static void Copy_emitter(const ir_node *node, const ir_node *op)
1546 const arch_register_t *in = arch_get_irn_register(op);
1547 const arch_register_t *out = arch_get_irn_register(node);
1552 /* copies of vf nodes aren't real... */
1553 if (arch_register_get_class(in) == &ia32_reg_classes[CLASS_ia32_vfp])
1556 if (get_irn_mode(node) == mode_E) {
1557 ia32_emitf(node, "\tmovsd %R, %R\n", in, out);
1559 ia32_emitf(node, "\tmovl %R, %R\n", in, out);
1563 static void emit_be_Copy(const ir_node *node)
1565 Copy_emitter(node, be_get_Copy_op(node));
1568 static void emit_be_CopyKeep(const ir_node *node)
1570 Copy_emitter(node, be_get_CopyKeep_op(node));
1574 * Emits code for exchange.
1576 static void emit_be_Perm(const ir_node *node)
1578 const arch_register_t *in0, *in1;
1579 const arch_register_class_t *cls0, *cls1;
1581 in0 = arch_get_irn_register(get_irn_n(node, 0));
1582 in1 = arch_get_irn_register(get_irn_n(node, 1));
1584 cls0 = arch_register_get_class(in0);
1585 cls1 = arch_register_get_class(in1);
1587 assert(cls0 == cls1 && "Register class mismatch at Perm");
1589 if (cls0 == &ia32_reg_classes[CLASS_ia32_gp]) {
1590 ia32_emitf(node, "\txchg %R, %R\n", in1, in0);
1591 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_xmm]) {
1592 ia32_emitf(NULL, "\txorpd %R, %R\n", in1, in0);
1593 ia32_emitf(NULL, "\txorpd %R, %R\n", in0, in1);
1594 ia32_emitf(node, "\txorpd %R, %R\n", in1, in0);
1595 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_vfp]) {
1597 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_st]) {
1600 panic("unexpected register class in be_Perm (%+F)", node);
1605 * Emits code for Constant loading.
1607 static void emit_ia32_Const(const ir_node *node)
1609 ia32_emitf(node, "\tmovl %I, %D0\n");
1612 /* helper function for emit_ia32_Minus64Bit */
1613 static void emit_mov(const ir_node* node, const arch_register_t *src, const arch_register_t *dst)
1615 ia32_emitf(node, "\tmovl %R, %R\n", src, dst);
1618 /* helper function for emit_ia32_Minus64Bit */
1619 static void emit_neg(const ir_node* node, const arch_register_t *reg)
1621 ia32_emitf(node, "\tnegl %R\n", reg);
1624 /* helper function for emit_ia32_Minus64Bit */
1625 static void emit_sbb0(const ir_node* node, const arch_register_t *reg)
1627 ia32_emitf(node, "\tsbbl $0, %R\n", reg);
1630 /* helper function for emit_ia32_Minus64Bit */
1631 static void emit_sbb(const ir_node* node, const arch_register_t *src, const arch_register_t *dst)
1633 ia32_emitf(node, "\tsbbl %R, %R\n", src, dst);
1636 /* helper function for emit_ia32_Minus64Bit */
1637 static void emit_xchg(const ir_node* node, const arch_register_t *src, const arch_register_t *dst)
1639 ia32_emitf(node, "\txchgl %R, %R\n", src, dst);
1642 /* helper function for emit_ia32_Minus64Bit */
1643 static void emit_zero(const ir_node* node, const arch_register_t *reg)
1645 ia32_emitf(node, "\txorl %R, %R\n", reg, reg);
1648 static void emit_ia32_Minus64Bit(const ir_node *node)
1650 const arch_register_t *in_lo = get_in_reg(node, 0);
1651 const arch_register_t *in_hi = get_in_reg(node, 1);
1652 const arch_register_t *out_lo = get_out_reg(node, 0);
1653 const arch_register_t *out_hi = get_out_reg(node, 1);
1655 if (out_lo == in_lo) {
1656 if (out_hi != in_hi) {
1657 /* a -> a, b -> d */
1660 /* a -> a, b -> b */
1663 } else if (out_lo == in_hi) {
1664 if (out_hi == in_lo) {
1665 /* a -> b, b -> a */
1666 emit_xchg(node, in_lo, in_hi);
1669 /* a -> b, b -> d */
1670 emit_mov(node, in_hi, out_hi);
1671 emit_mov(node, in_lo, out_lo);
1675 if (out_hi == in_lo) {
1676 /* a -> c, b -> a */
1677 emit_mov(node, in_lo, out_lo);
1679 } else if (out_hi == in_hi) {
1680 /* a -> c, b -> b */
1681 emit_mov(node, in_lo, out_lo);
1684 /* a -> c, b -> d */
1685 emit_mov(node, in_lo, out_lo);
1691 emit_neg( node, out_hi);
1692 emit_neg( node, out_lo);
1693 emit_sbb0(node, out_hi);
1697 emit_zero(node, out_hi);
1698 emit_neg( node, out_lo);
1699 emit_sbb( node, in_hi, out_hi);
1702 static void emit_ia32_GetEIP(const ir_node *node)
1704 ia32_emitf(node, "\tcall %s\n", pic_base_label);
1705 ia32_emitf(NULL, "%s:\n", pic_base_label);
1706 ia32_emitf(node, "\tpopl %D0\n");
1709 static void emit_ia32_ClimbFrame(const ir_node *node)
1711 const ia32_climbframe_attr_t *attr = get_ia32_climbframe_attr_const(node);
1713 ia32_emitf(node, "\tmovl %S0, %D0\n");
1714 ia32_emitf(node, "\tmovl $%u, %S1\n", attr->count);
1715 be_gas_emit_block_name(node);
1716 be_emit_cstring(":\n");
1717 be_emit_write_line();
1718 ia32_emitf(node, "\tmovl (%D0), %D0\n");
1719 ia32_emitf(node, "\tdec %S1\n");
1720 be_emit_cstring("\tjnz ");
1721 be_gas_emit_block_name(node);
1722 be_emit_finish_line_gas(node);
1725 static void emit_be_Return(const ir_node *node)
1727 unsigned pop = be_Return_get_pop(node);
1729 if (pop > 0 || be_Return_get_emit_pop(node)) {
1730 ia32_emitf(node, "\tret $%u\n", pop);
1732 ia32_emitf(node, "\tret\n");
1736 static void emit_Nothing(const ir_node *node)
1743 * Enters the emitter functions for handled nodes into the generic
1744 * pointer of an opcode.
1746 static void ia32_register_emitters(void)
1748 #define IA32_EMIT2(a,b) op_ia32_##a->ops.generic = (op_func)emit_ia32_##b
1749 #define IA32_EMIT(a) IA32_EMIT2(a,a)
1750 #define EMIT(a) op_##a->ops.generic = (op_func)emit_##a
1751 #define IGN(a) op_##a->ops.generic = (op_func)emit_Nothing
1752 #define BE_EMIT(a) op_be_##a->ops.generic = (op_func)emit_be_##a
1753 #define BE_IGN(a) op_be_##a->ops.generic = (op_func)emit_Nothing
1755 /* first clear the generic function pointer for all ops */
1756 clear_irp_opcodes_generic_func();
1758 /* register all emitter functions defined in spec */
1759 ia32_register_spec_emitters();
1761 /* other ia32 emitter functions */
1762 IA32_EMIT2(Conv_I2I8Bit, Conv_I2I);
1767 IA32_EMIT(Conv_FP2FP);
1768 IA32_EMIT(Conv_FP2I);
1769 IA32_EMIT(Conv_I2FP);
1770 IA32_EMIT(Conv_I2I);
1777 IA32_EMIT(Minus64Bit);
1778 IA32_EMIT(SwitchJmp);
1779 IA32_EMIT(ClimbFrame);
1782 /* benode emitter */
1802 typedef void (*emit_func_ptr) (const ir_node *);
1805 * Assign and emit an exception label if the current instruction can fail.
1807 static void ia32_assign_exc_label(ir_node *node)
1809 /* assign a new ID to the instruction */
1810 set_ia32_exc_label_id(node, ++exc_label_id);
1812 ia32_emit_exc_label(node);
1814 be_emit_pad_comment();
1815 be_emit_cstring("/* exception to Block ");
1816 ia32_emit_cfop_target(node);
1817 be_emit_cstring(" */\n");
1818 be_emit_write_line();
1822 * Emits code for a node.
1824 static void ia32_emit_node(ir_node *node)
1826 ir_op *op = get_irn_op(node);
1828 DBG((dbg, LEVEL_1, "emitting code for %+F\n", node));
1830 if (is_ia32_irn(node)) {
1831 if (get_ia32_exc_label(node)) {
1832 /* emit the exception label of this instruction */
1833 ia32_assign_exc_label(node);
1835 if (mark_spill_reload) {
1836 if (is_ia32_is_spill(node)) {
1837 ia32_emitf(NULL, "\txchg %ebx, %ebx /* spill mark */\n");
1839 if (is_ia32_is_reload(node)) {
1840 ia32_emitf(NULL, "\txchg %edx, %edx /* reload mark */\n");
1842 if (is_ia32_is_remat(node)) {
1843 ia32_emitf(NULL, "\txchg %ecx, %ecx /* remat mark */\n");
1847 if (op->ops.generic) {
1848 emit_func_ptr func = (emit_func_ptr) op->ops.generic;
1850 be_dbg_set_dbg_info(get_irn_dbg_info(node));
1855 ir_fprintf(stderr, "Error: No emit handler for node %+F (%+G, graph %+F)\n", node, node, current_ir_graph);
1861 * Emits gas alignment directives
1863 static void ia32_emit_alignment(unsigned align, unsigned skip)
1865 ia32_emitf(NULL, "\t.p2align %u,,%u\n", align, skip);
1869 * Emits gas alignment directives for Labels depended on cpu architecture.
1871 static void ia32_emit_align_label(void)
1873 unsigned align = ia32_cg_config.label_alignment;
1874 unsigned maximum_skip = ia32_cg_config.label_alignment_max_skip;
1875 ia32_emit_alignment(align, maximum_skip);
1879 * Test whether a block should be aligned.
1880 * For cpus in the P4/Athlon class it is useful to align jump labels to
1881 * 16 bytes. However we should only do that if the alignment nops before the
1882 * label aren't executed more often than we have jumps to the label.
1884 static int should_align_block(const ir_node *block)
1886 static const double DELTA = .0001;
1887 ir_graph *irg = get_irn_irg(block);
1888 ir_exec_freq *exec_freq = be_get_irg_exec_freq(irg);
1889 ir_node *prev = get_prev_block_sched(block);
1891 double prev_freq = 0; /**< execfreq of the fallthrough block */
1892 double jmp_freq = 0; /**< execfreq of all non-fallthrough blocks */
1895 if (exec_freq == NULL)
1897 if (ia32_cg_config.label_alignment_factor <= 0)
1900 block_freq = get_block_execfreq(exec_freq, block);
1901 if (block_freq < DELTA)
1904 n_cfgpreds = get_Block_n_cfgpreds(block);
1905 for (i = 0; i < n_cfgpreds; ++i) {
1906 const ir_node *pred = get_Block_cfgpred_block(block, i);
1907 double pred_freq = get_block_execfreq(exec_freq, pred);
1910 prev_freq += pred_freq;
1912 jmp_freq += pred_freq;
1916 if (prev_freq < DELTA && !(jmp_freq < DELTA))
1919 jmp_freq /= prev_freq;
1921 return jmp_freq > ia32_cg_config.label_alignment_factor;
1925 * Emit the block header for a block.
1927 * @param block the block
1928 * @param prev_block the previous block
1930 static void ia32_emit_block_header(ir_node *block)
1932 ir_graph *irg = current_ir_graph;
1933 int need_label = block_needs_label(block);
1935 ir_exec_freq *exec_freq = be_get_irg_exec_freq(irg);
1937 if (block == get_irg_end_block(irg))
1940 if (ia32_cg_config.label_alignment > 0) {
1941 /* align the current block if:
1942 * a) if should be aligned due to its execution frequency
1943 * b) there is no fall-through here
1945 if (should_align_block(block)) {
1946 ia32_emit_align_label();
1948 /* if the predecessor block has no fall-through,
1949 we can always align the label. */
1951 int has_fallthrough = 0;
1953 for (i = get_Block_n_cfgpreds(block) - 1; i >= 0; --i) {
1954 ir_node *cfg_pred = get_Block_cfgpred(block, i);
1955 if (can_be_fallthrough(cfg_pred)) {
1956 has_fallthrough = 1;
1961 if (!has_fallthrough)
1962 ia32_emit_align_label();
1967 be_gas_emit_block_name(block);
1970 be_emit_pad_comment();
1971 be_emit_cstring(" /* ");
1973 be_emit_cstring("\t/* ");
1974 be_gas_emit_block_name(block);
1975 be_emit_cstring(": ");
1978 be_emit_cstring("preds:");
1980 /* emit list of pred blocks in comment */
1981 arity = get_irn_arity(block);
1983 be_emit_cstring(" none");
1985 for (i = 0; i < arity; ++i) {
1986 ir_node *predblock = get_Block_cfgpred_block(block, i);
1987 be_emit_irprintf(" %d", get_irn_node_nr(predblock));
1990 if (exec_freq != NULL) {
1991 be_emit_irprintf(", freq: %f",
1992 get_block_execfreq(exec_freq, block));
1994 be_emit_cstring(" */\n");
1995 be_emit_write_line();
1999 * Walks over the nodes in a block connected by scheduling edges
2000 * and emits code for each node.
2002 static void ia32_gen_block(ir_node *block)
2006 ia32_emit_block_header(block);
2008 /* emit the contents of the block */
2009 be_dbg_set_dbg_info(get_irn_dbg_info(block));
2010 sched_foreach(block, node) {
2011 ia32_emit_node(node);
2015 typedef struct exc_entry {
2016 ir_node *exc_instr; /** The instruction that can issue an exception. */
2017 ir_node *block; /** The block to call then. */
2022 * Sets labels for control flow nodes (jump target).
2023 * Links control predecessors to there destination blocks.
2025 static void ia32_gen_labels(ir_node *block, void *data)
2027 exc_entry **exc_list = (exc_entry**)data;
2031 for (n = get_Block_n_cfgpreds(block) - 1; n >= 0; --n) {
2032 pred = get_Block_cfgpred(block, n);
2033 set_irn_link(pred, block);
2035 pred = skip_Proj(pred);
2036 if (is_ia32_irn(pred) && get_ia32_exc_label(pred)) {
2041 ARR_APP1(exc_entry, *exc_list, e);
2042 set_irn_link(pred, block);
2048 * Compare two exception_entries.
2050 static int cmp_exc_entry(const void *a, const void *b)
2052 const exc_entry *ea = (const exc_entry*)a;
2053 const exc_entry *eb = (const exc_entry*)b;
2055 if (get_ia32_exc_label_id(ea->exc_instr) < get_ia32_exc_label_id(eb->exc_instr))
2061 * Main driver. Emits the code for one routine.
2063 void ia32_gen_routine(ir_graph *irg)
2065 ir_entity *entity = get_irg_entity(irg);
2066 exc_entry *exc_list = NEW_ARR_F(exc_entry, 0);
2067 const arch_env_t *arch_env = be_get_irg_arch_env(irg);
2068 ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
2069 ir_node **blk_sched = irg_data->blk_sched;
2072 isa = (ia32_isa_t*) arch_env;
2073 do_pic = be_get_irg_options(irg)->pic;
2075 be_gas_elf_type_char = '@';
2077 ia32_register_emitters();
2079 get_unique_label(pic_base_label, sizeof(pic_base_label), "PIC_BASE");
2081 be_dbg_method_begin(entity);
2082 be_gas_emit_function_prolog(entity, ia32_cg_config.function_alignment);
2084 /* we use links to point to target blocks */
2085 ir_reserve_resources(irg, IR_RESOURCE_IRN_LINK);
2086 irg_block_walk_graph(irg, ia32_gen_labels, NULL, &exc_list);
2088 /* initialize next block links */
2089 n = ARR_LEN(blk_sched);
2090 for (i = 0; i < n; ++i) {
2091 ir_node *block = blk_sched[i];
2092 ir_node *prev = i > 0 ? blk_sched[i-1] : NULL;
2094 set_irn_link(block, prev);
2097 for (i = 0; i < n; ++i) {
2098 ir_node *block = blk_sched[i];
2100 ia32_gen_block(block);
2103 be_gas_emit_function_epilog(entity);
2104 be_dbg_method_end();
2106 be_emit_write_line();
2108 ir_free_resources(irg, IR_RESOURCE_IRN_LINK);
2110 /* Sort the exception table using the exception label id's.
2111 Those are ascending with ascending addresses. */
2112 qsort(exc_list, ARR_LEN(exc_list), sizeof(exc_list[0]), cmp_exc_entry);
2116 for (i = 0; i < ARR_LEN(exc_list); ++i) {
2117 be_emit_cstring("\t.long ");
2118 ia32_emit_exc_label(exc_list[i].exc_instr);
2120 be_emit_cstring("\t.long ");
2121 be_gas_emit_block_name(exc_list[i].block);
2125 DEL_ARR_F(exc_list);
2128 static const lc_opt_table_entry_t ia32_emitter_options[] = {
2129 LC_OPT_ENT_BOOL("mark_spill_reload", "mark spills and reloads with ud opcodes", &mark_spill_reload),
2133 /* ==== Experimental binary emitter ==== */
2135 static unsigned char reg_gp_map[N_ia32_gp_REGS];
2136 //static unsigned char reg_mmx_map[N_ia32_mmx_REGS];
2137 //static unsigned char reg_sse_map[N_ia32_xmm_REGS];
2139 static void build_reg_map(void)
2141 reg_gp_map[REG_GP_EAX] = 0x0;
2142 reg_gp_map[REG_GP_ECX] = 0x1;
2143 reg_gp_map[REG_GP_EDX] = 0x2;
2144 reg_gp_map[REG_GP_EBX] = 0x3;
2145 reg_gp_map[REG_GP_ESP] = 0x4;
2146 reg_gp_map[REG_GP_EBP] = 0x5;
2147 reg_gp_map[REG_GP_ESI] = 0x6;
2148 reg_gp_map[REG_GP_EDI] = 0x7;
2151 /** Returns the encoding for a pnc field. */
2152 static unsigned char pnc2cc(ia32_condition_code_t cc)
2157 /** Sign extension bit values for binops */
2159 UNSIGNED_IMM = 0, /**< unsigned immediate */
2160 SIGNEXT_IMM = 2, /**< sign extended immediate */
2163 /** The mod encoding of the ModR/M */
2165 MOD_IND = 0x00, /**< [reg1] */
2166 MOD_IND_BYTE_OFS = 0x40, /**< [reg1 + byte ofs] */
2167 MOD_IND_WORD_OFS = 0x80, /**< [reg1 + word ofs] */
2168 MOD_REG = 0xC0 /**< reg1 */
2171 /** create R/M encoding for ModR/M */
2172 #define ENC_RM(x) (x)
2173 /** create REG encoding for ModR/M */
2174 #define ENC_REG(x) ((x) << 3)
2176 /** create encoding for a SIB byte */
2177 #define ENC_SIB(scale, index, base) ((scale) << 6 | (index) << 3 | (base))
2179 /* Node: The following routines are supposed to append bytes, words, dwords
2180 to the output stream.
2181 Currently the implementation is stupid in that it still creates output
2182 for an "assembler" in the form of .byte, .long
2183 We will change this when enough infrastructure is there to create complete
2184 machine code in memory/object files */
2186 static void bemit8(const unsigned char byte)
2188 be_emit_irprintf("\t.byte 0x%x\n", byte);
2189 be_emit_write_line();
2192 static void bemit16(const unsigned short u16)
2194 be_emit_irprintf("\t.word 0x%x\n", u16);
2195 be_emit_write_line();
2198 static void bemit32(const unsigned u32)
2200 be_emit_irprintf("\t.long 0x%x\n", u32);
2201 be_emit_write_line();
2205 * Emit address of an entity. If @p is_relative is true then a relative
2206 * offset from behind the address to the entity is created.
2208 static void bemit_entity(ir_entity *entity, bool entity_sign, int offset,
2211 if (entity == NULL) {
2216 /* the final version should remember the position in the bytestream
2217 and patch it with the correct address at linktime... */
2218 be_emit_cstring("\t.long ");
2221 be_gas_emit_entity(entity);
2223 if (get_entity_owner(entity) == get_tls_type()) {
2224 if (get_entity_visibility(entity) == ir_visibility_external) {
2225 be_emit_cstring("@INDNTPOFF");
2227 be_emit_cstring("@NTPOFF");
2232 be_emit_cstring("-.");
2237 be_emit_irprintf("%+d", offset);
2240 be_emit_write_line();
2243 static void bemit_jmp_destination(const ir_node *dest_block)
2245 be_emit_cstring("\t.long ");
2246 be_gas_emit_block_name(dest_block);
2247 be_emit_cstring(" - . - 4\n");
2248 be_emit_write_line();
2251 /* end emit routines, all emitters following here should only use the functions
2254 typedef enum reg_modifier {
2259 /** Create a ModR/M byte for src1,src2 registers */
2260 static void bemit_modrr(const arch_register_t *src1,
2261 const arch_register_t *src2)
2263 unsigned char modrm = MOD_REG;
2264 modrm |= ENC_RM(reg_gp_map[src1->index]);
2265 modrm |= ENC_REG(reg_gp_map[src2->index]);
2269 /** Create a ModR/M8 byte for src1,src2 registers */
2270 static void bemit_modrr8(reg_modifier_t high_part1, const arch_register_t *src1,
2271 reg_modifier_t high_part2, const arch_register_t *src2)
2273 unsigned char modrm = MOD_REG;
2274 modrm |= ENC_RM(reg_gp_map[src1->index] + (high_part1 == REG_HIGH ? 4 : 0));
2275 modrm |= ENC_REG(reg_gp_map[src2->index] + (high_part2 == REG_HIGH ? 4 : 0));
2279 /** Create a ModR/M byte for one register and extension */
2280 static void bemit_modru(const arch_register_t *reg, unsigned ext)
2282 unsigned char modrm = MOD_REG;
2284 modrm |= ENC_RM(reg_gp_map[reg->index]);
2285 modrm |= ENC_REG(ext);
2289 /** Create a ModR/M8 byte for one register */
2290 static void bemit_modrm8(reg_modifier_t high_part, const arch_register_t *reg)
2292 unsigned char modrm = MOD_REG;
2293 assert(reg_gp_map[reg->index] < 4);
2294 modrm |= ENC_RM(reg_gp_map[reg->index] + (high_part == REG_HIGH ? 4 : 0));
2300 * Calculate the size of an signed immediate in bytes.
2302 * @param offset an offset
2304 static unsigned get_signed_imm_size(int offset)
2306 if (-128 <= offset && offset < 128) {
2308 } else if (-32768 <= offset && offset < 32768) {
2316 * Emit an address mode.
2318 * @param reg content of the reg field: either a register index or an opcode extension
2319 * @param node the node
2321 static void bemit_mod_am(unsigned reg, const ir_node *node)
2323 ir_entity *ent = get_ia32_am_sc(node);
2324 int offs = get_ia32_am_offs_int(node);
2325 ir_node *base = get_irn_n(node, n_ia32_base);
2326 int has_base = !is_ia32_NoReg_GP(base);
2327 ir_node *index = get_irn_n(node, n_ia32_index);
2328 int has_index = !is_ia32_NoReg_GP(index);
2331 unsigned emitoffs = 0;
2332 bool emitsib = false;
2335 /* set the mod part depending on displacement */
2337 modrm |= MOD_IND_WORD_OFS;
2339 } else if (offs == 0) {
2342 } else if (-128 <= offs && offs < 128) {
2343 modrm |= MOD_IND_BYTE_OFS;
2346 modrm |= MOD_IND_WORD_OFS;
2351 const arch_register_t *base_reg = arch_get_irn_register(base);
2352 base_enc = reg_gp_map[base_reg->index];
2354 /* Use the EBP encoding + MOD_IND if NO base register. There is
2355 * always a 32bit offset present in this case. */
2361 /* Determine if we need a SIB byte. */
2363 const arch_register_t *reg_index = arch_get_irn_register(index);
2364 int scale = get_ia32_am_scale(node);
2366 /* R/M set to ESP means SIB in 32bit mode. */
2367 modrm |= ENC_RM(0x04);
2368 sib = ENC_SIB(scale, reg_gp_map[reg_index->index], base_enc);
2370 } else if (base_enc == 0x04) {
2371 /* for the above reason we are forced to emit a SIB when base is ESP.
2372 * Only the base is used, index must be ESP too, which means no index.
2374 modrm |= ENC_RM(0x04);
2375 sib = ENC_SIB(0, 0x04, 0x04);
2378 modrm |= ENC_RM(base_enc);
2381 /* We are forced to emit an 8bit offset as EBP base without offset is a
2382 * special case for SIB without base register. */
2383 if (base_enc == 0x05 && emitoffs == 0) {
2384 modrm |= MOD_IND_BYTE_OFS;
2388 modrm |= ENC_REG(reg);
2394 /* emit displacement */
2395 if (emitoffs == 8) {
2396 bemit8((unsigned) offs);
2397 } else if (emitoffs == 32) {
2398 bemit_entity(ent, is_ia32_am_sc_sign(node), offs, false);
2403 * Emit a binop with a immediate operand.
2405 * @param node the node to emit
2406 * @param opcode_eax the opcode for the op eax, imm variant
2407 * @param opcode the opcode for the reg, imm variant
2408 * @param ruval the opcode extension for opcode
2410 static void bemit_binop_with_imm(
2411 const ir_node *node,
2412 unsigned char opcode_ax,
2413 unsigned char opcode, unsigned char ruval)
2415 /* Use in-reg, because some instructions (cmp, test) have no out-reg. */
2416 const ir_node *op = get_irn_n(node, n_ia32_binary_right);
2417 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(op);
2420 /* Some instructions (test) have no short form with 32bit value + 8bit
2422 if (attr->symconst != NULL || opcode & SIGNEXT_IMM) {
2425 /* check for sign extension */
2426 size = get_signed_imm_size(attr->offset);
2431 bemit8(opcode | SIGNEXT_IMM);
2432 /* cmp has this special mode */
2433 if (get_ia32_op_type(node) == ia32_AddrModeS) {
2434 bemit_mod_am(ruval, node);
2436 const arch_register_t *reg = get_in_reg(node, n_ia32_binary_left);
2437 bemit_modru(reg, ruval);
2439 bemit8((unsigned char)attr->offset);
2443 /* check for eax variant: this variant is shorter for 32bit immediates only */
2444 if (get_ia32_op_type(node) == ia32_AddrModeS) {
2446 bemit_mod_am(ruval, node);
2448 const arch_register_t *reg = get_in_reg(node, n_ia32_binary_left);
2449 if (reg->index == REG_GP_EAX) {
2453 bemit_modru(reg, ruval);
2456 bemit_entity(attr->symconst, attr->sc_sign, attr->offset, false);
2459 panic("invalid imm size?!?");
2465 static void bemit_binop_2(const ir_node *node, unsigned code)
2467 const arch_register_t *out = get_in_reg(node, n_ia32_binary_left);
2469 if (get_ia32_op_type(node) == ia32_Normal) {
2470 const arch_register_t *op2 = get_in_reg(node, n_ia32_binary_right);
2471 bemit_modrr(op2, out);
2473 bemit_mod_am(reg_gp_map[out->index], node);
2480 static void bemit_binop(const ir_node *node, const unsigned char opcodes[4])
2482 ir_node *right = get_irn_n(node, n_ia32_binary_right);
2483 if (is_ia32_Immediate(right)) {
2484 bemit_binop_with_imm(node, opcodes[1], opcodes[2], opcodes[3]);
2486 bemit_binop_2(node, opcodes[0]);
2493 static void bemit_unop(const ir_node *node, unsigned char code, unsigned char ext, int input)
2496 if (get_ia32_op_type(node) == ia32_Normal) {
2497 const arch_register_t *in = get_in_reg(node, input);
2498 bemit_modru(in, ext);
2500 bemit_mod_am(ext, node);
2504 static void bemit_unop_reg(const ir_node *node, unsigned char code, int input)
2506 const arch_register_t *out = get_out_reg(node, 0);
2507 bemit_unop(node, code, reg_gp_map[out->index], input);
2510 static void bemit_unop_mem(const ir_node *node, unsigned char code, unsigned char ext)
2512 unsigned size = get_mode_size_bits(get_ia32_ls_mode(node));
2515 bemit8(size == 8 ? code : code + 1);
2516 bemit_mod_am(ext, node);
2519 static void bemit_immediate(const ir_node *node, bool relative)
2521 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(node);
2522 bemit_entity(attr->symconst, attr->sc_sign, attr->offset, relative);
2525 static void bemit_copy(const ir_node *copy)
2527 const arch_register_t *in = get_in_reg(copy, 0);
2528 const arch_register_t *out = get_out_reg(copy, 0);
2532 /* copies of vf nodes aren't real... */
2533 if (arch_register_get_class(in) == &ia32_reg_classes[CLASS_ia32_vfp])
2536 if (get_irn_mode(copy) == mode_E) {
2539 assert(arch_register_get_class(in) == &ia32_reg_classes[CLASS_ia32_gp]);
2541 bemit_modrr(in, out);
2545 static void bemit_perm(const ir_node *node)
2547 const arch_register_t *in0 = arch_get_irn_register(get_irn_n(node, 0));
2548 const arch_register_t *in1 = arch_get_irn_register(get_irn_n(node, 1));
2549 const arch_register_class_t *cls0 = arch_register_get_class(in0);
2551 assert(cls0 == arch_register_get_class(in1) && "Register class mismatch at Perm");
2553 if (cls0 == &ia32_reg_classes[CLASS_ia32_gp]) {
2554 if (in0->index == REG_GP_EAX) {
2555 bemit8(0x90 + reg_gp_map[in1->index]);
2556 } else if (in1->index == REG_GP_EAX) {
2557 bemit8(0x90 + reg_gp_map[in0->index]);
2560 bemit_modrr(in0, in1);
2562 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_xmm]) {
2563 panic("unimplemented"); // TODO implement
2564 //ia32_emitf(NULL, "\txorpd %R, %R\n", in1, in0);
2565 //ia32_emitf(NULL, "\txorpd %R, %R\n", in0, in1);
2566 //ia32_emitf(node, "\txorpd %R, %R\n", in1, in0);
2567 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_vfp]) {
2569 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_st]) {
2572 panic("unexpected register class in be_Perm (%+F)", node);
2576 static void bemit_xor0(const ir_node *node)
2578 const arch_register_t *out = get_out_reg(node, 0);
2580 bemit_modrr(out, out);
2583 static void bemit_mov_const(const ir_node *node)
2585 const arch_register_t *out = get_out_reg(node, 0);
2586 bemit8(0xB8 + reg_gp_map[out->index]);
2587 bemit_immediate(node, false);
2591 * Creates a function for a Binop with 3 possible encodings.
2593 #define BINOP(op, op0, op1, op2, op2_ext) \
2594 static void bemit_ ## op(const ir_node *node) { \
2595 static const unsigned char op ## _codes[] = {op0, op1, op2, op2_ext}; \
2596 bemit_binop(node, op ## _codes); \
2599 /* insn def eax,imm imm */
2600 BINOP(add, 0x03, 0x05, 0x81, 0)
2601 BINOP(or, 0x0B, 0x0D, 0x81, 1)
2602 BINOP(adc, 0x13, 0x15, 0x81, 2)
2603 BINOP(sbb, 0x1B, 0x1D, 0x81, 3)
2604 BINOP(and, 0x23, 0x25, 0x81, 4)
2605 BINOP(sub, 0x2B, 0x2D, 0x81, 5)
2606 BINOP(xor, 0x33, 0x35, 0x81, 6)
2607 BINOP(test, 0x85, 0xA9, 0xF7, 0)
2609 #define BINOPMEM(op, ext) \
2610 static void bemit_##op(const ir_node *node) \
2613 unsigned size = get_mode_size_bits(get_ia32_ls_mode(node)); \
2616 val = get_irn_n(node, n_ia32_unary_op); \
2617 if (is_ia32_Immediate(val)) { \
2618 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(val); \
2619 int offset = attr->offset; \
2620 if (attr->symconst == NULL && get_signed_imm_size(offset) == 1) { \
2622 bemit_mod_am(ext, node); \
2626 bemit_mod_am(ext, node); \
2630 bemit_entity(attr->symconst, attr->sc_sign, offset, false); \
2634 bemit8(ext << 3 | 1); \
2635 bemit_mod_am(reg_gp_map[get_out_reg(val, 0)->index], node); \
2639 static void bemit_##op##8bit(const ir_node *node) \
2641 ir_node *val = get_irn_n(node, n_ia32_unary_op); \
2642 if (is_ia32_Immediate(val)) { \
2644 bemit_mod_am(ext, node); \
2645 bemit8(get_ia32_immediate_attr_const(val)->offset); \
2648 bemit_mod_am(reg_gp_map[get_out_reg(val, 0)->index], node); \
2660 * Creates a function for an Unop with code /ext encoding.
2662 #define UNOP(op, code, ext, input) \
2663 static void bemit_ ## op(const ir_node *node) { \
2664 bemit_unop(node, code, ext, input); \
2667 UNOP(not, 0xF7, 2, n_ia32_Not_val)
2668 UNOP(neg, 0xF7, 3, n_ia32_Neg_val)
2669 UNOP(mul, 0xF7, 4, n_ia32_Mul_right)
2670 UNOP(imul1op, 0xF7, 5, n_ia32_IMul1OP_right)
2671 UNOP(div, 0xF7, 6, n_ia32_Div_divisor)
2672 UNOP(idiv, 0xF7, 7, n_ia32_IDiv_divisor)
2674 /* TODO: am support for IJmp */
2675 UNOP(ijmp, 0xFF, 4, n_ia32_IJmp_target)
2677 #define SHIFT(op, ext) \
2678 static void bemit_##op(const ir_node *node) \
2680 const arch_register_t *out = get_out_reg(node, 0); \
2681 ir_node *count = get_irn_n(node, 1); \
2682 if (is_ia32_Immediate(count)) { \
2683 int offset = get_ia32_immediate_attr_const(count)->offset; \
2684 if (offset == 1) { \
2686 bemit_modru(out, ext); \
2689 bemit_modru(out, ext); \
2694 bemit_modru(out, ext); \
2698 static void bemit_##op##mem(const ir_node *node) \
2701 unsigned size = get_mode_size_bits(get_ia32_ls_mode(node)); \
2704 count = get_irn_n(node, 1); \
2705 if (is_ia32_Immediate(count)) { \
2706 int offset = get_ia32_immediate_attr_const(count)->offset; \
2707 if (offset == 1) { \
2708 bemit8(size == 8 ? 0xD0 : 0xD1); \
2709 bemit_mod_am(ext, node); \
2711 bemit8(size == 8 ? 0xC0 : 0xC1); \
2712 bemit_mod_am(ext, node); \
2716 bemit8(size == 8 ? 0xD2 : 0xD3); \
2717 bemit_mod_am(ext, node); \
2727 static void bemit_shld(const ir_node *node)
2729 const arch_register_t *in = get_in_reg(node, n_ia32_ShlD_val_low);
2730 const arch_register_t *out = get_out_reg(node, pn_ia32_ShlD_res);
2731 ir_node *count = get_irn_n(node, n_ia32_ShlD_count);
2733 if (is_ia32_Immediate(count)) {
2735 bemit_modrr(out, in);
2736 bemit8(get_ia32_immediate_attr_const(count)->offset);
2739 bemit_modrr(out, in);
2743 static void bemit_shrd(const ir_node *node)
2745 const arch_register_t *in = get_in_reg(node, n_ia32_ShrD_val_low);
2746 const arch_register_t *out = get_out_reg(node, pn_ia32_ShrD_res);
2747 ir_node *count = get_irn_n(node, n_ia32_ShrD_count);
2749 if (is_ia32_Immediate(count)) {
2751 bemit_modrr(out, in);
2752 bemit8(get_ia32_immediate_attr_const(count)->offset);
2755 bemit_modrr(out, in);
2760 * binary emitter for setcc.
2762 static void bemit_setcc(const ir_node *node)
2764 const arch_register_t *dreg = get_out_reg(node, pn_ia32_Setcc_res);
2766 ia32_condition_code_t cc = get_ia32_condcode(node);
2767 cc = determine_final_cc(node, n_ia32_Setcc_eflags, cc);
2768 if (cc & ia32_cc_float_parity_cases) {
2769 if (cc & ia32_cc_negated) {
2772 bemit8(0x90 | pnc2cc(cc));
2773 bemit_modrm8(REG_LOW, dreg);
2778 bemit_modrm8(REG_HIGH, dreg);
2780 /* orb %>dreg, %<dreg */
2782 bemit_modrr8(REG_LOW, dreg, REG_HIGH, dreg);
2786 bemit8(0x90 | pnc2cc(cc));
2787 bemit_modrm8(REG_LOW, dreg);
2792 bemit_modrm8(REG_HIGH, dreg);
2794 /* andb %>dreg, %<dreg */
2796 bemit_modrr8(REG_LOW, dreg, REG_HIGH, dreg);
2801 bemit8(0x90 | pnc2cc(cc));
2802 bemit_modrm8(REG_LOW, dreg);
2806 static void bemit_cmovcc(const ir_node *node)
2808 const ia32_attr_t *attr = get_ia32_attr_const(node);
2809 int ins_permuted = attr->data.ins_permuted;
2810 const arch_register_t *out = arch_irn_get_register(node, pn_ia32_res);
2811 ia32_condition_code_t cc = get_ia32_condcode(node);
2812 const arch_register_t *in_true;
2813 const arch_register_t *in_false;
2815 cc = determine_final_cc(node, n_ia32_CMovcc_eflags, cc);
2817 in_true = arch_get_irn_register(get_irn_n(node, n_ia32_CMovcc_val_true));
2818 in_false = arch_get_irn_register(get_irn_n(node, n_ia32_CMovcc_val_false));
2820 /* should be same constraint fullfilled? */
2821 if (out == in_false) {
2822 /* yes -> nothing to do */
2823 } else if (out == in_true) {
2824 assert(get_ia32_op_type(node) == ia32_Normal);
2825 ins_permuted = !ins_permuted;
2829 bemit8(0x8B); // mov %in_false, %out
2830 bemit_modrr(in_false, out);
2834 cc = ia32_negate_condition_code(cc);
2836 if (cc & ia32_cc_float_parity_cases)
2837 panic("cmov can't handle parity float cases");
2840 bemit8(0x40 | pnc2cc(cc));
2841 if (get_ia32_op_type(node) == ia32_Normal) {
2842 bemit_modrr(in_true, out);
2844 bemit_mod_am(reg_gp_map[out->index], node);
2848 static void bemit_cmp(const ir_node *node)
2850 unsigned ls_size = get_mode_size_bits(get_ia32_ls_mode(node));
2856 right = get_irn_n(node, n_ia32_binary_right);
2857 if (is_ia32_Immediate(right)) {
2858 /* Use in-reg, because some instructions (cmp, test) have no out-reg. */
2859 const ir_node *op = get_irn_n(node, n_ia32_binary_right);
2860 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(op);
2863 if (attr->symconst != NULL) {
2866 /* check for sign extension */
2867 size = get_signed_imm_size(attr->offset);
2872 bemit8(0x81 | SIGNEXT_IMM);
2873 /* cmp has this special mode */
2874 if (get_ia32_op_type(node) == ia32_AddrModeS) {
2875 bemit_mod_am(7, node);
2877 const arch_register_t *reg = get_in_reg(node, n_ia32_binary_left);
2878 bemit_modru(reg, 7);
2880 bemit8((unsigned char)attr->offset);
2884 /* check for eax variant: this variant is shorter for 32bit immediates only */
2885 if (get_ia32_op_type(node) == ia32_AddrModeS) {
2887 bemit_mod_am(7, node);
2889 const arch_register_t *reg = get_in_reg(node, n_ia32_binary_left);
2890 if (reg->index == REG_GP_EAX) {
2894 bemit_modru(reg, 7);
2897 if (ls_size == 16) {
2898 bemit16(attr->offset);
2900 bemit_entity(attr->symconst, attr->sc_sign, attr->offset, false);
2904 panic("invalid imm size?!?");
2906 const arch_register_t *out = get_in_reg(node, n_ia32_binary_left);
2908 if (get_ia32_op_type(node) == ia32_Normal) {
2909 const arch_register_t *op2 = get_in_reg(node, n_ia32_binary_right);
2910 bemit_modrr(op2, out);
2912 bemit_mod_am(reg_gp_map[out->index], node);
2917 static void bemit_cmp8bit(const ir_node *node)
2919 ir_node *right = get_irn_n(node, n_ia32_binary_right);
2920 if (is_ia32_Immediate(right)) {
2921 if (get_ia32_op_type(node) == ia32_Normal) {
2922 const arch_register_t *out = get_in_reg(node, n_ia32_Cmp_left);
2923 if (out->index == REG_GP_EAX) {
2927 bemit_modru(out, 7);
2931 bemit_mod_am(7, node);
2933 bemit8(get_ia32_immediate_attr_const(right)->offset);
2935 const arch_register_t *out = get_in_reg(node, n_ia32_Cmp_left);
2937 if (get_ia32_op_type(node) == ia32_Normal) {
2938 const arch_register_t *in = get_in_reg(node, n_ia32_Cmp_right);
2939 bemit_modrr(out, in);
2941 bemit_mod_am(reg_gp_map[out->index], node);
2946 static void bemit_test8bit(const ir_node *node)
2948 ir_node *right = get_irn_n(node, n_ia32_Test8Bit_right);
2949 if (is_ia32_Immediate(right)) {
2950 if (get_ia32_op_type(node) == ia32_Normal) {
2951 const arch_register_t *out = get_in_reg(node, n_ia32_Test8Bit_left);
2952 if (out->index == REG_GP_EAX) {
2956 bemit_modru(out, 0);
2960 bemit_mod_am(0, node);
2962 bemit8(get_ia32_immediate_attr_const(right)->offset);
2964 const arch_register_t *out = get_in_reg(node, n_ia32_Test8Bit_left);
2966 if (get_ia32_op_type(node) == ia32_Normal) {
2967 const arch_register_t *in = get_in_reg(node, n_ia32_Test8Bit_right);
2968 bemit_modrr(out, in);
2970 bemit_mod_am(reg_gp_map[out->index], node);
2975 static void bemit_imul(const ir_node *node)
2977 ir_node *right = get_irn_n(node, n_ia32_IMul_right);
2978 /* Do we need the immediate form? */
2979 if (is_ia32_Immediate(right)) {
2980 int imm = get_ia32_immediate_attr_const(right)->offset;
2981 if (get_signed_imm_size(imm) == 1) {
2982 bemit_unop_reg(node, 0x6B, n_ia32_IMul_left);
2985 bemit_unop_reg(node, 0x69, n_ia32_IMul_left);
2990 bemit_unop_reg(node, 0xAF, n_ia32_IMul_right);
2994 static void bemit_dec(const ir_node *node)
2996 const arch_register_t *out = get_out_reg(node, pn_ia32_Dec_res);
2997 bemit8(0x48 + reg_gp_map[out->index]);
3000 static void bemit_inc(const ir_node *node)
3002 const arch_register_t *out = get_out_reg(node, pn_ia32_Inc_res);
3003 bemit8(0x40 + reg_gp_map[out->index]);
3006 #define UNOPMEM(op, code, ext) \
3007 static void bemit_##op(const ir_node *node) \
3009 bemit_unop_mem(node, code, ext); \
3012 UNOPMEM(notmem, 0xF6, 2)
3013 UNOPMEM(negmem, 0xF6, 3)
3014 UNOPMEM(incmem, 0xFE, 0)
3015 UNOPMEM(decmem, 0xFE, 1)
3017 static void bemit_ldtls(const ir_node *node)
3019 const arch_register_t *out = get_out_reg(node, 0);
3021 bemit8(0x65); // gs:
3022 if (out->index == REG_GP_EAX) {
3023 bemit8(0xA1); // movl 0, %eax
3025 bemit8(0x8B); // movl 0, %reg
3026 bemit8(MOD_IND | ENC_REG(reg_gp_map[out->index]) | ENC_RM(0x05));
3034 static void bemit_lea(const ir_node *node)
3036 const arch_register_t *out = get_out_reg(node, 0);
3038 bemit_mod_am(reg_gp_map[out->index], node);
3041 /* helper function for bemit_minus64bit */
3042 static void bemit_helper_mov(const arch_register_t *src, const arch_register_t *dst)
3044 bemit8(0x8B); // movl %src, %dst
3045 bemit_modrr(src, dst);
3048 /* helper function for bemit_minus64bit */
3049 static void bemit_helper_neg(const arch_register_t *reg)
3051 bemit8(0xF7); // negl %reg
3052 bemit_modru(reg, 3);
3055 /* helper function for bemit_minus64bit */
3056 static void bemit_helper_sbb0(const arch_register_t *reg)
3058 bemit8(0x83); // sbbl $0, %reg
3059 bemit_modru(reg, 3);
3063 /* helper function for bemit_minus64bit */
3064 static void bemit_helper_sbb(const arch_register_t *src, const arch_register_t *dst)
3066 bemit8(0x1B); // sbbl %src, %dst
3067 bemit_modrr(src, dst);
3070 /* helper function for bemit_minus64bit */
3071 static void bemit_helper_xchg(const arch_register_t *src, const arch_register_t *dst)
3073 if (src->index == REG_GP_EAX) {
3074 bemit8(0x90 + reg_gp_map[dst->index]); // xchgl %eax, %dst
3075 } else if (dst->index == REG_GP_EAX) {
3076 bemit8(0x90 + reg_gp_map[src->index]); // xchgl %src, %eax
3078 bemit8(0x87); // xchgl %src, %dst
3079 bemit_modrr(src, dst);
3083 /* helper function for bemit_minus64bit */
3084 static void bemit_helper_zero(const arch_register_t *reg)
3086 bemit8(0x33); // xorl %reg, %reg
3087 bemit_modrr(reg, reg);
3090 static void bemit_minus64bit(const ir_node *node)
3092 const arch_register_t *in_lo = get_in_reg(node, 0);
3093 const arch_register_t *in_hi = get_in_reg(node, 1);
3094 const arch_register_t *out_lo = get_out_reg(node, 0);
3095 const arch_register_t *out_hi = get_out_reg(node, 1);
3097 if (out_lo == in_lo) {
3098 if (out_hi != in_hi) {
3099 /* a -> a, b -> d */
3102 /* a -> a, b -> b */
3105 } else if (out_lo == in_hi) {
3106 if (out_hi == in_lo) {
3107 /* a -> b, b -> a */
3108 bemit_helper_xchg(in_lo, in_hi);
3111 /* a -> b, b -> d */
3112 bemit_helper_mov(in_hi, out_hi);
3113 bemit_helper_mov(in_lo, out_lo);
3117 if (out_hi == in_lo) {
3118 /* a -> c, b -> a */
3119 bemit_helper_mov(in_lo, out_lo);
3121 } else if (out_hi == in_hi) {
3122 /* a -> c, b -> b */
3123 bemit_helper_mov(in_lo, out_lo);
3126 /* a -> c, b -> d */
3127 bemit_helper_mov(in_lo, out_lo);
3133 bemit_helper_neg( out_hi);
3134 bemit_helper_neg( out_lo);
3135 bemit_helper_sbb0(out_hi);
3139 bemit_helper_zero(out_hi);
3140 bemit_helper_neg( out_lo);
3141 bemit_helper_sbb( in_hi, out_hi);
3145 * Emit a single opcode.
3147 #define EMIT_SINGLEOP(op, code) \
3148 static void bemit_ ## op(const ir_node *node) { \
3153 //EMIT_SINGLEOP(daa, 0x27)
3154 //EMIT_SINGLEOP(das, 0x2F)
3155 //EMIT_SINGLEOP(aaa, 0x37)
3156 //EMIT_SINGLEOP(aas, 0x3F)
3157 //EMIT_SINGLEOP(nop, 0x90)
3158 EMIT_SINGLEOP(cwtl, 0x98)
3159 EMIT_SINGLEOP(cltd, 0x99)
3160 //EMIT_SINGLEOP(fwait, 0x9B)
3161 EMIT_SINGLEOP(sahf, 0x9E)
3162 //EMIT_SINGLEOP(popf, 0x9D)
3163 EMIT_SINGLEOP(leave, 0xC9)
3164 EMIT_SINGLEOP(int3, 0xCC)
3165 //EMIT_SINGLEOP(iret, 0xCF)
3166 //EMIT_SINGLEOP(xlat, 0xD7)
3167 //EMIT_SINGLEOP(lock, 0xF0)
3168 EMIT_SINGLEOP(rep, 0xF3)
3169 //EMIT_SINGLEOP(halt, 0xF4)
3170 EMIT_SINGLEOP(cmc, 0xF5)
3171 EMIT_SINGLEOP(stc, 0xF9)
3172 //EMIT_SINGLEOP(cli, 0xFA)
3173 //EMIT_SINGLEOP(sti, 0xFB)
3174 //EMIT_SINGLEOP(std, 0xFD)
3177 * Emits a MOV out, [MEM].
3179 static void bemit_load(const ir_node *node)
3181 const arch_register_t *out = get_out_reg(node, 0);
3183 if (out->index == REG_GP_EAX) {
3184 ir_node *base = get_irn_n(node, n_ia32_base);
3185 int has_base = !is_ia32_NoReg_GP(base);
3186 ir_node *index = get_irn_n(node, n_ia32_index);
3187 int has_index = !is_ia32_NoReg_GP(index);
3188 if (!has_base && !has_index) {
3189 ir_entity *ent = get_ia32_am_sc(node);
3190 int offs = get_ia32_am_offs_int(node);
3191 /* load from constant address to EAX can be encoded
3194 bemit_entity(ent, 0, offs, false);
3199 bemit_mod_am(reg_gp_map[out->index], node);
3203 * Emits a MOV [mem], in.
3205 static void bemit_store(const ir_node *node)
3207 const ir_node *value = get_irn_n(node, n_ia32_Store_val);
3208 unsigned size = get_mode_size_bits(get_ia32_ls_mode(node));
3210 if (is_ia32_Immediate(value)) {
3213 bemit_mod_am(0, node);
3214 bemit8(get_ia32_immediate_attr_const(value)->offset);
3215 } else if (size == 16) {
3218 bemit_mod_am(0, node);
3219 bemit16(get_ia32_immediate_attr_const(value)->offset);
3222 bemit_mod_am(0, node);
3223 bemit_immediate(value, false);
3226 const arch_register_t *in = get_in_reg(node, n_ia32_Store_val);
3228 if (in->index == REG_GP_EAX) {
3229 ir_node *base = get_irn_n(node, n_ia32_base);
3230 int has_base = !is_ia32_NoReg_GP(base);
3231 ir_node *index = get_irn_n(node, n_ia32_index);
3232 int has_index = !is_ia32_NoReg_GP(index);
3233 if (!has_base && !has_index) {
3234 ir_entity *ent = get_ia32_am_sc(node);
3235 int offs = get_ia32_am_offs_int(node);
3236 /* store to constant address from EAX can be encoded as
3237 * 0xA2/0xA3 [offset]*/
3245 bemit_entity(ent, 0, offs, false);
3257 bemit_mod_am(reg_gp_map[in->index], node);
3261 static void bemit_conv_i2i(const ir_node *node)
3263 ir_mode *smaller_mode = get_ia32_ls_mode(node);
3272 if (mode_is_signed(smaller_mode)) opcode |= 0x08;
3273 if (get_mode_size_bits(smaller_mode) == 16) opcode |= 0x01;
3274 bemit_unop_reg(node, opcode, n_ia32_Conv_I2I_val);
3280 static void bemit_push(const ir_node *node)
3282 const ir_node *value = get_irn_n(node, n_ia32_Push_val);
3284 if (is_ia32_Immediate(value)) {
3285 const ia32_immediate_attr_t *attr
3286 = get_ia32_immediate_attr_const(value);
3287 unsigned size = get_signed_imm_size(attr->offset);
3293 bemit8((unsigned char)attr->offset);
3298 bemit_immediate(value, false);
3301 } else if (is_ia32_NoReg_GP(value)) {
3303 bemit_mod_am(6, node);
3305 const arch_register_t *reg = get_in_reg(node, n_ia32_Push_val);
3306 bemit8(0x50 + reg_gp_map[reg->index]);
3313 static void bemit_pop(const ir_node *node)
3315 const arch_register_t *reg = get_out_reg(node, pn_ia32_Pop_res);
3316 bemit8(0x58 + reg_gp_map[reg->index]);
3319 static void bemit_popmem(const ir_node *node)
3322 bemit_mod_am(0, node);
3325 static void bemit_call(const ir_node *node)
3327 ir_node *proc = get_irn_n(node, n_ia32_Call_addr);
3329 if (is_ia32_Immediate(proc)) {
3331 bemit_immediate(proc, true);
3333 bemit_unop(node, 0xFF, 2, n_ia32_Call_addr);
3337 static void bemit_jmp(const ir_node *dest_block)
3340 bemit_jmp_destination(dest_block);
3343 static void bemit_jump(const ir_node *node)
3345 if (can_be_fallthrough(node))
3348 bemit_jmp(get_cfop_target_block(node));
3351 static void bemit_jcc(int pnc, const ir_node *dest_block)
3353 unsigned char cc = pnc2cc(pnc);
3356 bemit_jmp_destination(dest_block);
3359 static void bemit_jp(bool odd, const ir_node *dest_block)
3363 bemit_jmp_destination(dest_block);
3366 static void bemit_ia32_jcc(const ir_node *node)
3368 ia32_condition_code_t cc = get_ia32_condcode(node);
3369 const ir_node *proj_true;
3370 const ir_node *proj_false;
3371 const ir_node *dest_true;
3372 const ir_node *dest_false;
3373 const ir_node *block;
3375 cc = determine_final_cc(node, 0, cc);
3377 /* get both Projs */
3378 proj_true = get_proj(node, pn_ia32_Jcc_true);
3379 assert(proj_true && "Jcc without true Proj");
3381 proj_false = get_proj(node, pn_ia32_Jcc_false);
3382 assert(proj_false && "Jcc without false Proj");
3384 block = get_nodes_block(node);
3386 if (can_be_fallthrough(proj_true)) {
3387 /* exchange both proj's so the second one can be omitted */
3388 const ir_node *t = proj_true;
3390 proj_true = proj_false;
3392 cc = ia32_negate_condition_code(cc);
3395 dest_true = get_cfop_target_block(proj_true);
3396 dest_false = get_cfop_target_block(proj_false);
3398 if (cc & ia32_cc_float_parity_cases) {
3399 /* Some floating point comparisons require a test of the parity flag,
3400 * which indicates that the result is unordered */
3401 if (cc & ia32_cc_negated) {
3402 bemit_jp(false, dest_true);
3404 /* we need a local label if the false proj is a fallthrough
3405 * as the falseblock might have no label emitted then */
3406 if (can_be_fallthrough(proj_false)) {
3408 bemit8(0x06); // jp + 6
3410 bemit_jp(false, dest_false);
3414 bemit_jcc(cc, dest_true);
3416 /* the second Proj might be a fallthrough */
3417 if (can_be_fallthrough(proj_false)) {
3418 /* it's a fallthrough */
3420 bemit_jmp(dest_false);
3424 static void bemit_switchjmp(const ir_node *node)
3426 unsigned long interval;
3430 const arch_register_t *in;
3432 /* fill the table structure */
3433 generate_jump_table(&tbl, node);
3435 /* two-complement's magic make this work without overflow */
3436 interval = tbl.max_value - tbl.min_value;
3438 in = get_in_reg(node, 0);
3439 /* emit the table */
3440 if (get_signed_imm_size(interval) == 1) {
3441 bemit8(0x83); // cmpl $imm8, %in
3445 bemit8(0x81); // cmpl $imm32, %in
3449 bemit8(0x0F); // ja tbl.defProj
3451 ia32_emitf(tbl.defProj, ".long %L - . - 4\n");
3453 if (tbl.num_branches > 1) {
3455 bemit8(0xFF); // jmp *tbl.label(,%in,4)
3456 bemit8(MOD_IND | ENC_REG(4) | ENC_RM(0x04));
3457 bemit8(ENC_SIB(2, reg_gp_map[in->index], 0x05));
3458 be_emit_irprintf("\t.long %s\n", tbl.label);
3460 be_gas_emit_switch_section(GAS_SECTION_RODATA);
3461 be_emit_cstring(".align 4\n");
3462 be_emit_irprintf("%s:\n", tbl.label);
3464 last_value = tbl.branches[0].value;
3465 for (i = 0; i != tbl.num_branches; ++i) {
3466 while (last_value != tbl.branches[i].value) {
3467 ia32_emitf(tbl.defProj, ".long %L\n");
3470 ia32_emitf(tbl.branches[i].target, ".long %L\n");
3473 be_gas_emit_switch_section(GAS_SECTION_TEXT);
3475 /* one jump is enough */
3476 panic("switch only has one case");
3477 //ia32_emitf(tbl.branches[0].target, "\tjmp %L\n");
3480 be_emit_write_line();
3488 static void bemit_return(const ir_node *node)
3490 unsigned pop = be_Return_get_pop(node);
3491 if (pop > 0 || be_Return_get_emit_pop(node)) {
3493 assert(pop <= 0xffff);
3500 static void bemit_subsp(const ir_node *node)
3502 const arch_register_t *out;
3505 /* mov %esp, %out */
3507 out = get_out_reg(node, 1);
3508 bemit8(MOD_REG | ENC_REG(reg_gp_map[out->index]) | ENC_RM(0x04));
3511 static void bemit_incsp(const ir_node *node)
3514 const arch_register_t *reg;
3518 offs = be_get_IncSP_offset(node);
3529 size = get_signed_imm_size(offs);
3530 bemit8(size == 1 ? 0x83 : 0x81);
3532 reg = get_out_reg(node, 0);
3533 bemit_modru(reg, ext);
3542 static void bemit_copybi(const ir_node *node)
3544 unsigned size = get_ia32_copyb_size(node);
3546 bemit8(0xA4); // movsb
3549 bemit8(0xA5); // movsw
3553 bemit8(0xA5); // movsl
3557 static void bemit_fbinop(const ir_node *node, unsigned code, unsigned code_to)
3559 if (get_ia32_op_type(node) == ia32_Normal) {
3560 const ia32_x87_attr_t *x87_attr = get_ia32_x87_attr_const(node);
3561 const arch_register_t *in1 = x87_attr->x87[0];
3562 const arch_register_t *in = x87_attr->x87[1];
3563 const arch_register_t *out = x87_attr->x87[2];
3567 } else if (out == in) {
3571 if (out->index == 0) {
3573 bemit8(MOD_REG | ENC_REG(code) | ENC_RM(in->index));
3576 bemit8(MOD_REG | ENC_REG(code_to) | ENC_RM(out->index));
3579 if (get_mode_size_bits(get_ia32_ls_mode(node)) == 32) {
3584 bemit_mod_am(code, node);
3588 static void bemit_fbinopp(const ir_node *node, unsigned const code)
3590 const ia32_x87_attr_t *x87_attr = get_ia32_x87_attr_const(node);
3591 const arch_register_t *out = x87_attr->x87[2];
3593 bemit8(code + out->index);
3596 static void bemit_fabs(const ir_node *node)
3604 static void bemit_fadd(const ir_node *node)
3606 bemit_fbinop(node, 0, 0);
3609 static void bemit_faddp(const ir_node *node)
3611 bemit_fbinopp(node, 0xC0);
3614 static void bemit_fchs(const ir_node *node)
3622 static void bemit_fdiv(const ir_node *node)
3624 bemit_fbinop(node, 6, 7);
3627 static void bemit_fdivp(const ir_node *node)
3629 bemit_fbinopp(node, 0xF8);
3632 static void bemit_fdivr(const ir_node *node)
3634 bemit_fbinop(node, 7, 6);
3637 static void bemit_fdivrp(const ir_node *node)
3639 bemit_fbinopp(node, 0xF0);
3642 static void bemit_fild(const ir_node *node)
3644 switch (get_mode_size_bits(get_ia32_ls_mode(node))) {
3646 bemit8(0xDF); // filds
3647 bemit_mod_am(0, node);
3651 bemit8(0xDB); // fildl
3652 bemit_mod_am(0, node);
3656 bemit8(0xDF); // fildll
3657 bemit_mod_am(5, node);
3661 panic("invalid mode size");
3665 static void bemit_fist(const ir_node *node)
3667 switch (get_mode_size_bits(get_ia32_ls_mode(node))) {
3669 bemit8(0xDF); // fists
3673 bemit8(0xDB); // fistl
3677 panic("invalid mode size");
3679 bemit_mod_am(2, node);
3682 static void bemit_fistp(const ir_node *node)
3684 switch (get_mode_size_bits(get_ia32_ls_mode(node))) {
3686 bemit8(0xDF); // fistps
3687 bemit_mod_am(3, node);
3691 bemit8(0xDB); // fistpl
3692 bemit_mod_am(3, node);
3696 bemit8(0xDF); // fistpll
3697 bemit_mod_am(7, node);
3701 panic("invalid mode size");
3705 static void bemit_fld(const ir_node *node)
3707 switch (get_mode_size_bits(get_ia32_ls_mode(node))) {
3709 bemit8(0xD9); // flds
3710 bemit_mod_am(0, node);
3714 bemit8(0xDD); // fldl
3715 bemit_mod_am(0, node);
3720 bemit8(0xDB); // fldt
3721 bemit_mod_am(5, node);
3725 panic("invalid mode size");
3729 static void bemit_fld1(const ir_node *node)
3733 bemit8(0xE8); // fld1
3736 static void bemit_fldcw(const ir_node *node)
3738 bemit8(0xD9); // fldcw
3739 bemit_mod_am(5, node);
3742 static void bemit_fldz(const ir_node *node)
3746 bemit8(0xEE); // fldz
3749 static void bemit_fmul(const ir_node *node)
3751 bemit_fbinop(node, 1, 1);
3754 static void bemit_fmulp(const ir_node *node)
3756 bemit_fbinopp(node, 0xC8);
3759 static void bemit_fpop(const ir_node *node)
3761 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
3763 bemit8(0xD8 + attr->x87[0]->index);
3766 static void bemit_fpush(const ir_node *node)
3768 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
3770 bemit8(0xC0 + attr->x87[0]->index);
3773 static void bemit_fpushcopy(const ir_node *node)
3775 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
3777 bemit8(0xC0 + attr->x87[0]->index);
3780 static void bemit_fst(const ir_node *node)
3782 switch (get_mode_size_bits(get_ia32_ls_mode(node))) {
3784 bemit8(0xD9); // fsts
3788 bemit8(0xDD); // fstl
3792 panic("invalid mode size");
3794 bemit_mod_am(2, node);
3797 static void bemit_fstp(const ir_node *node)
3799 switch (get_mode_size_bits(get_ia32_ls_mode(node))) {
3801 bemit8(0xD9); // fstps
3802 bemit_mod_am(3, node);
3806 bemit8(0xDD); // fstpl
3807 bemit_mod_am(3, node);
3812 bemit8(0xDB); // fstpt
3813 bemit_mod_am(7, node);
3817 panic("invalid mode size");
3821 static void bemit_fsub(const ir_node *node)
3823 bemit_fbinop(node, 4, 5);
3826 static void bemit_fsubp(const ir_node *node)
3828 bemit_fbinopp(node, 0xE8);
3831 static void bemit_fsubr(const ir_node *node)
3833 bemit_fbinop(node, 5, 4);
3836 static void bemit_fsubrp(const ir_node *node)
3838 bemit_fbinopp(node, 0xE0);
3841 static void bemit_fnstcw(const ir_node *node)
3843 bemit8(0xD9); // fnstcw
3844 bemit_mod_am(7, node);
3847 static void bemit_fnstsw(void)
3849 bemit8(0xDF); // fnstsw %ax
3853 static void bemit_ftstfnstsw(const ir_node *node)
3857 bemit8(0xD9); // ftst
3862 static void bemit_fucomi(const ir_node *node)
3864 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
3865 bemit8(0xDB); // fucomi
3866 bemit8(0xE8 + attr->x87[1]->index);
3869 static void bemit_fucomip(const ir_node *node)
3871 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
3872 bemit8(0xDF); // fucomip
3873 bemit8(0xE8 + attr->x87[1]->index);
3876 static void bemit_fucomfnstsw(const ir_node *node)
3878 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
3879 bemit8(0xDD); // fucom
3880 bemit8(0xE0 + attr->x87[1]->index);
3884 static void bemit_fucompfnstsw(const ir_node *node)
3886 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
3887 bemit8(0xDD); // fucomp
3888 bemit8(0xE8 + attr->x87[1]->index);
3892 static void bemit_fucomppfnstsw(const ir_node *node)
3896 bemit8(0xDA); // fucompp
3901 static void bemit_fxch(const ir_node *node)
3903 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
3905 bemit8(0xC8 + attr->x87[0]->index);
3909 * The type of a emitter function.
3911 typedef void (*emit_func) (const ir_node *);
3914 * Set a node emitter. Make it a bit more type safe.
3916 static void register_emitter(ir_op *op, emit_func func)
3918 op->ops.generic = (op_func) func;
3921 static void ia32_register_binary_emitters(void)
3923 /* first clear the generic function pointer for all ops */
3924 clear_irp_opcodes_generic_func();
3926 /* benode emitter */
3927 register_emitter(op_be_Copy, bemit_copy);
3928 register_emitter(op_be_CopyKeep, bemit_copy);
3929 register_emitter(op_be_IncSP, bemit_incsp);
3930 register_emitter(op_be_Perm, bemit_perm);
3931 register_emitter(op_be_Return, bemit_return);
3932 register_emitter(op_ia32_Adc, bemit_adc);
3933 register_emitter(op_ia32_Add, bemit_add);
3934 register_emitter(op_ia32_AddMem, bemit_addmem);
3935 register_emitter(op_ia32_AddMem8Bit, bemit_addmem8bit);
3936 register_emitter(op_ia32_And, bemit_and);
3937 register_emitter(op_ia32_AndMem, bemit_andmem);
3938 register_emitter(op_ia32_AndMem8Bit, bemit_andmem8bit);
3939 register_emitter(op_ia32_Breakpoint, bemit_int3);
3940 register_emitter(op_ia32_CMovcc, bemit_cmovcc);
3941 register_emitter(op_ia32_Call, bemit_call);
3942 register_emitter(op_ia32_Cltd, bemit_cltd);
3943 register_emitter(op_ia32_Cmc, bemit_cmc);
3944 register_emitter(op_ia32_Cmp, bemit_cmp);
3945 register_emitter(op_ia32_Cmp8Bit, bemit_cmp8bit);
3946 register_emitter(op_ia32_Const, bemit_mov_const);
3947 register_emitter(op_ia32_Conv_I2I, bemit_conv_i2i);
3948 register_emitter(op_ia32_Conv_I2I8Bit, bemit_conv_i2i);
3949 register_emitter(op_ia32_CopyB_i, bemit_copybi);
3950 register_emitter(op_ia32_Cwtl, bemit_cwtl);
3951 register_emitter(op_ia32_Dec, bemit_dec);
3952 register_emitter(op_ia32_DecMem, bemit_decmem);
3953 register_emitter(op_ia32_Div, bemit_div);
3954 register_emitter(op_ia32_FldCW, bemit_fldcw);
3955 register_emitter(op_ia32_FnstCW, bemit_fnstcw);
3956 register_emitter(op_ia32_FtstFnstsw, bemit_ftstfnstsw);
3957 register_emitter(op_ia32_FucomFnstsw, bemit_fucomfnstsw);
3958 register_emitter(op_ia32_Fucomi, bemit_fucomi);
3959 register_emitter(op_ia32_FucompFnstsw, bemit_fucompfnstsw);
3960 register_emitter(op_ia32_Fucompi, bemit_fucomip);
3961 register_emitter(op_ia32_FucomppFnstsw, bemit_fucomppfnstsw);
3962 register_emitter(op_ia32_IDiv, bemit_idiv);
3963 register_emitter(op_ia32_IJmp, bemit_ijmp);
3964 register_emitter(op_ia32_IMul, bemit_imul);
3965 register_emitter(op_ia32_IMul1OP, bemit_imul1op);
3966 register_emitter(op_ia32_Inc, bemit_inc);
3967 register_emitter(op_ia32_IncMem, bemit_incmem);
3968 register_emitter(op_ia32_Jcc, bemit_ia32_jcc);
3969 register_emitter(op_ia32_Jmp, bemit_jump);
3970 register_emitter(op_ia32_LdTls, bemit_ldtls);
3971 register_emitter(op_ia32_Lea, bemit_lea);
3972 register_emitter(op_ia32_Leave, bemit_leave);
3973 register_emitter(op_ia32_Load, bemit_load);
3974 register_emitter(op_ia32_Minus64Bit, bemit_minus64bit);
3975 register_emitter(op_ia32_Mul, bemit_mul);
3976 register_emitter(op_ia32_Neg, bemit_neg);
3977 register_emitter(op_ia32_NegMem, bemit_negmem);
3978 register_emitter(op_ia32_Not, bemit_not);
3979 register_emitter(op_ia32_NotMem, bemit_notmem);
3980 register_emitter(op_ia32_Or, bemit_or);
3981 register_emitter(op_ia32_OrMem, bemit_ormem);
3982 register_emitter(op_ia32_OrMem8Bit, bemit_ormem8bit);
3983 register_emitter(op_ia32_Pop, bemit_pop);
3984 register_emitter(op_ia32_PopEbp, bemit_pop);
3985 register_emitter(op_ia32_PopMem, bemit_popmem);
3986 register_emitter(op_ia32_Push, bemit_push);
3987 register_emitter(op_ia32_RepPrefix, bemit_rep);
3988 register_emitter(op_ia32_Rol, bemit_rol);
3989 register_emitter(op_ia32_RolMem, bemit_rolmem);
3990 register_emitter(op_ia32_Ror, bemit_ror);
3991 register_emitter(op_ia32_RorMem, bemit_rormem);
3992 register_emitter(op_ia32_Sahf, bemit_sahf);
3993 register_emitter(op_ia32_Sar, bemit_sar);
3994 register_emitter(op_ia32_SarMem, bemit_sarmem);
3995 register_emitter(op_ia32_Sbb, bemit_sbb);
3996 register_emitter(op_ia32_Setcc, bemit_setcc);
3997 register_emitter(op_ia32_Shl, bemit_shl);
3998 register_emitter(op_ia32_ShlD, bemit_shld);
3999 register_emitter(op_ia32_ShlMem, bemit_shlmem);
4000 register_emitter(op_ia32_Shr, bemit_shr);
4001 register_emitter(op_ia32_ShrD, bemit_shrd);
4002 register_emitter(op_ia32_ShrMem, bemit_shrmem);
4003 register_emitter(op_ia32_Stc, bemit_stc);
4004 register_emitter(op_ia32_Store, bemit_store);
4005 register_emitter(op_ia32_Store8Bit, bemit_store);
4006 register_emitter(op_ia32_Sub, bemit_sub);
4007 register_emitter(op_ia32_SubMem, bemit_submem);
4008 register_emitter(op_ia32_SubMem8Bit, bemit_submem8bit);
4009 register_emitter(op_ia32_SubSP, bemit_subsp);
4010 register_emitter(op_ia32_SwitchJmp, bemit_switchjmp);
4011 register_emitter(op_ia32_Test, bemit_test);
4012 register_emitter(op_ia32_Test8Bit, bemit_test8bit);
4013 register_emitter(op_ia32_Xor, bemit_xor);
4014 register_emitter(op_ia32_Xor0, bemit_xor0);
4015 register_emitter(op_ia32_XorMem, bemit_xormem);
4016 register_emitter(op_ia32_XorMem8Bit, bemit_xormem8bit);
4017 register_emitter(op_ia32_fabs, bemit_fabs);
4018 register_emitter(op_ia32_fadd, bemit_fadd);
4019 register_emitter(op_ia32_faddp, bemit_faddp);
4020 register_emitter(op_ia32_fchs, bemit_fchs);
4021 register_emitter(op_ia32_fdiv, bemit_fdiv);
4022 register_emitter(op_ia32_fdivp, bemit_fdivp);
4023 register_emitter(op_ia32_fdivr, bemit_fdivr);
4024 register_emitter(op_ia32_fdivrp, bemit_fdivrp);
4025 register_emitter(op_ia32_fild, bemit_fild);
4026 register_emitter(op_ia32_fist, bemit_fist);
4027 register_emitter(op_ia32_fistp, bemit_fistp);
4028 register_emitter(op_ia32_fld, bemit_fld);
4029 register_emitter(op_ia32_fld1, bemit_fld1);
4030 register_emitter(op_ia32_fldz, bemit_fldz);
4031 register_emitter(op_ia32_fmul, bemit_fmul);
4032 register_emitter(op_ia32_fmulp, bemit_fmulp);
4033 register_emitter(op_ia32_fpop, bemit_fpop);
4034 register_emitter(op_ia32_fpush, bemit_fpush);
4035 register_emitter(op_ia32_fpushCopy, bemit_fpushcopy);
4036 register_emitter(op_ia32_fst, bemit_fst);
4037 register_emitter(op_ia32_fstp, bemit_fstp);
4038 register_emitter(op_ia32_fsub, bemit_fsub);
4039 register_emitter(op_ia32_fsubp, bemit_fsubp);
4040 register_emitter(op_ia32_fsubr, bemit_fsubr);
4041 register_emitter(op_ia32_fsubrp, bemit_fsubrp);
4042 register_emitter(op_ia32_fxch, bemit_fxch);
4044 /* ignore the following nodes */
4045 register_emitter(op_ia32_ProduceVal, emit_Nothing);
4046 register_emitter(op_be_Keep, emit_Nothing);
4047 register_emitter(op_be_Start, emit_Nothing);
4048 register_emitter(op_Phi, emit_Nothing);
4049 register_emitter(op_Start, emit_Nothing);
4052 static void gen_binary_block(ir_node *block)
4056 ia32_emit_block_header(block);
4058 /* emit the contents of the block */
4059 sched_foreach(block, node) {
4060 ia32_emit_node(node);
4064 void ia32_gen_binary_routine(ir_graph *irg)
4066 ir_entity *entity = get_irg_entity(irg);
4067 const arch_env_t *arch_env = be_get_irg_arch_env(irg);
4068 ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
4069 ir_node **blk_sched = irg_data->blk_sched;
4072 isa = (ia32_isa_t*) arch_env;
4074 ia32_register_binary_emitters();
4076 be_gas_emit_function_prolog(entity, ia32_cg_config.function_alignment);
4078 /* we use links to point to target blocks */
4079 ir_reserve_resources(irg, IR_RESOURCE_IRN_LINK);
4080 irg_block_walk_graph(irg, ia32_gen_labels, NULL, NULL);
4082 /* initialize next block links */
4083 n = ARR_LEN(blk_sched);
4084 for (i = 0; i < n; ++i) {
4085 ir_node *block = blk_sched[i];
4086 ir_node *prev = i > 0 ? blk_sched[i-1] : NULL;
4088 set_irn_link(block, prev);
4091 for (i = 0; i < n; ++i) {
4092 ir_node *block = blk_sched[i];
4093 gen_binary_block(block);
4096 be_gas_emit_function_epilog(entity);
4097 be_dbg_method_end();
4099 be_emit_write_line();
4101 ir_free_resources(irg, IR_RESOURCE_IRN_LINK);
4105 void ia32_init_emitter(void)
4107 lc_opt_entry_t *be_grp;
4108 lc_opt_entry_t *ia32_grp;
4110 be_grp = lc_opt_get_grp(firm_opt_get_root(), "be");
4111 ia32_grp = lc_opt_get_grp(be_grp, "ia32");
4113 lc_opt_add_table(ia32_grp, ia32_emitter_options);
4117 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.emitter");