2 * Copyright (C) 1995-2011 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This file implements the ia32 node emitter.
23 * @author Christian Wuerdig, Matthias Braun
25 * Summary table for x86 floatingpoint compares:
26 * (remember effect of unordered on x86: ZF=1, PF=1, CF=1)
34 * pnc_Leg => NP (ordered)
56 #include "iredges_t.h"
60 #include "raw_bitset.h"
69 #include "beemitter.h"
73 #include "ia32_emitter.h"
74 #include "ia32_common_transform.h"
75 #include "gen_ia32_emitter.h"
76 #include "gen_ia32_regalloc_if.h"
77 #include "ia32_nodes_attr.h"
78 #include "ia32_new_nodes.h"
79 #include "ia32_architecture.h"
80 #include "bearch_ia32_t.h"
82 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
84 static const ia32_isa_t *isa;
85 static char pic_base_label[128];
86 static ir_label_t exc_label_id;
87 static int mark_spill_reload = 0;
90 static bool sp_relative;
91 static int frame_type_size;
92 static int callframe_offset;
94 /** Return the next block in Block schedule */
95 static ir_node *get_prev_block_sched(const ir_node *block)
97 return (ir_node*)get_irn_link(block);
100 /** Checks if the current block is a fall-through target. */
101 static int is_fallthrough(const ir_node *cfgpred)
105 if (!is_Proj(cfgpred))
107 pred = get_Proj_pred(cfgpred);
108 if (is_ia32_SwitchJmp(pred))
115 * returns non-zero if the given block needs a label
116 * because of being a jump-target (and not a fall-through)
118 static int block_needs_label(const ir_node *block)
121 int n_cfgpreds = get_Block_n_cfgpreds(block);
123 if (get_Block_entity(block) != NULL)
126 if (n_cfgpreds == 0) {
128 } else if (n_cfgpreds == 1) {
129 ir_node *cfgpred = get_Block_cfgpred(block, 0);
130 ir_node *cfgpred_block = get_nodes_block(cfgpred);
132 if (get_prev_block_sched(block) == cfgpred_block
133 && is_fallthrough(cfgpred)) {
142 * Add a number to a prefix. This number will not be used a second time.
144 static char *get_unique_label(char *buf, size_t buflen, const char *prefix)
146 static unsigned long id = 0;
147 snprintf(buf, buflen, "%s%s%lu", be_gas_get_private_prefix(), prefix, ++id);
152 * Emit the name of the 8bit low register
154 static void emit_8bit_register(const arch_register_t *reg)
156 const char *reg_name = arch_register_get_name(reg);
157 assert(reg->index == REG_GP_EAX || reg->index == REG_GP_EBX
158 || reg->index == REG_GP_ECX || reg->index == REG_GP_EDX);
161 be_emit_char(reg_name[1]); /* get the basic name of the register */
166 * Emit the name of the 8bit high register
168 static void emit_8bit_register_high(const arch_register_t *reg)
170 const char *reg_name = arch_register_get_name(reg);
171 assert(reg->index == REG_GP_EAX || reg->index == REG_GP_EBX
172 || reg->index == REG_GP_ECX || reg->index == REG_GP_EDX);
175 be_emit_char(reg_name[1]); /* get the basic name of the register */
179 static void emit_16bit_register(const arch_register_t *reg)
181 const char *reg_name = arch_register_get_name(reg);
184 be_emit_string(reg_name+1); /* skip the 'e' prefix of the 32bit names */
188 * emit a register, possible shortened by a mode
190 * @param reg the register
191 * @param mode the mode of the register or NULL for full register
193 static void emit_register(const arch_register_t *reg, const ir_mode *mode)
195 const char *reg_name;
198 int size = get_mode_size_bits(mode);
200 case 8: emit_8bit_register(reg); return;
201 case 16: emit_16bit_register(reg); return;
203 assert(mode_is_float(mode) || size == 32);
206 reg_name = arch_register_get_name(reg);
209 be_emit_string(reg_name);
212 static void ia32_emit_entity(ir_entity *entity, int no_pic_adjust)
214 be_gas_emit_entity(entity);
216 if (get_entity_owner(entity) == get_tls_type()) {
217 if (!entity_has_definition(entity)) {
218 be_emit_cstring("@INDNTPOFF");
220 be_emit_cstring("@NTPOFF");
224 if (do_pic && !no_pic_adjust) {
226 be_emit_string(pic_base_label);
230 static void emit_ia32_Immediate_no_prefix(const ir_node *node)
232 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(node);
234 if (attr->symconst != NULL) {
237 ia32_emit_entity(attr->symconst, attr->no_pic_adjust);
239 if (attr->symconst == NULL || attr->offset != 0) {
240 if (attr->symconst != NULL) {
241 be_emit_irprintf("%+d", attr->offset);
243 be_emit_irprintf("0x%X", attr->offset);
248 static void emit_ia32_Immediate(const ir_node *node)
251 emit_ia32_Immediate_no_prefix(node);
254 static void ia32_emit_mode_suffix_mode(const ir_mode *mode)
256 assert(mode_is_int(mode) || mode_is_reference(mode));
257 switch (get_mode_size_bits(mode)) {
258 case 8: be_emit_char('b'); return;
259 case 16: be_emit_char('w'); return;
260 case 32: be_emit_char('l'); return;
261 /* gas docu says q is the suffix but gcc, objdump and icc use ll
263 case 64: be_emit_cstring("ll"); return;
265 panic("Can't output mode_suffix for %+F", mode);
268 static void ia32_emit_x87_mode_suffix(ir_node const *const node)
272 /* we only need to emit the mode on address mode */
273 if (get_ia32_op_type(node) == ia32_Normal)
276 mode = get_ia32_ls_mode(node);
277 assert(mode != NULL);
279 if (mode_is_float(mode)) {
280 switch (get_mode_size_bits(mode)) {
281 case 32: be_emit_char('s'); return;
282 case 64: be_emit_char('l'); return;
283 /* long doubles have different sizes due to alignment on different
287 case 128: be_emit_char('t'); return;
290 assert(mode_is_int(mode) || mode_is_reference(mode));
291 switch (get_mode_size_bits(mode)) {
292 case 16: be_emit_char('s'); return;
293 case 32: be_emit_char('l'); return;
294 /* gas docu says q is the suffix but gcc, objdump and icc use ll
296 case 64: be_emit_cstring("ll"); return;
299 panic("Can't output mode_suffix for %+F", mode);
302 static char get_xmm_mode_suffix(ir_mode *mode)
304 assert(mode_is_float(mode));
305 switch (get_mode_size_bits(mode)) {
308 default: panic("Invalid XMM mode");
312 static void ia32_emit_xmm_mode_suffix(ir_node const *const node)
314 ir_mode *mode = get_ia32_ls_mode(node);
315 assert(mode != NULL);
316 be_emit_char(get_xmm_mode_suffix(mode));
320 * Returns the target block for a control flow node.
322 static ir_node *get_cfop_target_block(const ir_node *irn)
324 assert(get_irn_mode(irn) == mode_X);
325 return (ir_node*)get_irn_link(irn);
329 * Emits the target label for a control flow node.
331 static void ia32_emit_cfop_target(const ir_node *node)
333 ir_node *block = get_cfop_target_block(node);
334 be_gas_emit_block_name(block);
338 * Emit the suffix for a compare instruction.
340 static void ia32_emit_condition_code(ia32_condition_code_t cc)
343 case ia32_cc_overflow: be_emit_cstring("o"); return;
344 case ia32_cc_not_overflow: be_emit_cstring("no"); return;
345 case ia32_cc_float_below:
346 case ia32_cc_float_unordered_below:
347 case ia32_cc_below: be_emit_cstring("b"); return;
348 case ia32_cc_float_above_equal:
349 case ia32_cc_float_unordered_above_equal:
350 case ia32_cc_above_equal: be_emit_cstring("ae"); return;
351 case ia32_cc_float_equal:
352 case ia32_cc_equal: be_emit_cstring("e"); return;
353 case ia32_cc_float_not_equal:
354 case ia32_cc_not_equal: be_emit_cstring("ne"); return;
355 case ia32_cc_float_below_equal:
356 case ia32_cc_float_unordered_below_equal:
357 case ia32_cc_below_equal: be_emit_cstring("be"); return;
358 case ia32_cc_float_above:
359 case ia32_cc_float_unordered_above:
360 case ia32_cc_above: be_emit_cstring("a"); return;
361 case ia32_cc_sign: be_emit_cstring("s"); return;
362 case ia32_cc_not_sign: be_emit_cstring("ns"); return;
363 case ia32_cc_parity: be_emit_cstring("p"); return;
364 case ia32_cc_not_parity: be_emit_cstring("np"); return;
365 case ia32_cc_less: be_emit_cstring("l"); return;
366 case ia32_cc_greater_equal: be_emit_cstring("ge"); return;
367 case ia32_cc_less_equal: be_emit_cstring("le"); return;
368 case ia32_cc_greater: be_emit_cstring("g"); return;
369 case ia32_cc_float_parity_cases:
370 case ia32_cc_additional_float_cases:
373 panic("Invalid ia32 condition code");
376 typedef enum ia32_emit_mod_t {
378 EMIT_RESPECT_LS = 1U << 0,
379 EMIT_ALTERNATE_AM = 1U << 1,
381 EMIT_HIGH_REG = 1U << 3,
382 EMIT_LOW_REG = 1U << 4,
383 EMIT_16BIT_REG = 1U << 5
385 ENUM_BITSET(ia32_emit_mod_t)
388 * Emits address mode.
390 static void ia32_emit_am(ir_node const *const node)
392 ir_entity *ent = get_ia32_am_sc(node);
393 int offs = get_ia32_am_offs_int(node);
394 ir_node *base = get_irn_n(node, n_ia32_base);
395 int has_base = !is_ia32_NoReg_GP(base);
396 ir_node *idx = get_irn_n(node, n_ia32_index);
397 int has_index = !is_ia32_NoReg_GP(idx);
399 /* just to be sure... */
400 assert(!is_ia32_use_frame(node) || get_ia32_frame_ent(node) != NULL);
402 if (get_ia32_am_tls_segment(node))
403 be_emit_cstring("%gs:");
407 const ia32_attr_t *attr = get_ia32_attr_const(node);
408 if (is_ia32_am_sc_sign(node))
410 ia32_emit_entity(ent, attr->data.am_sc_no_pic_adjust);
413 /* also handle special case if nothing is set */
414 if (offs != 0 || (ent == NULL && !has_base && !has_index)) {
416 be_emit_irprintf("%+d", offs);
418 be_emit_irprintf("%d", offs);
422 if (has_base || has_index) {
427 const arch_register_t *reg = arch_get_irn_register_in(node, n_ia32_base);
428 emit_register(reg, NULL);
431 /* emit index + scale */
433 const arch_register_t *reg = arch_get_irn_register_in(node, n_ia32_index);
436 emit_register(reg, NULL);
438 scale = get_ia32_am_scale(node);
440 be_emit_irprintf(",%d", 1 << scale);
447 static ia32_condition_code_t determine_final_cc(ir_node const *node, int flags_pos, ia32_condition_code_t cc);
449 void ia32_emitf(ir_node const *const node, char const *fmt, ...)
456 const char *start = fmt;
457 ia32_emit_mod_t mod = EMIT_NONE;
459 while (*fmt != '%' && *fmt != '\n' && *fmt != '\0')
462 be_emit_string_len(start, fmt - start);
467 be_emit_write_line();
481 case '*': mod |= EMIT_ALTERNATE_AM; break;
482 case '#': mod |= EMIT_RESPECT_LS; break;
483 case 'l': mod |= EMIT_LONG; break;
484 case '>': mod |= EMIT_HIGH_REG; break;
485 case '<': mod |= EMIT_LOW_REG; break;
486 case '^': mod |= EMIT_16BIT_REG; break;
495 arch_register_t const *reg;
505 if (get_ia32_op_type(node) == ia32_AddrModeS) {
508 assert(get_ia32_op_type(node) == ia32_Normal);
509 ia32_x87_attr_t const *const x87_attr = get_ia32_x87_attr_const(node);
510 arch_register_t const *const out = x87_attr->x87[2];
511 arch_register_t const * in = x87_attr->x87[1];
513 in = x87_attr->x87[0];
514 be_emit_irprintf("%%%s, %%%s", arch_register_get_name(in), arch_register_get_name(out));
520 if (mod & EMIT_ALTERNATE_AM)
526 reg = va_arg(ap, const arch_register_t*);
527 if (get_ia32_op_type(node) == ia32_AddrModeS) {
534 if (get_ia32_op_type(node) == ia32_AddrModeS) {
538 assert(get_ia32_op_type(node) == ia32_Normal);
542 default: goto unknown;
548 imm = get_irn_n(node, n_ia32_binary_right);
549 if (is_ia32_Immediate(imm)) {
550 emit_ia32_Immediate(imm);
551 be_emit_cstring(", ");
552 if (get_ia32_op_type(node) == ia32_AddrModeS) {
555 assert(get_ia32_op_type(node) == ia32_Normal);
556 reg = arch_get_irn_register_in(node, n_ia32_binary_left);
557 emit_register(reg, get_ia32_ls_mode(node));
560 if (get_ia32_op_type(node) == ia32_AddrModeS) {
563 assert(get_ia32_op_type(node) == ia32_Normal);
564 reg = arch_get_irn_register_in(node, n_ia32_binary_right);
565 emit_register(reg, get_ia32_ls_mode(node));
567 be_emit_cstring(", ");
568 reg = arch_get_irn_register_in(node, n_ia32_binary_left);
569 emit_register(reg, get_ia32_ls_mode(node));
574 if (*fmt < '0' || '9' < *fmt)
576 reg = arch_get_irn_register_out(node, *fmt++ - '0');
582 ia32_emit_x87_mode_suffix(node);
583 } else if (*fmt == 'R') {
585 /* NOTE: Work around a gas quirk for non-commutative operations if the
586 * destination register is not %st0. In this case r/non-r is swapped.
587 * %st0 = %st0 - %st1 -> fsub %st1, %st0 (as expected)
588 * %st0 = %st1 - %st0 -> fsubr %st1, %st0 (as expected)
589 * %st1 = %st0 - %st1 -> fsub %st0, %st1 (expected: fsubr)
590 * %st1 = %st1 - %st0 -> fsubr %st0, %st1 (expected: fsub)
591 * In fact this corresponds to the encoding of the instruction:
592 * - The r suffix selects whether %st0 is on the left (no r) or on the
593 * right (r) side of the executed operation.
594 * - The placement of %st0 selects whether the result is written to
595 * %st0 (right) or the other register (left).
596 * This results in testing whether the left operand register is %st0
597 * instead of the expected test whether the output register equals the
598 * left operand register. */
599 ia32_x87_attr_t const *const attr = get_ia32_x87_attr_const(node);
600 if (get_ia32_op_type(node) == ia32_Normal ?
601 attr->x87[0] != &ia32_registers[REG_ST0] :
602 attr->attr.data.ins_permuted)
604 } else if (*fmt == 'X') {
606 ia32_emit_xmm_mode_suffix(node);
607 } else if ('0' <= *fmt && *fmt <= '2') {
608 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
610 be_emit_string(attr->x87[*fmt++ - '0']->name);
619 if (!(mod & EMIT_ALTERNATE_AM))
621 emit_ia32_Immediate_no_prefix(imm);
625 ia32_emit_cfop_target(node);
629 ir_mode *mode = get_ia32_ls_mode(node);
632 if (mod & EMIT_RESPECT_LS) {
633 if (get_mode_size_bits(mode) == 32)
635 be_emit_char(mode_is_signed(mode) ? 's' : 'z');
637 ia32_emit_mode_suffix_mode(mode);
642 ia32_condition_code_t cc;
645 cc = (ia32_condition_code_t)va_arg(ap, int);
646 } else if ('0' <= *fmt && *fmt <= '9') {
647 cc = get_ia32_condcode(node);
648 cc = determine_final_cc(node, *fmt - '0', cc);
653 ia32_emit_condition_code(cc);
658 reg = va_arg(ap, const arch_register_t*);
660 if (mod & EMIT_ALTERNATE_AM)
662 if (mod & EMIT_HIGH_REG) {
663 emit_8bit_register_high(reg);
664 } else if (mod & EMIT_LOW_REG) {
665 emit_8bit_register(reg);
666 } else if (mod & EMIT_16BIT_REG) {
667 emit_16bit_register(reg);
669 emit_register(reg, mod & EMIT_RESPECT_LS ? get_ia32_ls_mode(node) : NULL);
677 if (*fmt < '0' || '9' < *fmt)
681 imm = get_irn_n(node, pos);
682 if (is_ia32_Immediate(imm)) {
685 reg = arch_get_irn_register_in(node, pos);
691 const char *str = va_arg(ap, const char*);
697 if (mod & EMIT_LONG) {
698 unsigned long num = va_arg(ap, unsigned long);
699 be_emit_irprintf("%lu", num);
701 unsigned num = va_arg(ap, unsigned);
702 be_emit_irprintf("%u", num);
707 if (mod & EMIT_LONG) {
708 long num = va_arg(ap, long);
709 be_emit_irprintf("%ld", num);
711 int num = va_arg(ap, int);
712 be_emit_irprintf("%d", num);
718 panic("unknown format conversion");
722 be_emit_finish_line_gas(node);
726 static void emit_ia32_IMul(const ir_node *node)
728 ir_node *left = get_irn_n(node, n_ia32_IMul_left);
729 const arch_register_t *out_reg = arch_get_irn_register_out(node, pn_ia32_IMul_res);
731 /* do we need the 3-address form? */
732 if (is_ia32_NoReg_GP(left) ||
733 arch_get_irn_register_in(node, n_ia32_IMul_left) != out_reg) {
734 ia32_emitf(node, "imul%M %#S4, %#AS3, %#D0");
736 ia32_emitf(node, "imul%M %#AS4, %#S3");
741 * walks up a tree of copies/perms/spills/reloads to find the original value
742 * that is moved around
744 static ir_node *find_original_value(ir_node *node)
746 if (irn_visited(node))
749 mark_irn_visited(node);
750 if (be_is_Copy(node)) {
751 return find_original_value(be_get_Copy_op(node));
752 } else if (be_is_CopyKeep(node)) {
753 return find_original_value(be_get_CopyKeep_op(node));
754 } else if (is_Proj(node)) {
755 ir_node *pred = get_Proj_pred(node);
756 if (be_is_Perm(pred)) {
757 return find_original_value(get_irn_n(pred, get_Proj_proj(node)));
758 } else if (be_is_MemPerm(pred)) {
759 return find_original_value(get_irn_n(pred, get_Proj_proj(node) + 1));
760 } else if (is_ia32_Load(pred)) {
761 return find_original_value(get_irn_n(pred, n_ia32_Load_mem));
762 } else if (is_ia32_Store(pred)) {
763 return find_original_value(get_irn_n(pred, n_ia32_Store_val));
767 } else if (is_Phi(node)) {
769 arity = get_irn_arity(node);
770 for (i = 0; i < arity; ++i) {
771 ir_node *in = get_irn_n(node, i);
772 ir_node *res = find_original_value(in);
783 static ia32_condition_code_t determine_final_cc(const ir_node *node,
784 int flags_pos, ia32_condition_code_t cc)
786 ir_node *flags = get_irn_n(node, flags_pos);
787 const ia32_attr_t *flags_attr;
788 flags = skip_Proj(flags);
790 if (is_ia32_Sahf(flags)) {
791 ir_node *cmp = get_irn_n(flags, n_ia32_Sahf_val);
792 if (!(is_ia32_FucomFnstsw(cmp) || is_ia32_FucompFnstsw(cmp)
793 || is_ia32_FucomppFnstsw(cmp) || is_ia32_FtstFnstsw(cmp))) {
794 inc_irg_visited(current_ir_graph);
795 cmp = find_original_value(cmp);
797 assert(is_ia32_FucomFnstsw(cmp) || is_ia32_FucompFnstsw(cmp)
798 || is_ia32_FucomppFnstsw(cmp) || is_ia32_FtstFnstsw(cmp));
801 flags_attr = get_ia32_attr_const(cmp);
803 flags_attr = get_ia32_attr_const(flags);
806 if (flags_attr->data.ins_permuted)
807 cc = ia32_invert_condition_code(cc);
812 * Emits an exception label for a given node.
814 static void ia32_emit_exc_label(const ir_node *node)
816 be_emit_string(be_gas_insn_label_prefix());
817 be_emit_irprintf("%lu", get_ia32_exc_label_id(node));
821 * Returns the Proj with projection number proj and NOT mode_M
823 static ir_node *get_proj(const ir_node *node, long proj)
827 assert(get_irn_mode(node) == mode_T && "expected mode_T node");
829 foreach_out_edge(node, edge) {
830 src = get_edge_src_irn(edge);
832 assert(is_Proj(src) && "Proj expected");
833 if (get_irn_mode(src) == mode_M)
836 if (get_Proj_proj(src) == proj)
842 static int can_be_fallthrough(const ir_node *node)
844 ir_node *target_block = get_cfop_target_block(node);
845 ir_node *block = get_nodes_block(node);
846 return get_prev_block_sched(target_block) == block;
850 * Emits the jump sequence for a conditional jump (cmp + jmp_true + jmp_false)
852 static void emit_ia32_Jcc(const ir_node *node)
854 int need_parity_label = 0;
855 ia32_condition_code_t cc = get_ia32_condcode(node);
856 const ir_node *proj_true;
857 const ir_node *proj_false;
859 cc = determine_final_cc(node, 0, cc);
862 proj_true = get_proj(node, pn_ia32_Jcc_true);
863 assert(proj_true && "Jcc without true Proj");
865 proj_false = get_proj(node, pn_ia32_Jcc_false);
866 assert(proj_false && "Jcc without false Proj");
868 if (can_be_fallthrough(proj_true)) {
869 /* exchange both proj's so the second one can be omitted */
870 const ir_node *t = proj_true;
872 proj_true = proj_false;
874 cc = ia32_negate_condition_code(cc);
877 if (cc & ia32_cc_float_parity_cases) {
878 /* Some floating point comparisons require a test of the parity flag,
879 * which indicates that the result is unordered */
880 if (cc & ia32_cc_negated) {
881 ia32_emitf(proj_true, "jp %L");
883 /* we need a local label if the false proj is a fallthrough
884 * as the falseblock might have no label emitted then */
885 if (can_be_fallthrough(proj_false)) {
886 need_parity_label = 1;
887 ia32_emitf(proj_false, "jp 1f");
889 ia32_emitf(proj_false, "jp %L");
893 ia32_emitf(proj_true, "j%PX %L", (int)cc);
894 if (need_parity_label) {
895 be_emit_cstring("1:\n");
896 be_emit_write_line();
899 /* the second Proj might be a fallthrough */
900 if (can_be_fallthrough(proj_false)) {
901 if (be_options.verbose_asm)
902 ia32_emitf(proj_false, "/* fallthrough to %L */");
904 ia32_emitf(proj_false, "jmp %L");
909 * Emits an ia32 Setcc. This is mostly easy but some floating point compares
912 static void emit_ia32_Setcc(const ir_node *node)
914 const arch_register_t *dreg = arch_get_irn_register_out(node, pn_ia32_Setcc_res);
916 ia32_condition_code_t cc = get_ia32_condcode(node);
917 cc = determine_final_cc(node, n_ia32_Setcc_eflags, cc);
918 if (cc & ia32_cc_float_parity_cases) {
919 if (cc & ia32_cc_negated) {
920 ia32_emitf(node, "set%PX %<R", (int)cc, dreg);
921 ia32_emitf(node, "setp %>R", dreg);
922 ia32_emitf(node, "orb %>R, %<R", dreg, dreg);
924 ia32_emitf(node, "set%PX %<R", (int)cc, dreg);
925 ia32_emitf(node, "setnp %>R", dreg);
926 ia32_emitf(node, "andb %>R, %<R", dreg, dreg);
929 ia32_emitf(node, "set%PX %#R", (int)cc, dreg);
933 static void emit_ia32_CMovcc(const ir_node *node)
935 const ia32_attr_t *attr = get_ia32_attr_const(node);
936 const arch_register_t *out = arch_get_irn_register_out(node, pn_ia32_res);
937 ia32_condition_code_t cc = get_ia32_condcode(node);
938 const arch_register_t *in_true;
939 const arch_register_t *in_false;
941 cc = determine_final_cc(node, n_ia32_CMovcc_eflags, cc);
942 /* although you can't set ins_permuted in the constructor it might still
943 * be set by memory operand folding
944 * Permuting inputs of a cmov means the condition is negated!
946 if (attr->data.ins_permuted)
947 cc = ia32_negate_condition_code(cc);
949 in_true = arch_get_irn_register(get_irn_n(node, n_ia32_CMovcc_val_true));
950 in_false = arch_get_irn_register(get_irn_n(node, n_ia32_CMovcc_val_false));
952 /* should be same constraint fullfilled? */
953 if (out == in_false) {
954 /* yes -> nothing to do */
955 } else if (out == in_true) {
956 const arch_register_t *tmp;
958 assert(get_ia32_op_type(node) == ia32_Normal);
960 cc = ia32_negate_condition_code(cc);
967 ia32_emitf(node, "movl %R, %R", in_false, out);
970 if (cc & ia32_cc_float_parity_cases) {
971 panic("CMov with floatingpoint compare/parity not supported yet");
974 ia32_emitf(node, "cmov%PX %#AR, %#R", (int)cc, in_true, out);
978 * Emits code for a SwitchJmp
980 static void emit_ia32_SwitchJmp(const ir_node *node)
982 ir_entity *jump_table = get_ia32_am_sc(node);
983 const ir_switch_table *table = get_ia32_switch_table(node);
985 ia32_emitf(node, "jmp %*AM");
986 be_emit_jump_table(node, table, jump_table, get_cfop_target_block);
990 * Emits code for a unconditional jump.
992 static void emit_ia32_Jmp(const ir_node *node)
994 /* we have a block schedule */
995 if (can_be_fallthrough(node)) {
996 if (be_options.verbose_asm)
997 ia32_emitf(node, "/* fallthrough to %L */");
999 ia32_emitf(node, "jmp %L");
1004 * Emit an inline assembler operand.
1006 * @param node the ia32_ASM node
1007 * @param s points to the operand (a %c)
1009 * @return pointer to the first char in s NOT in the current operand
1011 static const char* emit_asm_operand(const ir_node *node, const char *s)
1013 const ia32_attr_t *ia32_attr = get_ia32_attr_const(node);
1014 const ia32_asm_attr_t *attr = CONST_CAST_IA32_ATTR(ia32_asm_attr_t,
1016 const arch_register_t *reg;
1017 const ia32_asm_reg_t *asm_regs = attr->register_map;
1018 const ia32_asm_reg_t *asm_reg;
1027 /* parse modifiers */
1030 ir_fprintf(stderr, "Warning: asm text (%+F) ends with %%\n", node);
1055 "Warning: asm text (%+F) contains unknown modifier '%c' for asm op\n",
1062 if (sscanf(s, "%d%n", &num, &p) != 1) {
1063 ir_fprintf(stderr, "Warning: Couldn't parse assembler operand (%+F)\n",
1070 if (num < 0 || ARR_LEN(asm_regs) <= (size_t)num) {
1072 "Error: Custom assembler references invalid input/output (%+F)\n",
1076 asm_reg = & asm_regs[num];
1077 assert(asm_reg->valid);
1080 if (asm_reg->use_input == 0) {
1081 reg = arch_get_irn_register_out(node, asm_reg->inout_pos);
1083 ir_node *pred = get_irn_n(node, asm_reg->inout_pos);
1085 /* might be an immediate value */
1086 if (is_ia32_Immediate(pred)) {
1087 emit_ia32_Immediate(pred);
1090 reg = arch_get_irn_register_in(node, asm_reg->inout_pos);
1094 "Warning: no register assigned for %d asm op (%+F)\n",
1099 if (asm_reg->memory) {
1104 if (modifier != 0) {
1107 emit_8bit_register(reg);
1110 emit_8bit_register_high(reg);
1113 emit_16bit_register(reg);
1116 panic("Invalid asm op modifier");
1119 emit_register(reg, asm_reg->memory ? mode_Iu : asm_reg->mode);
1122 if (asm_reg->memory) {
1130 * Emits code for an ASM pseudo op.
1132 static void emit_ia32_Asm(const ir_node *node)
1134 const void *gen_attr = get_irn_generic_attr_const(node);
1135 const ia32_asm_attr_t *attr
1136 = CONST_CAST_IA32_ATTR(ia32_asm_attr_t, gen_attr);
1137 ident *asm_text = attr->asm_text;
1138 const char *s = get_id_str(asm_text);
1140 be_emit_cstring("#APP\n");
1141 be_emit_write_line();
1148 s = emit_asm_operand(node, s);
1154 be_emit_cstring("\n#NO_APP\n");
1155 be_emit_write_line();
1160 * Emit movsb/w instructions to make mov count divideable by 4
1162 static void emit_CopyB_prolog(unsigned size)
1165 ia32_emitf(NULL, "movsb");
1167 ia32_emitf(NULL, "movsw");
1171 * Emit rep movsd instruction for memcopy.
1173 static void emit_ia32_CopyB(const ir_node *node)
1175 unsigned size = get_ia32_copyb_size(node);
1177 emit_CopyB_prolog(size);
1178 ia32_emitf(node, "rep movsd");
1182 * Emits unrolled memcopy.
1184 static void emit_ia32_CopyB_i(const ir_node *node)
1186 unsigned size = get_ia32_copyb_size(node);
1188 emit_CopyB_prolog(size);
1192 ia32_emitf(NULL, "movsd");
1198 * Emit code for conversions (I, FP), (FP, I) and (FP, FP).
1200 static void emit_ia32_Conv_with_FP(const ir_node *node, const char* conv_f,
1203 ir_mode *ls_mode = get_ia32_ls_mode(node);
1204 int ls_bits = get_mode_size_bits(ls_mode);
1205 const char *conv = ls_bits == 32 ? conv_f : conv_d;
1207 ia32_emitf(node, "cvt%s %AS3, %D0", conv);
1210 static void emit_ia32_Conv_I2FP(const ir_node *node)
1212 emit_ia32_Conv_with_FP(node, "si2ss", "si2sd");
1215 static void emit_ia32_Conv_FP2I(const ir_node *node)
1217 emit_ia32_Conv_with_FP(node, "ss2si", "sd2si");
1220 static void emit_ia32_Conv_FP2FP(const ir_node *node)
1222 emit_ia32_Conv_with_FP(node, "sd2ss", "ss2sd");
1226 * Emits code to increase stack pointer.
1228 static void emit_be_IncSP(const ir_node *node)
1230 int offs = be_get_IncSP_offset(node);
1236 ia32_emitf(node, "subl $%u, %D0", offs);
1238 ia32_emitf(node, "addl $%u, %D0", -offs);
1243 * Emits code for Copy/CopyKeep.
1245 static void Copy_emitter(const ir_node *node, const ir_node *op)
1247 const arch_register_t *in = arch_get_irn_register(op);
1248 const arch_register_t *out = arch_get_irn_register(node);
1253 /* copies of vf nodes aren't real... */
1254 if (arch_register_get_class(in) == &ia32_reg_classes[CLASS_ia32_vfp])
1257 ia32_emitf(node, "movl %R, %R", in, out);
1260 static void emit_be_Copy(const ir_node *node)
1262 Copy_emitter(node, be_get_Copy_op(node));
1265 static void emit_be_CopyKeep(const ir_node *node)
1267 Copy_emitter(node, be_get_CopyKeep_op(node));
1271 * Emits code for exchange.
1273 static void emit_be_Perm(const ir_node *node)
1275 const arch_register_t *in0, *in1;
1276 const arch_register_class_t *cls0, *cls1;
1278 in0 = arch_get_irn_register(get_irn_n(node, 0));
1279 in1 = arch_get_irn_register(get_irn_n(node, 1));
1281 cls0 = arch_register_get_class(in0);
1282 cls1 = arch_register_get_class(in1);
1284 assert(cls0 == cls1 && "Register class mismatch at Perm");
1286 if (cls0 == &ia32_reg_classes[CLASS_ia32_gp]) {
1287 ia32_emitf(node, "xchg %R, %R", in1, in0);
1288 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_xmm]) {
1289 ia32_emitf(NULL, "xorpd %R, %R", in1, in0);
1290 ia32_emitf(NULL, "xorpd %R, %R", in0, in1);
1291 ia32_emitf(node, "xorpd %R, %R", in1, in0);
1292 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_vfp]) {
1294 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_st]) {
1297 panic("unexpected register class in be_Perm (%+F)", node);
1301 /* helper function for emit_ia32_Minus64Bit */
1302 static void emit_mov(const ir_node* node, const arch_register_t *src, const arch_register_t *dst)
1304 ia32_emitf(node, "movl %R, %R", src, dst);
1307 /* helper function for emit_ia32_Minus64Bit */
1308 static void emit_neg(const ir_node* node, const arch_register_t *reg)
1310 ia32_emitf(node, "negl %R", reg);
1313 /* helper function for emit_ia32_Minus64Bit */
1314 static void emit_sbb0(const ir_node* node, const arch_register_t *reg)
1316 ia32_emitf(node, "sbbl $0, %R", reg);
1319 /* helper function for emit_ia32_Minus64Bit */
1320 static void emit_sbb(const ir_node* node, const arch_register_t *src, const arch_register_t *dst)
1322 ia32_emitf(node, "sbbl %R, %R", src, dst);
1325 /* helper function for emit_ia32_Minus64Bit */
1326 static void emit_xchg(const ir_node* node, const arch_register_t *src, const arch_register_t *dst)
1328 ia32_emitf(node, "xchgl %R, %R", src, dst);
1331 /* helper function for emit_ia32_Minus64Bit */
1332 static void emit_zero(const ir_node* node, const arch_register_t *reg)
1334 ia32_emitf(node, "xorl %R, %R", reg, reg);
1337 static void emit_ia32_Minus64Bit(const ir_node *node)
1339 const arch_register_t *in_lo = arch_get_irn_register_in(node, 0);
1340 const arch_register_t *in_hi = arch_get_irn_register_in(node, 1);
1341 const arch_register_t *out_lo = arch_get_irn_register_out(node, 0);
1342 const arch_register_t *out_hi = arch_get_irn_register_out(node, 1);
1344 if (out_lo == in_lo) {
1345 if (out_hi != in_hi) {
1346 /* a -> a, b -> d */
1349 /* a -> a, b -> b */
1352 } else if (out_lo == in_hi) {
1353 if (out_hi == in_lo) {
1354 /* a -> b, b -> a */
1355 emit_xchg(node, in_lo, in_hi);
1358 /* a -> b, b -> d */
1359 emit_mov(node, in_hi, out_hi);
1360 emit_mov(node, in_lo, out_lo);
1364 if (out_hi == in_lo) {
1365 /* a -> c, b -> a */
1366 emit_mov(node, in_lo, out_lo);
1368 } else if (out_hi == in_hi) {
1369 /* a -> c, b -> b */
1370 emit_mov(node, in_lo, out_lo);
1373 /* a -> c, b -> d */
1374 emit_mov(node, in_lo, out_lo);
1380 emit_neg( node, out_hi);
1381 emit_neg( node, out_lo);
1382 emit_sbb0(node, out_hi);
1386 emit_zero(node, out_hi);
1387 emit_neg( node, out_lo);
1388 emit_sbb( node, in_hi, out_hi);
1391 static void emit_ia32_GetEIP(const ir_node *node)
1393 ia32_emitf(node, "call %s", pic_base_label);
1394 be_emit_irprintf("%s:\n", pic_base_label);
1395 be_emit_write_line();
1396 ia32_emitf(node, "popl %D0");
1399 static void emit_ia32_ClimbFrame(const ir_node *node)
1401 const ia32_climbframe_attr_t *attr = get_ia32_climbframe_attr_const(node);
1403 ia32_emitf(node, "movl %S0, %D0");
1404 ia32_emitf(node, "movl $%u, %S1", attr->count);
1405 be_gas_emit_block_name(node);
1406 be_emit_cstring(":\n");
1407 be_emit_write_line();
1408 ia32_emitf(node, "movl (%D0), %D0");
1409 ia32_emitf(node, "dec %S1");
1410 be_emit_cstring("\tjnz ");
1411 be_gas_emit_block_name(node);
1412 be_emit_finish_line_gas(node);
1415 static void emit_be_Return(const ir_node *node)
1417 unsigned pop = be_Return_get_pop(node);
1419 if (pop > 0 || be_Return_get_emit_pop(node)) {
1420 ia32_emitf(node, "ret $%u", pop);
1422 ia32_emitf(node, "ret");
1426 static void emit_Nothing(const ir_node *node)
1433 * Enters the emitter functions for handled nodes into the generic
1434 * pointer of an opcode.
1436 static void ia32_register_emitters(void)
1438 #define IA32_EMIT(a) op_ia32_##a->ops.generic = (op_func)emit_ia32_##a
1439 #define EMIT(a) op_##a->ops.generic = (op_func)emit_##a
1440 #define IGN(a) op_##a->ops.generic = (op_func)emit_Nothing
1441 #define BE_EMIT(a) op_be_##a->ops.generic = (op_func)emit_be_##a
1442 #define BE_IGN(a) op_be_##a->ops.generic = (op_func)emit_Nothing
1444 /* first clear the generic function pointer for all ops */
1445 ir_clear_opcodes_generic_func();
1447 /* register all emitter functions defined in spec */
1448 ia32_register_spec_emitters();
1450 /* other ia32 emitter functions */
1453 IA32_EMIT(Conv_FP2FP);
1454 IA32_EMIT(Conv_FP2I);
1455 IA32_EMIT(Conv_I2FP);
1462 IA32_EMIT(Minus64Bit);
1463 IA32_EMIT(SwitchJmp);
1464 IA32_EMIT(ClimbFrame);
1467 /* benode emitter */
1486 typedef void (*emit_func_ptr) (const ir_node *);
1489 * Assign and emit an exception label if the current instruction can fail.
1491 static void ia32_assign_exc_label(ir_node *node)
1493 /* assign a new ID to the instruction */
1494 set_ia32_exc_label_id(node, ++exc_label_id);
1496 ia32_emit_exc_label(node);
1498 be_emit_pad_comment();
1499 be_emit_cstring("/* exception to Block ");
1500 ia32_emit_cfop_target(node);
1501 be_emit_cstring(" */\n");
1502 be_emit_write_line();
1506 * Emits code for a node.
1508 static void ia32_emit_node(ir_node *node)
1510 ir_op *op = get_irn_op(node);
1512 DBG((dbg, LEVEL_1, "emitting code for %+F\n", node));
1514 if (is_ia32_irn(node)) {
1515 if (get_ia32_exc_label(node)) {
1516 /* emit the exception label of this instruction */
1517 ia32_assign_exc_label(node);
1519 if (mark_spill_reload) {
1520 if (is_ia32_is_spill(node)) {
1521 ia32_emitf(NULL, "xchg %ebx, %ebx /* spill mark */");
1523 if (is_ia32_is_reload(node)) {
1524 ia32_emitf(NULL, "xchg %edx, %edx /* reload mark */");
1526 if (is_ia32_is_remat(node)) {
1527 ia32_emitf(NULL, "xchg %ecx, %ecx /* remat mark */");
1531 if (op->ops.generic) {
1532 emit_func_ptr func = (emit_func_ptr) op->ops.generic;
1534 be_dwarf_location(get_irn_dbg_info(node));
1539 ir_fprintf(stderr, "Error: No emit handler for node %+F (%+G, graph %+F)\n", node, node, current_ir_graph);
1544 int sp_change = arch_get_sp_bias(node);
1545 if (sp_change != 0) {
1546 assert(sp_change != SP_BIAS_RESET);
1547 callframe_offset += sp_change;
1548 be_dwarf_callframe_offset(callframe_offset);
1554 * Emits gas alignment directives
1556 static void ia32_emit_alignment(unsigned align, unsigned skip)
1558 ia32_emitf(NULL, ".p2align %u,,%u", align, skip);
1562 * Emits gas alignment directives for Labels depended on cpu architecture.
1564 static void ia32_emit_align_label(void)
1566 unsigned align = ia32_cg_config.label_alignment;
1567 unsigned maximum_skip = ia32_cg_config.label_alignment_max_skip;
1568 ia32_emit_alignment(align, maximum_skip);
1572 * Test whether a block should be aligned.
1573 * For cpus in the P4/Athlon class it is useful to align jump labels to
1574 * 16 bytes. However we should only do that if the alignment nops before the
1575 * label aren't executed more often than we have jumps to the label.
1577 static int should_align_block(const ir_node *block)
1579 static const double DELTA = .0001;
1580 ir_node *prev = get_prev_block_sched(block);
1581 double prev_freq = 0; /**< execfreq of the fallthrough block */
1582 double jmp_freq = 0; /**< execfreq of all non-fallthrough blocks */
1586 if (ia32_cg_config.label_alignment_factor <= 0)
1589 block_freq = get_block_execfreq(block);
1590 if (block_freq < DELTA)
1593 n_cfgpreds = get_Block_n_cfgpreds(block);
1594 for (i = 0; i < n_cfgpreds; ++i) {
1595 const ir_node *pred = get_Block_cfgpred_block(block, i);
1596 double pred_freq = get_block_execfreq(pred);
1599 prev_freq += pred_freq;
1601 jmp_freq += pred_freq;
1605 if (prev_freq < DELTA && !(jmp_freq < DELTA))
1608 jmp_freq /= prev_freq;
1610 return jmp_freq > ia32_cg_config.label_alignment_factor;
1614 * Emit the block header for a block.
1616 * @param block the block
1617 * @param prev_block the previous block
1619 static void ia32_emit_block_header(ir_node *block)
1621 ir_graph *irg = current_ir_graph;
1622 int need_label = block_needs_label(block);
1624 if (block == get_irg_end_block(irg))
1627 if (ia32_cg_config.label_alignment > 0) {
1628 /* align the current block if:
1629 * a) if should be aligned due to its execution frequency
1630 * b) there is no fall-through here
1632 if (should_align_block(block)) {
1633 ia32_emit_align_label();
1635 /* if the predecessor block has no fall-through,
1636 we can always align the label. */
1638 int has_fallthrough = 0;
1640 for (i = get_Block_n_cfgpreds(block) - 1; i >= 0; --i) {
1641 ir_node *cfg_pred = get_Block_cfgpred(block, i);
1642 if (can_be_fallthrough(cfg_pred)) {
1643 has_fallthrough = 1;
1648 if (!has_fallthrough)
1649 ia32_emit_align_label();
1653 be_gas_begin_block(block, need_label);
1657 * Walks over the nodes in a block connected by scheduling edges
1658 * and emits code for each node.
1660 static void ia32_gen_block(ir_node *block)
1662 ia32_emit_block_header(block);
1665 ir_graph *irg = get_irn_irg(block);
1666 callframe_offset = 4; /* 4 bytes for the return address */
1667 /* ESP guessing, TODO perform a real ESP simulation */
1668 if (block != get_irg_start_block(irg)) {
1669 callframe_offset += frame_type_size;
1671 be_dwarf_callframe_offset(callframe_offset);
1674 /* emit the contents of the block */
1675 be_dwarf_location(get_irn_dbg_info(block));
1676 sched_foreach(block, node) {
1677 ia32_emit_node(node);
1681 typedef struct exc_entry {
1682 ir_node *exc_instr; /** The instruction that can issue an exception. */
1683 ir_node *block; /** The block to call then. */
1688 * Sets labels for control flow nodes (jump target).
1689 * Links control predecessors to there destination blocks.
1691 static void ia32_gen_labels(ir_node *block, void *data)
1693 exc_entry **exc_list = (exc_entry**)data;
1697 for (n = get_Block_n_cfgpreds(block) - 1; n >= 0; --n) {
1698 pred = get_Block_cfgpred(block, n);
1699 set_irn_link(pred, block);
1701 pred = skip_Proj(pred);
1702 if (is_ia32_irn(pred) && get_ia32_exc_label(pred)) {
1707 ARR_APP1(exc_entry, *exc_list, e);
1708 set_irn_link(pred, block);
1714 * Compare two exception_entries.
1716 static int cmp_exc_entry(const void *a, const void *b)
1718 const exc_entry *ea = (const exc_entry*)a;
1719 const exc_entry *eb = (const exc_entry*)b;
1721 if (get_ia32_exc_label_id(ea->exc_instr) < get_ia32_exc_label_id(eb->exc_instr))
1726 static parameter_dbg_info_t *construct_parameter_infos(ir_graph *irg)
1728 ir_entity *entity = get_irg_entity(irg);
1729 ir_type *type = get_entity_type(entity);
1730 size_t n_params = get_method_n_params(type);
1731 be_stack_layout_t *layout = be_get_irg_stack_layout(irg);
1732 ir_type *arg_type = layout->arg_type;
1733 size_t n_members = get_compound_n_members(arg_type);
1734 parameter_dbg_info_t *infos = XMALLOCNZ(parameter_dbg_info_t, n_params);
1737 for (i = 0; i < n_members; ++i) {
1738 ir_entity *member = get_compound_member(arg_type, i);
1740 if (!is_parameter_entity(member))
1742 param = get_entity_parameter_number(member);
1743 if (param == IR_VA_START_PARAMETER_NUMBER)
1745 assert(infos[param].entity == NULL && infos[param].reg == NULL);
1746 infos[param].reg = NULL;
1747 infos[param].entity = member;
1754 * Main driver. Emits the code for one routine.
1756 void ia32_gen_routine(ir_graph *irg)
1758 ir_entity *entity = get_irg_entity(irg);
1759 exc_entry *exc_list = NEW_ARR_F(exc_entry, 0);
1760 const arch_env_t *arch_env = be_get_irg_arch_env(irg);
1761 ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
1762 ir_node **blk_sched = irg_data->blk_sched;
1763 be_stack_layout_t *layout = be_get_irg_stack_layout(irg);
1764 parameter_dbg_info_t *infos;
1767 isa = (ia32_isa_t*) arch_env;
1768 do_pic = be_options.pic;
1770 be_gas_elf_type_char = '@';
1772 ia32_register_emitters();
1774 get_unique_label(pic_base_label, sizeof(pic_base_label), "PIC_BASE");
1776 infos = construct_parameter_infos(irg);
1777 be_gas_emit_function_prolog(entity, ia32_cg_config.function_alignment,
1781 sp_relative = layout->sp_relative;
1782 if (layout->sp_relative) {
1783 ir_type *frame_type = get_irg_frame_type(irg);
1784 frame_type_size = get_type_size_bytes(frame_type);
1785 be_dwarf_callframe_register(&ia32_registers[REG_ESP]);
1787 /* well not entirely correct here, we should emit this after the
1788 * "movl esp, ebp" */
1789 be_dwarf_callframe_register(&ia32_registers[REG_EBP]);
1790 /* TODO: do not hardcode the following */
1791 be_dwarf_callframe_offset(8);
1792 be_dwarf_callframe_spilloffset(&ia32_registers[REG_EBP], -8);
1795 /* we use links to point to target blocks */
1796 ir_reserve_resources(irg, IR_RESOURCE_IRN_LINK);
1797 irg_block_walk_graph(irg, ia32_gen_labels, NULL, &exc_list);
1799 /* initialize next block links */
1800 n = ARR_LEN(blk_sched);
1801 for (i = 0; i < n; ++i) {
1802 ir_node *block = blk_sched[i];
1803 ir_node *prev = i > 0 ? blk_sched[i-1] : NULL;
1805 set_irn_link(block, prev);
1808 for (i = 0; i < n; ++i) {
1809 ir_node *block = blk_sched[i];
1811 ia32_gen_block(block);
1814 be_gas_emit_function_epilog(entity);
1816 ir_free_resources(irg, IR_RESOURCE_IRN_LINK);
1818 /* Sort the exception table using the exception label id's.
1819 Those are ascending with ascending addresses. */
1820 qsort(exc_list, ARR_LEN(exc_list), sizeof(exc_list[0]), cmp_exc_entry);
1824 for (e = 0; e < ARR_LEN(exc_list); ++e) {
1825 be_emit_cstring("\t.long ");
1826 ia32_emit_exc_label(exc_list[e].exc_instr);
1828 be_emit_cstring("\t.long ");
1829 be_gas_emit_block_name(exc_list[e].block);
1833 DEL_ARR_F(exc_list);
1836 static const lc_opt_table_entry_t ia32_emitter_options[] = {
1837 LC_OPT_ENT_BOOL("mark_spill_reload", "mark spills and reloads with ud opcodes", &mark_spill_reload),
1841 /* ==== Experimental binary emitter ==== */
1843 static unsigned char reg_gp_map[N_ia32_gp_REGS];
1844 //static unsigned char reg_mmx_map[N_ia32_mmx_REGS];
1845 //static unsigned char reg_sse_map[N_ia32_xmm_REGS];
1847 static void build_reg_map(void)
1849 reg_gp_map[REG_GP_EAX] = 0x0;
1850 reg_gp_map[REG_GP_ECX] = 0x1;
1851 reg_gp_map[REG_GP_EDX] = 0x2;
1852 reg_gp_map[REG_GP_EBX] = 0x3;
1853 reg_gp_map[REG_GP_ESP] = 0x4;
1854 reg_gp_map[REG_GP_EBP] = 0x5;
1855 reg_gp_map[REG_GP_ESI] = 0x6;
1856 reg_gp_map[REG_GP_EDI] = 0x7;
1859 /** Returns the encoding for a pnc field. */
1860 static unsigned char pnc2cc(ia32_condition_code_t cc)
1865 /** Sign extension bit values for binops */
1867 UNSIGNED_IMM = 0, /**< unsigned immediate */
1868 SIGNEXT_IMM = 2, /**< sign extended immediate */
1871 /** The mod encoding of the ModR/M */
1873 MOD_IND = 0x00, /**< [reg1] */
1874 MOD_IND_BYTE_OFS = 0x40, /**< [reg1 + byte ofs] */
1875 MOD_IND_WORD_OFS = 0x80, /**< [reg1 + word ofs] */
1876 MOD_REG = 0xC0 /**< reg1 */
1879 /** create R/M encoding for ModR/M */
1880 #define ENC_RM(x) (x)
1881 /** create REG encoding for ModR/M */
1882 #define ENC_REG(x) ((x) << 3)
1884 /** create encoding for a SIB byte */
1885 #define ENC_SIB(scale, index, base) ((scale) << 6 | (index) << 3 | (base))
1887 /* Node: The following routines are supposed to append bytes, words, dwords
1888 to the output stream.
1889 Currently the implementation is stupid in that it still creates output
1890 for an "assembler" in the form of .byte, .long
1891 We will change this when enough infrastructure is there to create complete
1892 machine code in memory/object files */
1894 static void bemit8(const unsigned char byte)
1896 be_emit_irprintf("\t.byte 0x%x\n", byte);
1897 be_emit_write_line();
1900 static void bemit16(const unsigned short u16)
1902 be_emit_irprintf("\t.word 0x%x\n", u16);
1903 be_emit_write_line();
1906 static void bemit32(const unsigned u32)
1908 be_emit_irprintf("\t.long 0x%x\n", u32);
1909 be_emit_write_line();
1913 * Emit address of an entity. If @p is_relative is true then a relative
1914 * offset from behind the address to the entity is created.
1916 static void bemit_entity(ir_entity *entity, bool entity_sign, int offset,
1919 if (entity == NULL) {
1924 /* the final version should remember the position in the bytestream
1925 and patch it with the correct address at linktime... */
1926 be_emit_cstring("\t.long ");
1929 be_gas_emit_entity(entity);
1931 if (get_entity_owner(entity) == get_tls_type()) {
1932 if (!entity_has_definition(entity)) {
1933 be_emit_cstring("@INDNTPOFF");
1935 be_emit_cstring("@NTPOFF");
1940 be_emit_cstring("-.");
1945 be_emit_irprintf("%+d", offset);
1948 be_emit_write_line();
1951 static void bemit_jmp_destination(const ir_node *dest_block)
1953 be_emit_cstring("\t.long ");
1954 be_gas_emit_block_name(dest_block);
1955 be_emit_cstring(" - . - 4\n");
1956 be_emit_write_line();
1959 /* end emit routines, all emitters following here should only use the functions
1962 typedef enum reg_modifier {
1967 /** Create a ModR/M byte for src1,src2 registers */
1968 static void bemit_modrr(const arch_register_t *src1,
1969 const arch_register_t *src2)
1971 unsigned char modrm = MOD_REG;
1972 modrm |= ENC_RM(reg_gp_map[src1->index]);
1973 modrm |= ENC_REG(reg_gp_map[src2->index]);
1977 /** Create a ModR/M8 byte for src1,src2 registers */
1978 static void bemit_modrr8(reg_modifier_t high_part1, const arch_register_t *src1,
1979 reg_modifier_t high_part2, const arch_register_t *src2)
1981 unsigned char modrm = MOD_REG;
1982 modrm |= ENC_RM(reg_gp_map[src1->index] + (high_part1 == REG_HIGH ? 4 : 0));
1983 modrm |= ENC_REG(reg_gp_map[src2->index] + (high_part2 == REG_HIGH ? 4 : 0));
1987 /** Create a ModR/M byte for one register and extension */
1988 static void bemit_modru(const arch_register_t *reg, unsigned ext)
1990 unsigned char modrm = MOD_REG;
1992 modrm |= ENC_RM(reg_gp_map[reg->index]);
1993 modrm |= ENC_REG(ext);
1997 /** Create a ModR/M8 byte for one register */
1998 static void bemit_modrm8(reg_modifier_t high_part, const arch_register_t *reg)
2000 unsigned char modrm = MOD_REG;
2001 assert(reg_gp_map[reg->index] < 4);
2002 modrm |= ENC_RM(reg_gp_map[reg->index] + (high_part == REG_HIGH ? 4 : 0));
2008 * Calculate the size of an signed immediate in bytes.
2010 * @param offset an offset
2012 static unsigned get_signed_imm_size(int offset)
2014 if (-128 <= offset && offset < 128) {
2016 } else if (-32768 <= offset && offset < 32768) {
2024 * Emit an address mode.
2026 * @param reg content of the reg field: either a register index or an opcode extension
2027 * @param node the node
2029 static void bemit_mod_am(unsigned reg, const ir_node *node)
2031 ir_entity *ent = get_ia32_am_sc(node);
2032 int offs = get_ia32_am_offs_int(node);
2033 ir_node *base = get_irn_n(node, n_ia32_base);
2034 int has_base = !is_ia32_NoReg_GP(base);
2035 ir_node *idx = get_irn_n(node, n_ia32_index);
2036 int has_index = !is_ia32_NoReg_GP(idx);
2039 unsigned emitoffs = 0;
2040 bool emitsib = false;
2043 /* set the mod part depending on displacement */
2045 modrm |= MOD_IND_WORD_OFS;
2047 } else if (offs == 0) {
2050 } else if (-128 <= offs && offs < 128) {
2051 modrm |= MOD_IND_BYTE_OFS;
2054 modrm |= MOD_IND_WORD_OFS;
2059 const arch_register_t *base_reg = arch_get_irn_register(base);
2060 base_enc = reg_gp_map[base_reg->index];
2062 /* Use the EBP encoding + MOD_IND if NO base register. There is
2063 * always a 32bit offset present in this case. */
2069 /* Determine if we need a SIB byte. */
2071 const arch_register_t *reg_index = arch_get_irn_register(idx);
2072 int scale = get_ia32_am_scale(node);
2074 /* R/M set to ESP means SIB in 32bit mode. */
2075 modrm |= ENC_RM(0x04);
2076 sib = ENC_SIB(scale, reg_gp_map[reg_index->index], base_enc);
2078 } else if (base_enc == 0x04) {
2079 /* for the above reason we are forced to emit a SIB when base is ESP.
2080 * Only the base is used, index must be ESP too, which means no index.
2082 modrm |= ENC_RM(0x04);
2083 sib = ENC_SIB(0, 0x04, 0x04);
2086 modrm |= ENC_RM(base_enc);
2089 /* We are forced to emit an 8bit offset as EBP base without offset is a
2090 * special case for SIB without base register. */
2091 if (base_enc == 0x05 && emitoffs == 0) {
2092 modrm |= MOD_IND_BYTE_OFS;
2096 modrm |= ENC_REG(reg);
2102 /* emit displacement */
2103 if (emitoffs == 8) {
2104 bemit8((unsigned) offs);
2105 } else if (emitoffs == 32) {
2106 bemit_entity(ent, is_ia32_am_sc_sign(node), offs, false);
2111 * Emit a binop with a immediate operand.
2113 * @param node the node to emit
2114 * @param opcode_eax the opcode for the op eax, imm variant
2115 * @param opcode the opcode for the reg, imm variant
2116 * @param ruval the opcode extension for opcode
2118 static void bemit_binop_with_imm(
2119 const ir_node *node,
2120 unsigned char opcode_ax,
2121 unsigned char opcode, unsigned char ruval)
2123 /* Use in-reg, because some instructions (cmp, test) have no out-reg. */
2124 const ir_node *op = get_irn_n(node, n_ia32_binary_right);
2125 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(op);
2128 /* Some instructions (test) have no short form with 32bit value + 8bit
2130 if (attr->symconst != NULL || opcode & SIGNEXT_IMM) {
2133 /* check for sign extension */
2134 size = get_signed_imm_size(attr->offset);
2139 bemit8(opcode | SIGNEXT_IMM);
2140 /* cmp has this special mode */
2141 if (get_ia32_op_type(node) == ia32_AddrModeS) {
2142 bemit_mod_am(ruval, node);
2144 const arch_register_t *reg = arch_get_irn_register_in(node, n_ia32_binary_left);
2145 bemit_modru(reg, ruval);
2147 bemit8((unsigned char)attr->offset);
2151 /* check for eax variant: this variant is shorter for 32bit immediates only */
2152 if (get_ia32_op_type(node) == ia32_AddrModeS) {
2154 bemit_mod_am(ruval, node);
2156 const arch_register_t *reg = arch_get_irn_register_in(node, n_ia32_binary_left);
2157 if (reg->index == REG_GP_EAX) {
2161 bemit_modru(reg, ruval);
2164 bemit_entity(attr->symconst, attr->sc_sign, attr->offset, false);
2167 panic("invalid imm size?!?");
2173 static void bemit_binop_2(const ir_node *node, unsigned code)
2175 const arch_register_t *out = arch_get_irn_register_in(node, n_ia32_binary_left);
2177 if (get_ia32_op_type(node) == ia32_Normal) {
2178 const arch_register_t *op2 = arch_get_irn_register_in(node, n_ia32_binary_right);
2179 bemit_modrr(op2, out);
2181 bemit_mod_am(reg_gp_map[out->index], node);
2188 static void bemit_binop(const ir_node *node, const unsigned char opcodes[4])
2190 ir_node *right = get_irn_n(node, n_ia32_binary_right);
2191 if (is_ia32_Immediate(right)) {
2192 bemit_binop_with_imm(node, opcodes[1], opcodes[2], opcodes[3]);
2194 bemit_binop_2(node, opcodes[0]);
2201 static void bemit_unop(const ir_node *node, unsigned char code, unsigned char ext, int input)
2204 if (get_ia32_op_type(node) == ia32_Normal) {
2205 const arch_register_t *in = arch_get_irn_register_in(node, input);
2206 bemit_modru(in, ext);
2208 bemit_mod_am(ext, node);
2212 static void bemit_unop_reg(const ir_node *node, unsigned char code, int input)
2214 const arch_register_t *out = arch_get_irn_register_out(node, 0);
2215 bemit_unop(node, code, reg_gp_map[out->index], input);
2218 static void bemit_unop_mem(const ir_node *node, unsigned char code, unsigned char ext)
2220 unsigned size = get_mode_size_bits(get_ia32_ls_mode(node));
2223 bemit8(size == 8 ? code : code + 1);
2224 bemit_mod_am(ext, node);
2227 static void bemit_0f_unop_reg(ir_node const *const node, unsigned char const code, int const input)
2230 bemit_unop_reg(node, code, input);
2233 static void bemit_immediate(const ir_node *node, bool relative)
2235 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(node);
2236 bemit_entity(attr->symconst, attr->sc_sign, attr->offset, relative);
2239 static void bemit_copy(const ir_node *copy)
2241 const arch_register_t *in = arch_get_irn_register_in(copy, 0);
2242 const arch_register_t *out = arch_get_irn_register_out(copy, 0);
2246 /* copies of vf nodes aren't real... */
2247 if (arch_register_get_class(in) == &ia32_reg_classes[CLASS_ia32_vfp])
2250 assert(arch_register_get_class(in) == &ia32_reg_classes[CLASS_ia32_gp]);
2252 bemit_modrr(in, out);
2255 static void bemit_perm(const ir_node *node)
2257 const arch_register_t *in0 = arch_get_irn_register(get_irn_n(node, 0));
2258 const arch_register_t *in1 = arch_get_irn_register(get_irn_n(node, 1));
2259 const arch_register_class_t *cls0 = arch_register_get_class(in0);
2261 assert(cls0 == arch_register_get_class(in1) && "Register class mismatch at Perm");
2263 if (cls0 == &ia32_reg_classes[CLASS_ia32_gp]) {
2264 if (in0->index == REG_GP_EAX) {
2265 bemit8(0x90 + reg_gp_map[in1->index]);
2266 } else if (in1->index == REG_GP_EAX) {
2267 bemit8(0x90 + reg_gp_map[in0->index]);
2270 bemit_modrr(in0, in1);
2272 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_xmm]) {
2273 panic("unimplemented"); // TODO implement
2274 //ia32_emitf(NULL, "xorpd %R, %R", in1, in0);
2275 //ia32_emitf(NULL, "xorpd %R, %R", in0, in1);
2276 //ia32_emitf(node, "xorpd %R, %R", in1, in0);
2277 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_vfp]) {
2279 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_st]) {
2282 panic("unexpected register class in be_Perm (%+F)", node);
2286 static void bemit_xor0(const ir_node *node)
2288 const arch_register_t *out = arch_get_irn_register_out(node, 0);
2290 bemit_modrr(out, out);
2293 static void bemit_mov_const(const ir_node *node)
2295 const arch_register_t *out = arch_get_irn_register_out(node, 0);
2296 bemit8(0xB8 + reg_gp_map[out->index]);
2297 bemit_immediate(node, false);
2301 * Creates a function for a Binop with 3 possible encodings.
2303 #define BINOP(op, op0, op1, op2, op2_ext) \
2304 static void bemit_ ## op(const ir_node *node) { \
2305 static const unsigned char op ## _codes[] = {op0, op1, op2, op2_ext}; \
2306 bemit_binop(node, op ## _codes); \
2309 /* insn def eax,imm imm */
2310 BINOP(add, 0x03, 0x05, 0x81, 0)
2311 BINOP(or, 0x0B, 0x0D, 0x81, 1)
2312 BINOP(adc, 0x13, 0x15, 0x81, 2)
2313 BINOP(sbb, 0x1B, 0x1D, 0x81, 3)
2314 BINOP(and, 0x23, 0x25, 0x81, 4)
2315 BINOP(sub, 0x2B, 0x2D, 0x81, 5)
2316 BINOP(xor, 0x33, 0x35, 0x81, 6)
2317 BINOP(test, 0x85, 0xA9, 0xF7, 0)
2319 #define BINOPMEM(op, ext) \
2320 static void bemit_##op(const ir_node *node) \
2323 unsigned size = get_mode_size_bits(get_ia32_ls_mode(node)); \
2326 val = get_irn_n(node, n_ia32_unary_op); \
2327 if (is_ia32_Immediate(val)) { \
2328 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(val); \
2329 int offset = attr->offset; \
2330 if (attr->symconst == NULL && get_signed_imm_size(offset) == 1) { \
2332 bemit_mod_am(ext, node); \
2336 bemit_mod_am(ext, node); \
2340 bemit_entity(attr->symconst, attr->sc_sign, offset, false); \
2344 bemit8(ext << 3 | 1); \
2345 bemit_mod_am(reg_gp_map[arch_get_irn_register(val)->index], node); \
2349 static void bemit_##op##8bit(const ir_node *node) \
2351 ir_node *val = get_irn_n(node, n_ia32_unary_op); \
2352 if (is_ia32_Immediate(val)) { \
2354 bemit_mod_am(ext, node); \
2355 bemit8(get_ia32_immediate_attr_const(val)->offset); \
2358 bemit_mod_am(reg_gp_map[arch_get_irn_register(val)->index], node); \
2370 * Creates a function for an Unop with code /ext encoding.
2372 #define UNOP(op, code, ext, input) \
2373 static void bemit_ ## op(const ir_node *node) { \
2374 bemit_unop(node, code, ext, input); \
2377 UNOP(not, 0xF7, 2, n_ia32_Not_val)
2378 UNOP(neg, 0xF7, 3, n_ia32_Neg_val)
2379 UNOP(mul, 0xF7, 4, n_ia32_Mul_right)
2380 UNOP(imul1op, 0xF7, 5, n_ia32_IMul1OP_right)
2381 UNOP(div, 0xF7, 6, n_ia32_Div_divisor)
2382 UNOP(idiv, 0xF7, 7, n_ia32_IDiv_divisor)
2384 /* TODO: am support for IJmp */
2385 UNOP(ijmp, 0xFF, 4, n_ia32_IJmp_target)
2387 #define SHIFT(op, ext) \
2388 static void bemit_##op(const ir_node *node) \
2390 const arch_register_t *out = arch_get_irn_register_out(node, 0); \
2391 ir_node *count = get_irn_n(node, 1); \
2392 if (is_ia32_Immediate(count)) { \
2393 int offset = get_ia32_immediate_attr_const(count)->offset; \
2394 if (offset == 1) { \
2396 bemit_modru(out, ext); \
2399 bemit_modru(out, ext); \
2404 bemit_modru(out, ext); \
2408 static void bemit_##op##mem(const ir_node *node) \
2411 unsigned size = get_mode_size_bits(get_ia32_ls_mode(node)); \
2414 count = get_irn_n(node, 1); \
2415 if (is_ia32_Immediate(count)) { \
2416 int offset = get_ia32_immediate_attr_const(count)->offset; \
2417 if (offset == 1) { \
2418 bemit8(size == 8 ? 0xD0 : 0xD1); \
2419 bemit_mod_am(ext, node); \
2421 bemit8(size == 8 ? 0xC0 : 0xC1); \
2422 bemit_mod_am(ext, node); \
2426 bemit8(size == 8 ? 0xD2 : 0xD3); \
2427 bemit_mod_am(ext, node); \
2437 static void bemit_shld(const ir_node *node)
2439 const arch_register_t *in = arch_get_irn_register_in(node, n_ia32_ShlD_val_low);
2440 const arch_register_t *out = arch_get_irn_register_out(node, pn_ia32_ShlD_res);
2441 ir_node *count = get_irn_n(node, n_ia32_ShlD_count);
2443 if (is_ia32_Immediate(count)) {
2445 bemit_modrr(out, in);
2446 bemit8(get_ia32_immediate_attr_const(count)->offset);
2449 bemit_modrr(out, in);
2453 static void bemit_shrd(const ir_node *node)
2455 const arch_register_t *in = arch_get_irn_register_in(node, n_ia32_ShrD_val_low);
2456 const arch_register_t *out = arch_get_irn_register_out(node, pn_ia32_ShrD_res);
2457 ir_node *count = get_irn_n(node, n_ia32_ShrD_count);
2459 if (is_ia32_Immediate(count)) {
2461 bemit_modrr(out, in);
2462 bemit8(get_ia32_immediate_attr_const(count)->offset);
2465 bemit_modrr(out, in);
2469 static void bemit_sbb0(ir_node const *const node)
2471 arch_register_t const *const out = arch_get_irn_register_out(node, pn_ia32_Sbb0_res);
2472 unsigned char const reg = reg_gp_map[out->index];
2474 bemit8(MOD_REG | ENC_REG(reg) | ENC_RM(reg));
2478 * binary emitter for setcc.
2480 static void bemit_setcc(const ir_node *node)
2482 const arch_register_t *dreg = arch_get_irn_register_out(node, pn_ia32_Setcc_res);
2484 ia32_condition_code_t cc = get_ia32_condcode(node);
2485 cc = determine_final_cc(node, n_ia32_Setcc_eflags, cc);
2486 if (cc & ia32_cc_float_parity_cases) {
2487 if (cc & ia32_cc_negated) {
2490 bemit8(0x90 | pnc2cc(cc));
2491 bemit_modrm8(REG_LOW, dreg);
2496 bemit_modrm8(REG_HIGH, dreg);
2498 /* orb %>dreg, %<dreg */
2500 bemit_modrr8(REG_LOW, dreg, REG_HIGH, dreg);
2504 bemit8(0x90 | pnc2cc(cc));
2505 bemit_modrm8(REG_LOW, dreg);
2510 bemit_modrm8(REG_HIGH, dreg);
2512 /* andb %>dreg, %<dreg */
2514 bemit_modrr8(REG_LOW, dreg, REG_HIGH, dreg);
2519 bemit8(0x90 | pnc2cc(cc));
2520 bemit_modrm8(REG_LOW, dreg);
2524 static void bemit_bsf(ir_node const *const node)
2526 bemit_0f_unop_reg(node, 0xBC, n_ia32_Bsf_operand);
2529 static void bemit_bsr(ir_node const *const node)
2531 bemit_0f_unop_reg(node, 0xBD, n_ia32_Bsr_operand);
2534 static void bemit_bswap(ir_node const *const node)
2537 bemit_modru(arch_get_irn_register_out(node, pn_ia32_Bswap_res), 1);
2540 static void bemit_bt(ir_node const *const node)
2543 arch_register_t const *const lreg = arch_get_irn_register_in(node, n_ia32_Bt_left);
2544 ir_node const *const right = get_irn_n(node, n_ia32_Bt_right);
2545 if (is_ia32_Immediate(right)) {
2546 ia32_immediate_attr_t const *const attr = get_ia32_immediate_attr_const(right);
2547 int const offset = attr->offset;
2548 assert(!attr->symconst);
2549 assert(get_signed_imm_size(offset) == 1);
2551 bemit_modru(lreg, 4);
2555 bemit_modrr(lreg, arch_get_irn_register(right));
2559 static void bemit_cmovcc(const ir_node *node)
2561 const ia32_attr_t *attr = get_ia32_attr_const(node);
2562 int ins_permuted = attr->data.ins_permuted;
2563 const arch_register_t *out = arch_get_irn_register_out(node, pn_ia32_res);
2564 ia32_condition_code_t cc = get_ia32_condcode(node);
2565 const arch_register_t *in_true;
2566 const arch_register_t *in_false;
2568 cc = determine_final_cc(node, n_ia32_CMovcc_eflags, cc);
2570 in_true = arch_get_irn_register(get_irn_n(node, n_ia32_CMovcc_val_true));
2571 in_false = arch_get_irn_register(get_irn_n(node, n_ia32_CMovcc_val_false));
2573 /* should be same constraint fullfilled? */
2574 if (out == in_false) {
2575 /* yes -> nothing to do */
2576 } else if (out == in_true) {
2577 assert(get_ia32_op_type(node) == ia32_Normal);
2578 ins_permuted = !ins_permuted;
2582 bemit8(0x8B); // mov %in_false, %out
2583 bemit_modrr(in_false, out);
2587 cc = ia32_negate_condition_code(cc);
2589 if (cc & ia32_cc_float_parity_cases)
2590 panic("cmov can't handle parity float cases");
2593 bemit8(0x40 | pnc2cc(cc));
2594 if (get_ia32_op_type(node) == ia32_Normal) {
2595 bemit_modrr(in_true, out);
2597 bemit_mod_am(reg_gp_map[out->index], node);
2601 static void bemit_cmp(const ir_node *node)
2603 unsigned ls_size = get_mode_size_bits(get_ia32_ls_mode(node));
2609 right = get_irn_n(node, n_ia32_binary_right);
2610 if (is_ia32_Immediate(right)) {
2611 /* Use in-reg, because some instructions (cmp, test) have no out-reg. */
2612 const ir_node *op = get_irn_n(node, n_ia32_binary_right);
2613 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(op);
2616 if (attr->symconst != NULL) {
2619 /* check for sign extension */
2620 size = get_signed_imm_size(attr->offset);
2625 bemit8(0x81 | SIGNEXT_IMM);
2626 /* cmp has this special mode */
2627 if (get_ia32_op_type(node) == ia32_AddrModeS) {
2628 bemit_mod_am(7, node);
2630 const arch_register_t *reg = arch_get_irn_register_in(node, n_ia32_binary_left);
2631 bemit_modru(reg, 7);
2633 bemit8((unsigned char)attr->offset);
2637 /* check for eax variant: this variant is shorter for 32bit immediates only */
2638 if (get_ia32_op_type(node) == ia32_AddrModeS) {
2640 bemit_mod_am(7, node);
2642 const arch_register_t *reg = arch_get_irn_register_in(node, n_ia32_binary_left);
2643 if (reg->index == REG_GP_EAX) {
2647 bemit_modru(reg, 7);
2650 if (ls_size == 16) {
2651 bemit16(attr->offset);
2653 bemit_entity(attr->symconst, attr->sc_sign, attr->offset, false);
2657 panic("invalid imm size?!?");
2659 const arch_register_t *out = arch_get_irn_register_in(node, n_ia32_binary_left);
2661 if (get_ia32_op_type(node) == ia32_Normal) {
2662 const arch_register_t *op2 = arch_get_irn_register_in(node, n_ia32_binary_right);
2663 bemit_modrr(op2, out);
2665 bemit_mod_am(reg_gp_map[out->index], node);
2670 static void bemit_cmp8bit(const ir_node *node)
2672 ir_node *right = get_irn_n(node, n_ia32_binary_right);
2673 if (is_ia32_Immediate(right)) {
2674 if (get_ia32_op_type(node) == ia32_Normal) {
2675 const arch_register_t *out = arch_get_irn_register_in(node, n_ia32_Cmp_left);
2676 if (out->index == REG_GP_EAX) {
2680 bemit_modru(out, 7);
2684 bemit_mod_am(7, node);
2686 bemit8(get_ia32_immediate_attr_const(right)->offset);
2688 const arch_register_t *out = arch_get_irn_register_in(node, n_ia32_Cmp_left);
2690 if (get_ia32_op_type(node) == ia32_Normal) {
2691 const arch_register_t *in = arch_get_irn_register_in(node, n_ia32_Cmp_right);
2692 bemit_modrr(out, in);
2694 bemit_mod_am(reg_gp_map[out->index], node);
2699 static void bemit_test8bit(const ir_node *node)
2701 ir_node *right = get_irn_n(node, n_ia32_Test8Bit_right);
2702 if (is_ia32_Immediate(right)) {
2703 if (get_ia32_op_type(node) == ia32_Normal) {
2704 const arch_register_t *out = arch_get_irn_register_in(node, n_ia32_Test8Bit_left);
2705 if (out->index == REG_GP_EAX) {
2709 bemit_modru(out, 0);
2713 bemit_mod_am(0, node);
2715 bemit8(get_ia32_immediate_attr_const(right)->offset);
2717 const arch_register_t *out = arch_get_irn_register_in(node, n_ia32_Test8Bit_left);
2719 if (get_ia32_op_type(node) == ia32_Normal) {
2720 const arch_register_t *in = arch_get_irn_register_in(node, n_ia32_Test8Bit_right);
2721 bemit_modrr(out, in);
2723 bemit_mod_am(reg_gp_map[out->index], node);
2728 static void bemit_imul(const ir_node *node)
2730 ir_node *right = get_irn_n(node, n_ia32_IMul_right);
2731 /* Do we need the immediate form? */
2732 if (is_ia32_Immediate(right)) {
2733 int imm = get_ia32_immediate_attr_const(right)->offset;
2734 if (get_signed_imm_size(imm) == 1) {
2735 bemit_unop_reg(node, 0x6B, n_ia32_IMul_left);
2738 bemit_unop_reg(node, 0x69, n_ia32_IMul_left);
2742 bemit_0f_unop_reg(node, 0xAF, n_ia32_IMul_right);
2746 static void bemit_dec(const ir_node *node)
2748 const arch_register_t *out = arch_get_irn_register_out(node, pn_ia32_Dec_res);
2749 bemit8(0x48 + reg_gp_map[out->index]);
2752 static void bemit_inc(const ir_node *node)
2754 const arch_register_t *out = arch_get_irn_register_out(node, pn_ia32_Inc_res);
2755 bemit8(0x40 + reg_gp_map[out->index]);
2758 #define UNOPMEM(op, code, ext) \
2759 static void bemit_##op(const ir_node *node) \
2761 bemit_unop_mem(node, code, ext); \
2764 UNOPMEM(notmem, 0xF6, 2)
2765 UNOPMEM(negmem, 0xF6, 3)
2766 UNOPMEM(incmem, 0xFE, 0)
2767 UNOPMEM(decmem, 0xFE, 1)
2769 static void bemit_ldtls(const ir_node *node)
2771 const arch_register_t *out = arch_get_irn_register_out(node, 0);
2773 bemit8(0x65); // gs:
2774 if (out->index == REG_GP_EAX) {
2775 bemit8(0xA1); // movl 0, %eax
2777 bemit8(0x8B); // movl 0, %reg
2778 bemit8(MOD_IND | ENC_REG(reg_gp_map[out->index]) | ENC_RM(0x05));
2786 static void bemit_lea(const ir_node *node)
2788 const arch_register_t *out = arch_get_irn_register_out(node, 0);
2790 bemit_mod_am(reg_gp_map[out->index], node);
2793 /* helper function for bemit_minus64bit */
2794 static void bemit_helper_mov(const arch_register_t *src, const arch_register_t *dst)
2796 bemit8(0x8B); // movl %src, %dst
2797 bemit_modrr(src, dst);
2800 /* helper function for bemit_minus64bit */
2801 static void bemit_helper_neg(const arch_register_t *reg)
2803 bemit8(0xF7); // negl %reg
2804 bemit_modru(reg, 3);
2807 /* helper function for bemit_minus64bit */
2808 static void bemit_helper_sbb0(const arch_register_t *reg)
2810 bemit8(0x83); // sbbl $0, %reg
2811 bemit_modru(reg, 3);
2815 /* helper function for bemit_minus64bit */
2816 static void bemit_helper_sbb(const arch_register_t *src, const arch_register_t *dst)
2818 bemit8(0x1B); // sbbl %src, %dst
2819 bemit_modrr(src, dst);
2822 /* helper function for bemit_minus64bit */
2823 static void bemit_helper_xchg(const arch_register_t *src, const arch_register_t *dst)
2825 if (src->index == REG_GP_EAX) {
2826 bemit8(0x90 + reg_gp_map[dst->index]); // xchgl %eax, %dst
2827 } else if (dst->index == REG_GP_EAX) {
2828 bemit8(0x90 + reg_gp_map[src->index]); // xchgl %src, %eax
2830 bemit8(0x87); // xchgl %src, %dst
2831 bemit_modrr(src, dst);
2835 /* helper function for bemit_minus64bit */
2836 static void bemit_helper_zero(const arch_register_t *reg)
2838 bemit8(0x33); // xorl %reg, %reg
2839 bemit_modrr(reg, reg);
2842 static void bemit_minus64bit(const ir_node *node)
2844 const arch_register_t *in_lo = arch_get_irn_register_in(node, 0);
2845 const arch_register_t *in_hi = arch_get_irn_register_in(node, 1);
2846 const arch_register_t *out_lo = arch_get_irn_register_out(node, 0);
2847 const arch_register_t *out_hi = arch_get_irn_register_out(node, 1);
2849 if (out_lo == in_lo) {
2850 if (out_hi != in_hi) {
2851 /* a -> a, b -> d */
2854 /* a -> a, b -> b */
2857 } else if (out_lo == in_hi) {
2858 if (out_hi == in_lo) {
2859 /* a -> b, b -> a */
2860 bemit_helper_xchg(in_lo, in_hi);
2863 /* a -> b, b -> d */
2864 bemit_helper_mov(in_hi, out_hi);
2865 bemit_helper_mov(in_lo, out_lo);
2869 if (out_hi == in_lo) {
2870 /* a -> c, b -> a */
2871 bemit_helper_mov(in_lo, out_lo);
2873 } else if (out_hi == in_hi) {
2874 /* a -> c, b -> b */
2875 bemit_helper_mov(in_lo, out_lo);
2878 /* a -> c, b -> d */
2879 bemit_helper_mov(in_lo, out_lo);
2885 bemit_helper_neg( out_hi);
2886 bemit_helper_neg( out_lo);
2887 bemit_helper_sbb0(out_hi);
2891 bemit_helper_zero(out_hi);
2892 bemit_helper_neg( out_lo);
2893 bemit_helper_sbb( in_hi, out_hi);
2897 * Emit a single opcode.
2899 #define EMIT_SINGLEOP(op, code) \
2900 static void bemit_ ## op(const ir_node *node) { \
2905 //EMIT_SINGLEOP(daa, 0x27)
2906 //EMIT_SINGLEOP(das, 0x2F)
2907 //EMIT_SINGLEOP(aaa, 0x37)
2908 //EMIT_SINGLEOP(aas, 0x3F)
2909 //EMIT_SINGLEOP(nop, 0x90)
2910 EMIT_SINGLEOP(cwtl, 0x98)
2911 EMIT_SINGLEOP(cltd, 0x99)
2912 //EMIT_SINGLEOP(fwait, 0x9B)
2913 EMIT_SINGLEOP(sahf, 0x9E)
2914 //EMIT_SINGLEOP(popf, 0x9D)
2915 EMIT_SINGLEOP(leave, 0xC9)
2916 EMIT_SINGLEOP(int3, 0xCC)
2917 //EMIT_SINGLEOP(iret, 0xCF)
2918 //EMIT_SINGLEOP(xlat, 0xD7)
2919 //EMIT_SINGLEOP(lock, 0xF0)
2920 EMIT_SINGLEOP(rep, 0xF3)
2921 //EMIT_SINGLEOP(halt, 0xF4)
2922 EMIT_SINGLEOP(cmc, 0xF5)
2923 EMIT_SINGLEOP(stc, 0xF9)
2924 //EMIT_SINGLEOP(cli, 0xFA)
2925 //EMIT_SINGLEOP(sti, 0xFB)
2926 //EMIT_SINGLEOP(std, 0xFD)
2929 * Emits a MOV out, [MEM].
2931 static void bemit_load(const ir_node *node)
2933 const arch_register_t *out = arch_get_irn_register_out(node, 0);
2935 if (out->index == REG_GP_EAX) {
2936 ir_node *base = get_irn_n(node, n_ia32_base);
2937 int has_base = !is_ia32_NoReg_GP(base);
2938 ir_node *idx = get_irn_n(node, n_ia32_index);
2939 int has_index = !is_ia32_NoReg_GP(idx);
2940 if (!has_base && !has_index) {
2941 ir_entity *ent = get_ia32_am_sc(node);
2942 int offs = get_ia32_am_offs_int(node);
2943 /* load from constant address to EAX can be encoded
2946 bemit_entity(ent, 0, offs, false);
2951 bemit_mod_am(reg_gp_map[out->index], node);
2955 * Emits a MOV [mem], in.
2957 static void bemit_store(const ir_node *node)
2959 const ir_node *value = get_irn_n(node, n_ia32_Store_val);
2960 unsigned size = get_mode_size_bits(get_ia32_ls_mode(node));
2962 if (is_ia32_Immediate(value)) {
2965 bemit_mod_am(0, node);
2966 bemit8(get_ia32_immediate_attr_const(value)->offset);
2967 } else if (size == 16) {
2970 bemit_mod_am(0, node);
2971 bemit16(get_ia32_immediate_attr_const(value)->offset);
2974 bemit_mod_am(0, node);
2975 bemit_immediate(value, false);
2978 const arch_register_t *in = arch_get_irn_register_in(node, n_ia32_Store_val);
2980 if (in->index == REG_GP_EAX) {
2981 ir_node *base = get_irn_n(node, n_ia32_base);
2982 int has_base = !is_ia32_NoReg_GP(base);
2983 ir_node *idx = get_irn_n(node, n_ia32_index);
2984 int has_index = !is_ia32_NoReg_GP(idx);
2985 if (!has_base && !has_index) {
2986 ir_entity *ent = get_ia32_am_sc(node);
2987 int offs = get_ia32_am_offs_int(node);
2988 /* store to constant address from EAX can be encoded as
2989 * 0xA2/0xA3 [offset]*/
2997 bemit_entity(ent, 0, offs, false);
3009 bemit_mod_am(reg_gp_map[in->index], node);
3013 static void bemit_conv_i2i(const ir_node *node)
3018 ir_mode *const smaller_mode = get_ia32_ls_mode(node);
3019 unsigned opcode = 0xB6;
3020 if (mode_is_signed(smaller_mode)) opcode |= 0x08;
3021 if (get_mode_size_bits(smaller_mode) == 16) opcode |= 0x01;
3022 bemit_0f_unop_reg(node, opcode, n_ia32_Conv_I2I_val);
3025 static void bemit_popcnt(ir_node const *const node)
3028 bemit_0f_unop_reg(node, 0xB8, n_ia32_Popcnt_operand);
3034 static void bemit_push(const ir_node *node)
3036 const ir_node *value = get_irn_n(node, n_ia32_Push_val);
3038 if (is_ia32_Immediate(value)) {
3039 const ia32_immediate_attr_t *attr
3040 = get_ia32_immediate_attr_const(value);
3041 unsigned size = get_signed_imm_size(attr->offset);
3047 bemit8((unsigned char)attr->offset);
3052 bemit_immediate(value, false);
3055 } else if (is_ia32_NoReg_GP(value)) {
3057 bemit_mod_am(6, node);
3059 const arch_register_t *reg = arch_get_irn_register_in(node, n_ia32_Push_val);
3060 bemit8(0x50 + reg_gp_map[reg->index]);
3067 static void bemit_pop(const ir_node *node)
3069 const arch_register_t *reg = arch_get_irn_register_out(node, pn_ia32_Pop_res);
3070 bemit8(0x58 + reg_gp_map[reg->index]);
3073 static void bemit_popmem(const ir_node *node)
3076 bemit_mod_am(0, node);
3079 static void bemit_call(const ir_node *node)
3081 ir_node *proc = get_irn_n(node, n_ia32_Call_addr);
3083 if (is_ia32_Immediate(proc)) {
3085 bemit_immediate(proc, true);
3087 bemit_unop(node, 0xFF, 2, n_ia32_Call_addr);
3091 static void bemit_jmp(const ir_node *dest_block)
3094 bemit_jmp_destination(dest_block);
3097 static void bemit_jump(const ir_node *node)
3099 if (can_be_fallthrough(node))
3102 bemit_jmp(get_cfop_target_block(node));
3105 static void bemit_jcc(ia32_condition_code_t pnc, const ir_node *dest_block)
3107 unsigned char cc = pnc2cc(pnc);
3110 bemit_jmp_destination(dest_block);
3113 static void bemit_jp(bool odd, const ir_node *dest_block)
3117 bemit_jmp_destination(dest_block);
3120 static void bemit_ia32_jcc(const ir_node *node)
3122 ia32_condition_code_t cc = get_ia32_condcode(node);
3123 const ir_node *proj_true;
3124 const ir_node *proj_false;
3125 const ir_node *dest_true;
3126 const ir_node *dest_false;
3128 cc = determine_final_cc(node, 0, cc);
3130 /* get both Projs */
3131 proj_true = get_proj(node, pn_ia32_Jcc_true);
3132 assert(proj_true && "Jcc without true Proj");
3134 proj_false = get_proj(node, pn_ia32_Jcc_false);
3135 assert(proj_false && "Jcc without false Proj");
3137 if (can_be_fallthrough(proj_true)) {
3138 /* exchange both proj's so the second one can be omitted */
3139 const ir_node *t = proj_true;
3141 proj_true = proj_false;
3143 cc = ia32_negate_condition_code(cc);
3146 dest_true = get_cfop_target_block(proj_true);
3147 dest_false = get_cfop_target_block(proj_false);
3149 if (cc & ia32_cc_float_parity_cases) {
3150 /* Some floating point comparisons require a test of the parity flag,
3151 * which indicates that the result is unordered */
3152 if (cc & ia32_cc_negated) {
3153 bemit_jp(false, dest_true);
3155 /* we need a local label if the false proj is a fallthrough
3156 * as the falseblock might have no label emitted then */
3157 if (can_be_fallthrough(proj_false)) {
3159 bemit8(0x06); // jp + 6
3161 bemit_jp(false, dest_false);
3165 bemit_jcc(cc, dest_true);
3167 /* the second Proj might be a fallthrough */
3168 if (can_be_fallthrough(proj_false)) {
3169 /* it's a fallthrough */
3171 bemit_jmp(dest_false);
3175 static void bemit_switchjmp(const ir_node *node)
3177 ir_entity *jump_table = get_ia32_am_sc(node);
3178 const ir_switch_table *table = get_ia32_switch_table(node);
3180 bemit8(0xFF); // jmp *tbl.label(,%in,4)
3181 bemit_mod_am(0x05, node);
3183 be_emit_jump_table(node, table, jump_table, get_cfop_target_block);
3189 static void bemit_return(const ir_node *node)
3191 unsigned pop = be_Return_get_pop(node);
3192 if (pop > 0 || be_Return_get_emit_pop(node)) {
3194 assert(pop <= 0xffff);
3201 static void bemit_subsp(const ir_node *node)
3203 const arch_register_t *out;
3206 /* mov %esp, %out */
3208 out = arch_get_irn_register_out(node, 1);
3209 bemit8(MOD_REG | ENC_REG(reg_gp_map[out->index]) | ENC_RM(0x04));
3212 static void bemit_incsp(const ir_node *node)
3215 const arch_register_t *reg;
3219 offs = be_get_IncSP_offset(node);
3230 size = get_signed_imm_size(offs);
3231 bemit8(size == 1 ? 0x83 : 0x81);
3233 reg = arch_get_irn_register_out(node, 0);
3234 bemit_modru(reg, ext);
3243 static void bemit_copybi(const ir_node *node)
3245 unsigned size = get_ia32_copyb_size(node);
3247 bemit8(0xA4); // movsb
3250 bemit8(0xA5); // movsw
3254 bemit8(0xA5); // movsl
3258 static void bemit_fbinop(ir_node const *const node, unsigned const op_fwd, unsigned const op_rev)
3260 ia32_x87_attr_t const *const attr = get_ia32_x87_attr_const(node);
3261 arch_register_t const *const st0 = &ia32_registers[REG_ST0];
3262 if (get_ia32_op_type(node) == ia32_Normal) {
3263 arch_register_t const *const out = attr->x87[2];
3264 assert(out == attr->x87[0] || out == attr->x87[1]);
3265 assert(!attr->attr.data.ins_permuted);
3267 unsigned char op0 = 0xD8;
3268 if (out != st0) op0 |= 0x04;
3271 unsigned op = op_rev;
3272 arch_register_t const *reg = attr->x87[0];
3277 bemit8(MOD_REG | ENC_REG(op) | ENC_RM(reg->index));
3279 assert(attr->x87[2] == st0);
3281 unsigned const size = get_mode_size_bits(get_ia32_ls_mode(node));
3282 bemit8(size == 32 ? 0xD8 : 0xDC);
3283 bemit_mod_am(attr->attr.data.ins_permuted ? op_rev : op_fwd, node);
3287 static void bemit_fbinopp(const ir_node *node, unsigned const op_fwd, unsigned const op_rev)
3289 ia32_x87_attr_t const *const attr = get_ia32_x87_attr_const(node);
3291 bemit8((attr->x87[0] == &ia32_registers[REG_ST0] ? op_fwd : op_rev) + attr->x87[2]->index);
3294 static void bemit_fop_reg(ir_node const *const node, unsigned char const op0, unsigned char const op1)
3297 bemit8(op1 + get_ia32_x87_attr_const(node)->x87[0]->index);
3300 static void bemit_fabs(const ir_node *node)
3308 static void bemit_fadd(const ir_node *node)
3310 bemit_fbinop(node, 0, 0);
3313 static void bemit_faddp(const ir_node *node)
3315 bemit_fbinopp(node, 0xC0, 0xC0);
3318 static void bemit_fchs(const ir_node *node)
3326 static void bemit_fdiv(const ir_node *node)
3328 bemit_fbinop(node, 6, 7);
3331 static void bemit_fdivp(const ir_node *node)
3333 bemit_fbinopp(node, 0xF0, 0xF8);
3336 static void bemit_ffreep(ir_node const *const node)
3338 bemit_fop_reg(node, 0xDF, 0xC0);
3341 static void bemit_fild(const ir_node *node)
3343 switch (get_mode_size_bits(get_ia32_ls_mode(node))) {
3345 bemit8(0xDF); // filds
3346 bemit_mod_am(0, node);
3350 bemit8(0xDB); // fildl
3351 bemit_mod_am(0, node);
3355 bemit8(0xDF); // fildll
3356 bemit_mod_am(5, node);
3360 panic("invalid mode size");
3364 static void bemit_fist(const ir_node *node)
3366 switch (get_mode_size_bits(get_ia32_ls_mode(node))) {
3368 bemit8(0xDF); // fists
3372 bemit8(0xDB); // fistl
3376 panic("invalid mode size");
3378 bemit_mod_am(2, node);
3381 static void bemit_fistp(const ir_node *node)
3383 switch (get_mode_size_bits(get_ia32_ls_mode(node))) {
3385 bemit8(0xDF); // fistps
3386 bemit_mod_am(3, node);
3390 bemit8(0xDB); // fistpl
3391 bemit_mod_am(3, node);
3395 bemit8(0xDF); // fistpll
3396 bemit_mod_am(7, node);
3400 panic("invalid mode size");
3404 static void bemit_fisttp(ir_node const *const node)
3406 switch (get_mode_size_bits(get_ia32_ls_mode(node))) {
3407 case 16: bemit8(0xDF); break; // fisttps
3408 case 32: bemit8(0xDB); break; // fisttpl
3409 case 64: bemit8(0xDD); break; // fisttpll
3410 default: panic("Invalid mode size");
3412 bemit_mod_am(1, node);
3415 static void bemit_fld(const ir_node *node)
3417 switch (get_mode_size_bits(get_ia32_ls_mode(node))) {
3419 bemit8(0xD9); // flds
3420 bemit_mod_am(0, node);
3424 bemit8(0xDD); // fldl
3425 bemit_mod_am(0, node);
3430 bemit8(0xDB); // fldt
3431 bemit_mod_am(5, node);
3435 panic("invalid mode size");
3439 static void bemit_fld1(const ir_node *node)
3443 bemit8(0xE8); // fld1
3446 static void bemit_fldcw(const ir_node *node)
3448 bemit8(0xD9); // fldcw
3449 bemit_mod_am(5, node);
3452 static void bemit_fldz(const ir_node *node)
3456 bemit8(0xEE); // fldz
3459 static void bemit_fmul(const ir_node *node)
3461 bemit_fbinop(node, 1, 1);
3464 static void bemit_fmulp(const ir_node *node)
3466 bemit_fbinopp(node, 0xC8, 0xC8);
3469 static void bemit_fpop(const ir_node *node)
3471 bemit_fop_reg(node, 0xDD, 0xD8);
3474 static void bemit_fpush(const ir_node *node)
3476 bemit_fop_reg(node, 0xD9, 0xC0);
3479 static void bemit_fpushcopy(const ir_node *node)
3481 bemit_fop_reg(node, 0xD9, 0xC0);
3484 static void bemit_fst(const ir_node *node)
3486 switch (get_mode_size_bits(get_ia32_ls_mode(node))) {
3488 bemit8(0xD9); // fsts
3492 bemit8(0xDD); // fstl
3496 panic("invalid mode size");
3498 bemit_mod_am(2, node);
3501 static void bemit_fstp(const ir_node *node)
3503 switch (get_mode_size_bits(get_ia32_ls_mode(node))) {
3505 bemit8(0xD9); // fstps
3506 bemit_mod_am(3, node);
3510 bemit8(0xDD); // fstpl
3511 bemit_mod_am(3, node);
3516 bemit8(0xDB); // fstpt
3517 bemit_mod_am(7, node);
3521 panic("invalid mode size");
3525 static void bemit_fsub(const ir_node *node)
3527 bemit_fbinop(node, 4, 5);
3530 static void bemit_fsubp(const ir_node *node)
3532 bemit_fbinopp(node, 0xE0, 0xE8);
3535 static void bemit_fnstcw(const ir_node *node)
3537 bemit8(0xD9); // fnstcw
3538 bemit_mod_am(7, node);
3541 static void bemit_fnstsw(void)
3543 bemit8(0xDF); // fnstsw %ax
3547 static void bemit_ftstfnstsw(const ir_node *node)
3551 bemit8(0xD9); // ftst
3556 static void bemit_fucomi(const ir_node *node)
3558 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
3559 bemit8(0xDB); // fucomi
3560 bemit8(0xE8 + attr->x87[1]->index);
3563 static void bemit_fucomip(const ir_node *node)
3565 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
3566 bemit8(0xDF); // fucomip
3567 bemit8(0xE8 + attr->x87[1]->index);
3570 static void bemit_fucomfnstsw(const ir_node *node)
3572 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
3573 bemit8(0xDD); // fucom
3574 bemit8(0xE0 + attr->x87[1]->index);
3578 static void bemit_fucompfnstsw(const ir_node *node)
3580 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
3581 bemit8(0xDD); // fucomp
3582 bemit8(0xE8 + attr->x87[1]->index);
3586 static void bemit_fucomppfnstsw(const ir_node *node)
3590 bemit8(0xDA); // fucompp
3595 static void bemit_fxch(const ir_node *node)
3597 bemit_fop_reg(node, 0xD9, 0xC8);
3601 * The type of a emitter function.
3603 typedef void (*emit_func) (const ir_node *);
3606 * Set a node emitter. Make it a bit more type safe.
3608 static void register_emitter(ir_op *op, emit_func func)
3610 op->ops.generic = (op_func) func;
3613 static void ia32_register_binary_emitters(void)
3615 /* first clear the generic function pointer for all ops */
3616 ir_clear_opcodes_generic_func();
3618 /* benode emitter */
3619 register_emitter(op_be_Copy, bemit_copy);
3620 register_emitter(op_be_CopyKeep, bemit_copy);
3621 register_emitter(op_be_IncSP, bemit_incsp);
3622 register_emitter(op_be_Perm, bemit_perm);
3623 register_emitter(op_be_Return, bemit_return);
3624 register_emitter(op_ia32_Adc, bemit_adc);
3625 register_emitter(op_ia32_Add, bemit_add);
3626 register_emitter(op_ia32_AddMem, bemit_addmem);
3627 register_emitter(op_ia32_AddMem8Bit, bemit_addmem8bit);
3628 register_emitter(op_ia32_And, bemit_and);
3629 register_emitter(op_ia32_AndMem, bemit_andmem);
3630 register_emitter(op_ia32_AndMem8Bit, bemit_andmem8bit);
3631 register_emitter(op_ia32_Asm, emit_ia32_Asm); // TODO implement binary emitter
3632 register_emitter(op_ia32_Breakpoint, bemit_int3);
3633 register_emitter(op_ia32_Bsf, bemit_bsf);
3634 register_emitter(op_ia32_Bsr, bemit_bsr);
3635 register_emitter(op_ia32_Bswap, bemit_bswap);
3636 register_emitter(op_ia32_Bt, bemit_bt);
3637 register_emitter(op_ia32_CMovcc, bemit_cmovcc);
3638 register_emitter(op_ia32_Call, bemit_call);
3639 register_emitter(op_ia32_Cltd, bemit_cltd);
3640 register_emitter(op_ia32_Cmc, bemit_cmc);
3641 register_emitter(op_ia32_Cmp, bemit_cmp);
3642 register_emitter(op_ia32_Cmp8Bit, bemit_cmp8bit);
3643 register_emitter(op_ia32_Const, bemit_mov_const);
3644 register_emitter(op_ia32_Conv_I2I, bemit_conv_i2i);
3645 register_emitter(op_ia32_Conv_I2I8Bit, bemit_conv_i2i);
3646 register_emitter(op_ia32_CopyB_i, bemit_copybi);
3647 register_emitter(op_ia32_Cwtl, bemit_cwtl);
3648 register_emitter(op_ia32_Dec, bemit_dec);
3649 register_emitter(op_ia32_DecMem, bemit_decmem);
3650 register_emitter(op_ia32_Div, bemit_div);
3651 register_emitter(op_ia32_FldCW, bemit_fldcw);
3652 register_emitter(op_ia32_FnstCW, bemit_fnstcw);
3653 register_emitter(op_ia32_FtstFnstsw, bemit_ftstfnstsw);
3654 register_emitter(op_ia32_FucomFnstsw, bemit_fucomfnstsw);
3655 register_emitter(op_ia32_Fucomi, bemit_fucomi);
3656 register_emitter(op_ia32_FucompFnstsw, bemit_fucompfnstsw);
3657 register_emitter(op_ia32_Fucompi, bemit_fucomip);
3658 register_emitter(op_ia32_FucomppFnstsw, bemit_fucomppfnstsw);
3659 register_emitter(op_ia32_IDiv, bemit_idiv);
3660 register_emitter(op_ia32_IJmp, bemit_ijmp);
3661 register_emitter(op_ia32_IMul, bemit_imul);
3662 register_emitter(op_ia32_IMul1OP, bemit_imul1op);
3663 register_emitter(op_ia32_Inc, bemit_inc);
3664 register_emitter(op_ia32_IncMem, bemit_incmem);
3665 register_emitter(op_ia32_Jcc, bemit_ia32_jcc);
3666 register_emitter(op_ia32_Jmp, bemit_jump);
3667 register_emitter(op_ia32_LdTls, bemit_ldtls);
3668 register_emitter(op_ia32_Lea, bemit_lea);
3669 register_emitter(op_ia32_Leave, bemit_leave);
3670 register_emitter(op_ia32_Load, bemit_load);
3671 register_emitter(op_ia32_Minus64Bit, bemit_minus64bit);
3672 register_emitter(op_ia32_Mul, bemit_mul);
3673 register_emitter(op_ia32_Neg, bemit_neg);
3674 register_emitter(op_ia32_NegMem, bemit_negmem);
3675 register_emitter(op_ia32_Not, bemit_not);
3676 register_emitter(op_ia32_NotMem, bemit_notmem);
3677 register_emitter(op_ia32_Or, bemit_or);
3678 register_emitter(op_ia32_OrMem, bemit_ormem);
3679 register_emitter(op_ia32_OrMem8Bit, bemit_ormem8bit);
3680 register_emitter(op_ia32_Pop, bemit_pop);
3681 register_emitter(op_ia32_PopEbp, bemit_pop);
3682 register_emitter(op_ia32_PopMem, bemit_popmem);
3683 register_emitter(op_ia32_Popcnt, bemit_popcnt);
3684 register_emitter(op_ia32_Push, bemit_push);
3685 register_emitter(op_ia32_RepPrefix, bemit_rep);
3686 register_emitter(op_ia32_Rol, bemit_rol);
3687 register_emitter(op_ia32_RolMem, bemit_rolmem);
3688 register_emitter(op_ia32_Ror, bemit_ror);
3689 register_emitter(op_ia32_RorMem, bemit_rormem);
3690 register_emitter(op_ia32_Sahf, bemit_sahf);
3691 register_emitter(op_ia32_Sar, bemit_sar);
3692 register_emitter(op_ia32_SarMem, bemit_sarmem);
3693 register_emitter(op_ia32_Sbb, bemit_sbb);
3694 register_emitter(op_ia32_Sbb0, bemit_sbb0);
3695 register_emitter(op_ia32_Setcc, bemit_setcc);
3696 register_emitter(op_ia32_Shl, bemit_shl);
3697 register_emitter(op_ia32_ShlD, bemit_shld);
3698 register_emitter(op_ia32_ShlMem, bemit_shlmem);
3699 register_emitter(op_ia32_Shr, bemit_shr);
3700 register_emitter(op_ia32_ShrD, bemit_shrd);
3701 register_emitter(op_ia32_ShrMem, bemit_shrmem);
3702 register_emitter(op_ia32_Stc, bemit_stc);
3703 register_emitter(op_ia32_Store, bemit_store);
3704 register_emitter(op_ia32_Store8Bit, bemit_store);
3705 register_emitter(op_ia32_Sub, bemit_sub);
3706 register_emitter(op_ia32_SubMem, bemit_submem);
3707 register_emitter(op_ia32_SubMem8Bit, bemit_submem8bit);
3708 register_emitter(op_ia32_SubSP, bemit_subsp);
3709 register_emitter(op_ia32_SwitchJmp, bemit_switchjmp);
3710 register_emitter(op_ia32_Test, bemit_test);
3711 register_emitter(op_ia32_Test8Bit, bemit_test8bit);
3712 register_emitter(op_ia32_Xor, bemit_xor);
3713 register_emitter(op_ia32_Xor0, bemit_xor0);
3714 register_emitter(op_ia32_XorMem, bemit_xormem);
3715 register_emitter(op_ia32_XorMem8Bit, bemit_xormem8bit);
3716 register_emitter(op_ia32_fabs, bemit_fabs);
3717 register_emitter(op_ia32_fadd, bemit_fadd);
3718 register_emitter(op_ia32_faddp, bemit_faddp);
3719 register_emitter(op_ia32_fchs, bemit_fchs);
3720 register_emitter(op_ia32_fdiv, bemit_fdiv);
3721 register_emitter(op_ia32_fdivp, bemit_fdivp);
3722 register_emitter(op_ia32_ffreep, bemit_ffreep);
3723 register_emitter(op_ia32_fild, bemit_fild);
3724 register_emitter(op_ia32_fist, bemit_fist);
3725 register_emitter(op_ia32_fistp, bemit_fistp);
3726 register_emitter(op_ia32_fisttp, bemit_fisttp);
3727 register_emitter(op_ia32_fld, bemit_fld);
3728 register_emitter(op_ia32_fld1, bemit_fld1);
3729 register_emitter(op_ia32_fldz, bemit_fldz);
3730 register_emitter(op_ia32_fmul, bemit_fmul);
3731 register_emitter(op_ia32_fmulp, bemit_fmulp);
3732 register_emitter(op_ia32_fpop, bemit_fpop);
3733 register_emitter(op_ia32_fpush, bemit_fpush);
3734 register_emitter(op_ia32_fpushCopy, bemit_fpushcopy);
3735 register_emitter(op_ia32_fst, bemit_fst);
3736 register_emitter(op_ia32_fstp, bemit_fstp);
3737 register_emitter(op_ia32_fsub, bemit_fsub);
3738 register_emitter(op_ia32_fsubp, bemit_fsubp);
3739 register_emitter(op_ia32_fxch, bemit_fxch);
3741 /* ignore the following nodes */
3742 register_emitter(op_ia32_ProduceVal, emit_Nothing);
3743 register_emitter(op_ia32_Unknown, emit_Nothing);
3744 register_emitter(op_be_Keep, emit_Nothing);
3745 register_emitter(op_be_Start, emit_Nothing);
3746 register_emitter(op_Phi, emit_Nothing);
3747 register_emitter(op_Start, emit_Nothing);
3750 static void gen_binary_block(ir_node *block)
3752 ia32_emit_block_header(block);
3754 /* emit the contents of the block */
3755 sched_foreach(block, node) {
3756 ia32_emit_node(node);
3760 void ia32_gen_binary_routine(ir_graph *irg)
3762 ir_entity *entity = get_irg_entity(irg);
3763 const arch_env_t *arch_env = be_get_irg_arch_env(irg);
3764 ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
3765 ir_node **blk_sched = irg_data->blk_sched;
3767 parameter_dbg_info_t *infos;
3769 isa = (ia32_isa_t*) arch_env;
3771 ia32_register_binary_emitters();
3773 infos = construct_parameter_infos(irg);
3774 be_gas_emit_function_prolog(entity, ia32_cg_config.function_alignment,
3778 /* we use links to point to target blocks */
3779 ir_reserve_resources(irg, IR_RESOURCE_IRN_LINK);
3780 irg_block_walk_graph(irg, ia32_gen_labels, NULL, NULL);
3782 /* initialize next block links */
3783 n = ARR_LEN(blk_sched);
3784 for (i = 0; i < n; ++i) {
3785 ir_node *block = blk_sched[i];
3786 ir_node *prev = i > 0 ? blk_sched[i-1] : NULL;
3788 set_irn_link(block, prev);
3791 for (i = 0; i < n; ++i) {
3792 ir_node *block = blk_sched[i];
3793 gen_binary_block(block);
3796 be_gas_emit_function_epilog(entity);
3798 ir_free_resources(irg, IR_RESOURCE_IRN_LINK);
3802 void ia32_init_emitter(void)
3804 lc_opt_entry_t *be_grp;
3805 lc_opt_entry_t *ia32_grp;
3807 be_grp = lc_opt_get_grp(firm_opt_get_root(), "be");
3808 ia32_grp = lc_opt_get_grp(be_grp, "ia32");
3810 lc_opt_add_table(ia32_grp, ia32_emitter_options);
3814 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.emitter");