2 * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This file implements the ia32 node emitter.
23 * @author Christian Wuerdig, Matthias Braun
41 #include "iredges_t.h"
44 #include "raw_bitset.h"
47 #include "../besched_t.h"
48 #include "../benode_t.h"
50 #include "../be_dbgout.h"
51 #include "../beemitter.h"
52 #include "../begnuas.h"
53 #include "../beirg_t.h"
54 #include "../be_dbgout.h"
56 #include "ia32_emitter.h"
57 #include "gen_ia32_emitter.h"
58 #include "gen_ia32_regalloc_if.h"
59 #include "ia32_nodes_attr.h"
60 #include "ia32_new_nodes.h"
61 #include "ia32_map_regs.h"
62 #include "ia32_architecture.h"
63 #include "bearch_ia32_t.h"
65 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
67 #define BLOCK_PREFIX ".L"
69 #define SNPRINTF_BUF_LEN 128
71 static const arch_env_t *arch_env;
72 static const ia32_isa_t *isa;
73 static ia32_code_gen_t *cg;
75 static char pic_base_label[128];
76 static ir_label_t exc_label_id;
77 static int mark_spill_reload = 0;
79 /** Return the next block in Block schedule */
80 static ir_node *get_prev_block_sched(const ir_node *block)
82 return get_irn_link(block);
85 static int is_fallthrough(const ir_node *cfgpred)
89 if (!is_Proj(cfgpred))
91 pred = get_Proj_pred(cfgpred);
92 if (is_ia32_SwitchJmp(pred))
98 static int block_needs_label(const ir_node *block)
101 int n_cfgpreds = get_Block_n_cfgpreds(block);
103 if (n_cfgpreds == 0) {
105 } else if (n_cfgpreds == 1) {
106 ir_node *cfgpred = get_Block_cfgpred(block, 0);
107 ir_node *cfgpred_block = get_nodes_block(cfgpred);
109 if (get_prev_block_sched(block) == cfgpred_block
110 && is_fallthrough(cfgpred)) {
119 * Returns the register at in position pos.
121 static const arch_register_t *get_in_reg(const ir_node *irn, int pos)
124 const arch_register_t *reg = NULL;
126 assert(get_irn_arity(irn) > pos && "Invalid IN position");
128 /* The out register of the operator at position pos is the
129 in register we need. */
130 op = get_irn_n(irn, pos);
132 reg = arch_get_irn_register(arch_env, op);
134 assert(reg && "no in register found");
136 if (reg == &ia32_gp_regs[REG_GP_NOREG])
137 panic("trying to emit noreg for %+F input %d", irn, pos);
139 /* in case of unknown register: just return a valid register */
140 if (reg == &ia32_gp_regs[REG_GP_UKNWN]) {
141 const arch_register_req_t *req;
143 /* ask for the requirements */
144 req = arch_get_register_req(arch_env, irn, pos);
146 if (arch_register_req_is(req, limited)) {
147 /* in case of limited requirements: get the first allowed register */
148 unsigned idx = rbitset_next(req->limited, 0, 1);
149 reg = arch_register_for_index(req->cls, idx);
151 /* otherwise get first register in class */
152 reg = arch_register_for_index(req->cls, 0);
160 * Returns the register at out position pos.
162 static const arch_register_t *get_out_reg(const ir_node *irn, int pos)
165 const arch_register_t *reg = NULL;
167 /* 1st case: irn is not of mode_T, so it has only */
168 /* one OUT register -> good */
169 /* 2nd case: irn is of mode_T -> collect all Projs and ask the */
170 /* Proj with the corresponding projnum for the register */
172 if (get_irn_mode(irn) != mode_T) {
174 reg = arch_get_irn_register(arch_env, irn);
175 } else if (is_ia32_irn(irn)) {
176 reg = get_ia32_out_reg(irn, pos);
178 const ir_edge_t *edge;
180 foreach_out_edge(irn, edge) {
181 proj = get_edge_src_irn(edge);
182 assert(is_Proj(proj) && "non-Proj from mode_T node");
183 if (get_Proj_proj(proj) == pos) {
184 reg = arch_get_irn_register(arch_env, proj);
190 assert(reg && "no out register found");
195 * Add a number to a prefix. This number will not be used a second time.
197 static char *get_unique_label(char *buf, size_t buflen, const char *prefix)
199 static unsigned long id = 0;
200 snprintf(buf, buflen, "%s%lu", prefix, ++id);
204 /*************************************************************
206 * (_) | | / _| | | | |
207 * _ __ _ __ _ _ __ | |_| |_ | |__ ___| |_ __ ___ _ __
208 * | '_ \| '__| | '_ \| __| _| | '_ \ / _ \ | '_ \ / _ \ '__|
209 * | |_) | | | | | | | |_| | | | | | __/ | |_) | __/ |
210 * | .__/|_| |_|_| |_|\__|_| |_| |_|\___|_| .__/ \___|_|
213 *************************************************************/
215 static void emit_8bit_register(const arch_register_t *reg)
217 const char *reg_name = arch_register_get_name(reg);
220 be_emit_char(reg_name[1]);
224 static void emit_16bit_register(const arch_register_t *reg)
226 const char *reg_name = ia32_get_mapped_reg_name(isa->regs_16bit, reg);
229 be_emit_string(reg_name);
232 static void emit_register(const arch_register_t *reg, const ir_mode *mode)
234 const char *reg_name;
237 int size = get_mode_size_bits(mode);
239 case 8: emit_8bit_register(reg); return;
240 case 16: emit_16bit_register(reg); return;
242 assert(mode_is_float(mode) || size == 32);
245 reg_name = arch_register_get_name(reg);
248 be_emit_string(reg_name);
251 void ia32_emit_source_register(const ir_node *node, int pos)
253 const arch_register_t *reg = get_in_reg(node, pos);
255 emit_register(reg, NULL);
258 static void emit_ia32_Immediate(const ir_node *node);
260 void ia32_emit_8bit_source_register_or_immediate(const ir_node *node, int pos)
262 const arch_register_t *reg;
263 ir_node *in = get_irn_n(node, pos);
264 if (is_ia32_Immediate(in)) {
265 emit_ia32_Immediate(in);
269 reg = get_in_reg(node, pos);
270 emit_8bit_register(reg);
273 void ia32_emit_dest_register(const ir_node *node, int pos)
275 const arch_register_t *reg = get_out_reg(node, pos);
277 emit_register(reg, NULL);
280 void ia32_emit_8bit_dest_register(const ir_node *node, int pos)
282 const arch_register_t *reg = get_out_reg(node, pos);
284 emit_register(reg, mode_Bu);
287 void ia32_emit_x87_register(const ir_node *node, int pos)
289 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
293 be_emit_string(attr->x87[pos]->name);
296 static void ia32_emit_mode_suffix_mode(const ir_mode *mode)
298 if (mode_is_float(mode)) {
299 switch(get_mode_size_bits(mode)) {
300 case 32: be_emit_char('s'); return;
301 case 64: be_emit_char('l'); return;
303 case 96: be_emit_char('t'); return;
306 assert(mode_is_int(mode) || mode_is_reference(mode));
307 switch(get_mode_size_bits(mode)) {
308 /* gas docu says q is the suffix but gcc, objdump and icc use ll
310 case 64: be_emit_cstring("ll"); return;
311 case 32: be_emit_char('l'); return;
312 case 16: be_emit_char('w'); return;
313 case 8: be_emit_char('b'); return;
316 panic("Can't output mode_suffix for %+F", mode);
319 void ia32_emit_mode_suffix(const ir_node *node)
321 ir_mode *mode = get_ia32_ls_mode(node);
325 ia32_emit_mode_suffix_mode(mode);
328 void ia32_emit_x87_mode_suffix(const ir_node *node)
330 /* we only need to emit the mode on address mode */
331 if (get_ia32_op_type(node) != ia32_Normal) {
332 ir_mode *mode = get_ia32_ls_mode(node);
333 assert(mode != NULL);
334 ia32_emit_mode_suffix_mode(mode);
338 static char get_xmm_mode_suffix(ir_mode *mode)
340 assert(mode_is_float(mode));
341 switch(get_mode_size_bits(mode)) {
344 default: panic("Invalid XMM mode");
348 void ia32_emit_xmm_mode_suffix(const ir_node *node)
350 ir_mode *mode = get_ia32_ls_mode(node);
351 assert(mode != NULL);
353 be_emit_char(get_xmm_mode_suffix(mode));
356 void ia32_emit_xmm_mode_suffix_s(const ir_node *node)
358 ir_mode *mode = get_ia32_ls_mode(node);
359 assert(mode != NULL);
360 be_emit_char(get_xmm_mode_suffix(mode));
363 void ia32_emit_extend_suffix(const ir_mode *mode)
365 if (get_mode_size_bits(mode) == 32)
367 be_emit_char(mode_is_signed(mode) ? 's' : 'z');
370 void ia32_emit_source_register_or_immediate(const ir_node *node, int pos)
372 ir_node *in = get_irn_n(node, pos);
373 if (is_ia32_Immediate(in)) {
374 emit_ia32_Immediate(in);
376 const ir_mode *mode = get_ia32_ls_mode(node);
377 const arch_register_t *reg = get_in_reg(node, pos);
378 emit_register(reg, mode);
383 * Emits registers and/or address mode of a binary operation.
385 void ia32_emit_binop(const ir_node *node)
387 const ir_node *right_op = get_irn_n(node, n_ia32_binary_right);
388 const ir_mode *mode = get_ia32_ls_mode(node);
389 const arch_register_t *reg_left;
391 switch(get_ia32_op_type(node)) {
393 reg_left = get_in_reg(node, n_ia32_binary_left);
394 if (is_ia32_Immediate(right_op)) {
395 emit_ia32_Immediate(right_op);
396 be_emit_cstring(", ");
397 emit_register(reg_left, mode);
400 const arch_register_t *reg_right
401 = get_in_reg(node, n_ia32_binary_right);
402 emit_register(reg_right, mode);
403 be_emit_cstring(", ");
404 emit_register(reg_left, mode);
408 if (is_ia32_Immediate(right_op)) {
409 emit_ia32_Immediate(right_op);
410 be_emit_cstring(", ");
413 reg_left = get_in_reg(node, n_ia32_binary_left);
415 be_emit_cstring(", ");
416 emit_register(reg_left, mode);
420 panic("DestMode can't be output by %%binop anymore");
423 assert(0 && "unsupported op type");
428 * Emits registers and/or address mode of a binary operation.
430 void ia32_emit_x87_binop(const ir_node *node)
432 switch(get_ia32_op_type(node)) {
435 const ia32_x87_attr_t *x87_attr = get_ia32_x87_attr_const(node);
436 const arch_register_t *in1 = x87_attr->x87[0];
437 const arch_register_t *in2 = x87_attr->x87[1];
438 const arch_register_t *out = x87_attr->x87[2];
439 const arch_register_t *in;
441 in = out ? ((out == in2) ? in1 : in2) : in2;
442 out = out ? out : in1;
445 be_emit_string(arch_register_get_name(in));
446 be_emit_cstring(", %");
447 be_emit_string(arch_register_get_name(out));
455 assert(0 && "unsupported op type");
460 * Emits registers and/or address mode of a unary operation.
462 void ia32_emit_unop(const ir_node *node, int pos)
466 switch(get_ia32_op_type(node)) {
468 op = get_irn_n(node, pos);
469 if (is_ia32_Immediate(op)) {
470 emit_ia32_Immediate(op);
472 ia32_emit_source_register(node, pos);
480 assert(0 && "unsupported op type");
484 static void ia32_emit_entity(ir_entity *entity, int no_pic_adjust)
488 set_entity_backend_marked(entity, 1);
489 id = get_entity_ld_ident(entity);
492 if (get_entity_owner(entity) == get_tls_type()) {
493 if (get_entity_visibility(entity) == visibility_external_allocated) {
494 be_emit_cstring("@INDNTPOFF");
496 be_emit_cstring("@NTPOFF");
500 if (!no_pic_adjust && do_pic) {
501 /* TODO: only do this when necessary */
503 be_emit_string(pic_base_label);
508 * Emits address mode.
510 void ia32_emit_am(const ir_node *node)
512 ir_entity *ent = get_ia32_am_sc(node);
513 int offs = get_ia32_am_offs_int(node);
514 ir_node *base = get_irn_n(node, n_ia32_base);
515 int has_base = !is_ia32_NoReg_GP(base);
516 ir_node *index = get_irn_n(node, n_ia32_index);
517 int has_index = !is_ia32_NoReg_GP(index);
519 /* just to be sure... */
520 assert(!is_ia32_use_frame(node) || get_ia32_frame_ent(node) != NULL);
524 if (is_ia32_am_sc_sign(node))
526 ia32_emit_entity(ent, 0);
529 /* also handle special case if nothing is set */
530 if (offs != 0 || (ent == NULL && !has_base && !has_index)) {
532 be_emit_irprintf("%+d", offs);
534 be_emit_irprintf("%d", offs);
538 if (has_base || has_index) {
543 const arch_register_t *reg = get_in_reg(node, n_ia32_base);
544 emit_register(reg, NULL);
547 /* emit index + scale */
549 const arch_register_t *reg = get_in_reg(node, n_ia32_index);
552 emit_register(reg, NULL);
554 scale = get_ia32_am_scale(node);
556 be_emit_irprintf(",%d", 1 << scale);
563 static void emit_ia32_IMul(const ir_node *node)
565 ir_node *left = get_irn_n(node, n_ia32_IMul_left);
566 const arch_register_t *out_reg = get_out_reg(node, pn_ia32_IMul_res);
568 be_emit_cstring("\timul");
569 ia32_emit_mode_suffix(node);
572 ia32_emit_binop(node);
574 /* do we need the 3-address form? */
575 if (is_ia32_NoReg_GP(left) ||
576 get_in_reg(node, n_ia32_IMul_left) != out_reg) {
577 be_emit_cstring(", ");
578 emit_register(out_reg, get_ia32_ls_mode(node));
580 be_emit_finish_line_gas(node);
583 /*************************************************
586 * ___ _ __ ___ _| |_ ___ ___ _ __ __| |
587 * / _ \ '_ ` _ \| | __| / __/ _ \| '_ \ / _` |
588 * | __/ | | | | | | |_ | (_| (_) | | | | (_| |
589 * \___|_| |_| |_|_|\__| \___\___/|_| |_|\__,_|
591 *************************************************/
594 #define IA32_DO_EMIT(irn) ia32_fprintf_format(F, irn, cmd_buf, cmnt_buf)
597 * coding of conditions
599 struct cmp2conditon_t {
605 * positive conditions for signed compares
607 static const struct cmp2conditon_t cmp2condition_s[] = {
608 { NULL, pn_Cmp_False }, /* always false */
609 { "e", pn_Cmp_Eq }, /* == */
610 { "l", pn_Cmp_Lt }, /* < */
611 { "le", pn_Cmp_Le }, /* <= */
612 { "g", pn_Cmp_Gt }, /* > */
613 { "ge", pn_Cmp_Ge }, /* >= */
614 { "ne", pn_Cmp_Lg }, /* != */
615 { NULL, pn_Cmp_Leg}, /* always true */
619 * positive conditions for unsigned compares
621 static const struct cmp2conditon_t cmp2condition_u[] = {
622 { NULL, pn_Cmp_False }, /* always false */
623 { "e", pn_Cmp_Eq }, /* == */
624 { "b", pn_Cmp_Lt }, /* < */
625 { "be", pn_Cmp_Le }, /* <= */
626 { "a", pn_Cmp_Gt }, /* > */
627 { "ae", pn_Cmp_Ge }, /* >= */
628 { "ne", pn_Cmp_Lg }, /* != */
629 { NULL, pn_Cmp_Leg }, /* always true */
633 * walks up a tree of copies/perms/spills/reloads to find the original value
634 * that is moved around
636 static ir_node *find_original_value(ir_node *node)
638 if (irn_visited(node))
641 mark_irn_visited(node);
642 if (be_is_Copy(node)) {
643 return find_original_value(be_get_Copy_op(node));
644 } else if (be_is_CopyKeep(node)) {
645 return find_original_value(be_get_CopyKeep_op(node));
646 } else if (is_Proj(node)) {
647 ir_node *pred = get_Proj_pred(node);
648 if (be_is_Perm(pred)) {
649 return find_original_value(get_irn_n(pred, get_Proj_proj(node)));
650 } else if (be_is_MemPerm(pred)) {
651 return find_original_value(get_irn_n(pred, get_Proj_proj(node) + 1));
652 } else if (is_ia32_Load(pred)) {
653 return find_original_value(get_irn_n(pred, n_ia32_Load_mem));
657 } else if (is_ia32_Store(node)) {
658 return find_original_value(get_irn_n(node, n_ia32_Store_val));
659 } else if (is_Phi(node)) {
661 arity = get_irn_arity(node);
662 for (i = 0; i < arity; ++i) {
663 ir_node *in = get_irn_n(node, i);
664 ir_node *res = find_original_value(in);
675 static int determine_final_pnc(const ir_node *node, int flags_pos,
678 ir_node *flags = get_irn_n(node, flags_pos);
679 const ia32_attr_t *flags_attr;
680 flags = skip_Proj(flags);
682 if (is_ia32_Sahf(flags)) {
683 ir_node *cmp = get_irn_n(flags, n_ia32_Sahf_val);
684 if (!(is_ia32_FucomFnstsw(cmp) || is_ia32_FucompFnstsw(cmp)
685 || is_ia32_FucomppFnstsw(cmp) || is_ia32_FtstFnstsw(cmp))) {
686 inc_irg_visited(current_ir_graph);
687 cmp = find_original_value(cmp);
689 assert(is_ia32_FucomFnstsw(cmp) || is_ia32_FucompFnstsw(cmp)
690 || is_ia32_FucomppFnstsw(cmp) || is_ia32_FtstFnstsw(cmp));
693 flags_attr = get_ia32_attr_const(cmp);
694 if (flags_attr->data.ins_permuted)
695 pnc = get_mirrored_pnc(pnc);
696 pnc |= ia32_pn_Cmp_float;
697 } else if (is_ia32_Ucomi(flags) || is_ia32_Fucomi(flags)
698 || is_ia32_Fucompi(flags)) {
699 flags_attr = get_ia32_attr_const(flags);
701 if (flags_attr->data.ins_permuted)
702 pnc = get_mirrored_pnc(pnc);
703 pnc |= ia32_pn_Cmp_float;
705 flags_attr = get_ia32_attr_const(flags);
707 if (flags_attr->data.ins_permuted)
708 pnc = get_mirrored_pnc(pnc);
709 if (flags_attr->data.cmp_unsigned)
710 pnc |= ia32_pn_Cmp_unsigned;
716 static void ia32_emit_cmp_suffix(int pnc)
720 if ((pnc & ia32_pn_Cmp_float) || (pnc & ia32_pn_Cmp_unsigned)) {
722 assert(cmp2condition_u[pnc].num == pnc);
723 str = cmp2condition_u[pnc].name;
726 assert(cmp2condition_s[pnc].num == pnc);
727 str = cmp2condition_s[pnc].name;
733 void ia32_emit_cmp_suffix_node(const ir_node *node,
736 const ia32_attr_t *attr = get_ia32_attr_const(node);
738 pn_Cmp pnc = get_ia32_condcode(node);
740 pnc = determine_final_pnc(node, flags_pos, pnc);
741 if (attr->data.ins_permuted) {
742 if (pnc & ia32_pn_Cmp_float) {
743 pnc = get_negated_pnc(pnc, mode_F);
745 pnc = get_negated_pnc(pnc, mode_Iu);
749 ia32_emit_cmp_suffix(pnc);
753 * Returns the target block for a control flow node.
755 static ir_node *get_cfop_target_block(const ir_node *irn)
757 assert(get_irn_mode(irn) == mode_X);
758 return get_irn_link(irn);
762 * Emits a block label for the given block.
764 static void ia32_emit_block_name(const ir_node *block)
766 if (has_Block_label(block)) {
767 be_emit_string(be_gas_block_label_prefix());
768 be_emit_irprintf("%lu", get_Block_label(block));
770 be_emit_cstring(BLOCK_PREFIX);
771 be_emit_irprintf("%ld", get_irn_node_nr(block));
776 * Emits an exception label for a given node.
778 static void ia32_emit_exc_label(const ir_node *node)
780 be_emit_string(be_gas_insn_label_prefix());
781 be_emit_irprintf("%lu", get_ia32_exc_label_id(node));
785 * Emits the target label for a control flow node.
787 static void ia32_emit_cfop_target(const ir_node *node)
789 ir_node *block = get_cfop_target_block(node);
791 ia32_emit_block_name(block);
795 * Returns the Proj with projection number proj and NOT mode_M
797 static ir_node *get_proj(const ir_node *node, long proj)
799 const ir_edge_t *edge;
802 assert(get_irn_mode(node) == mode_T && "expected mode_T node");
804 foreach_out_edge(node, edge) {
805 src = get_edge_src_irn(edge);
807 assert(is_Proj(src) && "Proj expected");
808 if (get_irn_mode(src) == mode_M)
811 if (get_Proj_proj(src) == proj)
817 static int can_be_fallthrough(const ir_node *node)
819 ir_node *target_block = get_cfop_target_block(node);
820 ir_node *block = get_nodes_block(node);
821 return get_prev_block_sched(target_block) == block;
825 * Emits the jump sequence for a conditional jump (cmp + jmp_true + jmp_false)
827 static void emit_ia32_Jcc(const ir_node *node)
829 int need_parity_label = 0;
830 const ir_node *proj_true;
831 const ir_node *proj_false;
832 const ir_node *block;
833 pn_Cmp pnc = get_ia32_condcode(node);
835 pnc = determine_final_pnc(node, 0, pnc);
838 proj_true = get_proj(node, pn_ia32_Jcc_true);
839 assert(proj_true && "Jcc without true Proj");
841 proj_false = get_proj(node, pn_ia32_Jcc_false);
842 assert(proj_false && "Jcc without false Proj");
844 block = get_nodes_block(node);
846 if (can_be_fallthrough(proj_true)) {
847 /* exchange both proj's so the second one can be omitted */
848 const ir_node *t = proj_true;
850 proj_true = proj_false;
852 if (pnc & ia32_pn_Cmp_float) {
853 pnc = get_negated_pnc(pnc, mode_F);
855 pnc = get_negated_pnc(pnc, mode_Iu);
859 if (pnc & ia32_pn_Cmp_float) {
860 /* Some floating point comparisons require a test of the parity flag,
861 * which indicates that the result is unordered */
864 be_emit_cstring("\tjp ");
865 ia32_emit_cfop_target(proj_true);
866 be_emit_finish_line_gas(proj_true);
871 be_emit_cstring("\tjnp ");
872 ia32_emit_cfop_target(proj_true);
873 be_emit_finish_line_gas(proj_true);
879 /* we need a local label if the false proj is a fallthrough
880 * as the falseblock might have no label emitted then */
881 if (can_be_fallthrough(proj_false)) {
882 need_parity_label = 1;
883 be_emit_cstring("\tjp 1f");
885 be_emit_cstring("\tjp ");
886 ia32_emit_cfop_target(proj_false);
888 be_emit_finish_line_gas(proj_false);
894 be_emit_cstring("\tjp ");
895 ia32_emit_cfop_target(proj_true);
896 be_emit_finish_line_gas(proj_true);
904 be_emit_cstring("\tj");
905 ia32_emit_cmp_suffix(pnc);
907 ia32_emit_cfop_target(proj_true);
908 be_emit_finish_line_gas(proj_true);
911 if (need_parity_label) {
912 be_emit_cstring("1:");
913 be_emit_write_line();
916 /* the second Proj might be a fallthrough */
917 if (can_be_fallthrough(proj_false)) {
918 be_emit_cstring("\t/* fallthrough to ");
919 ia32_emit_cfop_target(proj_false);
920 be_emit_cstring(" */");
921 be_emit_finish_line_gas(proj_false);
923 be_emit_cstring("\tjmp ");
924 ia32_emit_cfop_target(proj_false);
925 be_emit_finish_line_gas(proj_false);
929 static void emit_ia32_CMov(const ir_node *node)
931 const ia32_attr_t *attr = get_ia32_attr_const(node);
932 int ins_permuted = attr->data.ins_permuted;
933 const arch_register_t *out = arch_get_irn_register(arch_env, node);
934 pn_Cmp pnc = get_ia32_condcode(node);
935 const arch_register_t *in_true;
936 const arch_register_t *in_false;
938 pnc = determine_final_pnc(node, n_ia32_CMov_eflags, pnc);
940 in_true = arch_get_irn_register(arch_env,
941 get_irn_n(node, n_ia32_CMov_val_true));
942 in_false = arch_get_irn_register(arch_env,
943 get_irn_n(node, n_ia32_CMov_val_false));
945 /* should be same constraint fullfilled? */
946 if (out == in_false) {
947 /* yes -> nothing to do */
948 } else if (out == in_true) {
949 const arch_register_t *tmp;
951 assert(get_ia32_op_type(node) == ia32_Normal);
953 ins_permuted = !ins_permuted;
960 be_emit_cstring("\tmovl ");
961 emit_register(in_false, NULL);
962 be_emit_cstring(", ");
963 emit_register(out, NULL);
964 be_emit_finish_line_gas(node);
968 if (pnc & ia32_pn_Cmp_float) {
969 pnc = get_negated_pnc(pnc, mode_F);
971 pnc = get_negated_pnc(pnc, mode_Iu);
975 /* TODO: handling of Nans isn't correct yet */
977 be_emit_cstring("\tcmov");
978 ia32_emit_cmp_suffix(pnc);
980 if (get_ia32_op_type(node) == ia32_AddrModeS) {
983 emit_register(in_true, get_ia32_ls_mode(node));
985 be_emit_cstring(", ");
986 emit_register(out, get_ia32_ls_mode(node));
987 be_emit_finish_line_gas(node);
990 /*********************************************************
993 * ___ _ __ ___ _| |_ _ _ _ _ __ ___ _ __ ___
994 * / _ \ '_ ` _ \| | __| | | | | | '_ ` _ \| '_ \/ __|
995 * | __/ | | | | | | |_ | | |_| | | | | | | |_) \__ \
996 * \___|_| |_| |_|_|\__| | |\__,_|_| |_| |_| .__/|___/
999 *********************************************************/
1001 /* jump table entry (target and corresponding number) */
1002 typedef struct _branch_t {
1007 /* jump table for switch generation */
1008 typedef struct _jmp_tbl_t {
1009 ir_node *defProj; /**< default target */
1010 long min_value; /**< smallest switch case */
1011 long max_value; /**< largest switch case */
1012 long num_branches; /**< number of jumps */
1013 char *label; /**< label of the jump table */
1014 branch_t *branches; /**< jump array */
1018 * Compare two variables of type branch_t. Used to sort all switch cases
1020 static int ia32_cmp_branch_t(const void *a, const void *b)
1022 branch_t *b1 = (branch_t *)a;
1023 branch_t *b2 = (branch_t *)b;
1025 if (b1->value <= b2->value)
1032 * Emits code for a SwitchJmp (creates a jump table if
1033 * possible otherwise a cmp-jmp cascade). Port from
1036 static void emit_ia32_SwitchJmp(const ir_node *node)
1038 unsigned long interval;
1044 const ir_edge_t *edge;
1046 /* fill the table structure */
1047 tbl.label = xmalloc(SNPRINTF_BUF_LEN);
1048 tbl.label = get_unique_label(tbl.label, SNPRINTF_BUF_LEN, ".TBL_");
1050 tbl.num_branches = get_irn_n_edges(node) - 1;
1051 tbl.branches = xcalloc(tbl.num_branches, sizeof(tbl.branches[0]));
1052 tbl.min_value = INT_MAX;
1053 tbl.max_value = INT_MIN;
1055 default_pn = get_ia32_condcode(node);
1057 /* go over all proj's and collect them */
1058 foreach_out_edge(node, edge) {
1059 proj = get_edge_src_irn(edge);
1060 assert(is_Proj(proj) && "Only proj allowed at SwitchJmp");
1062 pnc = get_Proj_proj(proj);
1064 /* check for default proj */
1065 if (pnc == default_pn) {
1066 assert(tbl.defProj == NULL && "found two default Projs at SwitchJmp");
1069 tbl.min_value = pnc < tbl.min_value ? pnc : tbl.min_value;
1070 tbl.max_value = pnc > tbl.max_value ? pnc : tbl.max_value;
1072 /* create branch entry */
1073 tbl.branches[i].target = proj;
1074 tbl.branches[i].value = pnc;
1079 assert(i == tbl.num_branches);
1081 /* sort the branches by their number */
1082 qsort(tbl.branches, tbl.num_branches, sizeof(tbl.branches[0]), ia32_cmp_branch_t);
1084 /* two-complement's magic make this work without overflow */
1085 interval = tbl.max_value - tbl.min_value;
1087 /* emit the table */
1088 be_emit_cstring("\tcmpl $");
1089 be_emit_irprintf("%u, ", interval);
1090 ia32_emit_source_register(node, 0);
1091 be_emit_finish_line_gas(node);
1093 be_emit_cstring("\tja ");
1094 ia32_emit_cfop_target(tbl.defProj);
1095 be_emit_finish_line_gas(node);
1097 if (tbl.num_branches > 1) {
1099 be_emit_cstring("\tjmp *");
1100 be_emit_string(tbl.label);
1101 be_emit_cstring("(,");
1102 ia32_emit_source_register(node, 0);
1103 be_emit_cstring(",4)");
1104 be_emit_finish_line_gas(node);
1106 be_gas_emit_switch_section(GAS_SECTION_RODATA);
1107 be_emit_cstring("\t.align 4\n");
1108 be_emit_write_line();
1110 be_emit_string(tbl.label);
1111 be_emit_cstring(":\n");
1112 be_emit_write_line();
1114 be_emit_cstring(".long ");
1115 ia32_emit_cfop_target(tbl.branches[0].target);
1116 be_emit_finish_line_gas(NULL);
1118 last_value = tbl.branches[0].value;
1119 for (i = 1; i < tbl.num_branches; ++i) {
1120 while (++last_value < tbl.branches[i].value) {
1121 be_emit_cstring(".long ");
1122 ia32_emit_cfop_target(tbl.defProj);
1123 be_emit_finish_line_gas(NULL);
1125 be_emit_cstring(".long ");
1126 ia32_emit_cfop_target(tbl.branches[i].target);
1127 be_emit_finish_line_gas(NULL);
1129 be_gas_emit_switch_section(GAS_SECTION_TEXT);
1131 /* one jump is enough */
1132 be_emit_cstring("\tjmp ");
1133 ia32_emit_cfop_target(tbl.branches[0].target);
1134 be_emit_finish_line_gas(node);
1144 * Emits code for a unconditional jump.
1146 static void emit_Jmp(const ir_node *node)
1150 /* for now, the code works for scheduled and non-schedules blocks */
1151 block = get_nodes_block(node);
1153 /* we have a block schedule */
1154 if (can_be_fallthrough(node)) {
1155 be_emit_cstring("\t/* fallthrough to ");
1156 ia32_emit_cfop_target(node);
1157 be_emit_cstring(" */");
1159 be_emit_cstring("\tjmp ");
1160 ia32_emit_cfop_target(node);
1162 be_emit_finish_line_gas(node);
1165 static void emit_ia32_Immediate(const ir_node *node)
1167 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(node);
1170 if (attr->symconst != NULL) {
1173 ia32_emit_entity(attr->symconst, 0);
1175 if (attr->symconst == NULL || attr->offset != 0) {
1176 if (attr->symconst != NULL) {
1177 be_emit_irprintf("%+d", attr->offset);
1179 be_emit_irprintf("0x%X", attr->offset);
1185 * Emit an inline assembler operand.
1187 * @param node the ia32_ASM node
1188 * @param s points to the operand (a %c)
1190 * @return pointer to the first char in s NOT in the current operand
1192 static const char* emit_asm_operand(const ir_node *node, const char *s)
1194 const ia32_attr_t *ia32_attr = get_ia32_attr_const(node);
1195 const ia32_asm_attr_t *attr = CONST_CAST_IA32_ATTR(ia32_asm_attr_t,
1197 const arch_register_t *reg;
1198 const ia32_asm_reg_t *asm_regs = attr->register_map;
1199 const ia32_asm_reg_t *asm_reg;
1200 const char *reg_name;
1209 /* parse modifiers */
1212 ir_fprintf(stderr, "Warning: asm text (%+F) ends with %\n", node);
1236 ir_fprintf(stderr, "Warning: asm text (%+F) contains unknown modifier "
1237 "'%c' for asm op\n", node, c);
1243 sscanf(s, "%d%n", &num, &p);
1245 ir_fprintf(stderr, "Warning: Couldn't parse assembler operand (%+F)\n",
1252 if (num < 0 || num >= ARR_LEN(asm_regs)) {
1253 ir_fprintf(stderr, "Error: Custom assembler references invalid "
1254 "input/output (%+F)\n", node);
1257 asm_reg = & asm_regs[num];
1258 assert(asm_reg->valid);
1261 if (asm_reg->use_input == 0) {
1262 reg = get_out_reg(node, asm_reg->inout_pos);
1264 ir_node *pred = get_irn_n(node, asm_reg->inout_pos);
1266 /* might be an immediate value */
1267 if (is_ia32_Immediate(pred)) {
1268 emit_ia32_Immediate(pred);
1271 reg = get_in_reg(node, asm_reg->inout_pos);
1274 ir_fprintf(stderr, "Warning: no register assigned for %d asm op "
1275 "(%+F)\n", num, node);
1279 if (asm_reg->memory) {
1284 if (modifier != 0) {
1288 reg_name = ia32_get_mapped_reg_name(isa->regs_8bit, reg);
1291 reg_name = ia32_get_mapped_reg_name(isa->regs_8bit_high, reg);
1294 reg_name = ia32_get_mapped_reg_name(isa->regs_16bit, reg);
1297 panic("Invalid asm op modifier");
1299 be_emit_string(reg_name);
1301 emit_register(reg, asm_reg->mode);
1304 if (asm_reg->memory) {
1312 * Emits code for an ASM pseudo op.
1314 static void emit_ia32_Asm(const ir_node *node)
1316 const void *gen_attr = get_irn_generic_attr_const(node);
1317 const ia32_asm_attr_t *attr
1318 = CONST_CAST_IA32_ATTR(ia32_asm_attr_t, gen_attr);
1319 ident *asm_text = attr->asm_text;
1320 const char *s = get_id_str(asm_text);
1322 be_emit_cstring("#APP\t");
1323 be_emit_finish_line_gas(node);
1330 s = emit_asm_operand(node, s);
1337 be_emit_write_line();
1339 be_emit_cstring("#NO_APP\n");
1340 be_emit_write_line();
1343 /**********************************
1346 * | | ___ _ __ _ _| |_) |
1347 * | | / _ \| '_ \| | | | _ <
1348 * | |___| (_) | |_) | |_| | |_) |
1349 * \_____\___/| .__/ \__, |____/
1352 **********************************/
1355 * Emit movsb/w instructions to make mov count divideable by 4
1357 static void emit_CopyB_prolog(unsigned size)
1359 be_emit_cstring("\tcld");
1360 be_emit_finish_line_gas(NULL);
1364 be_emit_cstring("\tmovsb");
1365 be_emit_finish_line_gas(NULL);
1368 be_emit_cstring("\tmovsw");
1369 be_emit_finish_line_gas(NULL);
1372 be_emit_cstring("\tmovsb");
1373 be_emit_finish_line_gas(NULL);
1374 be_emit_cstring("\tmovsw");
1375 be_emit_finish_line_gas(NULL);
1381 * Emit rep movsd instruction for memcopy.
1383 static void emit_ia32_CopyB(const ir_node *node)
1385 unsigned size = get_ia32_copyb_size(node);
1387 emit_CopyB_prolog(size);
1389 be_emit_cstring("\trep movsd");
1390 be_emit_finish_line_gas(node);
1394 * Emits unrolled memcopy.
1396 static void emit_ia32_CopyB_i(const ir_node *node)
1398 unsigned size = get_ia32_copyb_size(node);
1400 emit_CopyB_prolog(size & 0x3);
1404 be_emit_cstring("\tmovsd");
1405 be_emit_finish_line_gas(NULL);
1411 /***************************
1415 * | | / _ \| '_ \ \ / /
1416 * | |___| (_) | | | \ V /
1417 * \_____\___/|_| |_|\_/
1419 ***************************/
1422 * Emit code for conversions (I, FP), (FP, I) and (FP, FP).
1424 static void emit_ia32_Conv_with_FP(const ir_node *node)
1426 ir_mode *ls_mode = get_ia32_ls_mode(node);
1427 int ls_bits = get_mode_size_bits(ls_mode);
1429 be_emit_cstring("\tcvt");
1431 if (is_ia32_Conv_I2FP(node)) {
1432 if (ls_bits == 32) {
1433 be_emit_cstring("si2ss");
1435 be_emit_cstring("si2sd");
1437 } else if (is_ia32_Conv_FP2I(node)) {
1438 if (ls_bits == 32) {
1439 be_emit_cstring("ss2si");
1441 be_emit_cstring("sd2si");
1444 assert(is_ia32_Conv_FP2FP(node));
1445 if (ls_bits == 32) {
1446 be_emit_cstring("sd2ss");
1448 be_emit_cstring("ss2sd");
1453 switch(get_ia32_op_type(node)) {
1455 ia32_emit_source_register(node, n_ia32_unary_op);
1457 case ia32_AddrModeS:
1461 assert(0 && "unsupported op type for Conv");
1463 be_emit_cstring(", ");
1464 ia32_emit_dest_register(node, 0);
1465 be_emit_finish_line_gas(node);
1468 static void emit_ia32_Conv_I2FP(const ir_node *node)
1470 emit_ia32_Conv_with_FP(node);
1473 static void emit_ia32_Conv_FP2I(const ir_node *node)
1475 emit_ia32_Conv_with_FP(node);
1478 static void emit_ia32_Conv_FP2FP(const ir_node *node)
1480 emit_ia32_Conv_with_FP(node);
1484 * Emits code for an Int conversion.
1486 static void emit_ia32_Conv_I2I(const ir_node *node)
1488 const char *sign_suffix;
1489 ir_mode *smaller_mode = get_ia32_ls_mode(node);
1490 int smaller_bits = get_mode_size_bits(smaller_mode);
1492 const arch_register_t *in_reg, *out_reg;
1494 assert(!mode_is_float(smaller_mode));
1495 assert(smaller_bits == 8 || smaller_bits == 16);
1497 signed_mode = mode_is_signed(smaller_mode);
1498 sign_suffix = signed_mode ? "s" : "z";
1500 out_reg = get_out_reg(node, 0);
1502 switch(get_ia32_op_type(node)) {
1504 in_reg = get_in_reg(node, n_ia32_unary_op);
1506 if (in_reg == &ia32_gp_regs[REG_EAX] &&
1507 out_reg == &ia32_gp_regs[REG_EAX] &&
1511 /* argument and result are both in EAX and */
1512 /* signedness is ok: -> use the smaller cwtl opcode */
1513 be_emit_cstring("\tcwtl");
1515 be_emit_cstring("\tmov");
1516 be_emit_string(sign_suffix);
1517 ia32_emit_mode_suffix_mode(smaller_mode);
1518 be_emit_cstring("l ");
1519 emit_register(in_reg, smaller_mode);
1520 be_emit_cstring(", ");
1521 emit_register(out_reg, NULL);
1524 case ia32_AddrModeS: {
1525 be_emit_cstring("\tmov");
1526 be_emit_string(sign_suffix);
1527 ia32_emit_mode_suffix_mode(smaller_mode);
1528 be_emit_cstring("l ");
1530 be_emit_cstring(", ");
1531 emit_register(out_reg, NULL);
1535 panic("unsupported op type for Conv");
1537 be_emit_finish_line_gas(node);
1541 /*******************************************
1544 * | |__ ___ _ __ ___ __| | ___ ___
1545 * | '_ \ / _ \ '_ \ / _ \ / _` |/ _ \/ __|
1546 * | |_) | __/ | | | (_) | (_| | __/\__ \
1547 * |_.__/ \___|_| |_|\___/ \__,_|\___||___/
1549 *******************************************/
1552 * Emits a backend call
1554 static void emit_be_Call(const ir_node *node)
1556 ir_entity *ent = be_Call_get_entity(node);
1558 be_emit_cstring("\tcall ");
1560 ia32_emit_entity(ent, 1);
1562 const arch_register_t *reg = get_in_reg(node, be_pos_Call_ptr);
1564 emit_register(reg, NULL);
1566 be_emit_finish_line_gas(node);
1570 * Emits code to increase stack pointer.
1572 static void emit_be_IncSP(const ir_node *node)
1574 int offs = be_get_IncSP_offset(node);
1575 const arch_register_t *reg = arch_get_irn_register(arch_env, node);
1581 be_emit_cstring("\tsubl $");
1582 be_emit_irprintf("%u, ", offs);
1583 emit_register(reg, NULL);
1585 be_emit_cstring("\taddl $");
1586 be_emit_irprintf("%u, ", -offs);
1587 emit_register(reg, NULL);
1589 be_emit_finish_line_gas(node);
1593 * Emits code for Copy/CopyKeep.
1595 static void Copy_emitter(const ir_node *node, const ir_node *op)
1597 const arch_register_t *in = arch_get_irn_register(arch_env, op);
1598 const arch_register_t *out = arch_get_irn_register(arch_env, node);
1604 if (is_unknown_reg(in))
1606 /* copies of vf nodes aren't real... */
1607 if (arch_register_get_class(in) == &ia32_reg_classes[CLASS_ia32_vfp])
1610 mode = get_irn_mode(node);
1611 if (mode == mode_E) {
1612 be_emit_cstring("\tmovsd ");
1613 emit_register(in, NULL);
1614 be_emit_cstring(", ");
1615 emit_register(out, NULL);
1617 be_emit_cstring("\tmovl ");
1618 emit_register(in, NULL);
1619 be_emit_cstring(", ");
1620 emit_register(out, NULL);
1622 be_emit_finish_line_gas(node);
1625 static void emit_be_Copy(const ir_node *node)
1627 Copy_emitter(node, be_get_Copy_op(node));
1630 static void emit_be_CopyKeep(const ir_node *node)
1632 Copy_emitter(node, be_get_CopyKeep_op(node));
1636 * Emits code for exchange.
1638 static void emit_be_Perm(const ir_node *node)
1640 const arch_register_t *in0, *in1;
1641 const arch_register_class_t *cls0, *cls1;
1643 in0 = arch_get_irn_register(arch_env, get_irn_n(node, 0));
1644 in1 = arch_get_irn_register(arch_env, get_irn_n(node, 1));
1646 cls0 = arch_register_get_class(in0);
1647 cls1 = arch_register_get_class(in1);
1649 assert(cls0 == cls1 && "Register class mismatch at Perm");
1651 if (cls0 == &ia32_reg_classes[CLASS_ia32_gp]) {
1652 be_emit_cstring("\txchg ");
1653 emit_register(in1, NULL);
1654 be_emit_cstring(", ");
1655 emit_register(in0, NULL);
1656 be_emit_finish_line_gas(node);
1657 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_xmm]) {
1658 be_emit_cstring("\txorpd ");
1659 emit_register(in1, NULL);
1660 be_emit_cstring(", ");
1661 emit_register(in0, NULL);
1662 be_emit_finish_line_gas(NULL);
1664 be_emit_cstring("\txorpd ");
1665 emit_register(in0, NULL);
1666 be_emit_cstring(", ");
1667 emit_register(in1, NULL);
1668 be_emit_finish_line_gas(NULL);
1670 be_emit_cstring("\txorpd ");
1671 emit_register(in1, NULL);
1672 be_emit_cstring(", ");
1673 emit_register(in0, NULL);
1674 be_emit_finish_line_gas(node);
1675 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_vfp]) {
1677 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_st]) {
1680 panic("unexpected register class in be_Perm (%+F)", node);
1685 * Emits code for Constant loading.
1687 static void emit_ia32_Const(const ir_node *node)
1689 be_emit_cstring("\tmovl ");
1690 emit_ia32_Immediate(node);
1691 be_emit_cstring(", ");
1692 ia32_emit_dest_register(node, 0);
1694 be_emit_finish_line_gas(node);
1698 * Emits code to load the TLS base
1700 static void emit_ia32_LdTls(const ir_node *node)
1702 be_emit_cstring("\tmovl %gs:0, ");
1703 ia32_emit_dest_register(node, 0);
1704 be_emit_finish_line_gas(node);
1707 /* helper function for emit_ia32_Minus64Bit */
1708 static void emit_mov(const ir_node* node, const arch_register_t *src, const arch_register_t *dst)
1710 be_emit_cstring("\tmovl ");
1711 emit_register(src, NULL);
1712 be_emit_cstring(", ");
1713 emit_register(dst, NULL);
1714 be_emit_finish_line_gas(node);
1717 /* helper function for emit_ia32_Minus64Bit */
1718 static void emit_neg(const ir_node* node, const arch_register_t *reg)
1720 be_emit_cstring("\tnegl ");
1721 emit_register(reg, NULL);
1722 be_emit_finish_line_gas(node);
1725 /* helper function for emit_ia32_Minus64Bit */
1726 static void emit_sbb0(const ir_node* node, const arch_register_t *reg)
1728 be_emit_cstring("\tsbbl $0, ");
1729 emit_register(reg, NULL);
1730 be_emit_finish_line_gas(node);
1733 /* helper function for emit_ia32_Minus64Bit */
1734 static void emit_sbb(const ir_node* node, const arch_register_t *src, const arch_register_t *dst)
1736 be_emit_cstring("\tsbbl ");
1737 emit_register(src, NULL);
1738 be_emit_cstring(", ");
1739 emit_register(dst, NULL);
1740 be_emit_finish_line_gas(node);
1743 /* helper function for emit_ia32_Minus64Bit */
1744 static void emit_xchg(const ir_node* node, const arch_register_t *src, const arch_register_t *dst)
1746 be_emit_cstring("\txchgl ");
1747 emit_register(src, NULL);
1748 be_emit_cstring(", ");
1749 emit_register(dst, NULL);
1750 be_emit_finish_line_gas(node);
1753 /* helper function for emit_ia32_Minus64Bit */
1754 static void emit_zero(const ir_node* node, const arch_register_t *reg)
1756 be_emit_cstring("\txorl ");
1757 emit_register(reg, NULL);
1758 be_emit_cstring(", ");
1759 emit_register(reg, NULL);
1760 be_emit_finish_line_gas(node);
1763 static void emit_ia32_Minus64Bit(const ir_node *node)
1765 const arch_register_t *in_lo = get_in_reg(node, 0);
1766 const arch_register_t *in_hi = get_in_reg(node, 1);
1767 const arch_register_t *out_lo = get_out_reg(node, 0);
1768 const arch_register_t *out_hi = get_out_reg(node, 1);
1770 if (out_lo == in_lo) {
1771 if (out_hi != in_hi) {
1772 /* a -> a, b -> d */
1775 /* a -> a, b -> b */
1778 } else if (out_lo == in_hi) {
1779 if (out_hi == in_lo) {
1780 /* a -> b, b -> a */
1781 emit_xchg(node, in_lo, in_hi);
1784 /* a -> b, b -> d */
1785 emit_mov(node, in_hi, out_hi);
1786 emit_mov(node, in_lo, out_lo);
1790 if (out_hi == in_lo) {
1791 /* a -> c, b -> a */
1792 emit_mov(node, in_lo, out_lo);
1794 } else if (out_hi == in_hi) {
1795 /* a -> c, b -> b */
1796 emit_mov(node, in_lo, out_lo);
1799 /* a -> c, b -> d */
1800 emit_mov(node, in_lo, out_lo);
1806 emit_neg( node, out_hi);
1807 emit_neg( node, out_lo);
1808 emit_sbb0(node, out_hi);
1812 emit_zero(node, out_hi);
1813 emit_neg( node, out_lo);
1814 emit_sbb( node, in_hi, out_hi);
1817 static void emit_ia32_GetEIP(const ir_node *node)
1819 be_emit_cstring("\tcall ");
1820 be_emit_string(pic_base_label);
1821 be_emit_finish_line_gas(node);
1823 be_emit_string(pic_base_label);
1824 be_emit_cstring(":\n");
1825 be_emit_write_line();
1827 be_emit_cstring("\tpopl ");
1828 ia32_emit_dest_register(node, 0);
1830 be_emit_write_line();
1833 static void emit_be_Return(const ir_node *node)
1836 be_emit_cstring("\tret");
1838 pop = be_Return_get_pop(node);
1839 if (pop > 0 || be_Return_get_emit_pop(node)) {
1840 be_emit_irprintf(" $%d", pop);
1842 be_emit_finish_line_gas(node);
1845 static void emit_Nothing(const ir_node *node)
1851 /***********************************************************************************
1854 * _ __ ___ __ _ _ _ __ | |_ _ __ __ _ _ __ ___ _____ _____ _ __| | __
1855 * | '_ ` _ \ / _` | | '_ \ | _| '__/ _` | '_ ` _ \ / _ \ \ /\ / / _ \| '__| |/ /
1856 * | | | | | | (_| | | | | | | | | | | (_| | | | | | | __/\ V V / (_) | | | <
1857 * |_| |_| |_|\__,_|_|_| |_| |_| |_| \__,_|_| |_| |_|\___| \_/\_/ \___/|_| |_|\_\
1859 ***********************************************************************************/
1862 * Enters the emitter functions for handled nodes into the generic
1863 * pointer of an opcode.
1865 static void ia32_register_emitters(void)
1867 #define IA32_EMIT2(a,b) op_ia32_##a->ops.generic = (op_func)emit_ia32_##b
1868 #define IA32_EMIT(a) IA32_EMIT2(a,a)
1869 #define EMIT(a) op_##a->ops.generic = (op_func)emit_##a
1870 #define IGN(a) op_##a->ops.generic = (op_func)emit_Nothing
1871 #define BE_EMIT(a) op_be_##a->ops.generic = (op_func)emit_be_##a
1872 #define BE_IGN(a) op_be_##a->ops.generic = (op_func)emit_Nothing
1874 /* first clear the generic function pointer for all ops */
1875 clear_irp_opcodes_generic_func();
1877 /* register all emitter functions defined in spec */
1878 ia32_register_spec_emitters();
1880 /* other ia32 emitter functions */
1884 IA32_EMIT(SwitchJmp);
1887 IA32_EMIT(Conv_I2FP);
1888 IA32_EMIT(Conv_FP2I);
1889 IA32_EMIT(Conv_FP2FP);
1890 IA32_EMIT(Conv_I2I);
1891 IA32_EMIT2(Conv_I2I8Bit, Conv_I2I);
1894 IA32_EMIT(Minus64Bit);
1898 /* benode emitter */
1923 typedef void (*emit_func_ptr) (const ir_node *);
1926 * Emits code for a node.
1928 static void ia32_emit_node(ir_node *node)
1930 ir_op *op = get_irn_op(node);
1932 DBG((dbg, LEVEL_1, "emitting code for %+F\n", node));
1934 if (is_ia32_irn(node)) {
1935 if (get_ia32_exc_label(node)) {
1936 /* emit the exception label of this instruction */
1937 ia32_assign_exc_label(node);
1939 if (mark_spill_reload) {
1940 if (is_ia32_is_spill(node)) {
1941 be_emit_cstring("\txchg %ebx, %ebx /* spill mark */\n");
1942 be_emit_write_line();
1944 if (is_ia32_is_reload(node)) {
1945 be_emit_cstring("\txchg %edx, %edx /* reload mark */\n");
1946 be_emit_write_line();
1948 if (is_ia32_is_remat(node)) {
1949 be_emit_cstring("\txchg %ecx, %ecx /* remat mark */\n");
1950 be_emit_write_line();
1954 if (op->ops.generic) {
1955 emit_func_ptr func = (emit_func_ptr) op->ops.generic;
1957 be_dbg_set_dbg_info(get_irn_dbg_info(node));
1962 ir_fprintf(stderr, "Error: No emit handler for node %+F (%+G, graph %+F)\n", node, node, current_ir_graph);
1968 * Emits gas alignment directives
1970 static void ia32_emit_alignment(unsigned align, unsigned skip)
1972 be_emit_cstring("\t.p2align ");
1973 be_emit_irprintf("%u,,%u\n", align, skip);
1974 be_emit_write_line();
1978 * Emits gas alignment directives for Labels depended on cpu architecture.
1980 static void ia32_emit_align_label(void)
1982 unsigned align = ia32_cg_config.label_alignment;
1983 unsigned maximum_skip = ia32_cg_config.label_alignment_max_skip;
1984 ia32_emit_alignment(align, maximum_skip);
1988 * Test whether a block should be aligned.
1989 * For cpus in the P4/Athlon class it is useful to align jump labels to
1990 * 16 bytes. However we should only do that if the alignment nops before the
1991 * label aren't executed more often than we have jumps to the label.
1993 static int should_align_block(const ir_node *block)
1995 static const double DELTA = .0001;
1996 ir_exec_freq *exec_freq = cg->birg->exec_freq;
1997 ir_node *prev = get_prev_block_sched(block);
1999 double prev_freq = 0; /**< execfreq of the fallthrough block */
2000 double jmp_freq = 0; /**< execfreq of all non-fallthrough blocks */
2003 if (exec_freq == NULL)
2005 if (ia32_cg_config.label_alignment_factor <= 0)
2008 block_freq = get_block_execfreq(exec_freq, block);
2009 if (block_freq < DELTA)
2012 n_cfgpreds = get_Block_n_cfgpreds(block);
2013 for(i = 0; i < n_cfgpreds; ++i) {
2014 const ir_node *pred = get_Block_cfgpred_block(block, i);
2015 double pred_freq = get_block_execfreq(exec_freq, pred);
2018 prev_freq += pred_freq;
2020 jmp_freq += pred_freq;
2024 if (prev_freq < DELTA && !(jmp_freq < DELTA))
2027 jmp_freq /= prev_freq;
2029 return jmp_freq > ia32_cg_config.label_alignment_factor;
2033 * Emit the block header for a block.
2035 * @param block the block
2036 * @param prev_block the previous block
2038 static void ia32_emit_block_header(ir_node *block)
2040 ir_graph *irg = current_ir_graph;
2041 int need_label = block_needs_label(block);
2043 ir_exec_freq *exec_freq = cg->birg->exec_freq;
2045 if (block == get_irg_end_block(irg) || block == get_irg_start_block(irg))
2048 if (ia32_cg_config.label_alignment > 0) {
2049 /* align the current block if:
2050 * a) if should be aligned due to its execution frequency
2051 * b) there is no fall-through here
2053 if (should_align_block(block)) {
2054 ia32_emit_align_label();
2056 /* if the predecessor block has no fall-through,
2057 we can always align the label. */
2059 int has_fallthrough = 0;
2061 for (i = get_Block_n_cfgpreds(block) - 1; i >= 0; --i) {
2062 ir_node *cfg_pred = get_Block_cfgpred(block, i);
2063 if (can_be_fallthrough(cfg_pred)) {
2064 has_fallthrough = 1;
2069 if (!has_fallthrough)
2070 ia32_emit_align_label();
2074 if (need_label || has_Block_label(block)) {
2075 ia32_emit_block_name(block);
2078 be_emit_pad_comment();
2079 be_emit_cstring(" /* ");
2081 be_emit_cstring("\t/* ");
2082 ia32_emit_block_name(block);
2083 be_emit_cstring(": ");
2086 be_emit_cstring("preds:");
2088 /* emit list of pred blocks in comment */
2089 arity = get_irn_arity(block);
2090 for (i = 0; i < arity; ++i) {
2091 ir_node *predblock = get_Block_cfgpred_block(block, i);
2092 be_emit_irprintf(" %d", get_irn_node_nr(predblock));
2094 if (exec_freq != NULL) {
2095 be_emit_irprintf(" freq: %f",
2096 get_block_execfreq(exec_freq, block));
2098 be_emit_cstring(" */\n");
2099 be_emit_write_line();
2103 * Walks over the nodes in a block connected by scheduling edges
2104 * and emits code for each node.
2106 static void ia32_gen_block(ir_node *block)
2110 ia32_emit_block_header(block);
2112 /* emit the contents of the block */
2113 be_dbg_set_dbg_info(get_irn_dbg_info(block));
2114 sched_foreach(block, node) {
2115 ia32_emit_node(node);
2119 typedef struct exc_entry {
2120 ir_node *exc_instr; /** The instruction that can issue an exception. */
2121 ir_node *block; /** The block to call then. */
2126 * Sets labels for control flow nodes (jump target).
2127 * Links control predecessors to there destination blocks.
2129 static void ia32_gen_labels(ir_node *block, void *data)
2131 exc_entry **exc_list = data;
2135 for (n = get_Block_n_cfgpreds(block) - 1; n >= 0; --n) {
2136 pred = get_Block_cfgpred(block, n);
2137 set_irn_link(pred, block);
2139 pred = skip_Proj(pred);
2140 if (is_ia32_irn(pred) && get_ia32_exc_label(pred)) {
2145 ARR_APP1(exc_entry, *exc_list, e);
2146 set_irn_link(pred, block);
2152 * Assign and emit an exception label if the current instruction can fail.
2154 void ia32_assign_exc_label(ir_node *node)
2156 if (get_ia32_exc_label(node)) {
2157 /* assign a new ID to the instruction */
2158 set_ia32_exc_label_id(node, ++exc_label_id);
2160 ia32_emit_exc_label(node);
2162 be_emit_pad_comment();
2163 be_emit_cstring("/* exception to Block ");
2164 ia32_emit_cfop_target(node);
2165 be_emit_cstring(" */\n");
2166 be_emit_write_line();
2171 * Compare two exception_entries.
2173 static int cmp_exc_entry(const void *a, const void *b)
2175 const exc_entry *ea = a;
2176 const exc_entry *eb = b;
2178 if (get_ia32_exc_label_id(ea->exc_instr) < get_ia32_exc_label_id(eb->exc_instr))
2184 * Main driver. Emits the code for one routine.
2186 void ia32_gen_routine(ia32_code_gen_t *ia32_cg, ir_graph *irg)
2188 ir_entity *entity = get_irg_entity(irg);
2189 exc_entry *exc_list = NEW_ARR_F(exc_entry, 0);
2193 isa = (const ia32_isa_t*) cg->arch_env;
2194 arch_env = cg->arch_env;
2195 do_pic = cg->birg->main_env->options->pic;
2197 ia32_register_emitters();
2199 get_unique_label(pic_base_label, sizeof(pic_base_label), ".PIC_BASE");
2201 be_dbg_method_begin(entity, be_abi_get_stack_layout(cg->birg->abi));
2202 be_gas_emit_function_prolog(entity, ia32_cg_config.function_alignment);
2204 /* we use links to point to target blocks */
2205 ir_reserve_resources(irg, IR_RESOURCE_IRN_LINK);
2206 irg_block_walk_graph(irg, ia32_gen_labels, NULL, &exc_list);
2208 /* initialize next block links */
2209 n = ARR_LEN(cg->blk_sched);
2210 for (i = 0; i < n; ++i) {
2211 ir_node *block = cg->blk_sched[i];
2212 ir_node *prev = i > 0 ? cg->blk_sched[i-1] : NULL;
2214 set_irn_link(block, prev);
2217 for (i = 0; i < n; ++i) {
2218 ir_node *block = cg->blk_sched[i];
2220 ia32_gen_block(block);
2223 be_gas_emit_function_epilog(entity);
2224 be_dbg_method_end();
2226 be_emit_write_line();
2228 ir_free_resources(irg, IR_RESOURCE_IRN_LINK);
2230 /* Sort the exception table using the exception label id's.
2231 Those are ascending with ascending addresses. */
2232 qsort(exc_list, ARR_LEN(exc_list), sizeof(exc_list[0]), cmp_exc_entry);
2236 for (i = 0; i < ARR_LEN(exc_list); ++i) {
2237 be_emit_cstring("\t.long ");
2238 ia32_emit_exc_label(exc_list[i].exc_instr);
2240 be_emit_cstring("\t.long ");
2241 ia32_emit_block_name(exc_list[i].block);
2245 DEL_ARR_F(exc_list);
2248 static const lc_opt_table_entry_t ia32_emitter_options[] = {
2249 LC_OPT_ENT_BOOL("mark_spill_reload", "mark spills and reloads with ud opcodes", &mark_spill_reload),
2253 void ia32_init_emitter(void)
2255 lc_opt_entry_t *be_grp;
2256 lc_opt_entry_t *ia32_grp;
2258 be_grp = lc_opt_get_grp(firm_opt_get_root(), "be");
2259 ia32_grp = lc_opt_get_grp(be_grp, "ia32");
2261 lc_opt_add_table(ia32_grp, ia32_emitter_options);
2263 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.emitter");