2 * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This file implements the ia32 node emitter.
23 * @author Christian Wuerdig, Matthias Braun
26 * Summary table for x86 floatingpoint compares:
33 * pnc_Leg => NP (ordered)
55 #include "iredges_t.h"
59 #include "raw_bitset.h"
63 #include "../besched.h"
64 #include "../benode.h"
66 #include "../be_dbgout.h"
67 #include "../beemitter.h"
68 #include "../begnuas.h"
70 #include "../be_dbgout.h"
72 #include "ia32_emitter.h"
73 #include "ia32_common_transform.h"
74 #include "gen_ia32_emitter.h"
75 #include "gen_ia32_regalloc_if.h"
76 #include "ia32_nodes_attr.h"
77 #include "ia32_new_nodes.h"
78 #include "ia32_map_regs.h"
79 #include "ia32_architecture.h"
80 #include "bearch_ia32_t.h"
82 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
84 #define SNPRINTF_BUF_LEN 128
86 static const ia32_isa_t *isa;
87 static ia32_code_gen_t *cg;
88 static char pic_base_label[128];
89 static ir_label_t exc_label_id;
90 static int mark_spill_reload = 0;
93 /** Return the next block in Block schedule */
94 static ir_node *get_prev_block_sched(const ir_node *block)
96 return get_irn_link(block);
99 /** Checks if the current block is a fall-through target. */
100 static int is_fallthrough(const ir_node *cfgpred)
104 if (!is_Proj(cfgpred))
106 pred = get_Proj_pred(cfgpred);
107 if (is_ia32_SwitchJmp(pred))
114 * returns non-zero if the given block needs a label
115 * because of being a jump-target (and not a fall-through)
117 static int block_needs_label(const ir_node *block)
120 int n_cfgpreds = get_Block_n_cfgpreds(block);
122 if (has_Block_entity(block))
125 if (n_cfgpreds == 0) {
127 } else if (n_cfgpreds == 1) {
128 ir_node *cfgpred = get_Block_cfgpred(block, 0);
129 ir_node *cfgpred_block = get_nodes_block(cfgpred);
131 if (get_prev_block_sched(block) == cfgpred_block
132 && is_fallthrough(cfgpred)) {
141 * Returns the register at in position pos.
143 static const arch_register_t *get_in_reg(const ir_node *irn, int pos)
146 const arch_register_t *reg = NULL;
148 assert(get_irn_arity(irn) > pos && "Invalid IN position");
150 /* The out register of the operator at position pos is the
151 in register we need. */
152 op = get_irn_n(irn, pos);
154 reg = arch_get_irn_register(op);
156 assert(reg && "no in register found");
158 if (reg == &ia32_gp_regs[REG_GP_NOREG])
159 panic("trying to emit noreg for %+F input %d", irn, pos);
165 * Returns the register at out position pos.
167 static const arch_register_t *get_out_reg(const ir_node *irn, int pos)
170 const arch_register_t *reg = NULL;
172 /* 1st case: irn is not of mode_T, so it has only */
173 /* one OUT register -> good */
174 /* 2nd case: irn is of mode_T -> collect all Projs and ask the */
175 /* Proj with the corresponding projnum for the register */
177 if (get_irn_mode(irn) != mode_T) {
179 reg = arch_get_irn_register(irn);
180 } else if (is_ia32_irn(irn)) {
181 reg = arch_irn_get_register(irn, pos);
183 const ir_edge_t *edge;
185 foreach_out_edge(irn, edge) {
186 proj = get_edge_src_irn(edge);
187 assert(is_Proj(proj) && "non-Proj from mode_T node");
188 if (get_Proj_proj(proj) == pos) {
189 reg = arch_get_irn_register(proj);
195 assert(reg && "no out register found");
200 * Add a number to a prefix. This number will not be used a second time.
202 static char *get_unique_label(char *buf, size_t buflen, const char *prefix)
204 static unsigned long id = 0;
205 snprintf(buf, buflen, "%s%s%lu", be_gas_get_private_prefix(), prefix, ++id);
209 /*************************************************************
211 * (_) | | / _| | | | |
212 * _ __ _ __ _ _ __ | |_| |_ | |__ ___| |_ __ ___ _ __
213 * | '_ \| '__| | '_ \| __| _| | '_ \ / _ \ | '_ \ / _ \ '__|
214 * | |_) | | | | | | | |_| | | | | | __/ | |_) | __/ |
215 * | .__/|_| |_|_| |_|\__|_| |_| |_|\___|_| .__/ \___|_|
218 *************************************************************/
221 * Emit the name of the 8bit low register
223 static void emit_8bit_register(const arch_register_t *reg)
225 const char *reg_name = arch_register_get_name(reg);
228 be_emit_char(reg_name[1]);
233 * Emit the name of the 8bit high register
235 static void emit_8bit_register_high(const arch_register_t *reg)
237 const char *reg_name = arch_register_get_name(reg);
240 be_emit_char(reg_name[1]);
244 static void emit_16bit_register(const arch_register_t *reg)
246 const char *reg_name = ia32_get_mapped_reg_name(isa->regs_16bit, reg);
249 be_emit_string(reg_name);
253 * emit a register, possible shortened by a mode
255 * @param reg the register
256 * @param mode the mode of the register or NULL for full register
258 static void emit_register(const arch_register_t *reg, const ir_mode *mode)
260 const char *reg_name;
263 int size = get_mode_size_bits(mode);
265 case 8: emit_8bit_register(reg); return;
266 case 16: emit_16bit_register(reg); return;
268 assert(mode_is_float(mode) || size == 32);
271 reg_name = arch_register_get_name(reg);
274 be_emit_string(reg_name);
277 void ia32_emit_source_register(const ir_node *node, int pos)
279 const arch_register_t *reg = get_in_reg(node, pos);
281 emit_register(reg, NULL);
284 static void ia32_emit_entity(ir_entity *entity, int no_pic_adjust)
286 be_gas_emit_entity(entity);
288 if (get_entity_owner(entity) == get_tls_type()) {
289 if (get_entity_visibility(entity) == ir_visibility_external) {
290 be_emit_cstring("@INDNTPOFF");
292 be_emit_cstring("@NTPOFF");
296 if (do_pic && !no_pic_adjust) {
298 be_emit_string(pic_base_label);
302 static void emit_ia32_Immediate_no_prefix(const ir_node *node)
304 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(node);
306 if (attr->symconst != NULL) {
309 ia32_emit_entity(attr->symconst, attr->no_pic_adjust);
311 if (attr->symconst == NULL || attr->offset != 0) {
312 if (attr->symconst != NULL) {
313 be_emit_irprintf("%+d", attr->offset);
315 be_emit_irprintf("0x%X", attr->offset);
320 static void emit_ia32_Immediate(const ir_node *node)
323 emit_ia32_Immediate_no_prefix(node);
326 void ia32_emit_8bit_source_register_or_immediate(const ir_node *node, int pos)
328 const arch_register_t *reg;
329 const ir_node *in = get_irn_n(node, pos);
330 if (is_ia32_Immediate(in)) {
331 emit_ia32_Immediate(in);
335 reg = get_in_reg(node, pos);
336 emit_8bit_register(reg);
339 void ia32_emit_8bit_high_source_register(const ir_node *node, int pos)
341 const arch_register_t *reg = get_in_reg(node, pos);
342 emit_8bit_register_high(reg);
345 void ia32_emit_16bit_source_register_or_immediate(const ir_node *node, int pos)
347 const arch_register_t *reg;
348 const ir_node *in = get_irn_n(node, pos);
349 if (is_ia32_Immediate(in)) {
350 emit_ia32_Immediate(in);
354 reg = get_in_reg(node, pos);
355 emit_16bit_register(reg);
358 void ia32_emit_dest_register(const ir_node *node, int pos)
360 const arch_register_t *reg = get_out_reg(node, pos);
362 emit_register(reg, NULL);
365 void ia32_emit_dest_register_size(const ir_node *node, int pos)
367 const arch_register_t *reg = get_out_reg(node, pos);
369 emit_register(reg, get_ia32_ls_mode(node));
372 void ia32_emit_8bit_dest_register(const ir_node *node, int pos)
374 const arch_register_t *reg = get_out_reg(node, pos);
376 emit_register(reg, mode_Bu);
379 void ia32_emit_x87_register(const ir_node *node, int pos)
381 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
385 be_emit_string(attr->x87[pos]->name);
388 static void ia32_emit_mode_suffix_mode(const ir_mode *mode)
390 assert(mode_is_int(mode) || mode_is_reference(mode));
391 switch (get_mode_size_bits(mode)) {
392 case 8: be_emit_char('b'); return;
393 case 16: be_emit_char('w'); return;
394 case 32: be_emit_char('l'); return;
395 /* gas docu says q is the suffix but gcc, objdump and icc use ll
397 case 64: be_emit_cstring("ll"); return;
399 panic("Can't output mode_suffix for %+F", mode);
402 void ia32_emit_mode_suffix(const ir_node *node)
404 ir_mode *mode = get_ia32_ls_mode(node);
408 ia32_emit_mode_suffix_mode(mode);
411 void ia32_emit_x87_mode_suffix(const ir_node *node)
415 /* we only need to emit the mode on address mode */
416 if (get_ia32_op_type(node) == ia32_Normal)
419 mode = get_ia32_ls_mode(node);
420 assert(mode != NULL);
422 if (mode_is_float(mode)) {
423 switch (get_mode_size_bits(mode)) {
424 case 32: be_emit_char('s'); return;
425 case 64: be_emit_char('l'); return;
426 /* long doubles have different sizes due to alignment on different
430 case 128: be_emit_char('t'); return;
433 assert(mode_is_int(mode) || mode_is_reference(mode));
434 switch (get_mode_size_bits(mode)) {
435 case 16: be_emit_char('s'); return;
436 case 32: be_emit_char('l'); return;
437 /* gas docu says q is the suffix but gcc, objdump and icc use ll
439 case 64: be_emit_cstring("ll"); return;
442 panic("Can't output mode_suffix for %+F", mode);
445 static char get_xmm_mode_suffix(ir_mode *mode)
447 assert(mode_is_float(mode));
448 switch (get_mode_size_bits(mode)) {
451 default: panic("Invalid XMM mode");
455 void ia32_emit_xmm_mode_suffix(const ir_node *node)
457 ir_mode *mode = get_ia32_ls_mode(node);
458 assert(mode != NULL);
460 be_emit_char(get_xmm_mode_suffix(mode));
463 void ia32_emit_xmm_mode_suffix_s(const ir_node *node)
465 ir_mode *mode = get_ia32_ls_mode(node);
466 assert(mode != NULL);
467 be_emit_char(get_xmm_mode_suffix(mode));
470 void ia32_emit_extend_suffix(const ir_node *node)
472 ir_mode *mode = get_ia32_ls_mode(node);
473 if (get_mode_size_bits(mode) == 32)
475 be_emit_char(mode_is_signed(mode) ? 's' : 'z');
476 ia32_emit_mode_suffix_mode(mode);
479 void ia32_emit_source_register_or_immediate(const ir_node *node, int pos)
481 ir_node *in = get_irn_n(node, pos);
482 if (is_ia32_Immediate(in)) {
483 emit_ia32_Immediate(in);
485 const ir_mode *mode = get_ia32_ls_mode(node);
486 const arch_register_t *reg = get_in_reg(node, pos);
487 emit_register(reg, mode);
492 * Returns the target block for a control flow node.
494 static ir_node *get_cfop_target_block(const ir_node *irn)
496 assert(get_irn_mode(irn) == mode_X);
497 return get_irn_link(irn);
501 * Emits the target label for a control flow node.
503 static void ia32_emit_cfop_target(const ir_node *node)
505 ir_node *block = get_cfop_target_block(node);
506 be_gas_emit_block_name(block);
510 * positive conditions for signed compares
512 static const char *const cmp2condition_s[] = {
513 NULL, /* always false */
520 NULL /* always true */
524 * positive conditions for unsigned compares
526 static const char *const cmp2condition_u[] = {
527 NULL, /* always false */
534 NULL /* always true */
538 * Emit the suffix for a compare instruction.
540 static void ia32_emit_cmp_suffix(int pnc)
544 if (pnc == ia32_pn_Cmp_parity) {
549 if (pnc & ia32_pn_Cmp_float || pnc & ia32_pn_Cmp_unsigned) {
550 str = cmp2condition_u[pnc & 7];
552 str = cmp2condition_s[pnc & 7];
558 typedef enum ia32_emit_mod_t {
559 EMIT_RESPECT_LS = 1U << 0,
560 EMIT_ALTERNATE_AM = 1U << 1,
562 EMIT_HIGH_REG = 1U << 3,
563 EMIT_LOW_REG = 1U << 4
567 * Emits address mode.
569 void ia32_emit_am(const ir_node *node)
571 ir_entity *ent = get_ia32_am_sc(node);
572 int offs = get_ia32_am_offs_int(node);
573 ir_node *base = get_irn_n(node, n_ia32_base);
574 int has_base = !is_ia32_NoReg_GP(base);
575 ir_node *index = get_irn_n(node, n_ia32_index);
576 int has_index = !is_ia32_NoReg_GP(index);
578 /* just to be sure... */
579 assert(!is_ia32_use_frame(node) || get_ia32_frame_ent(node) != NULL);
583 const ia32_attr_t *attr = get_ia32_attr_const(node);
584 if (is_ia32_am_sc_sign(node))
586 ia32_emit_entity(ent, attr->data.am_sc_no_pic_adjust);
589 /* also handle special case if nothing is set */
590 if (offs != 0 || (ent == NULL && !has_base && !has_index)) {
592 be_emit_irprintf("%+d", offs);
594 be_emit_irprintf("%d", offs);
598 if (has_base || has_index) {
603 const arch_register_t *reg = get_in_reg(node, n_ia32_base);
604 emit_register(reg, NULL);
607 /* emit index + scale */
609 const arch_register_t *reg = get_in_reg(node, n_ia32_index);
612 emit_register(reg, NULL);
614 scale = get_ia32_am_scale(node);
616 be_emit_irprintf(",%d", 1 << scale);
624 * fmt parameter output
625 * ---- ---------------------- ---------------------------------------------
627 * %AM <node> address mode of the node
628 * %AR const arch_register_t* address mode of the node or register
629 * %ASx <node> address mode of the node or source register x
630 * %Dx <node> destination register x
631 * %I <node> immediate of the node
632 * %L <node> control flow target of the node
633 * %M <node> mode suffix of the node
634 * %P int condition code
635 * %R const arch_register_t* register
636 * %Sx <node> source register x
637 * %s const char* string
638 * %u unsigned int unsigned int
639 * %d signed int signed int
642 * # modifier for %ASx, %D, %R, and %S uses ls mode of node to alter register width
643 * * modifier does not prefix immediates with $, but AM with *
644 * l modifier for %lu and %ld
645 * > modifier to output high 8bit register (ah, bh)
646 * < modifier to output low 8bit register (al, bl)
648 static void ia32_emitf(const ir_node *node, const char *fmt, ...)
654 const char *start = fmt;
655 ia32_emit_mod_t mod = 0;
657 while (*fmt != '%' && *fmt != '\n' && *fmt != '\0')
660 be_emit_string_len(start, fmt - start);
664 be_emit_finish_line_gas(node);
677 case '*': mod |= EMIT_ALTERNATE_AM; break;
678 case '#': mod |= EMIT_RESPECT_LS; break;
679 case 'l': mod |= EMIT_LONG; break;
680 case '>': mod |= EMIT_HIGH_REG; break;
681 case '<': mod |= EMIT_LOW_REG; break;
698 if (mod & EMIT_ALTERNATE_AM)
704 const arch_register_t *reg = va_arg(ap, const arch_register_t*);
705 if (get_ia32_op_type(node) == ia32_AddrModeS) {
708 if (mod & EMIT_ALTERNATE_AM)
710 emit_register(reg, NULL);
716 if (get_ia32_op_type(node) == ia32_AddrModeS) {
720 assert(get_ia32_op_type(node) == ia32_Normal);
725 default: goto unknown;
732 const arch_register_t *reg;
734 if (*fmt < '0' || '9' <= *fmt)
738 reg = get_out_reg(node, pos);
739 emit_register(reg, mod & EMIT_RESPECT_LS ? get_ia32_ls_mode(node) : NULL);
744 if (!(mod & EMIT_ALTERNATE_AM))
746 emit_ia32_Immediate_no_prefix(node);
750 ia32_emit_cfop_target(node);
754 ia32_emit_mode_suffix_mode(get_ia32_ls_mode(node));
759 int pnc = va_arg(ap, int);
760 ia32_emit_cmp_suffix(pnc);
765 const arch_register_t *reg = va_arg(ap, const arch_register_t*);
766 if (mod & EMIT_HIGH_REG) {
767 emit_8bit_register_high(reg);
768 } else if (mod & EMIT_LOW_REG) {
769 emit_8bit_register(reg);
771 emit_register(reg, mod & EMIT_RESPECT_LS ? get_ia32_ls_mode(node) : NULL);
781 if (*fmt < '0' || '9' <= *fmt)
785 in = get_irn_n(node, pos);
786 if (is_ia32_Immediate(in)) {
787 if (!(mod & EMIT_ALTERNATE_AM))
789 emit_ia32_Immediate_no_prefix(in);
791 const arch_register_t *reg;
793 if (mod & EMIT_ALTERNATE_AM)
795 reg = get_in_reg(node, pos);
796 emit_register(reg, mod & EMIT_RESPECT_LS ? get_ia32_ls_mode(node) : NULL);
802 const char *str = va_arg(ap, const char*);
808 if (mod & EMIT_LONG) {
809 unsigned long num = va_arg(ap, unsigned long);
810 be_emit_irprintf("%lu", num);
812 unsigned num = va_arg(ap, unsigned);
813 be_emit_irprintf("%u", num);
818 if (mod & EMIT_LONG) {
819 long num = va_arg(ap, long);
820 be_emit_irprintf("%ld", num);
822 int num = va_arg(ap, int);
823 be_emit_irprintf("%d", num);
829 panic("unknown format conversion in ia32_emitf()");
837 * Emits registers and/or address mode of a binary operation.
839 void ia32_emit_binop(const ir_node *node)
841 if (is_ia32_Immediate(get_irn_n(node, n_ia32_binary_right))) {
842 ia32_emitf(node, "%#S4, %#AS3");
844 ia32_emitf(node, "%#AS4, %#S3");
849 * Emits registers and/or address mode of a binary operation.
851 void ia32_emit_x87_binop(const ir_node *node)
853 switch (get_ia32_op_type(node)) {
856 const ia32_x87_attr_t *x87_attr = get_ia32_x87_attr_const(node);
857 const arch_register_t *in1 = x87_attr->x87[0];
858 const arch_register_t *in = x87_attr->x87[1];
859 const arch_register_t *out = x87_attr->x87[2];
863 } else if (out == in) {
868 be_emit_string(arch_register_get_name(in));
869 be_emit_cstring(", %");
870 be_emit_string(arch_register_get_name(out));
878 assert(0 && "unsupported op type");
883 * Emits registers and/or address mode of a unary operation.
885 void ia32_emit_unop(const ir_node *node, int pos)
889 ia32_emitf(node, fmt);
892 static void emit_ia32_IMul(const ir_node *node)
894 ir_node *left = get_irn_n(node, n_ia32_IMul_left);
895 const arch_register_t *out_reg = get_out_reg(node, pn_ia32_IMul_res);
897 /* do we need the 3-address form? */
898 if (is_ia32_NoReg_GP(left) ||
899 get_in_reg(node, n_ia32_IMul_left) != out_reg) {
900 ia32_emitf(node, "\timul%M %#S4, %#AS3, %#D0\n");
902 ia32_emitf(node, "\timul%M %#AS4, %#S3\n");
907 * walks up a tree of copies/perms/spills/reloads to find the original value
908 * that is moved around
910 static ir_node *find_original_value(ir_node *node)
912 if (irn_visited(node))
915 mark_irn_visited(node);
916 if (be_is_Copy(node)) {
917 return find_original_value(be_get_Copy_op(node));
918 } else if (be_is_CopyKeep(node)) {
919 return find_original_value(be_get_CopyKeep_op(node));
920 } else if (is_Proj(node)) {
921 ir_node *pred = get_Proj_pred(node);
922 if (be_is_Perm(pred)) {
923 return find_original_value(get_irn_n(pred, get_Proj_proj(node)));
924 } else if (be_is_MemPerm(pred)) {
925 return find_original_value(get_irn_n(pred, get_Proj_proj(node) + 1));
926 } else if (is_ia32_Load(pred)) {
927 return find_original_value(get_irn_n(pred, n_ia32_Load_mem));
931 } else if (is_ia32_Store(node)) {
932 return find_original_value(get_irn_n(node, n_ia32_Store_val));
933 } else if (is_Phi(node)) {
935 arity = get_irn_arity(node);
936 for (i = 0; i < arity; ++i) {
937 ir_node *in = get_irn_n(node, i);
938 ir_node *res = find_original_value(in);
949 static int determine_final_pnc(const ir_node *node, int flags_pos, int pnc)
951 ir_node *flags = get_irn_n(node, flags_pos);
952 const ia32_attr_t *flags_attr;
953 flags = skip_Proj(flags);
955 if (is_ia32_Sahf(flags)) {
956 ir_node *cmp = get_irn_n(flags, n_ia32_Sahf_val);
957 if (!(is_ia32_FucomFnstsw(cmp) || is_ia32_FucompFnstsw(cmp)
958 || is_ia32_FucomppFnstsw(cmp) || is_ia32_FtstFnstsw(cmp))) {
959 inc_irg_visited(current_ir_graph);
960 cmp = find_original_value(cmp);
962 assert(is_ia32_FucomFnstsw(cmp) || is_ia32_FucompFnstsw(cmp)
963 || is_ia32_FucomppFnstsw(cmp) || is_ia32_FtstFnstsw(cmp));
966 flags_attr = get_ia32_attr_const(cmp);
967 if (flags_attr->data.ins_permuted)
968 pnc = get_mirrored_pnc(pnc);
969 pnc |= ia32_pn_Cmp_float;
970 } else if (is_ia32_Ucomi(flags) || is_ia32_Fucomi(flags)
971 || is_ia32_Fucompi(flags)) {
972 flags_attr = get_ia32_attr_const(flags);
974 if (flags_attr->data.ins_permuted)
975 pnc = get_mirrored_pnc(pnc);
976 pnc |= ia32_pn_Cmp_float;
978 flags_attr = get_ia32_attr_const(flags);
980 if (flags_attr->data.ins_permuted)
981 pnc = get_mirrored_pnc(pnc);
982 if (flags_attr->data.cmp_unsigned)
983 pnc |= ia32_pn_Cmp_unsigned;
989 static pn_Cmp ia32_get_negated_pnc(pn_Cmp pnc)
991 ir_mode *mode = pnc & ia32_pn_Cmp_float ? mode_F : mode_Iu;
992 return get_negated_pnc(pnc, mode);
995 void ia32_emit_cmp_suffix_node(const ir_node *node, int flags_pos)
997 pn_Cmp pnc = get_ia32_condcode(node);
998 pnc = determine_final_pnc(node, flags_pos, pnc);
1000 ia32_emit_cmp_suffix(pnc);
1004 * Emits an exception label for a given node.
1006 static void ia32_emit_exc_label(const ir_node *node)
1008 be_emit_string(be_gas_insn_label_prefix());
1009 be_emit_irprintf("%lu", get_ia32_exc_label_id(node));
1013 * Returns the Proj with projection number proj and NOT mode_M
1015 static ir_node *get_proj(const ir_node *node, long proj)
1017 const ir_edge_t *edge;
1020 assert(get_irn_mode(node) == mode_T && "expected mode_T node");
1022 foreach_out_edge(node, edge) {
1023 src = get_edge_src_irn(edge);
1025 assert(is_Proj(src) && "Proj expected");
1026 if (get_irn_mode(src) == mode_M)
1029 if (get_Proj_proj(src) == proj)
1035 static int can_be_fallthrough(const ir_node *node)
1037 ir_node *target_block = get_cfop_target_block(node);
1038 ir_node *block = get_nodes_block(node);
1039 return get_prev_block_sched(target_block) == block;
1043 * Emits the jump sequence for a conditional jump (cmp + jmp_true + jmp_false)
1045 static void emit_ia32_Jcc(const ir_node *node)
1047 int need_parity_label = 0;
1048 const ir_node *proj_true;
1049 const ir_node *proj_false;
1050 pn_Cmp pnc = get_ia32_condcode(node);
1052 pnc = determine_final_pnc(node, 0, pnc);
1054 /* get both Projs */
1055 proj_true = get_proj(node, pn_ia32_Jcc_true);
1056 assert(proj_true && "Jcc without true Proj");
1058 proj_false = get_proj(node, pn_ia32_Jcc_false);
1059 assert(proj_false && "Jcc without false Proj");
1061 if (can_be_fallthrough(proj_true)) {
1062 /* exchange both proj's so the second one can be omitted */
1063 const ir_node *t = proj_true;
1065 proj_true = proj_false;
1067 pnc = ia32_get_negated_pnc(pnc);
1070 if (pnc & ia32_pn_Cmp_float) {
1071 /* Some floating point comparisons require a test of the parity flag,
1072 * which indicates that the result is unordered */
1073 switch (pnc & 0x0f) {
1075 ia32_emitf(proj_true, "\tjp %L\n");
1080 ia32_emitf(proj_true, "\tjnp %L\n");
1086 /* we need a local label if the false proj is a fallthrough
1087 * as the falseblock might have no label emitted then */
1088 if (can_be_fallthrough(proj_false)) {
1089 need_parity_label = 1;
1090 ia32_emitf(proj_false, "\tjp 1f\n");
1092 ia32_emitf(proj_false, "\tjp %L\n");
1099 ia32_emitf(proj_true, "\tjp %L\n");
1107 ia32_emitf(proj_true, "\tj%P %L\n", pnc);
1110 if (need_parity_label) {
1111 ia32_emitf(NULL, "1:\n");
1114 /* the second Proj might be a fallthrough */
1115 if (can_be_fallthrough(proj_false)) {
1116 ia32_emitf(proj_false, "\t/* fallthrough to %L */\n");
1118 ia32_emitf(proj_false, "\tjmp %L\n");
1123 * Emits an ia32 Setcc. This is mostly easy but some floating point compares
1126 static void emit_ia32_Setcc(const ir_node *node)
1128 const arch_register_t *dreg = get_out_reg(node, pn_ia32_Setcc_res);
1130 pn_Cmp pnc = get_ia32_condcode(node);
1131 pnc = determine_final_pnc(node, n_ia32_Setcc_eflags, pnc);
1132 if (pnc & ia32_pn_Cmp_float) {
1133 switch (pnc & 0x0f) {
1135 ia32_emitf(node, "\tsetp %#R\n", dreg);
1139 ia32_emitf(node, "\tsetnp %#R\n", dreg);
1145 ia32_emitf(node, "\tset%P %<R\n", pnc, dreg);
1146 ia32_emitf(node, "\tsetnp %>R\n", dreg);
1147 ia32_emitf(node, "\tandb %>R, %<R\n", dreg, dreg);
1153 ia32_emitf(node, "\tset%P %<R\n", pnc, dreg);
1154 ia32_emitf(node, "\tsetp %>R\n", dreg);
1155 ia32_emitf(node, "\torb %>R, %<R\n", dreg, dreg);
1162 ia32_emitf(node, "\tset%P %#R\n", pnc, dreg);
1165 static void emit_ia32_CMovcc(const ir_node *node)
1167 const ia32_attr_t *attr = get_ia32_attr_const(node);
1168 const arch_register_t *out = arch_irn_get_register(node, pn_ia32_res);
1169 pn_Cmp pnc = get_ia32_condcode(node);
1170 const arch_register_t *in_true;
1171 const arch_register_t *in_false;
1173 pnc = determine_final_pnc(node, n_ia32_CMovcc_eflags, pnc);
1174 /* although you can't set ins_permuted in the constructor it might still
1175 * be set by memory operand folding
1176 * Permuting inputs of a cmov means the condition is negated!
1178 if (attr->data.ins_permuted)
1179 pnc = ia32_get_negated_pnc(pnc);
1181 in_true = arch_get_irn_register(get_irn_n(node, n_ia32_CMovcc_val_true));
1182 in_false = arch_get_irn_register(get_irn_n(node, n_ia32_CMovcc_val_false));
1184 /* should be same constraint fullfilled? */
1185 if (out == in_false) {
1186 /* yes -> nothing to do */
1187 } else if (out == in_true) {
1188 const arch_register_t *tmp;
1190 assert(get_ia32_op_type(node) == ia32_Normal);
1192 pnc = ia32_get_negated_pnc(pnc);
1199 ia32_emitf(node, "\tmovl %R, %R\n", in_false, out);
1202 /* TODO: handling of Nans isn't correct yet */
1203 if (pnc & ia32_pn_Cmp_float) {
1204 switch (pnc & 0x0f) {
1213 panic("CMov with floatingpoint compare/parity not supported yet");
1217 ia32_emitf(node, "\tcmov%P %#AR, %#R\n", pnc, in_true, out);
1220 /*********************************************************
1223 * ___ _ __ ___ _| |_ _ _ _ _ __ ___ _ __ ___
1224 * / _ \ '_ ` _ \| | __| | | | | | '_ ` _ \| '_ \/ __|
1225 * | __/ | | | | | | |_ | | |_| | | | | | | |_) \__ \
1226 * \___|_| |_| |_|_|\__| | |\__,_|_| |_| |_| .__/|___/
1229 *********************************************************/
1231 /* jump table entry (target and corresponding number) */
1232 typedef struct _branch_t {
1237 /* jump table for switch generation */
1238 typedef struct _jmp_tbl_t {
1239 ir_node *defProj; /**< default target */
1240 long min_value; /**< smallest switch case */
1241 long max_value; /**< largest switch case */
1242 long num_branches; /**< number of jumps */
1243 char label[SNPRINTF_BUF_LEN]; /**< label of the jump table */
1244 branch_t *branches; /**< jump array */
1248 * Compare two variables of type branch_t. Used to sort all switch cases
1250 static int ia32_cmp_branch_t(const void *a, const void *b)
1252 branch_t *b1 = (branch_t *)a;
1253 branch_t *b2 = (branch_t *)b;
1255 if (b1->value <= b2->value)
1261 static void generate_jump_table(jmp_tbl_t *tbl, const ir_node *node)
1267 const ir_edge_t *edge;
1269 /* fill the table structure */
1270 get_unique_label(tbl->label, SNPRINTF_BUF_LEN, "TBL_");
1271 tbl->defProj = NULL;
1272 tbl->num_branches = get_irn_n_edges(node) - 1;
1273 tbl->branches = XMALLOCNZ(branch_t, tbl->num_branches);
1274 tbl->min_value = LONG_MAX;
1275 tbl->max_value = LONG_MIN;
1277 default_pn = get_ia32_condcode(node);
1279 /* go over all proj's and collect them */
1280 foreach_out_edge(node, edge) {
1281 proj = get_edge_src_irn(edge);
1282 assert(is_Proj(proj) && "Only proj allowed at SwitchJmp");
1284 pnc = get_Proj_proj(proj);
1286 /* check for default proj */
1287 if (pnc == default_pn) {
1288 assert(tbl->defProj == NULL && "found two default Projs at SwitchJmp");
1289 tbl->defProj = proj;
1291 tbl->min_value = pnc < tbl->min_value ? pnc : tbl->min_value;
1292 tbl->max_value = pnc > tbl->max_value ? pnc : tbl->max_value;
1294 /* create branch entry */
1295 tbl->branches[i].target = proj;
1296 tbl->branches[i].value = pnc;
1301 assert(i == tbl->num_branches);
1303 /* sort the branches by their number */
1304 qsort(tbl->branches, tbl->num_branches, sizeof(tbl->branches[0]), ia32_cmp_branch_t);
1308 * Emits code for a SwitchJmp (creates a jump table if
1309 * possible otherwise a cmp-jmp cascade). Port from
1312 static void emit_ia32_SwitchJmp(const ir_node *node)
1314 unsigned long interval;
1318 /* fill the table structure */
1319 generate_jump_table(&tbl, node);
1321 /* two-complement's magic make this work without overflow */
1322 interval = tbl.max_value - tbl.min_value;
1324 /* emit the table */
1325 ia32_emitf(node, "\tcmpl $%u, %S0\n", interval);
1326 ia32_emitf(tbl.defProj, "\tja %L\n");
1328 if (tbl.num_branches > 1) {
1330 ia32_emitf(node, "\tjmp *%s(,%S0,4)\n", tbl.label);
1332 be_gas_emit_switch_section(GAS_SECTION_RODATA);
1333 ia32_emitf(NULL, "\t.align 4\n");
1334 ia32_emitf(NULL, "%s:\n", tbl.label);
1336 last_value = tbl.branches[0].value;
1337 for (i = 0; i != tbl.num_branches; ++i) {
1338 while (last_value != tbl.branches[i].value) {
1339 ia32_emitf(tbl.defProj, ".long %L\n");
1342 ia32_emitf(tbl.branches[i].target, ".long %L\n");
1345 be_gas_emit_switch_section(GAS_SECTION_TEXT);
1347 /* one jump is enough */
1348 ia32_emitf(tbl.branches[0].target, "\tjmp %L\n");
1355 * Emits code for a unconditional jump.
1357 static void emit_ia32_Jmp(const ir_node *node)
1361 /* for now, the code works for scheduled and non-schedules blocks */
1362 block = get_nodes_block(node);
1364 /* we have a block schedule */
1365 if (can_be_fallthrough(node)) {
1366 ia32_emitf(node, "\t/* fallthrough to %L */\n");
1368 ia32_emitf(node, "\tjmp %L\n");
1373 * Emit an inline assembler operand.
1375 * @param node the ia32_ASM node
1376 * @param s points to the operand (a %c)
1378 * @return pointer to the first char in s NOT in the current operand
1380 static const char* emit_asm_operand(const ir_node *node, const char *s)
1382 const ia32_attr_t *ia32_attr = get_ia32_attr_const(node);
1383 const ia32_asm_attr_t *attr = CONST_CAST_IA32_ATTR(ia32_asm_attr_t,
1385 const arch_register_t *reg;
1386 const ia32_asm_reg_t *asm_regs = attr->register_map;
1387 const ia32_asm_reg_t *asm_reg;
1388 const char *reg_name;
1397 /* parse modifiers */
1400 ir_fprintf(stderr, "Warning: asm text (%+F) ends with %%\n", node);
1425 "Warning: asm text (%+F) contains unknown modifier '%c' for asm op\n",
1432 sscanf(s, "%d%n", &num, &p);
1434 ir_fprintf(stderr, "Warning: Couldn't parse assembler operand (%+F)\n",
1441 if (num < 0 || ARR_LEN(asm_regs) <= num) {
1443 "Error: Custom assembler references invalid input/output (%+F)\n",
1447 asm_reg = & asm_regs[num];
1448 assert(asm_reg->valid);
1451 if (asm_reg->use_input == 0) {
1452 reg = get_out_reg(node, asm_reg->inout_pos);
1454 ir_node *pred = get_irn_n(node, asm_reg->inout_pos);
1456 /* might be an immediate value */
1457 if (is_ia32_Immediate(pred)) {
1458 emit_ia32_Immediate(pred);
1461 reg = get_in_reg(node, asm_reg->inout_pos);
1465 "Warning: no register assigned for %d asm op (%+F)\n",
1470 if (asm_reg->memory) {
1475 if (modifier != 0) {
1479 reg_name = ia32_get_mapped_reg_name(isa->regs_8bit, reg);
1482 reg_name = ia32_get_mapped_reg_name(isa->regs_8bit_high, reg);
1485 reg_name = ia32_get_mapped_reg_name(isa->regs_16bit, reg);
1488 panic("Invalid asm op modifier");
1490 be_emit_string(reg_name);
1492 emit_register(reg, asm_reg->mode);
1495 if (asm_reg->memory) {
1503 * Emits code for an ASM pseudo op.
1505 static void emit_ia32_Asm(const ir_node *node)
1507 const void *gen_attr = get_irn_generic_attr_const(node);
1508 const ia32_asm_attr_t *attr
1509 = CONST_CAST_IA32_ATTR(ia32_asm_attr_t, gen_attr);
1510 ident *asm_text = attr->asm_text;
1511 const char *s = get_id_str(asm_text);
1513 ia32_emitf(node, "#APP\t\n");
1520 s = emit_asm_operand(node, s);
1526 ia32_emitf(NULL, "\n#NO_APP\n");
1529 /**********************************
1532 * | | ___ _ __ _ _| |_) |
1533 * | | / _ \| '_ \| | | | _ <
1534 * | |___| (_) | |_) | |_| | |_) |
1535 * \_____\___/| .__/ \__, |____/
1538 **********************************/
1541 * Emit movsb/w instructions to make mov count divideable by 4
1543 static void emit_CopyB_prolog(unsigned size)
1546 ia32_emitf(NULL, "\tmovsb\n");
1548 ia32_emitf(NULL, "\tmovsw\n");
1552 * Emit rep movsd instruction for memcopy.
1554 static void emit_ia32_CopyB(const ir_node *node)
1556 unsigned size = get_ia32_copyb_size(node);
1558 emit_CopyB_prolog(size);
1559 ia32_emitf(node, "\trep movsd\n");
1563 * Emits unrolled memcopy.
1565 static void emit_ia32_CopyB_i(const ir_node *node)
1567 unsigned size = get_ia32_copyb_size(node);
1569 emit_CopyB_prolog(size);
1573 ia32_emitf(NULL, "\tmovsd\n");
1579 /***************************
1583 * | | / _ \| '_ \ \ / /
1584 * | |___| (_) | | | \ V /
1585 * \_____\___/|_| |_|\_/
1587 ***************************/
1590 * Emit code for conversions (I, FP), (FP, I) and (FP, FP).
1592 static void emit_ia32_Conv_with_FP(const ir_node *node, const char* conv_f,
1595 ir_mode *ls_mode = get_ia32_ls_mode(node);
1596 int ls_bits = get_mode_size_bits(ls_mode);
1597 const char *conv = ls_bits == 32 ? conv_f : conv_d;
1599 ia32_emitf(node, "\tcvt%s %AS3, %D0\n", conv);
1602 static void emit_ia32_Conv_I2FP(const ir_node *node)
1604 emit_ia32_Conv_with_FP(node, "si2ss", "si2sd");
1607 static void emit_ia32_Conv_FP2I(const ir_node *node)
1609 emit_ia32_Conv_with_FP(node, "ss2si", "sd2si");
1612 static void emit_ia32_Conv_FP2FP(const ir_node *node)
1614 emit_ia32_Conv_with_FP(node, "sd2ss", "ss2sd");
1618 * Emits code for an Int conversion.
1620 static void emit_ia32_Conv_I2I(const ir_node *node)
1622 ir_mode *smaller_mode = get_ia32_ls_mode(node);
1623 int signed_mode = mode_is_signed(smaller_mode);
1624 const char *sign_suffix;
1626 assert(!mode_is_float(smaller_mode));
1628 sign_suffix = signed_mode ? "s" : "z";
1629 ia32_emitf(node, "\tmov%s%Ml %#AS3, %D0\n", sign_suffix);
1635 static void emit_ia32_Call(const ir_node *node)
1637 /* Special case: Call must not have its immediates prefixed by $, instead
1638 * address mode is prefixed by *. */
1639 ia32_emitf(node, "\tcall %*AS3\n");
1643 /*******************************************
1646 * | |__ ___ _ __ ___ __| | ___ ___
1647 * | '_ \ / _ \ '_ \ / _ \ / _` |/ _ \/ __|
1648 * | |_) | __/ | | | (_) | (_| | __/\__ \
1649 * |_.__/ \___|_| |_|\___/ \__,_|\___||___/
1651 *******************************************/
1654 * Emits code to increase stack pointer.
1656 static void emit_be_IncSP(const ir_node *node)
1658 int offs = be_get_IncSP_offset(node);
1664 ia32_emitf(node, "\tsubl $%u, %D0\n", offs);
1666 ia32_emitf(node, "\taddl $%u, %D0\n", -offs);
1671 * Emits code for Copy/CopyKeep.
1673 static void Copy_emitter(const ir_node *node, const ir_node *op)
1675 const arch_register_t *in = arch_get_irn_register(op);
1676 const arch_register_t *out = arch_get_irn_register(node);
1681 /* copies of vf nodes aren't real... */
1682 if (arch_register_get_class(in) == &ia32_reg_classes[CLASS_ia32_vfp])
1685 if (get_irn_mode(node) == mode_E) {
1686 ia32_emitf(node, "\tmovsd %R, %R\n", in, out);
1688 ia32_emitf(node, "\tmovl %R, %R\n", in, out);
1692 static void emit_be_Copy(const ir_node *node)
1694 Copy_emitter(node, be_get_Copy_op(node));
1697 static void emit_be_CopyKeep(const ir_node *node)
1699 Copy_emitter(node, be_get_CopyKeep_op(node));
1703 * Emits code for exchange.
1705 static void emit_be_Perm(const ir_node *node)
1707 const arch_register_t *in0, *in1;
1708 const arch_register_class_t *cls0, *cls1;
1710 in0 = arch_get_irn_register(get_irn_n(node, 0));
1711 in1 = arch_get_irn_register(get_irn_n(node, 1));
1713 cls0 = arch_register_get_class(in0);
1714 cls1 = arch_register_get_class(in1);
1716 assert(cls0 == cls1 && "Register class mismatch at Perm");
1718 if (cls0 == &ia32_reg_classes[CLASS_ia32_gp]) {
1719 ia32_emitf(node, "\txchg %R, %R\n", in1, in0);
1720 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_xmm]) {
1721 ia32_emitf(NULL, "\txorpd %R, %R\n", in1, in0);
1722 ia32_emitf(NULL, "\txorpd %R, %R\n", in0, in1);
1723 ia32_emitf(node, "\txorpd %R, %R\n", in1, in0);
1724 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_vfp]) {
1726 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_st]) {
1729 panic("unexpected register class in be_Perm (%+F)", node);
1734 * Emits code for Constant loading.
1736 static void emit_ia32_Const(const ir_node *node)
1738 ia32_emitf(node, "\tmovl %I, %D0\n");
1742 * Emits code to load the TLS base
1744 static void emit_ia32_LdTls(const ir_node *node)
1746 ia32_emitf(node, "\tmovl %%gs:0, %D0\n");
1749 /* helper function for emit_ia32_Minus64Bit */
1750 static void emit_mov(const ir_node* node, const arch_register_t *src, const arch_register_t *dst)
1752 ia32_emitf(node, "\tmovl %R, %R\n", src, dst);
1755 /* helper function for emit_ia32_Minus64Bit */
1756 static void emit_neg(const ir_node* node, const arch_register_t *reg)
1758 ia32_emitf(node, "\tnegl %R\n", reg);
1761 /* helper function for emit_ia32_Minus64Bit */
1762 static void emit_sbb0(const ir_node* node, const arch_register_t *reg)
1764 ia32_emitf(node, "\tsbbl $0, %R\n", reg);
1767 /* helper function for emit_ia32_Minus64Bit */
1768 static void emit_sbb(const ir_node* node, const arch_register_t *src, const arch_register_t *dst)
1770 ia32_emitf(node, "\tsbbl %R, %R\n", src, dst);
1773 /* helper function for emit_ia32_Minus64Bit */
1774 static void emit_xchg(const ir_node* node, const arch_register_t *src, const arch_register_t *dst)
1776 ia32_emitf(node, "\txchgl %R, %R\n", src, dst);
1779 /* helper function for emit_ia32_Minus64Bit */
1780 static void emit_zero(const ir_node* node, const arch_register_t *reg)
1782 ia32_emitf(node, "\txorl %R, %R\n", reg, reg);
1785 static void emit_ia32_Minus64Bit(const ir_node *node)
1787 const arch_register_t *in_lo = get_in_reg(node, 0);
1788 const arch_register_t *in_hi = get_in_reg(node, 1);
1789 const arch_register_t *out_lo = get_out_reg(node, 0);
1790 const arch_register_t *out_hi = get_out_reg(node, 1);
1792 if (out_lo == in_lo) {
1793 if (out_hi != in_hi) {
1794 /* a -> a, b -> d */
1797 /* a -> a, b -> b */
1800 } else if (out_lo == in_hi) {
1801 if (out_hi == in_lo) {
1802 /* a -> b, b -> a */
1803 emit_xchg(node, in_lo, in_hi);
1806 /* a -> b, b -> d */
1807 emit_mov(node, in_hi, out_hi);
1808 emit_mov(node, in_lo, out_lo);
1812 if (out_hi == in_lo) {
1813 /* a -> c, b -> a */
1814 emit_mov(node, in_lo, out_lo);
1816 } else if (out_hi == in_hi) {
1817 /* a -> c, b -> b */
1818 emit_mov(node, in_lo, out_lo);
1821 /* a -> c, b -> d */
1822 emit_mov(node, in_lo, out_lo);
1828 emit_neg( node, out_hi);
1829 emit_neg( node, out_lo);
1830 emit_sbb0(node, out_hi);
1834 emit_zero(node, out_hi);
1835 emit_neg( node, out_lo);
1836 emit_sbb( node, in_hi, out_hi);
1839 static void emit_ia32_GetEIP(const ir_node *node)
1841 ia32_emitf(node, "\tcall %s\n", pic_base_label);
1842 ia32_emitf(NULL, "%s:\n", pic_base_label);
1843 ia32_emitf(node, "\tpopl %D0\n");
1846 static void emit_ia32_ClimbFrame(const ir_node *node)
1848 const ia32_climbframe_attr_t *attr = get_ia32_climbframe_attr_const(node);
1850 ia32_emitf(node, "\tmovl %S0, %D0\n");
1851 ia32_emitf(node, "\tmovl $%u, %S1\n", attr->count);
1852 be_gas_emit_block_name(node);
1853 be_emit_cstring(":\n");
1854 be_emit_write_line();
1855 ia32_emitf(node, "\tmovl (%D0), %D0\n");
1856 ia32_emitf(node, "\tdec %S1\n");
1857 be_emit_cstring("\tjnz ");
1858 be_gas_emit_block_name(node);
1859 be_emit_finish_line_gas(node);
1862 static void emit_be_Return(const ir_node *node)
1864 unsigned pop = be_Return_get_pop(node);
1866 if (pop > 0 || be_Return_get_emit_pop(node)) {
1867 ia32_emitf(node, "\tret $%u\n", pop);
1869 ia32_emitf(node, "\tret\n");
1873 static void emit_Nothing(const ir_node *node)
1879 /***********************************************************************************
1882 * _ __ ___ __ _ _ _ __ | |_ _ __ __ _ _ __ ___ _____ _____ _ __| | __
1883 * | '_ ` _ \ / _` | | '_ \ | _| '__/ _` | '_ ` _ \ / _ \ \ /\ / / _ \| '__| |/ /
1884 * | | | | | | (_| | | | | | | | | | | (_| | | | | | | __/\ V V / (_) | | | <
1885 * |_| |_| |_|\__,_|_|_| |_| |_| |_| \__,_|_| |_| |_|\___| \_/\_/ \___/|_| |_|\_\
1887 ***********************************************************************************/
1890 * Enters the emitter functions for handled nodes into the generic
1891 * pointer of an opcode.
1893 static void ia32_register_emitters(void)
1895 #define IA32_EMIT2(a,b) op_ia32_##a->ops.generic = (op_func)emit_ia32_##b
1896 #define IA32_EMIT(a) IA32_EMIT2(a,a)
1897 #define EMIT(a) op_##a->ops.generic = (op_func)emit_##a
1898 #define IGN(a) op_##a->ops.generic = (op_func)emit_Nothing
1899 #define BE_EMIT(a) op_be_##a->ops.generic = (op_func)emit_be_##a
1900 #define BE_IGN(a) op_be_##a->ops.generic = (op_func)emit_Nothing
1902 /* first clear the generic function pointer for all ops */
1903 clear_irp_opcodes_generic_func();
1905 /* register all emitter functions defined in spec */
1906 ia32_register_spec_emitters();
1908 /* other ia32 emitter functions */
1909 IA32_EMIT2(Conv_I2I8Bit, Conv_I2I);
1914 IA32_EMIT(Conv_FP2FP);
1915 IA32_EMIT(Conv_FP2I);
1916 IA32_EMIT(Conv_I2FP);
1917 IA32_EMIT(Conv_I2I);
1925 IA32_EMIT(Minus64Bit);
1926 IA32_EMIT(SwitchJmp);
1927 IA32_EMIT(ClimbFrame);
1930 /* benode emitter */
1951 typedef void (*emit_func_ptr) (const ir_node *);
1954 * Assign and emit an exception label if the current instruction can fail.
1956 static void ia32_assign_exc_label(ir_node *node)
1958 /* assign a new ID to the instruction */
1959 set_ia32_exc_label_id(node, ++exc_label_id);
1961 ia32_emit_exc_label(node);
1963 be_emit_pad_comment();
1964 be_emit_cstring("/* exception to Block ");
1965 ia32_emit_cfop_target(node);
1966 be_emit_cstring(" */\n");
1967 be_emit_write_line();
1971 * Emits code for a node.
1973 static void ia32_emit_node(ir_node *node)
1975 ir_op *op = get_irn_op(node);
1977 DBG((dbg, LEVEL_1, "emitting code for %+F\n", node));
1979 if (is_ia32_irn(node)) {
1980 if (get_ia32_exc_label(node)) {
1981 /* emit the exception label of this instruction */
1982 ia32_assign_exc_label(node);
1984 if (mark_spill_reload) {
1985 if (is_ia32_is_spill(node)) {
1986 ia32_emitf(NULL, "\txchg %ebx, %ebx /* spill mark */\n");
1988 if (is_ia32_is_reload(node)) {
1989 ia32_emitf(NULL, "\txchg %edx, %edx /* reload mark */\n");
1991 if (is_ia32_is_remat(node)) {
1992 ia32_emitf(NULL, "\txchg %ecx, %ecx /* remat mark */\n");
1996 if (op->ops.generic) {
1997 emit_func_ptr func = (emit_func_ptr) op->ops.generic;
1999 be_dbg_set_dbg_info(get_irn_dbg_info(node));
2004 ir_fprintf(stderr, "Error: No emit handler for node %+F (%+G, graph %+F)\n", node, node, current_ir_graph);
2010 * Emits gas alignment directives
2012 static void ia32_emit_alignment(unsigned align, unsigned skip)
2014 ia32_emitf(NULL, "\t.p2align %u,,%u\n", align, skip);
2018 * Emits gas alignment directives for Labels depended on cpu architecture.
2020 static void ia32_emit_align_label(void)
2022 unsigned align = ia32_cg_config.label_alignment;
2023 unsigned maximum_skip = ia32_cg_config.label_alignment_max_skip;
2024 ia32_emit_alignment(align, maximum_skip);
2028 * Test whether a block should be aligned.
2029 * For cpus in the P4/Athlon class it is useful to align jump labels to
2030 * 16 bytes. However we should only do that if the alignment nops before the
2031 * label aren't executed more often than we have jumps to the label.
2033 static int should_align_block(const ir_node *block)
2035 static const double DELTA = .0001;
2036 ir_exec_freq *exec_freq = cg->birg->exec_freq;
2037 ir_node *prev = get_prev_block_sched(block);
2039 double prev_freq = 0; /**< execfreq of the fallthrough block */
2040 double jmp_freq = 0; /**< execfreq of all non-fallthrough blocks */
2043 if (exec_freq == NULL)
2045 if (ia32_cg_config.label_alignment_factor <= 0)
2048 block_freq = get_block_execfreq(exec_freq, block);
2049 if (block_freq < DELTA)
2052 n_cfgpreds = get_Block_n_cfgpreds(block);
2053 for (i = 0; i < n_cfgpreds; ++i) {
2054 const ir_node *pred = get_Block_cfgpred_block(block, i);
2055 double pred_freq = get_block_execfreq(exec_freq, pred);
2058 prev_freq += pred_freq;
2060 jmp_freq += pred_freq;
2064 if (prev_freq < DELTA && !(jmp_freq < DELTA))
2067 jmp_freq /= prev_freq;
2069 return jmp_freq > ia32_cg_config.label_alignment_factor;
2073 * Emit the block header for a block.
2075 * @param block the block
2076 * @param prev_block the previous block
2078 static void ia32_emit_block_header(ir_node *block)
2080 ir_graph *irg = current_ir_graph;
2081 int need_label = block_needs_label(block);
2083 ir_exec_freq *exec_freq = cg->birg->exec_freq;
2085 if (block == get_irg_end_block(irg))
2088 if (ia32_cg_config.label_alignment > 0) {
2089 /* align the current block if:
2090 * a) if should be aligned due to its execution frequency
2091 * b) there is no fall-through here
2093 if (should_align_block(block)) {
2094 ia32_emit_align_label();
2096 /* if the predecessor block has no fall-through,
2097 we can always align the label. */
2099 int has_fallthrough = 0;
2101 for (i = get_Block_n_cfgpreds(block) - 1; i >= 0; --i) {
2102 ir_node *cfg_pred = get_Block_cfgpred(block, i);
2103 if (can_be_fallthrough(cfg_pred)) {
2104 has_fallthrough = 1;
2109 if (!has_fallthrough)
2110 ia32_emit_align_label();
2115 be_gas_emit_block_name(block);
2118 be_emit_pad_comment();
2119 be_emit_cstring(" /* ");
2121 be_emit_cstring("\t/* ");
2122 be_gas_emit_block_name(block);
2123 be_emit_cstring(": ");
2126 be_emit_cstring("preds:");
2128 /* emit list of pred blocks in comment */
2129 arity = get_irn_arity(block);
2131 be_emit_cstring(" none");
2133 for (i = 0; i < arity; ++i) {
2134 ir_node *predblock = get_Block_cfgpred_block(block, i);
2135 be_emit_irprintf(" %d", get_irn_node_nr(predblock));
2138 if (exec_freq != NULL) {
2139 be_emit_irprintf(", freq: %f",
2140 get_block_execfreq(exec_freq, block));
2142 be_emit_cstring(" */\n");
2143 be_emit_write_line();
2147 * Walks over the nodes in a block connected by scheduling edges
2148 * and emits code for each node.
2150 static void ia32_gen_block(ir_node *block)
2154 ia32_emit_block_header(block);
2156 /* emit the contents of the block */
2157 be_dbg_set_dbg_info(get_irn_dbg_info(block));
2158 sched_foreach(block, node) {
2159 ia32_emit_node(node);
2163 typedef struct exc_entry {
2164 ir_node *exc_instr; /** The instruction that can issue an exception. */
2165 ir_node *block; /** The block to call then. */
2170 * Sets labels for control flow nodes (jump target).
2171 * Links control predecessors to there destination blocks.
2173 static void ia32_gen_labels(ir_node *block, void *data)
2175 exc_entry **exc_list = data;
2179 for (n = get_Block_n_cfgpreds(block) - 1; n >= 0; --n) {
2180 pred = get_Block_cfgpred(block, n);
2181 set_irn_link(pred, block);
2183 pred = skip_Proj(pred);
2184 if (is_ia32_irn(pred) && get_ia32_exc_label(pred)) {
2189 ARR_APP1(exc_entry, *exc_list, e);
2190 set_irn_link(pred, block);
2196 * Compare two exception_entries.
2198 static int cmp_exc_entry(const void *a, const void *b)
2200 const exc_entry *ea = a;
2201 const exc_entry *eb = b;
2203 if (get_ia32_exc_label_id(ea->exc_instr) < get_ia32_exc_label_id(eb->exc_instr))
2209 * Main driver. Emits the code for one routine.
2211 void ia32_gen_routine(ia32_code_gen_t *ia32_cg, ir_graph *irg)
2213 ir_entity *entity = get_irg_entity(irg);
2214 exc_entry *exc_list = NEW_ARR_F(exc_entry, 0);
2219 do_pic = cg->birg->main_env->options->pic;
2221 be_gas_elf_type_char = '@';
2223 ia32_register_emitters();
2225 get_unique_label(pic_base_label, sizeof(pic_base_label), "PIC_BASE");
2227 be_dbg_method_begin(entity, be_abi_get_stack_layout(cg->birg->abi));
2228 be_gas_emit_function_prolog(entity, ia32_cg_config.function_alignment);
2230 /* we use links to point to target blocks */
2231 ir_reserve_resources(irg, IR_RESOURCE_IRN_LINK);
2232 irg_block_walk_graph(irg, ia32_gen_labels, NULL, &exc_list);
2234 /* initialize next block links */
2235 n = ARR_LEN(cg->blk_sched);
2236 for (i = 0; i < n; ++i) {
2237 ir_node *block = cg->blk_sched[i];
2238 ir_node *prev = i > 0 ? cg->blk_sched[i-1] : NULL;
2240 set_irn_link(block, prev);
2243 for (i = 0; i < n; ++i) {
2244 ir_node *block = cg->blk_sched[i];
2246 ia32_gen_block(block);
2249 be_gas_emit_function_epilog(entity);
2250 be_dbg_method_end();
2252 be_emit_write_line();
2254 ir_free_resources(irg, IR_RESOURCE_IRN_LINK);
2256 /* Sort the exception table using the exception label id's.
2257 Those are ascending with ascending addresses. */
2258 qsort(exc_list, ARR_LEN(exc_list), sizeof(exc_list[0]), cmp_exc_entry);
2262 for (i = 0; i < ARR_LEN(exc_list); ++i) {
2263 be_emit_cstring("\t.long ");
2264 ia32_emit_exc_label(exc_list[i].exc_instr);
2266 be_emit_cstring("\t.long ");
2267 be_gas_emit_block_name(exc_list[i].block);
2271 DEL_ARR_F(exc_list);
2274 static const lc_opt_table_entry_t ia32_emitter_options[] = {
2275 LC_OPT_ENT_BOOL("mark_spill_reload", "mark spills and reloads with ud opcodes", &mark_spill_reload),
2279 /* ==== Experimental binary emitter ==== */
2281 static unsigned char reg_gp_map[N_ia32_gp_REGS];
2282 //static unsigned char reg_mmx_map[N_ia32_mmx_REGS];
2283 //static unsigned char reg_sse_map[N_ia32_xmm_REGS];
2284 static unsigned char pnc_map_signed[8];
2285 static unsigned char pnc_map_unsigned[8];
2287 static void build_reg_map(void)
2289 reg_gp_map[REG_EAX] = 0x0;
2290 reg_gp_map[REG_ECX] = 0x1;
2291 reg_gp_map[REG_EDX] = 0x2;
2292 reg_gp_map[REG_EBX] = 0x3;
2293 reg_gp_map[REG_ESP] = 0x4;
2294 reg_gp_map[REG_EBP] = 0x5;
2295 reg_gp_map[REG_ESI] = 0x6;
2296 reg_gp_map[REG_EDI] = 0x7;
2298 pnc_map_signed[pn_Cmp_Eq] = 0x04;
2299 pnc_map_signed[pn_Cmp_Lt] = 0x0C;
2300 pnc_map_signed[pn_Cmp_Le] = 0x0E;
2301 pnc_map_signed[pn_Cmp_Gt] = 0x0F;
2302 pnc_map_signed[pn_Cmp_Ge] = 0x0D;
2303 pnc_map_signed[pn_Cmp_Lg] = 0x05;
2305 pnc_map_unsigned[pn_Cmp_Eq] = 0x04;
2306 pnc_map_unsigned[pn_Cmp_Lt] = 0x02;
2307 pnc_map_unsigned[pn_Cmp_Le] = 0x06;
2308 pnc_map_unsigned[pn_Cmp_Gt] = 0x07;
2309 pnc_map_unsigned[pn_Cmp_Ge] = 0x03;
2310 pnc_map_unsigned[pn_Cmp_Lg] = 0x05;
2313 /** Returns the encoding for a pnc field. */
2314 static unsigned char pnc2cc(int pnc)
2317 if (pnc == ia32_pn_Cmp_parity) {
2319 } else if (pnc & ia32_pn_Cmp_float || pnc & ia32_pn_Cmp_unsigned) {
2320 cc = pnc_map_unsigned[pnc & 0x07];
2322 cc = pnc_map_signed[pnc & 0x07];
2328 /** Sign extension bit values for binops */
2330 UNSIGNED_IMM = 0, /**< unsigned immediate */
2331 SIGNEXT_IMM = 2, /**< sign extended immediate */
2334 /** The mod encoding of the ModR/M */
2336 MOD_IND = 0x00, /**< [reg1] */
2337 MOD_IND_BYTE_OFS = 0x40, /**< [reg1 + byte ofs] */
2338 MOD_IND_WORD_OFS = 0x80, /**< [reg1 + word ofs] */
2339 MOD_REG = 0xC0 /**< reg1 */
2342 /** create R/M encoding for ModR/M */
2343 #define ENC_RM(x) (x)
2344 /** create REG encoding for ModR/M */
2345 #define ENC_REG(x) ((x) << 3)
2347 /** create encoding for a SIB byte */
2348 #define ENC_SIB(scale, index, base) ((scale) << 6 | (index) << 3 | (base))
2350 /* Node: The following routines are supposed to append bytes, words, dwords
2351 to the output stream.
2352 Currently the implementation is stupid in that it still creates output
2353 for an "assembler" in the form of .byte, .long
2354 We will change this when enough infrastructure is there to create complete
2355 machine code in memory/object files */
2357 static void bemit8(const unsigned char byte)
2359 be_emit_irprintf("\t.byte 0x%x\n", byte);
2360 be_emit_write_line();
2363 static void bemit16(const unsigned short u16)
2365 be_emit_irprintf("\t.word 0x%x\n", u16);
2366 be_emit_write_line();
2369 static void bemit32(const unsigned u32)
2371 be_emit_irprintf("\t.long 0x%x\n", u32);
2372 be_emit_write_line();
2376 * Emit address of an entity. If @p is_relative is true then a relative
2377 * offset from behind the address to the entity is created.
2379 static void bemit_entity(ir_entity *entity, bool entity_sign, int offset,
2382 if (entity == NULL) {
2387 /* the final version should remember the position in the bytestream
2388 and patch it with the correct address at linktime... */
2389 be_emit_cstring("\t.long ");
2392 be_gas_emit_entity(entity);
2394 if (get_entity_owner(entity) == get_tls_type()) {
2395 if (get_entity_visibility(entity) == ir_visibility_external) {
2396 be_emit_cstring("@INDNTPOFF");
2398 be_emit_cstring("@NTPOFF");
2403 be_emit_cstring("-.");
2408 be_emit_irprintf("%+d", offset);
2411 be_emit_write_line();
2414 static void bemit_jmp_destination(const ir_node *dest_block)
2416 be_emit_cstring("\t.long ");
2417 be_gas_emit_block_name(dest_block);
2418 be_emit_cstring(" - . - 4\n");
2419 be_emit_write_line();
2422 /* end emit routines, all emitters following here should only use the functions
2425 typedef enum reg_modifier {
2430 /** Create a ModR/M byte for src1,src2 registers */
2431 static void bemit_modrr(const arch_register_t *src1,
2432 const arch_register_t *src2)
2434 unsigned char modrm = MOD_REG;
2435 modrm |= ENC_RM(reg_gp_map[src1->index]);
2436 modrm |= ENC_REG(reg_gp_map[src2->index]);
2440 /** Create a ModR/M8 byte for src1,src2 registers */
2441 static void bemit_modrr8(reg_modifier_t high_part1, const arch_register_t *src1,
2442 reg_modifier_t high_part2, const arch_register_t *src2)
2444 unsigned char modrm = MOD_REG;
2445 modrm |= ENC_RM(reg_gp_map[src1->index] + (high_part1 == REG_HIGH ? 4 : 0));
2446 modrm |= ENC_REG(reg_gp_map[src2->index] + (high_part2 == REG_HIGH ? 4 : 0));
2450 /** Create a ModR/M byte for one register and extension */
2451 static void bemit_modru(const arch_register_t *reg, unsigned ext)
2453 unsigned char modrm = MOD_REG;
2455 modrm |= ENC_RM(reg_gp_map[reg->index]);
2456 modrm |= ENC_REG(ext);
2460 /** Create a ModR/M8 byte for one register */
2461 static void bemit_modrm8(reg_modifier_t high_part, const arch_register_t *reg)
2463 unsigned char modrm = MOD_REG;
2464 assert(reg_gp_map[reg->index] < 4);
2465 modrm |= ENC_RM(reg_gp_map[reg->index] + (high_part == REG_HIGH ? 4 : 0));
2471 * Calculate the size of an signed immediate in bytes.
2473 * @param offset an offset
2475 static unsigned get_signed_imm_size(int offset)
2477 if (-128 <= offset && offset < 128) {
2479 } else if (-32768 <= offset && offset < 32768) {
2487 * Emit an address mode.
2489 * @param reg content of the reg field: either a register index or an opcode extension
2490 * @param node the node
2492 static void bemit_mod_am(unsigned reg, const ir_node *node)
2494 ir_entity *ent = get_ia32_am_sc(node);
2495 int offs = get_ia32_am_offs_int(node);
2496 ir_node *base = get_irn_n(node, n_ia32_base);
2497 int has_base = !is_ia32_NoReg_GP(base);
2498 ir_node *index = get_irn_n(node, n_ia32_index);
2499 int has_index = !is_ia32_NoReg_GP(index);
2502 unsigned emitoffs = 0;
2503 bool emitsib = false;
2506 /* set the mod part depending on displacement */
2508 modrm |= MOD_IND_WORD_OFS;
2510 } else if (offs == 0) {
2513 } else if (-128 <= offs && offs < 128) {
2514 modrm |= MOD_IND_BYTE_OFS;
2517 modrm |= MOD_IND_WORD_OFS;
2522 const arch_register_t *base_reg = arch_get_irn_register(base);
2523 base_enc = reg_gp_map[base_reg->index];
2525 /* Use the EBP encoding + MOD_IND if NO base register. There is
2526 * always a 32bit offset present in this case. */
2532 /* Determine if we need a SIB byte. */
2534 const arch_register_t *reg_index = arch_get_irn_register(index);
2535 int scale = get_ia32_am_scale(node);
2537 /* R/M set to ESP means SIB in 32bit mode. */
2538 modrm |= ENC_RM(0x04);
2539 sib = ENC_SIB(scale, reg_gp_map[reg_index->index], base_enc);
2541 } else if (base_enc == 0x04) {
2542 /* for the above reason we are forced to emit a SIB when base is ESP.
2543 * Only the base is used, index must be ESP too, which means no index.
2545 modrm |= ENC_RM(0x04);
2546 sib = ENC_SIB(0, 0x04, 0x04);
2549 modrm |= ENC_RM(base_enc);
2552 /* We are forced to emit an 8bit offset as EBP base without offset is a
2553 * special case for SIB without base register. */
2554 if (base_enc == 0x05 && emitoffs == 0) {
2555 modrm |= MOD_IND_BYTE_OFS;
2559 modrm |= ENC_REG(reg);
2565 /* emit displacement */
2566 if (emitoffs == 8) {
2567 bemit8((unsigned) offs);
2568 } else if (emitoffs == 32) {
2569 bemit_entity(ent, is_ia32_am_sc_sign(node), offs, false);
2574 * Emit a binop with a immediate operand.
2576 * @param node the node to emit
2577 * @param opcode_eax the opcode for the op eax, imm variant
2578 * @param opcode the opcode for the reg, imm variant
2579 * @param ruval the opcode extension for opcode
2581 static void bemit_binop_with_imm(
2582 const ir_node *node,
2583 unsigned char opcode_ax,
2584 unsigned char opcode, unsigned char ruval)
2586 /* Use in-reg, because some instructions (cmp, test) have no out-reg. */
2587 const ir_node *op = get_irn_n(node, n_ia32_binary_right);
2588 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(op);
2591 /* Some instructions (test) have no short form with 32bit value + 8bit
2593 if (attr->symconst != NULL || opcode & SIGNEXT_IMM) {
2596 /* check for sign extension */
2597 size = get_signed_imm_size(attr->offset);
2602 bemit8(opcode | SIGNEXT_IMM);
2603 /* cmp has this special mode */
2604 if (get_ia32_op_type(node) == ia32_AddrModeS) {
2605 bemit_mod_am(ruval, node);
2607 const arch_register_t *reg = get_in_reg(node, n_ia32_binary_left);
2608 bemit_modru(reg, ruval);
2610 bemit8((unsigned char)attr->offset);
2614 /* check for eax variant: this variant is shorter for 32bit immediates only */
2615 if (get_ia32_op_type(node) == ia32_AddrModeS) {
2617 bemit_mod_am(ruval, node);
2619 const arch_register_t *reg = get_in_reg(node, n_ia32_binary_left);
2620 if (reg->index == REG_EAX) {
2624 bemit_modru(reg, ruval);
2627 bemit_entity(attr->symconst, attr->sc_sign, attr->offset, false);
2630 panic("invalid imm size?!?");
2636 static void bemit_binop_2(const ir_node *node, unsigned code)
2638 const arch_register_t *out = get_in_reg(node, n_ia32_binary_left);
2640 if (get_ia32_op_type(node) == ia32_Normal) {
2641 const arch_register_t *op2 = get_in_reg(node, n_ia32_binary_right);
2642 bemit_modrr(op2, out);
2644 bemit_mod_am(reg_gp_map[out->index], node);
2651 static void bemit_binop(const ir_node *node, const unsigned char opcodes[4])
2653 ir_node *right = get_irn_n(node, n_ia32_binary_right);
2654 if (is_ia32_Immediate(right)) {
2655 bemit_binop_with_imm(node, opcodes[1], opcodes[2], opcodes[3]);
2657 bemit_binop_2(node, opcodes[0]);
2664 static void bemit_unop(const ir_node *node, unsigned char code, unsigned char ext, int input)
2667 if (get_ia32_op_type(node) == ia32_Normal) {
2668 const arch_register_t *in = get_in_reg(node, input);
2669 bemit_modru(in, ext);
2671 bemit_mod_am(ext, node);
2675 static void bemit_unop_reg(const ir_node *node, unsigned char code, int input)
2677 const arch_register_t *out = get_out_reg(node, 0);
2678 bemit_unop(node, code, reg_gp_map[out->index], input);
2681 static void bemit_unop_mem(const ir_node *node, unsigned char code, unsigned char ext)
2683 unsigned size = get_mode_size_bits(get_ia32_ls_mode(node));
2686 bemit8(size == 8 ? code : code + 1);
2687 bemit_mod_am(ext, node);
2690 static void bemit_immediate(const ir_node *node, bool relative)
2692 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(node);
2693 bemit_entity(attr->symconst, attr->sc_sign, attr->offset, relative);
2696 static void bemit_copy(const ir_node *copy)
2698 const arch_register_t *in = get_in_reg(copy, 0);
2699 const arch_register_t *out = get_out_reg(copy, 0);
2703 /* copies of vf nodes aren't real... */
2704 if (arch_register_get_class(in) == &ia32_reg_classes[CLASS_ia32_vfp])
2707 if (get_irn_mode(copy) == mode_E) {
2710 assert(arch_register_get_class(in) == &ia32_reg_classes[CLASS_ia32_gp]);
2712 bemit_modrr(in, out);
2716 static void bemit_perm(const ir_node *node)
2718 const arch_register_t *in0 = arch_get_irn_register(get_irn_n(node, 0));
2719 const arch_register_t *in1 = arch_get_irn_register(get_irn_n(node, 1));
2720 const arch_register_class_t *cls0 = arch_register_get_class(in0);
2722 assert(cls0 == arch_register_get_class(in1) && "Register class mismatch at Perm");
2724 if (cls0 == &ia32_reg_classes[CLASS_ia32_gp]) {
2725 if (in0->index == REG_EAX) {
2726 bemit8(0x90 + reg_gp_map[in1->index]);
2727 } else if (in1->index == REG_EAX) {
2728 bemit8(0x90 + reg_gp_map[in0->index]);
2731 bemit_modrr(in0, in1);
2733 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_xmm]) {
2734 panic("unimplemented"); // TODO implement
2735 //ia32_emitf(NULL, "\txorpd %R, %R\n", in1, in0);
2736 //ia32_emitf(NULL, "\txorpd %R, %R\n", in0, in1);
2737 //ia32_emitf(node, "\txorpd %R, %R\n", in1, in0);
2738 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_vfp]) {
2740 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_st]) {
2743 panic("unexpected register class in be_Perm (%+F)", node);
2747 static void bemit_xor0(const ir_node *node)
2749 const arch_register_t *out = get_out_reg(node, 0);
2751 bemit_modrr(out, out);
2754 static void bemit_mov_const(const ir_node *node)
2756 const arch_register_t *out = get_out_reg(node, 0);
2757 bemit8(0xB8 + reg_gp_map[out->index]);
2758 bemit_immediate(node, false);
2762 * Creates a function for a Binop with 3 possible encodings.
2764 #define BINOP(op, op0, op1, op2, op2_ext) \
2765 static void bemit_ ## op(const ir_node *node) { \
2766 static const unsigned char op ## _codes[] = {op0, op1, op2, op2_ext}; \
2767 bemit_binop(node, op ## _codes); \
2770 /* insn def eax,imm imm */
2771 BINOP(add, 0x03, 0x05, 0x81, 0)
2772 BINOP(or, 0x0B, 0x0D, 0x81, 1)
2773 BINOP(adc, 0x13, 0x15, 0x81, 2)
2774 BINOP(sbb, 0x1B, 0x1D, 0x81, 3)
2775 BINOP(and, 0x23, 0x25, 0x81, 4)
2776 BINOP(sub, 0x2B, 0x2D, 0x81, 5)
2777 BINOP(xor, 0x33, 0x35, 0x81, 6)
2778 BINOP(test, 0x85, 0xA9, 0xF7, 0)
2780 #define BINOPMEM(op, ext) \
2781 static void bemit_##op(const ir_node *node) \
2784 unsigned size = get_mode_size_bits(get_ia32_ls_mode(node)); \
2787 val = get_irn_n(node, n_ia32_unary_op); \
2788 if (is_ia32_Immediate(val)) { \
2789 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(val); \
2790 int offset = attr->offset; \
2791 if (attr->symconst == NULL && get_signed_imm_size(offset) == 1) { \
2793 bemit_mod_am(ext, node); \
2797 bemit_mod_am(ext, node); \
2801 bemit_entity(attr->symconst, attr->sc_sign, offset, false); \
2805 bemit8(ext << 3 | 1); \
2806 bemit_mod_am(reg_gp_map[get_out_reg(val, 0)->index], node); \
2810 static void bemit_##op##8bit(const ir_node *node) \
2812 ir_node *val = get_irn_n(node, n_ia32_unary_op); \
2813 if (is_ia32_Immediate(val)) { \
2815 bemit_mod_am(ext, node); \
2816 bemit8(get_ia32_immediate_attr_const(val)->offset); \
2819 bemit_mod_am(reg_gp_map[get_out_reg(val, 0)->index], node); \
2831 * Creates a function for an Unop with code /ext encoding.
2833 #define UNOP(op, code, ext, input) \
2834 static void bemit_ ## op(const ir_node *node) { \
2835 bemit_unop(node, code, ext, input); \
2838 UNOP(not, 0xF7, 2, n_ia32_Not_val)
2839 UNOP(neg, 0xF7, 3, n_ia32_Neg_val)
2840 UNOP(mul, 0xF7, 4, n_ia32_Mul_right)
2841 UNOP(imul1op, 0xF7, 5, n_ia32_IMul1OP_right)
2842 UNOP(div, 0xF7, 6, n_ia32_Div_divisor)
2843 UNOP(idiv, 0xF7, 7, n_ia32_IDiv_divisor)
2845 /* TODO: am support for IJmp */
2846 UNOP(ijmp, 0xFF, 4, n_ia32_IJmp_target)
2848 #define SHIFT(op, ext) \
2849 static void bemit_##op(const ir_node *node) \
2851 const arch_register_t *out = get_out_reg(node, 0); \
2852 ir_node *count = get_irn_n(node, 1); \
2853 if (is_ia32_Immediate(count)) { \
2854 int offset = get_ia32_immediate_attr_const(count)->offset; \
2855 if (offset == 1) { \
2857 bemit_modru(out, ext); \
2860 bemit_modru(out, ext); \
2865 bemit_modru(out, ext); \
2869 static void bemit_##op##mem(const ir_node *node) \
2872 unsigned size = get_mode_size_bits(get_ia32_ls_mode(node)); \
2875 count = get_irn_n(node, 1); \
2876 if (is_ia32_Immediate(count)) { \
2877 int offset = get_ia32_immediate_attr_const(count)->offset; \
2878 if (offset == 1) { \
2879 bemit8(size == 8 ? 0xD0 : 0xD1); \
2880 bemit_mod_am(ext, node); \
2882 bemit8(size == 8 ? 0xC0 : 0xC1); \
2883 bemit_mod_am(ext, node); \
2887 bemit8(size == 8 ? 0xD2 : 0xD3); \
2888 bemit_mod_am(ext, node); \
2898 static void bemit_shld(const ir_node *node)
2900 const arch_register_t *in = get_in_reg(node, n_ia32_ShlD_val_low);
2901 const arch_register_t *out = get_out_reg(node, pn_ia32_ShlD_res);
2902 ir_node *count = get_irn_n(node, n_ia32_ShlD_count);
2904 if (is_ia32_Immediate(count)) {
2906 bemit_modrr(out, in);
2907 bemit8(get_ia32_immediate_attr_const(count)->offset);
2910 bemit_modrr(out, in);
2914 static void bemit_shrd(const ir_node *node)
2916 const arch_register_t *in = get_in_reg(node, n_ia32_ShrD_val_low);
2917 const arch_register_t *out = get_out_reg(node, pn_ia32_ShrD_res);
2918 ir_node *count = get_irn_n(node, n_ia32_ShrD_count);
2920 if (is_ia32_Immediate(count)) {
2922 bemit_modrr(out, in);
2923 bemit8(get_ia32_immediate_attr_const(count)->offset);
2926 bemit_modrr(out, in);
2931 * binary emitter for setcc.
2933 static void bemit_setcc(const ir_node *node)
2935 const arch_register_t *dreg = get_out_reg(node, pn_ia32_Setcc_res);
2937 pn_Cmp pnc = get_ia32_condcode(node);
2938 pnc = determine_final_pnc(node, n_ia32_Setcc_eflags, pnc);
2939 if (pnc & ia32_pn_Cmp_float) {
2940 switch (pnc & 0x0f) {
2945 bemit_modrm8(REG_LOW, dreg);
2952 bemit_modrm8(REG_LOW, dreg);
2960 bemit8(0x90 | pnc2cc(pnc));
2961 bemit_modrm8(REG_LOW, dreg);
2966 bemit_modrm8(REG_HIGH, dreg);
2968 /* andb %>dreg, %<dreg */
2970 bemit_modrr8(REG_LOW, dreg, REG_HIGH, dreg);
2978 bemit8(0x90 | pnc2cc(pnc));
2979 bemit_modrm8(REG_LOW, dreg);
2984 bemit_modrm8(REG_HIGH, dreg);
2986 /* orb %>dreg, %<dreg */
2988 bemit_modrr8(REG_LOW, dreg, REG_HIGH, dreg);
2997 bemit8(0x90 | pnc2cc(pnc));
2998 bemit_modrm8(REG_LOW, dreg);
3001 static void bemit_cmovcc(const ir_node *node)
3003 const ia32_attr_t *attr = get_ia32_attr_const(node);
3004 int ins_permuted = attr->data.ins_permuted;
3005 const arch_register_t *out = arch_irn_get_register(node, pn_ia32_res);
3006 pn_Cmp pnc = get_ia32_condcode(node);
3007 const arch_register_t *in_true;
3008 const arch_register_t *in_false;
3010 pnc = determine_final_pnc(node, n_ia32_CMovcc_eflags, pnc);
3012 in_true = arch_get_irn_register(get_irn_n(node, n_ia32_CMovcc_val_true));
3013 in_false = arch_get_irn_register(get_irn_n(node, n_ia32_CMovcc_val_false));
3015 /* should be same constraint fullfilled? */
3016 if (out == in_false) {
3017 /* yes -> nothing to do */
3018 } else if (out == in_true) {
3019 assert(get_ia32_op_type(node) == ia32_Normal);
3020 ins_permuted = !ins_permuted;
3024 bemit8(0x8B); // mov %in_false, %out
3025 bemit_modrr(in_false, out);
3029 pnc = ia32_get_negated_pnc(pnc);
3031 /* TODO: handling of Nans isn't correct yet */
3034 bemit8(0x40 | pnc2cc(pnc));
3035 if (get_ia32_op_type(node) == ia32_Normal) {
3036 bemit_modrr(in_true, out);
3038 bemit_mod_am(reg_gp_map[out->index], node);
3042 static void bemit_cmp(const ir_node *node)
3044 unsigned ls_size = get_mode_size_bits(get_ia32_ls_mode(node));
3050 right = get_irn_n(node, n_ia32_binary_right);
3051 if (is_ia32_Immediate(right)) {
3052 /* Use in-reg, because some instructions (cmp, test) have no out-reg. */
3053 const ir_node *op = get_irn_n(node, n_ia32_binary_right);
3054 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(op);
3057 if (attr->symconst != NULL) {
3060 /* check for sign extension */
3061 size = get_signed_imm_size(attr->offset);
3066 bemit8(0x81 | SIGNEXT_IMM);
3067 /* cmp has this special mode */
3068 if (get_ia32_op_type(node) == ia32_AddrModeS) {
3069 bemit_mod_am(7, node);
3071 const arch_register_t *reg = get_in_reg(node, n_ia32_binary_left);
3072 bemit_modru(reg, 7);
3074 bemit8((unsigned char)attr->offset);
3078 /* check for eax variant: this variant is shorter for 32bit immediates only */
3079 if (get_ia32_op_type(node) == ia32_AddrModeS) {
3081 bemit_mod_am(7, node);
3083 const arch_register_t *reg = get_in_reg(node, n_ia32_binary_left);
3084 if (reg->index == REG_EAX) {
3088 bemit_modru(reg, 7);
3091 if (ls_size == 16) {
3092 bemit16(attr->offset);
3094 bemit_entity(attr->symconst, attr->sc_sign, attr->offset, false);
3098 panic("invalid imm size?!?");
3100 const arch_register_t *out = get_in_reg(node, n_ia32_binary_left);
3102 if (get_ia32_op_type(node) == ia32_Normal) {
3103 const arch_register_t *op2 = get_in_reg(node, n_ia32_binary_right);
3104 bemit_modrr(op2, out);
3106 bemit_mod_am(reg_gp_map[out->index], node);
3111 static void bemit_cmp8bit(const ir_node *node)
3113 ir_node *right = get_irn_n(node, n_ia32_binary_right);
3114 if (is_ia32_Immediate(right)) {
3115 if (get_ia32_op_type(node) == ia32_Normal) {
3116 const arch_register_t *out = get_in_reg(node, n_ia32_Cmp_left);
3117 if (out->index == REG_EAX) {
3121 bemit_modru(out, 7);
3125 bemit_mod_am(7, node);
3127 bemit8(get_ia32_immediate_attr_const(right)->offset);
3129 const arch_register_t *out = get_in_reg(node, n_ia32_Cmp_left);
3131 if (get_ia32_op_type(node) == ia32_Normal) {
3132 const arch_register_t *in = get_in_reg(node, n_ia32_Cmp_right);
3133 bemit_modrr(out, in);
3135 bemit_mod_am(reg_gp_map[out->index], node);
3140 static void bemit_test8bit(const ir_node *node)
3142 ir_node *right = get_irn_n(node, n_ia32_Test8Bit_right);
3143 if (is_ia32_Immediate(right)) {
3144 if (get_ia32_op_type(node) == ia32_Normal) {
3145 const arch_register_t *out = get_in_reg(node, n_ia32_Test8Bit_left);
3146 if (out->index == REG_EAX) {
3150 bemit_modru(out, 0);
3154 bemit_mod_am(0, node);
3156 bemit8(get_ia32_immediate_attr_const(right)->offset);
3158 const arch_register_t *out = get_in_reg(node, n_ia32_Test8Bit_left);
3160 if (get_ia32_op_type(node) == ia32_Normal) {
3161 const arch_register_t *in = get_in_reg(node, n_ia32_Test8Bit_right);
3162 bemit_modrr(out, in);
3164 bemit_mod_am(reg_gp_map[out->index], node);
3169 static void bemit_imul(const ir_node *node)
3171 ir_node *right = get_irn_n(node, n_ia32_IMul_right);
3172 /* Do we need the immediate form? */
3173 if (is_ia32_Immediate(right)) {
3174 int imm = get_ia32_immediate_attr_const(right)->offset;
3175 if (get_signed_imm_size(imm) == 1) {
3176 bemit_unop_reg(node, 0x6B, n_ia32_IMul_left);
3179 bemit_unop_reg(node, 0x69, n_ia32_IMul_left);
3184 bemit_unop_reg(node, 0xAF, n_ia32_IMul_right);
3188 static void bemit_dec(const ir_node *node)
3190 const arch_register_t *out = get_out_reg(node, pn_ia32_Dec_res);
3191 bemit8(0x48 + reg_gp_map[out->index]);
3194 static void bemit_inc(const ir_node *node)
3196 const arch_register_t *out = get_out_reg(node, pn_ia32_Inc_res);
3197 bemit8(0x40 + reg_gp_map[out->index]);
3200 #define UNOPMEM(op, code, ext) \
3201 static void bemit_##op(const ir_node *node) \
3203 bemit_unop_mem(node, code, ext); \
3206 UNOPMEM(notmem, 0xF6, 2)
3207 UNOPMEM(negmem, 0xF6, 3)
3208 UNOPMEM(incmem, 0xFE, 0)
3209 UNOPMEM(decmem, 0xFE, 1)
3211 static void bemit_ldtls(const ir_node *node)
3213 const arch_register_t *out = get_out_reg(node, 0);
3215 bemit8(0x65); // gs:
3216 if (out->index == REG_EAX) {
3217 bemit8(0xA1); // movl 0, %eax
3219 bemit8(0x8B); // movl 0, %reg
3220 bemit8(MOD_IND | ENC_REG(reg_gp_map[out->index]) | ENC_RM(0x05));
3228 static void bemit_lea(const ir_node *node)
3230 const arch_register_t *out = get_out_reg(node, 0);
3232 bemit_mod_am(reg_gp_map[out->index], node);
3235 /* helper function for bemit_minus64bit */
3236 static void bemit_helper_mov(const arch_register_t *src, const arch_register_t *dst)
3238 bemit8(0x8B); // movl %src, %dst
3239 bemit_modrr(src, dst);
3242 /* helper function for bemit_minus64bit */
3243 static void bemit_helper_neg(const arch_register_t *reg)
3245 bemit8(0xF7); // negl %reg
3246 bemit_modru(reg, 3);
3249 /* helper function for bemit_minus64bit */
3250 static void bemit_helper_sbb0(const arch_register_t *reg)
3252 bemit8(0x83); // sbbl $0, %reg
3253 bemit_modru(reg, 3);
3257 /* helper function for bemit_minus64bit */
3258 static void bemit_helper_sbb(const arch_register_t *src, const arch_register_t *dst)
3260 bemit8(0x1B); // sbbl %src, %dst
3261 bemit_modrr(src, dst);
3264 /* helper function for bemit_minus64bit */
3265 static void bemit_helper_xchg(const arch_register_t *src, const arch_register_t *dst)
3267 if (src->index == REG_EAX) {
3268 bemit8(0x90 + reg_gp_map[dst->index]); // xchgl %eax, %dst
3269 } else if (dst->index == REG_EAX) {
3270 bemit8(0x90 + reg_gp_map[src->index]); // xchgl %src, %eax
3272 bemit8(0x87); // xchgl %src, %dst
3273 bemit_modrr(src, dst);
3277 /* helper function for bemit_minus64bit */
3278 static void bemit_helper_zero(const arch_register_t *reg)
3280 bemit8(0x33); // xorl %reg, %reg
3281 bemit_modrr(reg, reg);
3284 static void bemit_minus64bit(const ir_node *node)
3286 const arch_register_t *in_lo = get_in_reg(node, 0);
3287 const arch_register_t *in_hi = get_in_reg(node, 1);
3288 const arch_register_t *out_lo = get_out_reg(node, 0);
3289 const arch_register_t *out_hi = get_out_reg(node, 1);
3291 if (out_lo == in_lo) {
3292 if (out_hi != in_hi) {
3293 /* a -> a, b -> d */
3296 /* a -> a, b -> b */
3299 } else if (out_lo == in_hi) {
3300 if (out_hi == in_lo) {
3301 /* a -> b, b -> a */
3302 bemit_helper_xchg(in_lo, in_hi);
3305 /* a -> b, b -> d */
3306 bemit_helper_mov(in_hi, out_hi);
3307 bemit_helper_mov(in_lo, out_lo);
3311 if (out_hi == in_lo) {
3312 /* a -> c, b -> a */
3313 bemit_helper_mov(in_lo, out_lo);
3315 } else if (out_hi == in_hi) {
3316 /* a -> c, b -> b */
3317 bemit_helper_mov(in_lo, out_lo);
3320 /* a -> c, b -> d */
3321 bemit_helper_mov(in_lo, out_lo);
3327 bemit_helper_neg( out_hi);
3328 bemit_helper_neg( out_lo);
3329 bemit_helper_sbb0(out_hi);
3333 bemit_helper_zero(out_hi);
3334 bemit_helper_neg( out_lo);
3335 bemit_helper_sbb( in_hi, out_hi);
3339 * Emit a single opcode.
3341 #define EMIT_SINGLEOP(op, code) \
3342 static void bemit_ ## op(const ir_node *node) { \
3347 //EMIT_SINGLEOP(daa, 0x27)
3348 //EMIT_SINGLEOP(das, 0x2F)
3349 //EMIT_SINGLEOP(aaa, 0x37)
3350 //EMIT_SINGLEOP(aas, 0x3F)
3351 //EMIT_SINGLEOP(nop, 0x90)
3352 EMIT_SINGLEOP(cwtl, 0x98)
3353 EMIT_SINGLEOP(cltd, 0x99)
3354 //EMIT_SINGLEOP(fwait, 0x9B)
3355 EMIT_SINGLEOP(sahf, 0x9E)
3356 //EMIT_SINGLEOP(popf, 0x9D)
3357 EMIT_SINGLEOP(leave, 0xC9)
3358 EMIT_SINGLEOP(int3, 0xCC)
3359 //EMIT_SINGLEOP(iret, 0xCF)
3360 //EMIT_SINGLEOP(xlat, 0xD7)
3361 //EMIT_SINGLEOP(lock, 0xF0)
3362 EMIT_SINGLEOP(rep, 0xF3)
3363 //EMIT_SINGLEOP(halt, 0xF4)
3364 EMIT_SINGLEOP(cmc, 0xF5)
3365 EMIT_SINGLEOP(stc, 0xF9)
3366 //EMIT_SINGLEOP(cli, 0xFA)
3367 //EMIT_SINGLEOP(sti, 0xFB)
3368 //EMIT_SINGLEOP(std, 0xFD)
3371 * Emits a MOV out, [MEM].
3373 static void bemit_load(const ir_node *node)
3375 const arch_register_t *out = get_out_reg(node, 0);
3377 if (out->index == REG_EAX) {
3378 ir_node *base = get_irn_n(node, n_ia32_base);
3379 int has_base = !is_ia32_NoReg_GP(base);
3380 ir_node *index = get_irn_n(node, n_ia32_index);
3381 int has_index = !is_ia32_NoReg_GP(index);
3382 if (!has_base && !has_index) {
3383 ir_entity *ent = get_ia32_am_sc(node);
3384 int offs = get_ia32_am_offs_int(node);
3385 /* load from constant address to EAX can be encoded
3388 bemit_entity(ent, 0, offs, false);
3393 bemit_mod_am(reg_gp_map[out->index], node);
3397 * Emits a MOV [mem], in.
3399 static void bemit_store(const ir_node *node)
3401 const ir_node *value = get_irn_n(node, n_ia32_Store_val);
3402 unsigned size = get_mode_size_bits(get_ia32_ls_mode(node));
3404 if (is_ia32_Immediate(value)) {
3407 bemit_mod_am(0, node);
3408 bemit8(get_ia32_immediate_attr_const(value)->offset);
3409 } else if (size == 16) {
3412 bemit_mod_am(0, node);
3413 bemit16(get_ia32_immediate_attr_const(value)->offset);
3416 bemit_mod_am(0, node);
3417 bemit_immediate(value, false);
3420 const arch_register_t *in = get_in_reg(node, n_ia32_Store_val);
3422 if (in->index == REG_EAX) {
3423 ir_node *base = get_irn_n(node, n_ia32_base);
3424 int has_base = !is_ia32_NoReg_GP(base);
3425 ir_node *index = get_irn_n(node, n_ia32_index);
3426 int has_index = !is_ia32_NoReg_GP(index);
3427 if (!has_base && !has_index) {
3428 ir_entity *ent = get_ia32_am_sc(node);
3429 int offs = get_ia32_am_offs_int(node);
3430 /* store to constant address from EAX can be encoded as
3431 * 0xA2/0xA3 [offset]*/
3439 bemit_entity(ent, 0, offs, false);
3451 bemit_mod_am(reg_gp_map[in->index], node);
3455 static void bemit_conv_i2i(const ir_node *node)
3457 ir_mode *smaller_mode = get_ia32_ls_mode(node);
3466 if (mode_is_signed(smaller_mode)) opcode |= 0x08;
3467 if (get_mode_size_bits(smaller_mode) == 16) opcode |= 0x01;
3468 bemit_unop_reg(node, opcode, n_ia32_Conv_I2I_val);
3474 static void bemit_push(const ir_node *node)
3476 const ir_node *value = get_irn_n(node, n_ia32_Push_val);
3478 if (is_ia32_Immediate(value)) {
3479 const ia32_immediate_attr_t *attr
3480 = get_ia32_immediate_attr_const(value);
3481 unsigned size = get_signed_imm_size(attr->offset);
3487 bemit8((unsigned char)attr->offset);
3492 bemit_immediate(value, false);
3495 } else if (is_ia32_NoReg_GP(value)) {
3497 bemit_mod_am(6, node);
3499 const arch_register_t *reg = get_in_reg(node, n_ia32_Push_val);
3500 bemit8(0x50 + reg_gp_map[reg->index]);
3507 static void bemit_pop(const ir_node *node)
3509 const arch_register_t *reg = get_out_reg(node, pn_ia32_Pop_res);
3510 bemit8(0x58 + reg_gp_map[reg->index]);
3513 static void bemit_popmem(const ir_node *node)
3516 bemit_mod_am(0, node);
3519 static void bemit_call(const ir_node *node)
3521 ir_node *proc = get_irn_n(node, n_ia32_Call_addr);
3523 if (is_ia32_Immediate(proc)) {
3525 bemit_immediate(proc, true);
3527 bemit_unop(node, 0xFF, 2, n_ia32_Call_addr);
3531 static void bemit_jmp(const ir_node *dest_block)
3534 bemit_jmp_destination(dest_block);
3537 static void bemit_jump(const ir_node *node)
3539 if (can_be_fallthrough(node))
3542 bemit_jmp(get_cfop_target_block(node));
3545 static void bemit_jcc(int pnc, const ir_node *dest_block)
3547 unsigned char cc = pnc2cc(pnc);
3550 bemit_jmp_destination(dest_block);
3553 static void bemit_jp(bool odd, const ir_node *dest_block)
3557 bemit_jmp_destination(dest_block);
3560 static void bemit_ia32_jcc(const ir_node *node)
3562 int pnc = get_ia32_condcode(node);
3563 const ir_node *proj_true;
3564 const ir_node *proj_false;
3565 const ir_node *dest_true;
3566 const ir_node *dest_false;
3567 const ir_node *block;
3569 pnc = determine_final_pnc(node, 0, pnc);
3571 /* get both Projs */
3572 proj_true = get_proj(node, pn_ia32_Jcc_true);
3573 assert(proj_true && "Jcc without true Proj");
3575 proj_false = get_proj(node, pn_ia32_Jcc_false);
3576 assert(proj_false && "Jcc without false Proj");
3578 block = get_nodes_block(node);
3580 if (can_be_fallthrough(proj_true)) {
3581 /* exchange both proj's so the second one can be omitted */
3582 const ir_node *t = proj_true;
3584 proj_true = proj_false;
3586 pnc = ia32_get_negated_pnc(pnc);
3589 dest_true = get_cfop_target_block(proj_true);
3590 dest_false = get_cfop_target_block(proj_false);
3592 if (pnc & ia32_pn_Cmp_float) {
3593 /* Some floating point comparisons require a test of the parity flag,
3594 * which indicates that the result is unordered */
3597 bemit_jp(false, dest_true);
3602 bemit_jp(true, dest_true);
3608 /* we need a local label if the false proj is a fallthrough
3609 * as the falseblock might have no label emitted then */
3610 if (can_be_fallthrough(proj_false)) {
3612 bemit8(0x06); // jp + 6
3614 bemit_jp(false, dest_false);
3621 bemit_jp(false, dest_true);
3629 bemit_jcc(pnc, dest_true);
3632 /* the second Proj might be a fallthrough */
3633 if (can_be_fallthrough(proj_false)) {
3634 /* it's a fallthrough */
3636 bemit_jmp(dest_false);
3640 static void bemit_switchjmp(const ir_node *node)
3642 unsigned long interval;
3646 const arch_register_t *in;
3648 /* fill the table structure */
3649 generate_jump_table(&tbl, node);
3651 /* two-complement's magic make this work without overflow */
3652 interval = tbl.max_value - tbl.min_value;
3654 in = get_in_reg(node, 0);
3655 /* emit the table */
3656 if (get_signed_imm_size(interval) == 1) {
3657 bemit8(0x83); // cmpl $imm8, %in
3661 bemit8(0x81); // cmpl $imm32, %in
3665 bemit8(0x0F); // ja tbl.defProj
3667 ia32_emitf(tbl.defProj, ".long %L - . - 4\n");
3669 if (tbl.num_branches > 1) {
3671 bemit8(0xFF); // jmp *tbl.label(,%in,4)
3672 bemit8(MOD_IND | ENC_REG(4) | ENC_RM(0x04));
3673 bemit8(ENC_SIB(2, reg_gp_map[in->index], 0x05));
3674 be_emit_irprintf("\t.long %s\n", tbl.label);
3676 be_gas_emit_switch_section(GAS_SECTION_RODATA);
3677 be_emit_cstring(".align 4\n");
3678 be_emit_irprintf("%s:\n", tbl.label);
3680 last_value = tbl.branches[0].value;
3681 for (i = 0; i != tbl.num_branches; ++i) {
3682 while (last_value != tbl.branches[i].value) {
3683 ia32_emitf(tbl.defProj, ".long %L\n");
3686 ia32_emitf(tbl.branches[i].target, ".long %L\n");
3689 be_gas_emit_switch_section(GAS_SECTION_TEXT);
3691 /* one jump is enough */
3692 panic("switch only has one case");
3693 //ia32_emitf(tbl.branches[0].target, "\tjmp %L\n");
3696 be_emit_write_line();
3704 static void bemit_return(const ir_node *node)
3706 unsigned pop = be_Return_get_pop(node);
3707 if (pop > 0 || be_Return_get_emit_pop(node)) {
3709 assert(pop <= 0xffff);
3716 static void bemit_subsp(const ir_node *node)
3718 const arch_register_t *out;
3721 /* mov %esp, %out */
3723 out = get_out_reg(node, 1);
3724 bemit8(MOD_REG | ENC_REG(reg_gp_map[out->index]) | ENC_RM(0x04));
3727 static void bemit_incsp(const ir_node *node)
3730 const arch_register_t *reg;
3734 offs = be_get_IncSP_offset(node);
3745 size = get_signed_imm_size(offs);
3746 bemit8(size == 1 ? 0x83 : 0x81);
3748 reg = get_out_reg(node, 0);
3749 bemit_modru(reg, ext);
3758 static void bemit_copybi(const ir_node *node)
3760 unsigned size = get_ia32_copyb_size(node);
3762 bemit8(0xA4); // movsb
3765 bemit8(0xA5); // movsw
3769 bemit8(0xA5); // movsl
3773 static void bemit_fbinop(const ir_node *node, unsigned code, unsigned code_to)
3775 if (get_ia32_op_type(node) == ia32_Normal) {
3776 const ia32_x87_attr_t *x87_attr = get_ia32_x87_attr_const(node);
3777 const arch_register_t *in1 = x87_attr->x87[0];
3778 const arch_register_t *in = x87_attr->x87[1];
3779 const arch_register_t *out = x87_attr->x87[2];
3783 } else if (out == in) {
3787 if (out->index == 0) {
3789 bemit8(MOD_REG | ENC_REG(code) | ENC_RM(in->index));
3792 bemit8(MOD_REG | ENC_REG(code_to) | ENC_RM(out->index));
3795 if (get_mode_size_bits(get_ia32_ls_mode(node)) == 32) {
3800 bemit_mod_am(code, node);
3804 static void bemit_fbinopp(const ir_node *node, unsigned const code)
3806 const ia32_x87_attr_t *x87_attr = get_ia32_x87_attr_const(node);
3807 const arch_register_t *out = x87_attr->x87[2];
3809 bemit8(code + out->index);
3812 static void bemit_fabs(const ir_node *node)
3820 static void bemit_fadd(const ir_node *node)
3822 bemit_fbinop(node, 0, 0);
3825 static void bemit_faddp(const ir_node *node)
3827 bemit_fbinopp(node, 0xC0);
3830 static void bemit_fchs(const ir_node *node)
3838 static void bemit_fdiv(const ir_node *node)
3840 bemit_fbinop(node, 6, 7);
3843 static void bemit_fdivp(const ir_node *node)
3845 bemit_fbinopp(node, 0xF8);
3848 static void bemit_fdivr(const ir_node *node)
3850 bemit_fbinop(node, 7, 6);
3853 static void bemit_fdivrp(const ir_node *node)
3855 bemit_fbinopp(node, 0xF0);
3858 static void bemit_fild(const ir_node *node)
3860 switch (get_mode_size_bits(get_ia32_ls_mode(node))) {
3862 bemit8(0xDF); // filds
3863 bemit_mod_am(0, node);
3867 bemit8(0xDB); // fildl
3868 bemit_mod_am(0, node);
3872 bemit8(0xDF); // fildll
3873 bemit_mod_am(5, node);
3877 panic("invalid mode size");
3881 static void bemit_fist(const ir_node *node)
3883 switch (get_mode_size_bits(get_ia32_ls_mode(node))) {
3885 bemit8(0xDF); // fists
3889 bemit8(0xDB); // fistl
3893 panic("invalid mode size");
3895 bemit_mod_am(2, node);
3898 static void bemit_fistp(const ir_node *node)
3900 switch (get_mode_size_bits(get_ia32_ls_mode(node))) {
3902 bemit8(0xDF); // fistps
3903 bemit_mod_am(3, node);
3907 bemit8(0xDB); // fistpl
3908 bemit_mod_am(3, node);
3912 bemit8(0xDF); // fistpll
3913 bemit_mod_am(7, node);
3917 panic("invalid mode size");
3921 static void bemit_fld(const ir_node *node)
3923 switch (get_mode_size_bits(get_ia32_ls_mode(node))) {
3925 bemit8(0xD9); // flds
3926 bemit_mod_am(0, node);
3930 bemit8(0xDD); // fldl
3931 bemit_mod_am(0, node);
3936 bemit8(0xDB); // fldt
3937 bemit_mod_am(5, node);
3941 panic("invalid mode size");
3945 static void bemit_fld1(const ir_node *node)
3949 bemit8(0xE8); // fld1
3952 static void bemit_fldcw(const ir_node *node)
3954 bemit8(0xD9); // fldcw
3955 bemit_mod_am(5, node);
3958 static void bemit_fldz(const ir_node *node)
3962 bemit8(0xEE); // fldz
3965 static void bemit_fmul(const ir_node *node)
3967 bemit_fbinop(node, 1, 1);
3970 static void bemit_fmulp(const ir_node *node)
3972 bemit_fbinopp(node, 0xC8);
3975 static void bemit_fpop(const ir_node *node)
3977 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
3979 bemit8(0xD8 + attr->x87[0]->index);
3982 static void bemit_fpush(const ir_node *node)
3984 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
3986 bemit8(0xC0 + attr->x87[0]->index);
3989 static void bemit_fpushcopy(const ir_node *node)
3991 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
3993 bemit8(0xC0 + attr->x87[0]->index);
3996 static void bemit_fst(const ir_node *node)
3998 switch (get_mode_size_bits(get_ia32_ls_mode(node))) {
4000 bemit8(0xD9); // fsts
4004 bemit8(0xDD); // fstl
4008 panic("invalid mode size");
4010 bemit_mod_am(2, node);
4013 static void bemit_fstp(const ir_node *node)
4015 switch (get_mode_size_bits(get_ia32_ls_mode(node))) {
4017 bemit8(0xD9); // fstps
4018 bemit_mod_am(3, node);
4022 bemit8(0xDD); // fstpl
4023 bemit_mod_am(3, node);
4028 bemit8(0xDB); // fstpt
4029 bemit_mod_am(7, node);
4033 panic("invalid mode size");
4037 static void bemit_fsub(const ir_node *node)
4039 bemit_fbinop(node, 4, 5);
4042 static void bemit_fsubp(const ir_node *node)
4044 bemit_fbinopp(node, 0xE8);
4047 static void bemit_fsubr(const ir_node *node)
4049 bemit_fbinop(node, 5, 4);
4052 static void bemit_fsubrp(const ir_node *node)
4054 bemit_fbinopp(node, 0xE0);
4057 static void bemit_fnstcw(const ir_node *node)
4059 bemit8(0xD9); // fnstcw
4060 bemit_mod_am(7, node);
4063 static void bemit_fnstsw(void)
4065 bemit8(0xDF); // fnstsw %ax
4069 static void bemit_ftstfnstsw(const ir_node *node)
4073 bemit8(0xD9); // ftst
4078 static void bemit_fucomi(const ir_node *node)
4080 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
4081 bemit8(0xDB); // fucomi
4082 bemit8(0xE8 + attr->x87[1]->index);
4085 static void bemit_fucomip(const ir_node *node)
4087 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
4088 bemit8(0xDF); // fucomip
4089 bemit8(0xE8 + attr->x87[1]->index);
4092 static void bemit_fucomfnstsw(const ir_node *node)
4094 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
4095 bemit8(0xDD); // fucom
4096 bemit8(0xE0 + attr->x87[1]->index);
4100 static void bemit_fucompfnstsw(const ir_node *node)
4102 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
4103 bemit8(0xDD); // fucomp
4104 bemit8(0xE8 + attr->x87[1]->index);
4108 static void bemit_fucomppfnstsw(const ir_node *node)
4112 bemit8(0xDA); // fucompp
4117 static void bemit_fxch(const ir_node *node)
4119 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
4121 bemit8(0xC8 + attr->x87[0]->index);
4125 * The type of a emitter function.
4127 typedef void (*emit_func) (const ir_node *);
4130 * Set a node emitter. Make it a bit more type safe.
4132 static void register_emitter(ir_op *op, emit_func func)
4134 op->ops.generic = (op_func) func;
4137 static void ia32_register_binary_emitters(void)
4139 /* first clear the generic function pointer for all ops */
4140 clear_irp_opcodes_generic_func();
4142 /* benode emitter */
4143 register_emitter(op_be_Copy, bemit_copy);
4144 register_emitter(op_be_CopyKeep, bemit_copy);
4145 register_emitter(op_be_IncSP, bemit_incsp);
4146 register_emitter(op_be_Perm, bemit_perm);
4147 register_emitter(op_be_Return, bemit_return);
4148 register_emitter(op_ia32_Adc, bemit_adc);
4149 register_emitter(op_ia32_Add, bemit_add);
4150 register_emitter(op_ia32_AddMem, bemit_addmem);
4151 register_emitter(op_ia32_AddMem8Bit, bemit_addmem8bit);
4152 register_emitter(op_ia32_And, bemit_and);
4153 register_emitter(op_ia32_AndMem, bemit_andmem);
4154 register_emitter(op_ia32_AndMem8Bit, bemit_andmem8bit);
4155 register_emitter(op_ia32_Breakpoint, bemit_int3);
4156 register_emitter(op_ia32_CMovcc, bemit_cmovcc);
4157 register_emitter(op_ia32_Call, bemit_call);
4158 register_emitter(op_ia32_Cltd, bemit_cltd);
4159 register_emitter(op_ia32_Cmc, bemit_cmc);
4160 register_emitter(op_ia32_Cmp, bemit_cmp);
4161 register_emitter(op_ia32_Cmp8Bit, bemit_cmp8bit);
4162 register_emitter(op_ia32_Const, bemit_mov_const);
4163 register_emitter(op_ia32_Conv_I2I, bemit_conv_i2i);
4164 register_emitter(op_ia32_Conv_I2I8Bit, bemit_conv_i2i);
4165 register_emitter(op_ia32_CopyB_i, bemit_copybi);
4166 register_emitter(op_ia32_Cwtl, bemit_cwtl);
4167 register_emitter(op_ia32_Dec, bemit_dec);
4168 register_emitter(op_ia32_DecMem, bemit_decmem);
4169 register_emitter(op_ia32_Div, bemit_div);
4170 register_emitter(op_ia32_FldCW, bemit_fldcw);
4171 register_emitter(op_ia32_FnstCW, bemit_fnstcw);
4172 register_emitter(op_ia32_FtstFnstsw, bemit_ftstfnstsw);
4173 register_emitter(op_ia32_FucomFnstsw, bemit_fucomfnstsw);
4174 register_emitter(op_ia32_Fucomi, bemit_fucomi);
4175 register_emitter(op_ia32_FucompFnstsw, bemit_fucompfnstsw);
4176 register_emitter(op_ia32_Fucompi, bemit_fucomip);
4177 register_emitter(op_ia32_FucomppFnstsw, bemit_fucomppfnstsw);
4178 register_emitter(op_ia32_IDiv, bemit_idiv);
4179 register_emitter(op_ia32_IJmp, bemit_ijmp);
4180 register_emitter(op_ia32_IMul, bemit_imul);
4181 register_emitter(op_ia32_IMul1OP, bemit_imul1op);
4182 register_emitter(op_ia32_Inc, bemit_inc);
4183 register_emitter(op_ia32_IncMem, bemit_incmem);
4184 register_emitter(op_ia32_Jcc, bemit_ia32_jcc);
4185 register_emitter(op_ia32_Jmp, bemit_jump);
4186 register_emitter(op_ia32_LdTls, bemit_ldtls);
4187 register_emitter(op_ia32_Lea, bemit_lea);
4188 register_emitter(op_ia32_Leave, bemit_leave);
4189 register_emitter(op_ia32_Load, bemit_load);
4190 register_emitter(op_ia32_Minus64Bit, bemit_minus64bit);
4191 register_emitter(op_ia32_Mul, bemit_mul);
4192 register_emitter(op_ia32_Neg, bemit_neg);
4193 register_emitter(op_ia32_NegMem, bemit_negmem);
4194 register_emitter(op_ia32_Not, bemit_not);
4195 register_emitter(op_ia32_NotMem, bemit_notmem);
4196 register_emitter(op_ia32_Or, bemit_or);
4197 register_emitter(op_ia32_OrMem, bemit_ormem);
4198 register_emitter(op_ia32_OrMem8Bit, bemit_ormem8bit);
4199 register_emitter(op_ia32_Pop, bemit_pop);
4200 register_emitter(op_ia32_PopEbp, bemit_pop);
4201 register_emitter(op_ia32_PopMem, bemit_popmem);
4202 register_emitter(op_ia32_Push, bemit_push);
4203 register_emitter(op_ia32_RepPrefix, bemit_rep);
4204 register_emitter(op_ia32_Rol, bemit_rol);
4205 register_emitter(op_ia32_RolMem, bemit_rolmem);
4206 register_emitter(op_ia32_Ror, bemit_ror);
4207 register_emitter(op_ia32_RorMem, bemit_rormem);
4208 register_emitter(op_ia32_Sahf, bemit_sahf);
4209 register_emitter(op_ia32_Sar, bemit_sar);
4210 register_emitter(op_ia32_SarMem, bemit_sarmem);
4211 register_emitter(op_ia32_Sbb, bemit_sbb);
4212 register_emitter(op_ia32_Setcc, bemit_setcc);
4213 register_emitter(op_ia32_Shl, bemit_shl);
4214 register_emitter(op_ia32_ShlD, bemit_shld);
4215 register_emitter(op_ia32_ShlMem, bemit_shlmem);
4216 register_emitter(op_ia32_Shr, bemit_shr);
4217 register_emitter(op_ia32_ShrD, bemit_shrd);
4218 register_emitter(op_ia32_ShrMem, bemit_shrmem);
4219 register_emitter(op_ia32_Stc, bemit_stc);
4220 register_emitter(op_ia32_Store, bemit_store);
4221 register_emitter(op_ia32_Store8Bit, bemit_store);
4222 register_emitter(op_ia32_Sub, bemit_sub);
4223 register_emitter(op_ia32_SubMem, bemit_submem);
4224 register_emitter(op_ia32_SubMem8Bit, bemit_submem8bit);
4225 register_emitter(op_ia32_SubSP, bemit_subsp);
4226 register_emitter(op_ia32_SwitchJmp, bemit_switchjmp);
4227 register_emitter(op_ia32_Test, bemit_test);
4228 register_emitter(op_ia32_Test8Bit, bemit_test8bit);
4229 register_emitter(op_ia32_Xor, bemit_xor);
4230 register_emitter(op_ia32_Xor0, bemit_xor0);
4231 register_emitter(op_ia32_XorMem, bemit_xormem);
4232 register_emitter(op_ia32_XorMem8Bit, bemit_xormem8bit);
4233 register_emitter(op_ia32_fabs, bemit_fabs);
4234 register_emitter(op_ia32_fadd, bemit_fadd);
4235 register_emitter(op_ia32_faddp, bemit_faddp);
4236 register_emitter(op_ia32_fchs, bemit_fchs);
4237 register_emitter(op_ia32_fdiv, bemit_fdiv);
4238 register_emitter(op_ia32_fdivp, bemit_fdivp);
4239 register_emitter(op_ia32_fdivr, bemit_fdivr);
4240 register_emitter(op_ia32_fdivrp, bemit_fdivrp);
4241 register_emitter(op_ia32_fild, bemit_fild);
4242 register_emitter(op_ia32_fist, bemit_fist);
4243 register_emitter(op_ia32_fistp, bemit_fistp);
4244 register_emitter(op_ia32_fld, bemit_fld);
4245 register_emitter(op_ia32_fld1, bemit_fld1);
4246 register_emitter(op_ia32_fldz, bemit_fldz);
4247 register_emitter(op_ia32_fmul, bemit_fmul);
4248 register_emitter(op_ia32_fmulp, bemit_fmulp);
4249 register_emitter(op_ia32_fpop, bemit_fpop);
4250 register_emitter(op_ia32_fpush, bemit_fpush);
4251 register_emitter(op_ia32_fpushCopy, bemit_fpushcopy);
4252 register_emitter(op_ia32_fst, bemit_fst);
4253 register_emitter(op_ia32_fstp, bemit_fstp);
4254 register_emitter(op_ia32_fsub, bemit_fsub);
4255 register_emitter(op_ia32_fsubp, bemit_fsubp);
4256 register_emitter(op_ia32_fsubr, bemit_fsubr);
4257 register_emitter(op_ia32_fsubrp, bemit_fsubrp);
4258 register_emitter(op_ia32_fxch, bemit_fxch);
4260 /* ignore the following nodes */
4261 register_emitter(op_ia32_ProduceVal, emit_Nothing);
4262 register_emitter(op_be_Barrier, emit_Nothing);
4263 register_emitter(op_be_Keep, emit_Nothing);
4264 register_emitter(op_be_Start, emit_Nothing);
4265 register_emitter(op_Phi, emit_Nothing);
4266 register_emitter(op_Start, emit_Nothing);
4269 static void gen_binary_block(ir_node *block)
4273 ia32_emit_block_header(block);
4275 /* emit the contents of the block */
4276 sched_foreach(block, node) {
4277 ia32_emit_node(node);
4281 void ia32_gen_binary_routine(ia32_code_gen_t *ia32_cg, ir_graph *irg)
4283 ir_entity *entity = get_irg_entity(irg);
4289 ia32_register_binary_emitters();
4291 be_gas_emit_function_prolog(entity, ia32_cg_config.function_alignment);
4293 /* we use links to point to target blocks */
4294 ir_reserve_resources(irg, IR_RESOURCE_IRN_LINK);
4295 irg_block_walk_graph(irg, ia32_gen_labels, NULL, NULL);
4297 /* initialize next block links */
4298 n = ARR_LEN(cg->blk_sched);
4299 for (i = 0; i < n; ++i) {
4300 ir_node *block = cg->blk_sched[i];
4301 ir_node *prev = i > 0 ? cg->blk_sched[i-1] : NULL;
4303 set_irn_link(block, prev);
4306 for (i = 0; i < n; ++i) {
4307 ir_node *block = cg->blk_sched[i];
4308 gen_binary_block(block);
4311 be_gas_emit_function_epilog(entity);
4312 be_dbg_method_end();
4314 be_emit_write_line();
4316 ir_free_resources(irg, IR_RESOURCE_IRN_LINK);
4322 void ia32_init_emitter(void)
4324 lc_opt_entry_t *be_grp;
4325 lc_opt_entry_t *ia32_grp;
4327 be_grp = lc_opt_get_grp(firm_opt_get_root(), "be");
4328 ia32_grp = lc_opt_get_grp(be_grp, "ia32");
4330 lc_opt_add_table(ia32_grp, ia32_emitter_options);
4334 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.emitter");