2 * Copyright (C) 1995-2011 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This file implements the ia32 node emitter.
23 * @author Christian Wuerdig, Matthias Braun
26 * Summary table for x86 floatingpoint compares:
27 * (remember effect of unordered on x86: ZF=1, PF=1, CF=1)
35 * pnc_Leg => NP (ordered)
57 #include "iredges_t.h"
61 #include "raw_bitset.h"
65 #include "../besched.h"
66 #include "../benode.h"
68 #include "../be_dbgout.h"
69 #include "../beemitter.h"
70 #include "../begnuas.h"
72 #include "../be_dbgout.h"
74 #include "ia32_emitter.h"
75 #include "ia32_common_transform.h"
76 #include "gen_ia32_emitter.h"
77 #include "gen_ia32_regalloc_if.h"
78 #include "ia32_nodes_attr.h"
79 #include "ia32_new_nodes.h"
80 #include "ia32_architecture.h"
81 #include "bearch_ia32_t.h"
83 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
85 #define SNPRINTF_BUF_LEN 128
87 static const ia32_isa_t *isa;
88 static char pic_base_label[128];
89 static ir_label_t exc_label_id;
90 static int mark_spill_reload = 0;
93 /** Return the next block in Block schedule */
94 static ir_node *get_prev_block_sched(const ir_node *block)
96 return (ir_node*)get_irn_link(block);
99 /** Checks if the current block is a fall-through target. */
100 static int is_fallthrough(const ir_node *cfgpred)
104 if (!is_Proj(cfgpred))
106 pred = get_Proj_pred(cfgpred);
107 if (is_ia32_SwitchJmp(pred))
114 * returns non-zero if the given block needs a label
115 * because of being a jump-target (and not a fall-through)
117 static int block_needs_label(const ir_node *block)
120 int n_cfgpreds = get_Block_n_cfgpreds(block);
122 if (has_Block_entity(block))
125 if (n_cfgpreds == 0) {
127 } else if (n_cfgpreds == 1) {
128 ir_node *cfgpred = get_Block_cfgpred(block, 0);
129 ir_node *cfgpred_block = get_nodes_block(cfgpred);
131 if (get_prev_block_sched(block) == cfgpred_block
132 && is_fallthrough(cfgpred)) {
141 * Returns the register at in position pos.
143 static const arch_register_t *get_in_reg(const ir_node *irn, int pos)
146 const arch_register_t *reg = NULL;
148 assert(get_irn_arity(irn) > pos && "Invalid IN position");
150 /* The out register of the operator at position pos is the
151 in register we need. */
152 op = get_irn_n(irn, pos);
154 reg = arch_get_irn_register(op);
156 assert(reg && "no in register found");
158 if (reg == &ia32_registers[REG_GP_NOREG])
159 panic("trying to emit noreg for %+F input %d", irn, pos);
165 * Returns the register at out position pos.
167 static const arch_register_t *get_out_reg(const ir_node *irn, int pos)
170 const arch_register_t *reg = NULL;
172 /* 1st case: irn is not of mode_T, so it has only */
173 /* one OUT register -> good */
174 /* 2nd case: irn is of mode_T -> collect all Projs and ask the */
175 /* Proj with the corresponding projnum for the register */
177 if (get_irn_mode(irn) != mode_T) {
179 reg = arch_get_irn_register(irn);
180 } else if (is_ia32_irn(irn)) {
181 reg = arch_irn_get_register(irn, pos);
183 const ir_edge_t *edge;
185 foreach_out_edge(irn, edge) {
186 proj = get_edge_src_irn(edge);
187 assert(is_Proj(proj) && "non-Proj from mode_T node");
188 if (get_Proj_proj(proj) == pos) {
189 reg = arch_get_irn_register(proj);
195 assert(reg && "no out register found");
200 * Add a number to a prefix. This number will not be used a second time.
202 static char *get_unique_label(char *buf, size_t buflen, const char *prefix)
204 static unsigned long id = 0;
205 snprintf(buf, buflen, "%s%s%lu", be_gas_get_private_prefix(), prefix, ++id);
210 * Emit the name of the 8bit low register
212 static void emit_8bit_register(const arch_register_t *reg)
214 const char *reg_name = arch_register_get_name(reg);
215 assert(reg->index == REG_GP_EAX || reg->index == REG_GP_EBX
216 || reg->index == REG_GP_ECX || reg->index == REG_GP_EDX);
219 be_emit_char(reg_name[1]); /* get the basic name of the register */
224 * Emit the name of the 8bit high register
226 static void emit_8bit_register_high(const arch_register_t *reg)
228 const char *reg_name = arch_register_get_name(reg);
229 assert(reg->index == REG_GP_EAX || reg->index == REG_GP_EBX
230 || reg->index == REG_GP_ECX || reg->index == REG_GP_EDX);
233 be_emit_char(reg_name[1]); /* get the basic name of the register */
237 static void emit_16bit_register(const arch_register_t *reg)
239 const char *reg_name = arch_register_get_name(reg);
242 be_emit_string(reg_name+1); /* skip the 'e' prefix of the 32bit names */
246 * emit a register, possible shortened by a mode
248 * @param reg the register
249 * @param mode the mode of the register or NULL for full register
251 static void emit_register(const arch_register_t *reg, const ir_mode *mode)
253 const char *reg_name;
256 int size = get_mode_size_bits(mode);
258 case 8: emit_8bit_register(reg); return;
259 case 16: emit_16bit_register(reg); return;
261 assert(mode_is_float(mode) || size == 32);
264 reg_name = arch_register_get_name(reg);
267 be_emit_string(reg_name);
270 void ia32_emit_source_register(const ir_node *node, int pos)
272 const arch_register_t *reg = get_in_reg(node, pos);
274 emit_register(reg, NULL);
277 static void ia32_emit_entity(ir_entity *entity, int no_pic_adjust)
279 be_gas_emit_entity(entity);
281 if (get_entity_owner(entity) == get_tls_type()) {
282 if (get_entity_visibility(entity) == ir_visibility_external) {
283 be_emit_cstring("@INDNTPOFF");
285 be_emit_cstring("@NTPOFF");
289 if (do_pic && !no_pic_adjust) {
291 be_emit_string(pic_base_label);
295 static void emit_ia32_Immediate_no_prefix(const ir_node *node)
297 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(node);
299 if (attr->symconst != NULL) {
302 ia32_emit_entity(attr->symconst, attr->no_pic_adjust);
304 if (attr->symconst == NULL || attr->offset != 0) {
305 if (attr->symconst != NULL) {
306 be_emit_irprintf("%+d", attr->offset);
308 be_emit_irprintf("0x%X", attr->offset);
313 static void emit_ia32_Immediate(const ir_node *node)
316 emit_ia32_Immediate_no_prefix(node);
319 void ia32_emit_8bit_source_register_or_immediate(const ir_node *node, int pos)
321 const arch_register_t *reg;
322 const ir_node *in = get_irn_n(node, pos);
323 if (is_ia32_Immediate(in)) {
324 emit_ia32_Immediate(in);
328 reg = get_in_reg(node, pos);
329 emit_8bit_register(reg);
332 void ia32_emit_8bit_high_source_register(const ir_node *node, int pos)
334 const arch_register_t *reg = get_in_reg(node, pos);
335 emit_8bit_register_high(reg);
338 void ia32_emit_16bit_source_register_or_immediate(const ir_node *node, int pos)
340 const arch_register_t *reg;
341 const ir_node *in = get_irn_n(node, pos);
342 if (is_ia32_Immediate(in)) {
343 emit_ia32_Immediate(in);
347 reg = get_in_reg(node, pos);
348 emit_16bit_register(reg);
351 void ia32_emit_dest_register(const ir_node *node, int pos)
353 const arch_register_t *reg = get_out_reg(node, pos);
355 emit_register(reg, NULL);
358 void ia32_emit_dest_register_size(const ir_node *node, int pos)
360 const arch_register_t *reg = get_out_reg(node, pos);
362 emit_register(reg, get_ia32_ls_mode(node));
365 void ia32_emit_8bit_dest_register(const ir_node *node, int pos)
367 const arch_register_t *reg = get_out_reg(node, pos);
369 emit_register(reg, mode_Bu);
372 void ia32_emit_x87_register(const ir_node *node, int pos)
374 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
378 be_emit_string(attr->x87[pos]->name);
381 static void ia32_emit_mode_suffix_mode(const ir_mode *mode)
383 assert(mode_is_int(mode) || mode_is_reference(mode));
384 switch (get_mode_size_bits(mode)) {
385 case 8: be_emit_char('b'); return;
386 case 16: be_emit_char('w'); return;
387 case 32: be_emit_char('l'); return;
388 /* gas docu says q is the suffix but gcc, objdump and icc use ll
390 case 64: be_emit_cstring("ll"); return;
392 panic("Can't output mode_suffix for %+F", mode);
395 void ia32_emit_mode_suffix(const ir_node *node)
397 ir_mode *mode = get_ia32_ls_mode(node);
401 ia32_emit_mode_suffix_mode(mode);
404 void ia32_emit_x87_mode_suffix(const ir_node *node)
408 /* we only need to emit the mode on address mode */
409 if (get_ia32_op_type(node) == ia32_Normal)
412 mode = get_ia32_ls_mode(node);
413 assert(mode != NULL);
415 if (mode_is_float(mode)) {
416 switch (get_mode_size_bits(mode)) {
417 case 32: be_emit_char('s'); return;
418 case 64: be_emit_char('l'); return;
419 /* long doubles have different sizes due to alignment on different
423 case 128: be_emit_char('t'); return;
426 assert(mode_is_int(mode) || mode_is_reference(mode));
427 switch (get_mode_size_bits(mode)) {
428 case 16: be_emit_char('s'); return;
429 case 32: be_emit_char('l'); return;
430 /* gas docu says q is the suffix but gcc, objdump and icc use ll
432 case 64: be_emit_cstring("ll"); return;
435 panic("Can't output mode_suffix for %+F", mode);
438 static char get_xmm_mode_suffix(ir_mode *mode)
440 assert(mode_is_float(mode));
441 switch (get_mode_size_bits(mode)) {
444 default: panic("Invalid XMM mode");
448 void ia32_emit_xmm_mode_suffix(const ir_node *node)
450 ir_mode *mode = get_ia32_ls_mode(node);
451 assert(mode != NULL);
453 be_emit_char(get_xmm_mode_suffix(mode));
456 void ia32_emit_xmm_mode_suffix_s(const ir_node *node)
458 ir_mode *mode = get_ia32_ls_mode(node);
459 assert(mode != NULL);
460 be_emit_char(get_xmm_mode_suffix(mode));
463 void ia32_emit_extend_suffix(const ir_node *node)
465 ir_mode *mode = get_ia32_ls_mode(node);
466 if (get_mode_size_bits(mode) == 32)
468 be_emit_char(mode_is_signed(mode) ? 's' : 'z');
469 ia32_emit_mode_suffix_mode(mode);
472 void ia32_emit_source_register_or_immediate(const ir_node *node, int pos)
474 ir_node *in = get_irn_n(node, pos);
475 if (is_ia32_Immediate(in)) {
476 emit_ia32_Immediate(in);
478 const ir_mode *mode = get_ia32_ls_mode(node);
479 const arch_register_t *reg = get_in_reg(node, pos);
480 emit_register(reg, mode);
485 * Returns the target block for a control flow node.
487 static ir_node *get_cfop_target_block(const ir_node *irn)
489 assert(get_irn_mode(irn) == mode_X);
490 return (ir_node*)get_irn_link(irn);
494 * Emits the target label for a control flow node.
496 static void ia32_emit_cfop_target(const ir_node *node)
498 ir_node *block = get_cfop_target_block(node);
499 be_gas_emit_block_name(block);
503 * Emit the suffix for a compare instruction.
505 static void ia32_emit_condition_code(ia32_condition_code_t cc)
508 case ia32_cc_overflow: be_emit_cstring("o"); return;
509 case ia32_cc_not_overflow: be_emit_cstring("no"); return;
510 case ia32_cc_float_below:
511 case ia32_cc_float_unordered_below:
512 case ia32_cc_below: be_emit_cstring("b"); return;
513 case ia32_cc_float_above_equal:
514 case ia32_cc_float_unordered_above_equal:
515 case ia32_cc_above_equal: be_emit_cstring("ae"); return;
516 case ia32_cc_float_equal:
517 case ia32_cc_equal: be_emit_cstring("e"); return;
518 case ia32_cc_float_not_equal:
519 case ia32_cc_not_equal: be_emit_cstring("ne"); return;
520 case ia32_cc_float_below_equal:
521 case ia32_cc_float_unordered_below_equal:
522 case ia32_cc_below_equal: be_emit_cstring("be"); return;
523 case ia32_cc_float_above:
524 case ia32_cc_float_unordered_above:
525 case ia32_cc_above: be_emit_cstring("a"); return;
526 case ia32_cc_sign: be_emit_cstring("s"); return;
527 case ia32_cc_not_sign: be_emit_cstring("ns"); return;
528 case ia32_cc_parity: be_emit_cstring("p"); return;
529 case ia32_cc_not_parity: be_emit_cstring("np"); return;
530 case ia32_cc_less: be_emit_cstring("l"); return;
531 case ia32_cc_greater_equal: be_emit_cstring("ge"); return;
532 case ia32_cc_less_equal: be_emit_cstring("le"); return;
533 case ia32_cc_greater: be_emit_cstring("g"); return;
534 case ia32_cc_float_parity_cases:
535 case ia32_cc_additional_float_cases:
538 panic("Invalid ia32 condition code");
541 typedef enum ia32_emit_mod_t {
543 EMIT_RESPECT_LS = 1U << 0,
544 EMIT_ALTERNATE_AM = 1U << 1,
546 EMIT_HIGH_REG = 1U << 3,
547 EMIT_LOW_REG = 1U << 4
549 ENUM_BITSET(ia32_emit_mod_t)
552 * Emits address mode.
554 void ia32_emit_am(const ir_node *node)
556 ir_entity *ent = get_ia32_am_sc(node);
557 int offs = get_ia32_am_offs_int(node);
558 ir_node *base = get_irn_n(node, n_ia32_base);
559 int has_base = !is_ia32_NoReg_GP(base);
560 ir_node *index = get_irn_n(node, n_ia32_index);
561 int has_index = !is_ia32_NoReg_GP(index);
563 /* just to be sure... */
564 assert(!is_ia32_use_frame(node) || get_ia32_frame_ent(node) != NULL);
566 if (get_ia32_am_tls_segment(node))
567 be_emit_cstring("%gs:");
571 const ia32_attr_t *attr = get_ia32_attr_const(node);
572 if (is_ia32_am_sc_sign(node))
574 ia32_emit_entity(ent, attr->data.am_sc_no_pic_adjust);
577 /* also handle special case if nothing is set */
578 if (offs != 0 || (ent == NULL && !has_base && !has_index)) {
580 be_emit_irprintf("%+d", offs);
582 be_emit_irprintf("%d", offs);
586 if (has_base || has_index) {
591 const arch_register_t *reg = get_in_reg(node, n_ia32_base);
592 emit_register(reg, NULL);
595 /* emit index + scale */
597 const arch_register_t *reg = get_in_reg(node, n_ia32_index);
600 emit_register(reg, NULL);
602 scale = get_ia32_am_scale(node);
604 be_emit_irprintf(",%d", 1 << scale);
612 * fmt parameter output
613 * ---- ---------------------- ---------------------------------------------
615 * %AM <node> address mode of the node
616 * %AR const arch_register_t* address mode of the node or register
617 * %ASx <node> address mode of the node or source register x
618 * %Dx <node> destination register x
619 * %I <node> immediate of the node
620 * %L <node> control flow target of the node
621 * %M <node> mode suffix of the node
622 * %P int condition code
623 * %R const arch_register_t* register
624 * %Sx <node> source register x
625 * %s const char* string
626 * %u unsigned int unsigned int
627 * %d signed int signed int
630 * # modifier for %ASx, %D, %R, and %S uses ls mode of node to alter register width
631 * * modifier does not prefix immediates with $, but AM with *
632 * l modifier for %lu and %ld
633 * > modifier to output high 8bit register (ah, bh)
634 * < modifier to output low 8bit register (al, bl)
636 static void ia32_emitf(const ir_node *node, const char *fmt, ...)
642 const char *start = fmt;
643 ia32_emit_mod_t mod = EMIT_NONE;
645 while (*fmt != '%' && *fmt != '\n' && *fmt != '\0')
648 be_emit_string_len(start, fmt - start);
652 be_emit_finish_line_gas(node);
665 case '*': mod |= EMIT_ALTERNATE_AM; break;
666 case '#': mod |= EMIT_RESPECT_LS; break;
667 case 'l': mod |= EMIT_LONG; break;
668 case '>': mod |= EMIT_HIGH_REG; break;
669 case '<': mod |= EMIT_LOW_REG; break;
686 if (mod & EMIT_ALTERNATE_AM)
692 const arch_register_t *reg = va_arg(ap, const arch_register_t*);
693 if (get_ia32_op_type(node) == ia32_AddrModeS) {
696 if (mod & EMIT_ALTERNATE_AM)
698 emit_register(reg, NULL);
704 if (get_ia32_op_type(node) == ia32_AddrModeS) {
708 assert(get_ia32_op_type(node) == ia32_Normal);
713 default: goto unknown;
720 const arch_register_t *reg;
722 if (*fmt < '0' || '9' <= *fmt)
726 reg = get_out_reg(node, pos);
727 emit_register(reg, mod & EMIT_RESPECT_LS ? get_ia32_ls_mode(node) : NULL);
732 if (!(mod & EMIT_ALTERNATE_AM))
734 emit_ia32_Immediate_no_prefix(node);
738 ia32_emit_cfop_target(node);
742 ia32_emit_mode_suffix_mode(get_ia32_ls_mode(node));
747 ia32_condition_code_t cc = va_arg(ap, ia32_condition_code_t);
748 ia32_emit_condition_code(cc);
753 const arch_register_t *reg = va_arg(ap, const arch_register_t*);
754 if (mod & EMIT_HIGH_REG) {
755 emit_8bit_register_high(reg);
756 } else if (mod & EMIT_LOW_REG) {
757 emit_8bit_register(reg);
759 emit_register(reg, mod & EMIT_RESPECT_LS ? get_ia32_ls_mode(node) : NULL);
769 if (*fmt < '0' || '9' <= *fmt)
773 in = get_irn_n(node, pos);
774 if (is_ia32_Immediate(in)) {
775 if (!(mod & EMIT_ALTERNATE_AM))
777 emit_ia32_Immediate_no_prefix(in);
779 const arch_register_t *reg;
781 if (mod & EMIT_ALTERNATE_AM)
783 reg = get_in_reg(node, pos);
784 emit_register(reg, mod & EMIT_RESPECT_LS ? get_ia32_ls_mode(node) : NULL);
790 const char *str = va_arg(ap, const char*);
796 if (mod & EMIT_LONG) {
797 unsigned long num = va_arg(ap, unsigned long);
798 be_emit_irprintf("%lu", num);
800 unsigned num = va_arg(ap, unsigned);
801 be_emit_irprintf("%u", num);
806 if (mod & EMIT_LONG) {
807 long num = va_arg(ap, long);
808 be_emit_irprintf("%ld", num);
810 int num = va_arg(ap, int);
811 be_emit_irprintf("%d", num);
817 panic("unknown format conversion in ia32_emitf()");
825 * Emits registers and/or address mode of a binary operation.
827 void ia32_emit_binop(const ir_node *node)
829 if (is_ia32_Immediate(get_irn_n(node, n_ia32_binary_right))) {
830 ia32_emitf(node, "%#S4, %#AS3");
832 ia32_emitf(node, "%#AS4, %#S3");
837 * Emits registers and/or address mode of a binary operation.
839 void ia32_emit_x87_binop(const ir_node *node)
841 switch (get_ia32_op_type(node)) {
844 const ia32_x87_attr_t *x87_attr = get_ia32_x87_attr_const(node);
845 const arch_register_t *in1 = x87_attr->x87[0];
846 const arch_register_t *in = x87_attr->x87[1];
847 const arch_register_t *out = x87_attr->x87[2];
851 } else if (out == in) {
856 be_emit_string(arch_register_get_name(in));
857 be_emit_cstring(", %");
858 be_emit_string(arch_register_get_name(out));
866 assert(0 && "unsupported op type");
871 * Emits registers and/or address mode of a unary operation.
873 void ia32_emit_unop(const ir_node *node, int pos)
877 ia32_emitf(node, fmt);
880 static void emit_ia32_IMul(const ir_node *node)
882 ir_node *left = get_irn_n(node, n_ia32_IMul_left);
883 const arch_register_t *out_reg = get_out_reg(node, pn_ia32_IMul_res);
885 /* do we need the 3-address form? */
886 if (is_ia32_NoReg_GP(left) ||
887 get_in_reg(node, n_ia32_IMul_left) != out_reg) {
888 ia32_emitf(node, "\timul%M %#S4, %#AS3, %#D0\n");
890 ia32_emitf(node, "\timul%M %#AS4, %#S3\n");
895 * walks up a tree of copies/perms/spills/reloads to find the original value
896 * that is moved around
898 static ir_node *find_original_value(ir_node *node)
900 if (irn_visited(node))
903 mark_irn_visited(node);
904 if (be_is_Copy(node)) {
905 return find_original_value(be_get_Copy_op(node));
906 } else if (be_is_CopyKeep(node)) {
907 return find_original_value(be_get_CopyKeep_op(node));
908 } else if (is_Proj(node)) {
909 ir_node *pred = get_Proj_pred(node);
910 if (be_is_Perm(pred)) {
911 return find_original_value(get_irn_n(pred, get_Proj_proj(node)));
912 } else if (be_is_MemPerm(pred)) {
913 return find_original_value(get_irn_n(pred, get_Proj_proj(node) + 1));
914 } else if (is_ia32_Load(pred)) {
915 return find_original_value(get_irn_n(pred, n_ia32_Load_mem));
916 } else if (is_ia32_Store(pred)) {
917 return find_original_value(get_irn_n(pred, n_ia32_Store_val));
921 } else if (is_Phi(node)) {
923 arity = get_irn_arity(node);
924 for (i = 0; i < arity; ++i) {
925 ir_node *in = get_irn_n(node, i);
926 ir_node *res = find_original_value(in);
937 static int determine_final_cc(const ir_node *node, int flags_pos, int cc)
939 ir_node *flags = get_irn_n(node, flags_pos);
940 const ia32_attr_t *flags_attr;
941 flags = skip_Proj(flags);
943 if (is_ia32_Sahf(flags)) {
944 ir_node *cmp = get_irn_n(flags, n_ia32_Sahf_val);
945 if (!(is_ia32_FucomFnstsw(cmp) || is_ia32_FucompFnstsw(cmp)
946 || is_ia32_FucomppFnstsw(cmp) || is_ia32_FtstFnstsw(cmp))) {
947 inc_irg_visited(current_ir_graph);
948 cmp = find_original_value(cmp);
950 assert(is_ia32_FucomFnstsw(cmp) || is_ia32_FucompFnstsw(cmp)
951 || is_ia32_FucomppFnstsw(cmp) || is_ia32_FtstFnstsw(cmp));
954 flags_attr = get_ia32_attr_const(cmp);
956 flags_attr = get_ia32_attr_const(flags);
959 if (flags_attr->data.ins_permuted)
960 cc = ia32_invert_condition_code(cc);
964 void ia32_emit_cmp_suffix_node(const ir_node *node, int flags_pos)
966 ia32_condition_code_t cc = get_ia32_condcode(node);
967 cc = determine_final_cc(node, flags_pos, cc);
969 ia32_emit_condition_code(cc);
973 * Emits an exception label for a given node.
975 static void ia32_emit_exc_label(const ir_node *node)
977 be_emit_string(be_gas_insn_label_prefix());
978 be_emit_irprintf("%lu", get_ia32_exc_label_id(node));
982 * Returns the Proj with projection number proj and NOT mode_M
984 static ir_node *get_proj(const ir_node *node, long proj)
986 const ir_edge_t *edge;
989 assert(get_irn_mode(node) == mode_T && "expected mode_T node");
991 foreach_out_edge(node, edge) {
992 src = get_edge_src_irn(edge);
994 assert(is_Proj(src) && "Proj expected");
995 if (get_irn_mode(src) == mode_M)
998 if (get_Proj_proj(src) == proj)
1004 static int can_be_fallthrough(const ir_node *node)
1006 ir_node *target_block = get_cfop_target_block(node);
1007 ir_node *block = get_nodes_block(node);
1008 return get_prev_block_sched(target_block) == block;
1012 * Emits the jump sequence for a conditional jump (cmp + jmp_true + jmp_false)
1014 static void emit_ia32_Jcc(const ir_node *node)
1016 int need_parity_label = 0;
1017 ia32_condition_code_t cc = get_ia32_condcode(node);
1018 const ir_node *proj_true;
1019 const ir_node *proj_false;
1021 cc = determine_final_cc(node, 0, cc);
1023 /* get both Projs */
1024 proj_true = get_proj(node, pn_ia32_Jcc_true);
1025 assert(proj_true && "Jcc without true Proj");
1027 proj_false = get_proj(node, pn_ia32_Jcc_false);
1028 assert(proj_false && "Jcc without false Proj");
1030 if (can_be_fallthrough(proj_true)) {
1031 /* exchange both proj's so the second one can be omitted */
1032 const ir_node *t = proj_true;
1034 proj_true = proj_false;
1036 cc = ia32_negate_condition_code(cc);
1039 if (cc & ia32_cc_float_parity_cases) {
1040 /* Some floating point comparisons require a test of the parity flag,
1041 * which indicates that the result is unordered */
1042 if (cc & ia32_cc_negated) {
1043 ia32_emitf(proj_true, "\tjp %L\n");
1045 /* we need a local label if the false proj is a fallthrough
1046 * as the falseblock might have no label emitted then */
1047 if (can_be_fallthrough(proj_false)) {
1048 need_parity_label = 1;
1049 ia32_emitf(proj_false, "\tjp 1f\n");
1051 ia32_emitf(proj_false, "\tjp %L\n");
1055 ia32_emitf(proj_true, "\tj%P %L\n", cc);
1056 if (need_parity_label) {
1057 ia32_emitf(NULL, "1:\n");
1060 /* the second Proj might be a fallthrough */
1061 if (can_be_fallthrough(proj_false)) {
1062 ia32_emitf(proj_false, "\t/* fallthrough to %L */\n");
1064 ia32_emitf(proj_false, "\tjmp %L\n");
1069 * Emits an ia32 Setcc. This is mostly easy but some floating point compares
1072 static void emit_ia32_Setcc(const ir_node *node)
1074 const arch_register_t *dreg = get_out_reg(node, pn_ia32_Setcc_res);
1076 ia32_condition_code_t cc = get_ia32_condcode(node);
1077 cc = determine_final_cc(node, n_ia32_Setcc_eflags, cc);
1078 if (cc & ia32_cc_float_parity_cases) {
1079 if (cc & ia32_cc_negated) {
1080 ia32_emitf(node, "\tset%P %<R\n", cc, dreg);
1081 ia32_emitf(node, "\tsetp %>R\n", dreg);
1082 ia32_emitf(node, "\torb %>R, %<R\n", dreg, dreg);
1084 ia32_emitf(node, "\tset%P %<R\n", cc, dreg);
1085 ia32_emitf(node, "\tsetnp %>R\n", dreg);
1086 ia32_emitf(node, "\tandb %>R, %<R\n", dreg, dreg);
1089 ia32_emitf(node, "\tset%P %#R\n", cc, dreg);
1093 static void emit_ia32_CMovcc(const ir_node *node)
1095 const ia32_attr_t *attr = get_ia32_attr_const(node);
1096 const arch_register_t *out = arch_irn_get_register(node, pn_ia32_res);
1097 ia32_condition_code_t cc = get_ia32_condcode(node);
1098 const arch_register_t *in_true;
1099 const arch_register_t *in_false;
1101 cc = determine_final_cc(node, n_ia32_CMovcc_eflags, cc);
1102 /* although you can't set ins_permuted in the constructor it might still
1103 * be set by memory operand folding
1104 * Permuting inputs of a cmov means the condition is negated!
1106 if (attr->data.ins_permuted)
1107 cc = ia32_negate_condition_code(cc);
1109 in_true = arch_get_irn_register(get_irn_n(node, n_ia32_CMovcc_val_true));
1110 in_false = arch_get_irn_register(get_irn_n(node, n_ia32_CMovcc_val_false));
1112 /* should be same constraint fullfilled? */
1113 if (out == in_false) {
1114 /* yes -> nothing to do */
1115 } else if (out == in_true) {
1116 const arch_register_t *tmp;
1118 assert(get_ia32_op_type(node) == ia32_Normal);
1120 cc = ia32_negate_condition_code(cc);
1127 ia32_emitf(node, "\tmovl %R, %R\n", in_false, out);
1130 if (cc & ia32_cc_float_parity_cases) {
1131 panic("CMov with floatingpoint compare/parity not supported yet");
1134 ia32_emitf(node, "\tcmov%P %#AR, %#R\n", cc, in_true, out);
1138 /* jump table entry (target and corresponding number) */
1139 typedef struct branch_t {
1144 /* jump table for switch generation */
1145 typedef struct jmp_tbl_t {
1146 ir_node *defProj; /**< default target */
1147 long min_value; /**< smallest switch case */
1148 long max_value; /**< largest switch case */
1149 long num_branches; /**< number of jumps */
1150 char label[SNPRINTF_BUF_LEN]; /**< label of the jump table */
1151 branch_t *branches; /**< jump array */
1155 * Compare two variables of type branch_t. Used to sort all switch cases
1157 static int ia32_cmp_branch_t(const void *a, const void *b)
1159 branch_t *b1 = (branch_t *)a;
1160 branch_t *b2 = (branch_t *)b;
1162 if (b1->value <= b2->value)
1168 static void generate_jump_table(jmp_tbl_t *tbl, const ir_node *node)
1171 long default_pn = get_ia32_default_pn(node);
1173 const ir_edge_t *edge;
1175 /* fill the table structure */
1176 get_unique_label(tbl->label, SNPRINTF_BUF_LEN, "TBL_");
1177 tbl->defProj = NULL;
1178 tbl->num_branches = get_irn_n_edges(node) - 1;
1179 tbl->branches = XMALLOCNZ(branch_t, tbl->num_branches);
1180 tbl->min_value = LONG_MAX;
1181 tbl->max_value = LONG_MIN;
1184 /* go over all proj's and collect them */
1185 foreach_out_edge(node, edge) {
1187 proj = get_edge_src_irn(edge);
1188 assert(is_Proj(proj) && "Only proj allowed at SwitchJmp");
1190 pn = get_Proj_proj(proj);
1192 /* check for default proj */
1193 if (pn == default_pn) {
1194 assert(tbl->defProj == NULL && "found two default Projs at SwitchJmp");
1195 tbl->defProj = proj;
1197 tbl->min_value = pn < tbl->min_value ? pn : tbl->min_value;
1198 tbl->max_value = pn > tbl->max_value ? pn : tbl->max_value;
1200 /* create branch entry */
1201 tbl->branches[i].target = proj;
1202 tbl->branches[i].value = pn;
1207 assert(i == tbl->num_branches);
1209 /* sort the branches by their number */
1210 qsort(tbl->branches, tbl->num_branches, sizeof(tbl->branches[0]), ia32_cmp_branch_t);
1214 * Emits code for a SwitchJmp (creates a jump table if
1215 * possible otherwise a cmp-jmp cascade). Port from
1218 static void emit_ia32_SwitchJmp(const ir_node *node)
1220 unsigned long interval;
1224 /* fill the table structure */
1225 generate_jump_table(&tbl, node);
1227 /* two-complement's magic make this work without overflow */
1228 interval = tbl.max_value - tbl.min_value;
1230 /* emit the table */
1231 ia32_emitf(node, "\tcmpl $%u, %S0\n", interval);
1232 ia32_emitf(tbl.defProj, "\tja %L\n");
1234 if (tbl.num_branches > 1) {
1236 ia32_emitf(node, "\tjmp *%s(,%S0,4)\n", tbl.label);
1238 be_gas_emit_switch_section(GAS_SECTION_RODATA);
1239 ia32_emitf(NULL, "\t.align 4\n");
1240 ia32_emitf(NULL, "%s:\n", tbl.label);
1242 last_value = tbl.branches[0].value;
1243 for (i = 0; i != tbl.num_branches; ++i) {
1244 while (last_value != tbl.branches[i].value) {
1245 ia32_emitf(tbl.defProj, ".long %L\n");
1248 ia32_emitf(tbl.branches[i].target, ".long %L\n");
1251 be_gas_emit_switch_section(GAS_SECTION_TEXT);
1253 /* one jump is enough */
1254 ia32_emitf(tbl.branches[0].target, "\tjmp %L\n");
1261 * Emits code for a unconditional jump.
1263 static void emit_ia32_Jmp(const ir_node *node)
1265 /* we have a block schedule */
1266 if (can_be_fallthrough(node)) {
1267 ia32_emitf(node, "\t/* fallthrough to %L */\n");
1269 ia32_emitf(node, "\tjmp %L\n");
1274 * Emit an inline assembler operand.
1276 * @param node the ia32_ASM node
1277 * @param s points to the operand (a %c)
1279 * @return pointer to the first char in s NOT in the current operand
1281 static const char* emit_asm_operand(const ir_node *node, const char *s)
1283 const ia32_attr_t *ia32_attr = get_ia32_attr_const(node);
1284 const ia32_asm_attr_t *attr = CONST_CAST_IA32_ATTR(ia32_asm_attr_t,
1286 const arch_register_t *reg;
1287 const ia32_asm_reg_t *asm_regs = attr->register_map;
1288 const ia32_asm_reg_t *asm_reg;
1297 /* parse modifiers */
1300 ir_fprintf(stderr, "Warning: asm text (%+F) ends with %%\n", node);
1325 "Warning: asm text (%+F) contains unknown modifier '%c' for asm op\n",
1332 if (sscanf(s, "%d%n", &num, &p) != 1) {
1333 ir_fprintf(stderr, "Warning: Couldn't parse assembler operand (%+F)\n",
1340 if (num < 0 || ARR_LEN(asm_regs) <= (size_t)num) {
1342 "Error: Custom assembler references invalid input/output (%+F)\n",
1346 asm_reg = & asm_regs[num];
1347 assert(asm_reg->valid);
1350 if (asm_reg->use_input == 0) {
1351 reg = get_out_reg(node, asm_reg->inout_pos);
1353 ir_node *pred = get_irn_n(node, asm_reg->inout_pos);
1355 /* might be an immediate value */
1356 if (is_ia32_Immediate(pred)) {
1357 emit_ia32_Immediate(pred);
1360 reg = get_in_reg(node, asm_reg->inout_pos);
1364 "Warning: no register assigned for %d asm op (%+F)\n",
1369 if (asm_reg->memory) {
1374 if (modifier != 0) {
1377 emit_8bit_register(reg);
1380 emit_8bit_register_high(reg);
1383 emit_16bit_register(reg);
1386 panic("Invalid asm op modifier");
1389 emit_register(reg, asm_reg->mode);
1392 if (asm_reg->memory) {
1400 * Emits code for an ASM pseudo op.
1402 static void emit_ia32_Asm(const ir_node *node)
1404 const void *gen_attr = get_irn_generic_attr_const(node);
1405 const ia32_asm_attr_t *attr
1406 = CONST_CAST_IA32_ATTR(ia32_asm_attr_t, gen_attr);
1407 ident *asm_text = attr->asm_text;
1408 const char *s = get_id_str(asm_text);
1410 ia32_emitf(node, "#APP\t\n");
1417 s = emit_asm_operand(node, s);
1423 ia32_emitf(NULL, "\n#NO_APP\n");
1428 * Emit movsb/w instructions to make mov count divideable by 4
1430 static void emit_CopyB_prolog(unsigned size)
1433 ia32_emitf(NULL, "\tmovsb\n");
1435 ia32_emitf(NULL, "\tmovsw\n");
1439 * Emit rep movsd instruction for memcopy.
1441 static void emit_ia32_CopyB(const ir_node *node)
1443 unsigned size = get_ia32_copyb_size(node);
1445 emit_CopyB_prolog(size);
1446 ia32_emitf(node, "\trep movsd\n");
1450 * Emits unrolled memcopy.
1452 static void emit_ia32_CopyB_i(const ir_node *node)
1454 unsigned size = get_ia32_copyb_size(node);
1456 emit_CopyB_prolog(size);
1460 ia32_emitf(NULL, "\tmovsd\n");
1466 * Emit code for conversions (I, FP), (FP, I) and (FP, FP).
1468 static void emit_ia32_Conv_with_FP(const ir_node *node, const char* conv_f,
1471 ir_mode *ls_mode = get_ia32_ls_mode(node);
1472 int ls_bits = get_mode_size_bits(ls_mode);
1473 const char *conv = ls_bits == 32 ? conv_f : conv_d;
1475 ia32_emitf(node, "\tcvt%s %AS3, %D0\n", conv);
1478 static void emit_ia32_Conv_I2FP(const ir_node *node)
1480 emit_ia32_Conv_with_FP(node, "si2ss", "si2sd");
1483 static void emit_ia32_Conv_FP2I(const ir_node *node)
1485 emit_ia32_Conv_with_FP(node, "ss2si", "sd2si");
1488 static void emit_ia32_Conv_FP2FP(const ir_node *node)
1490 emit_ia32_Conv_with_FP(node, "sd2ss", "ss2sd");
1494 * Emits code for an Int conversion.
1496 static void emit_ia32_Conv_I2I(const ir_node *node)
1498 ir_mode *smaller_mode = get_ia32_ls_mode(node);
1499 int signed_mode = mode_is_signed(smaller_mode);
1500 const char *sign_suffix;
1502 assert(!mode_is_float(smaller_mode));
1504 sign_suffix = signed_mode ? "s" : "z";
1505 ia32_emitf(node, "\tmov%s%Ml %#AS3, %D0\n", sign_suffix);
1511 static void emit_ia32_Call(const ir_node *node)
1513 /* Special case: Call must not have its immediates prefixed by $, instead
1514 * address mode is prefixed by *. */
1515 ia32_emitf(node, "\tcall %*AS3\n");
1520 * Emits code to increase stack pointer.
1522 static void emit_be_IncSP(const ir_node *node)
1524 int offs = be_get_IncSP_offset(node);
1530 ia32_emitf(node, "\tsubl $%u, %D0\n", offs);
1532 ia32_emitf(node, "\taddl $%u, %D0\n", -offs);
1537 * Emits code for Copy/CopyKeep.
1539 static void Copy_emitter(const ir_node *node, const ir_node *op)
1541 const arch_register_t *in = arch_get_irn_register(op);
1542 const arch_register_t *out = arch_get_irn_register(node);
1547 /* copies of vf nodes aren't real... */
1548 if (arch_register_get_class(in) == &ia32_reg_classes[CLASS_ia32_vfp])
1551 if (get_irn_mode(node) == mode_E) {
1552 ia32_emitf(node, "\tmovsd %R, %R\n", in, out);
1554 ia32_emitf(node, "\tmovl %R, %R\n", in, out);
1558 static void emit_be_Copy(const ir_node *node)
1560 Copy_emitter(node, be_get_Copy_op(node));
1563 static void emit_be_CopyKeep(const ir_node *node)
1565 Copy_emitter(node, be_get_CopyKeep_op(node));
1569 * Emits code for exchange.
1571 static void emit_be_Perm(const ir_node *node)
1573 const arch_register_t *in0, *in1;
1574 const arch_register_class_t *cls0, *cls1;
1576 in0 = arch_get_irn_register(get_irn_n(node, 0));
1577 in1 = arch_get_irn_register(get_irn_n(node, 1));
1579 cls0 = arch_register_get_class(in0);
1580 cls1 = arch_register_get_class(in1);
1582 assert(cls0 == cls1 && "Register class mismatch at Perm");
1584 if (cls0 == &ia32_reg_classes[CLASS_ia32_gp]) {
1585 ia32_emitf(node, "\txchg %R, %R\n", in1, in0);
1586 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_xmm]) {
1587 ia32_emitf(NULL, "\txorpd %R, %R\n", in1, in0);
1588 ia32_emitf(NULL, "\txorpd %R, %R\n", in0, in1);
1589 ia32_emitf(node, "\txorpd %R, %R\n", in1, in0);
1590 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_vfp]) {
1592 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_st]) {
1595 panic("unexpected register class in be_Perm (%+F)", node);
1600 * Emits code for Constant loading.
1602 static void emit_ia32_Const(const ir_node *node)
1604 ia32_emitf(node, "\tmovl %I, %D0\n");
1607 /* helper function for emit_ia32_Minus64Bit */
1608 static void emit_mov(const ir_node* node, const arch_register_t *src, const arch_register_t *dst)
1610 ia32_emitf(node, "\tmovl %R, %R\n", src, dst);
1613 /* helper function for emit_ia32_Minus64Bit */
1614 static void emit_neg(const ir_node* node, const arch_register_t *reg)
1616 ia32_emitf(node, "\tnegl %R\n", reg);
1619 /* helper function for emit_ia32_Minus64Bit */
1620 static void emit_sbb0(const ir_node* node, const arch_register_t *reg)
1622 ia32_emitf(node, "\tsbbl $0, %R\n", reg);
1625 /* helper function for emit_ia32_Minus64Bit */
1626 static void emit_sbb(const ir_node* node, const arch_register_t *src, const arch_register_t *dst)
1628 ia32_emitf(node, "\tsbbl %R, %R\n", src, dst);
1631 /* helper function for emit_ia32_Minus64Bit */
1632 static void emit_xchg(const ir_node* node, const arch_register_t *src, const arch_register_t *dst)
1634 ia32_emitf(node, "\txchgl %R, %R\n", src, dst);
1637 /* helper function for emit_ia32_Minus64Bit */
1638 static void emit_zero(const ir_node* node, const arch_register_t *reg)
1640 ia32_emitf(node, "\txorl %R, %R\n", reg, reg);
1643 static void emit_ia32_Minus64Bit(const ir_node *node)
1645 const arch_register_t *in_lo = get_in_reg(node, 0);
1646 const arch_register_t *in_hi = get_in_reg(node, 1);
1647 const arch_register_t *out_lo = get_out_reg(node, 0);
1648 const arch_register_t *out_hi = get_out_reg(node, 1);
1650 if (out_lo == in_lo) {
1651 if (out_hi != in_hi) {
1652 /* a -> a, b -> d */
1655 /* a -> a, b -> b */
1658 } else if (out_lo == in_hi) {
1659 if (out_hi == in_lo) {
1660 /* a -> b, b -> a */
1661 emit_xchg(node, in_lo, in_hi);
1664 /* a -> b, b -> d */
1665 emit_mov(node, in_hi, out_hi);
1666 emit_mov(node, in_lo, out_lo);
1670 if (out_hi == in_lo) {
1671 /* a -> c, b -> a */
1672 emit_mov(node, in_lo, out_lo);
1674 } else if (out_hi == in_hi) {
1675 /* a -> c, b -> b */
1676 emit_mov(node, in_lo, out_lo);
1679 /* a -> c, b -> d */
1680 emit_mov(node, in_lo, out_lo);
1686 emit_neg( node, out_hi);
1687 emit_neg( node, out_lo);
1688 emit_sbb0(node, out_hi);
1692 emit_zero(node, out_hi);
1693 emit_neg( node, out_lo);
1694 emit_sbb( node, in_hi, out_hi);
1697 static void emit_ia32_GetEIP(const ir_node *node)
1699 ia32_emitf(node, "\tcall %s\n", pic_base_label);
1700 ia32_emitf(NULL, "%s:\n", pic_base_label);
1701 ia32_emitf(node, "\tpopl %D0\n");
1704 static void emit_ia32_ClimbFrame(const ir_node *node)
1706 const ia32_climbframe_attr_t *attr = get_ia32_climbframe_attr_const(node);
1708 ia32_emitf(node, "\tmovl %S0, %D0\n");
1709 ia32_emitf(node, "\tmovl $%u, %S1\n", attr->count);
1710 be_gas_emit_block_name(node);
1711 be_emit_cstring(":\n");
1712 be_emit_write_line();
1713 ia32_emitf(node, "\tmovl (%D0), %D0\n");
1714 ia32_emitf(node, "\tdec %S1\n");
1715 be_emit_cstring("\tjnz ");
1716 be_gas_emit_block_name(node);
1717 be_emit_finish_line_gas(node);
1720 static void emit_be_Return(const ir_node *node)
1722 unsigned pop = be_Return_get_pop(node);
1724 if (pop > 0 || be_Return_get_emit_pop(node)) {
1725 ia32_emitf(node, "\tret $%u\n", pop);
1727 ia32_emitf(node, "\tret\n");
1731 static void emit_Nothing(const ir_node *node)
1738 * Enters the emitter functions for handled nodes into the generic
1739 * pointer of an opcode.
1741 static void ia32_register_emitters(void)
1743 #define IA32_EMIT2(a,b) op_ia32_##a->ops.generic = (op_func)emit_ia32_##b
1744 #define IA32_EMIT(a) IA32_EMIT2(a,a)
1745 #define EMIT(a) op_##a->ops.generic = (op_func)emit_##a
1746 #define IGN(a) op_##a->ops.generic = (op_func)emit_Nothing
1747 #define BE_EMIT(a) op_be_##a->ops.generic = (op_func)emit_be_##a
1748 #define BE_IGN(a) op_be_##a->ops.generic = (op_func)emit_Nothing
1750 /* first clear the generic function pointer for all ops */
1751 clear_irp_opcodes_generic_func();
1753 /* register all emitter functions defined in spec */
1754 ia32_register_spec_emitters();
1756 /* other ia32 emitter functions */
1757 IA32_EMIT2(Conv_I2I8Bit, Conv_I2I);
1762 IA32_EMIT(Conv_FP2FP);
1763 IA32_EMIT(Conv_FP2I);
1764 IA32_EMIT(Conv_I2FP);
1765 IA32_EMIT(Conv_I2I);
1772 IA32_EMIT(Minus64Bit);
1773 IA32_EMIT(SwitchJmp);
1774 IA32_EMIT(ClimbFrame);
1777 /* benode emitter */
1797 typedef void (*emit_func_ptr) (const ir_node *);
1800 * Assign and emit an exception label if the current instruction can fail.
1802 static void ia32_assign_exc_label(ir_node *node)
1804 /* assign a new ID to the instruction */
1805 set_ia32_exc_label_id(node, ++exc_label_id);
1807 ia32_emit_exc_label(node);
1809 be_emit_pad_comment();
1810 be_emit_cstring("/* exception to Block ");
1811 ia32_emit_cfop_target(node);
1812 be_emit_cstring(" */\n");
1813 be_emit_write_line();
1817 * Emits code for a node.
1819 static void ia32_emit_node(ir_node *node)
1821 ir_op *op = get_irn_op(node);
1823 DBG((dbg, LEVEL_1, "emitting code for %+F\n", node));
1825 if (is_ia32_irn(node)) {
1826 if (get_ia32_exc_label(node)) {
1827 /* emit the exception label of this instruction */
1828 ia32_assign_exc_label(node);
1830 if (mark_spill_reload) {
1831 if (is_ia32_is_spill(node)) {
1832 ia32_emitf(NULL, "\txchg %ebx, %ebx /* spill mark */\n");
1834 if (is_ia32_is_reload(node)) {
1835 ia32_emitf(NULL, "\txchg %edx, %edx /* reload mark */\n");
1837 if (is_ia32_is_remat(node)) {
1838 ia32_emitf(NULL, "\txchg %ecx, %ecx /* remat mark */\n");
1842 if (op->ops.generic) {
1843 emit_func_ptr func = (emit_func_ptr) op->ops.generic;
1845 be_dbg_set_dbg_info(get_irn_dbg_info(node));
1850 ir_fprintf(stderr, "Error: No emit handler for node %+F (%+G, graph %+F)\n", node, node, current_ir_graph);
1856 * Emits gas alignment directives
1858 static void ia32_emit_alignment(unsigned align, unsigned skip)
1860 ia32_emitf(NULL, "\t.p2align %u,,%u\n", align, skip);
1864 * Emits gas alignment directives for Labels depended on cpu architecture.
1866 static void ia32_emit_align_label(void)
1868 unsigned align = ia32_cg_config.label_alignment;
1869 unsigned maximum_skip = ia32_cg_config.label_alignment_max_skip;
1870 ia32_emit_alignment(align, maximum_skip);
1874 * Test whether a block should be aligned.
1875 * For cpus in the P4/Athlon class it is useful to align jump labels to
1876 * 16 bytes. However we should only do that if the alignment nops before the
1877 * label aren't executed more often than we have jumps to the label.
1879 static int should_align_block(const ir_node *block)
1881 static const double DELTA = .0001;
1882 ir_graph *irg = get_irn_irg(block);
1883 ir_exec_freq *exec_freq = be_get_irg_exec_freq(irg);
1884 ir_node *prev = get_prev_block_sched(block);
1886 double prev_freq = 0; /**< execfreq of the fallthrough block */
1887 double jmp_freq = 0; /**< execfreq of all non-fallthrough blocks */
1890 if (exec_freq == NULL)
1892 if (ia32_cg_config.label_alignment_factor <= 0)
1895 block_freq = get_block_execfreq(exec_freq, block);
1896 if (block_freq < DELTA)
1899 n_cfgpreds = get_Block_n_cfgpreds(block);
1900 for (i = 0; i < n_cfgpreds; ++i) {
1901 const ir_node *pred = get_Block_cfgpred_block(block, i);
1902 double pred_freq = get_block_execfreq(exec_freq, pred);
1905 prev_freq += pred_freq;
1907 jmp_freq += pred_freq;
1911 if (prev_freq < DELTA && !(jmp_freq < DELTA))
1914 jmp_freq /= prev_freq;
1916 return jmp_freq > ia32_cg_config.label_alignment_factor;
1920 * Emit the block header for a block.
1922 * @param block the block
1923 * @param prev_block the previous block
1925 static void ia32_emit_block_header(ir_node *block)
1927 ir_graph *irg = current_ir_graph;
1928 int need_label = block_needs_label(block);
1930 ir_exec_freq *exec_freq = be_get_irg_exec_freq(irg);
1932 if (block == get_irg_end_block(irg))
1935 if (ia32_cg_config.label_alignment > 0) {
1936 /* align the current block if:
1937 * a) if should be aligned due to its execution frequency
1938 * b) there is no fall-through here
1940 if (should_align_block(block)) {
1941 ia32_emit_align_label();
1943 /* if the predecessor block has no fall-through,
1944 we can always align the label. */
1946 int has_fallthrough = 0;
1948 for (i = get_Block_n_cfgpreds(block) - 1; i >= 0; --i) {
1949 ir_node *cfg_pred = get_Block_cfgpred(block, i);
1950 if (can_be_fallthrough(cfg_pred)) {
1951 has_fallthrough = 1;
1956 if (!has_fallthrough)
1957 ia32_emit_align_label();
1962 be_gas_emit_block_name(block);
1965 be_emit_pad_comment();
1966 be_emit_cstring(" /* ");
1968 be_emit_cstring("\t/* ");
1969 be_gas_emit_block_name(block);
1970 be_emit_cstring(": ");
1973 be_emit_cstring("preds:");
1975 /* emit list of pred blocks in comment */
1976 arity = get_irn_arity(block);
1978 be_emit_cstring(" none");
1980 for (i = 0; i < arity; ++i) {
1981 ir_node *predblock = get_Block_cfgpred_block(block, i);
1982 be_emit_irprintf(" %d", get_irn_node_nr(predblock));
1985 if (exec_freq != NULL) {
1986 be_emit_irprintf(", freq: %f",
1987 get_block_execfreq(exec_freq, block));
1989 be_emit_cstring(" */\n");
1990 be_emit_write_line();
1994 * Walks over the nodes in a block connected by scheduling edges
1995 * and emits code for each node.
1997 static void ia32_gen_block(ir_node *block)
2001 ia32_emit_block_header(block);
2003 /* emit the contents of the block */
2004 be_dbg_set_dbg_info(get_irn_dbg_info(block));
2005 sched_foreach(block, node) {
2006 ia32_emit_node(node);
2010 typedef struct exc_entry {
2011 ir_node *exc_instr; /** The instruction that can issue an exception. */
2012 ir_node *block; /** The block to call then. */
2017 * Sets labels for control flow nodes (jump target).
2018 * Links control predecessors to there destination blocks.
2020 static void ia32_gen_labels(ir_node *block, void *data)
2022 exc_entry **exc_list = (exc_entry**)data;
2026 for (n = get_Block_n_cfgpreds(block) - 1; n >= 0; --n) {
2027 pred = get_Block_cfgpred(block, n);
2028 set_irn_link(pred, block);
2030 pred = skip_Proj(pred);
2031 if (is_ia32_irn(pred) && get_ia32_exc_label(pred)) {
2036 ARR_APP1(exc_entry, *exc_list, e);
2037 set_irn_link(pred, block);
2043 * Compare two exception_entries.
2045 static int cmp_exc_entry(const void *a, const void *b)
2047 const exc_entry *ea = (const exc_entry*)a;
2048 const exc_entry *eb = (const exc_entry*)b;
2050 if (get_ia32_exc_label_id(ea->exc_instr) < get_ia32_exc_label_id(eb->exc_instr))
2056 * Main driver. Emits the code for one routine.
2058 void ia32_gen_routine(ir_graph *irg)
2060 ir_entity *entity = get_irg_entity(irg);
2061 exc_entry *exc_list = NEW_ARR_F(exc_entry, 0);
2062 const arch_env_t *arch_env = be_get_irg_arch_env(irg);
2063 ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
2064 ir_node **blk_sched = irg_data->blk_sched;
2067 isa = (ia32_isa_t*) arch_env;
2068 do_pic = be_get_irg_options(irg)->pic;
2070 be_gas_elf_type_char = '@';
2072 ia32_register_emitters();
2074 get_unique_label(pic_base_label, sizeof(pic_base_label), "PIC_BASE");
2076 be_dbg_method_begin(entity);
2077 be_gas_emit_function_prolog(entity, ia32_cg_config.function_alignment);
2079 /* we use links to point to target blocks */
2080 ir_reserve_resources(irg, IR_RESOURCE_IRN_LINK);
2081 irg_block_walk_graph(irg, ia32_gen_labels, NULL, &exc_list);
2083 /* initialize next block links */
2084 n = ARR_LEN(blk_sched);
2085 for (i = 0; i < n; ++i) {
2086 ir_node *block = blk_sched[i];
2087 ir_node *prev = i > 0 ? blk_sched[i-1] : NULL;
2089 set_irn_link(block, prev);
2092 for (i = 0; i < n; ++i) {
2093 ir_node *block = blk_sched[i];
2095 ia32_gen_block(block);
2098 be_gas_emit_function_epilog(entity);
2099 be_dbg_method_end();
2101 be_emit_write_line();
2103 ir_free_resources(irg, IR_RESOURCE_IRN_LINK);
2105 /* Sort the exception table using the exception label id's.
2106 Those are ascending with ascending addresses. */
2107 qsort(exc_list, ARR_LEN(exc_list), sizeof(exc_list[0]), cmp_exc_entry);
2111 for (i = 0; i < ARR_LEN(exc_list); ++i) {
2112 be_emit_cstring("\t.long ");
2113 ia32_emit_exc_label(exc_list[i].exc_instr);
2115 be_emit_cstring("\t.long ");
2116 be_gas_emit_block_name(exc_list[i].block);
2120 DEL_ARR_F(exc_list);
2123 static const lc_opt_table_entry_t ia32_emitter_options[] = {
2124 LC_OPT_ENT_BOOL("mark_spill_reload", "mark spills and reloads with ud opcodes", &mark_spill_reload),
2128 /* ==== Experimental binary emitter ==== */
2130 static unsigned char reg_gp_map[N_ia32_gp_REGS];
2131 //static unsigned char reg_mmx_map[N_ia32_mmx_REGS];
2132 //static unsigned char reg_sse_map[N_ia32_xmm_REGS];
2134 static void build_reg_map(void)
2136 reg_gp_map[REG_GP_EAX] = 0x0;
2137 reg_gp_map[REG_GP_ECX] = 0x1;
2138 reg_gp_map[REG_GP_EDX] = 0x2;
2139 reg_gp_map[REG_GP_EBX] = 0x3;
2140 reg_gp_map[REG_GP_ESP] = 0x4;
2141 reg_gp_map[REG_GP_EBP] = 0x5;
2142 reg_gp_map[REG_GP_ESI] = 0x6;
2143 reg_gp_map[REG_GP_EDI] = 0x7;
2146 /** Returns the encoding for a pnc field. */
2147 static unsigned char pnc2cc(ia32_condition_code_t cc)
2152 /** Sign extension bit values for binops */
2154 UNSIGNED_IMM = 0, /**< unsigned immediate */
2155 SIGNEXT_IMM = 2, /**< sign extended immediate */
2158 /** The mod encoding of the ModR/M */
2160 MOD_IND = 0x00, /**< [reg1] */
2161 MOD_IND_BYTE_OFS = 0x40, /**< [reg1 + byte ofs] */
2162 MOD_IND_WORD_OFS = 0x80, /**< [reg1 + word ofs] */
2163 MOD_REG = 0xC0 /**< reg1 */
2166 /** create R/M encoding for ModR/M */
2167 #define ENC_RM(x) (x)
2168 /** create REG encoding for ModR/M */
2169 #define ENC_REG(x) ((x) << 3)
2171 /** create encoding for a SIB byte */
2172 #define ENC_SIB(scale, index, base) ((scale) << 6 | (index) << 3 | (base))
2174 /* Node: The following routines are supposed to append bytes, words, dwords
2175 to the output stream.
2176 Currently the implementation is stupid in that it still creates output
2177 for an "assembler" in the form of .byte, .long
2178 We will change this when enough infrastructure is there to create complete
2179 machine code in memory/object files */
2181 static void bemit8(const unsigned char byte)
2183 be_emit_irprintf("\t.byte 0x%x\n", byte);
2184 be_emit_write_line();
2187 static void bemit16(const unsigned short u16)
2189 be_emit_irprintf("\t.word 0x%x\n", u16);
2190 be_emit_write_line();
2193 static void bemit32(const unsigned u32)
2195 be_emit_irprintf("\t.long 0x%x\n", u32);
2196 be_emit_write_line();
2200 * Emit address of an entity. If @p is_relative is true then a relative
2201 * offset from behind the address to the entity is created.
2203 static void bemit_entity(ir_entity *entity, bool entity_sign, int offset,
2206 if (entity == NULL) {
2211 /* the final version should remember the position in the bytestream
2212 and patch it with the correct address at linktime... */
2213 be_emit_cstring("\t.long ");
2216 be_gas_emit_entity(entity);
2218 if (get_entity_owner(entity) == get_tls_type()) {
2219 if (get_entity_visibility(entity) == ir_visibility_external) {
2220 be_emit_cstring("@INDNTPOFF");
2222 be_emit_cstring("@NTPOFF");
2227 be_emit_cstring("-.");
2232 be_emit_irprintf("%+d", offset);
2235 be_emit_write_line();
2238 static void bemit_jmp_destination(const ir_node *dest_block)
2240 be_emit_cstring("\t.long ");
2241 be_gas_emit_block_name(dest_block);
2242 be_emit_cstring(" - . - 4\n");
2243 be_emit_write_line();
2246 /* end emit routines, all emitters following here should only use the functions
2249 typedef enum reg_modifier {
2254 /** Create a ModR/M byte for src1,src2 registers */
2255 static void bemit_modrr(const arch_register_t *src1,
2256 const arch_register_t *src2)
2258 unsigned char modrm = MOD_REG;
2259 modrm |= ENC_RM(reg_gp_map[src1->index]);
2260 modrm |= ENC_REG(reg_gp_map[src2->index]);
2264 /** Create a ModR/M8 byte for src1,src2 registers */
2265 static void bemit_modrr8(reg_modifier_t high_part1, const arch_register_t *src1,
2266 reg_modifier_t high_part2, const arch_register_t *src2)
2268 unsigned char modrm = MOD_REG;
2269 modrm |= ENC_RM(reg_gp_map[src1->index] + (high_part1 == REG_HIGH ? 4 : 0));
2270 modrm |= ENC_REG(reg_gp_map[src2->index] + (high_part2 == REG_HIGH ? 4 : 0));
2274 /** Create a ModR/M byte for one register and extension */
2275 static void bemit_modru(const arch_register_t *reg, unsigned ext)
2277 unsigned char modrm = MOD_REG;
2279 modrm |= ENC_RM(reg_gp_map[reg->index]);
2280 modrm |= ENC_REG(ext);
2284 /** Create a ModR/M8 byte for one register */
2285 static void bemit_modrm8(reg_modifier_t high_part, const arch_register_t *reg)
2287 unsigned char modrm = MOD_REG;
2288 assert(reg_gp_map[reg->index] < 4);
2289 modrm |= ENC_RM(reg_gp_map[reg->index] + (high_part == REG_HIGH ? 4 : 0));
2295 * Calculate the size of an signed immediate in bytes.
2297 * @param offset an offset
2299 static unsigned get_signed_imm_size(int offset)
2301 if (-128 <= offset && offset < 128) {
2303 } else if (-32768 <= offset && offset < 32768) {
2311 * Emit an address mode.
2313 * @param reg content of the reg field: either a register index or an opcode extension
2314 * @param node the node
2316 static void bemit_mod_am(unsigned reg, const ir_node *node)
2318 ir_entity *ent = get_ia32_am_sc(node);
2319 int offs = get_ia32_am_offs_int(node);
2320 ir_node *base = get_irn_n(node, n_ia32_base);
2321 int has_base = !is_ia32_NoReg_GP(base);
2322 ir_node *index = get_irn_n(node, n_ia32_index);
2323 int has_index = !is_ia32_NoReg_GP(index);
2326 unsigned emitoffs = 0;
2327 bool emitsib = false;
2330 /* set the mod part depending on displacement */
2332 modrm |= MOD_IND_WORD_OFS;
2334 } else if (offs == 0) {
2337 } else if (-128 <= offs && offs < 128) {
2338 modrm |= MOD_IND_BYTE_OFS;
2341 modrm |= MOD_IND_WORD_OFS;
2346 const arch_register_t *base_reg = arch_get_irn_register(base);
2347 base_enc = reg_gp_map[base_reg->index];
2349 /* Use the EBP encoding + MOD_IND if NO base register. There is
2350 * always a 32bit offset present in this case. */
2356 /* Determine if we need a SIB byte. */
2358 const arch_register_t *reg_index = arch_get_irn_register(index);
2359 int scale = get_ia32_am_scale(node);
2361 /* R/M set to ESP means SIB in 32bit mode. */
2362 modrm |= ENC_RM(0x04);
2363 sib = ENC_SIB(scale, reg_gp_map[reg_index->index], base_enc);
2365 } else if (base_enc == 0x04) {
2366 /* for the above reason we are forced to emit a SIB when base is ESP.
2367 * Only the base is used, index must be ESP too, which means no index.
2369 modrm |= ENC_RM(0x04);
2370 sib = ENC_SIB(0, 0x04, 0x04);
2373 modrm |= ENC_RM(base_enc);
2376 /* We are forced to emit an 8bit offset as EBP base without offset is a
2377 * special case for SIB without base register. */
2378 if (base_enc == 0x05 && emitoffs == 0) {
2379 modrm |= MOD_IND_BYTE_OFS;
2383 modrm |= ENC_REG(reg);
2389 /* emit displacement */
2390 if (emitoffs == 8) {
2391 bemit8((unsigned) offs);
2392 } else if (emitoffs == 32) {
2393 bemit_entity(ent, is_ia32_am_sc_sign(node), offs, false);
2398 * Emit a binop with a immediate operand.
2400 * @param node the node to emit
2401 * @param opcode_eax the opcode for the op eax, imm variant
2402 * @param opcode the opcode for the reg, imm variant
2403 * @param ruval the opcode extension for opcode
2405 static void bemit_binop_with_imm(
2406 const ir_node *node,
2407 unsigned char opcode_ax,
2408 unsigned char opcode, unsigned char ruval)
2410 /* Use in-reg, because some instructions (cmp, test) have no out-reg. */
2411 const ir_node *op = get_irn_n(node, n_ia32_binary_right);
2412 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(op);
2415 /* Some instructions (test) have no short form with 32bit value + 8bit
2417 if (attr->symconst != NULL || opcode & SIGNEXT_IMM) {
2420 /* check for sign extension */
2421 size = get_signed_imm_size(attr->offset);
2426 bemit8(opcode | SIGNEXT_IMM);
2427 /* cmp has this special mode */
2428 if (get_ia32_op_type(node) == ia32_AddrModeS) {
2429 bemit_mod_am(ruval, node);
2431 const arch_register_t *reg = get_in_reg(node, n_ia32_binary_left);
2432 bemit_modru(reg, ruval);
2434 bemit8((unsigned char)attr->offset);
2438 /* check for eax variant: this variant is shorter for 32bit immediates only */
2439 if (get_ia32_op_type(node) == ia32_AddrModeS) {
2441 bemit_mod_am(ruval, node);
2443 const arch_register_t *reg = get_in_reg(node, n_ia32_binary_left);
2444 if (reg->index == REG_GP_EAX) {
2448 bemit_modru(reg, ruval);
2451 bemit_entity(attr->symconst, attr->sc_sign, attr->offset, false);
2454 panic("invalid imm size?!?");
2460 static void bemit_binop_2(const ir_node *node, unsigned code)
2462 const arch_register_t *out = get_in_reg(node, n_ia32_binary_left);
2464 if (get_ia32_op_type(node) == ia32_Normal) {
2465 const arch_register_t *op2 = get_in_reg(node, n_ia32_binary_right);
2466 bemit_modrr(op2, out);
2468 bemit_mod_am(reg_gp_map[out->index], node);
2475 static void bemit_binop(const ir_node *node, const unsigned char opcodes[4])
2477 ir_node *right = get_irn_n(node, n_ia32_binary_right);
2478 if (is_ia32_Immediate(right)) {
2479 bemit_binop_with_imm(node, opcodes[1], opcodes[2], opcodes[3]);
2481 bemit_binop_2(node, opcodes[0]);
2488 static void bemit_unop(const ir_node *node, unsigned char code, unsigned char ext, int input)
2491 if (get_ia32_op_type(node) == ia32_Normal) {
2492 const arch_register_t *in = get_in_reg(node, input);
2493 bemit_modru(in, ext);
2495 bemit_mod_am(ext, node);
2499 static void bemit_unop_reg(const ir_node *node, unsigned char code, int input)
2501 const arch_register_t *out = get_out_reg(node, 0);
2502 bemit_unop(node, code, reg_gp_map[out->index], input);
2505 static void bemit_unop_mem(const ir_node *node, unsigned char code, unsigned char ext)
2507 unsigned size = get_mode_size_bits(get_ia32_ls_mode(node));
2510 bemit8(size == 8 ? code : code + 1);
2511 bemit_mod_am(ext, node);
2514 static void bemit_immediate(const ir_node *node, bool relative)
2516 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(node);
2517 bemit_entity(attr->symconst, attr->sc_sign, attr->offset, relative);
2520 static void bemit_copy(const ir_node *copy)
2522 const arch_register_t *in = get_in_reg(copy, 0);
2523 const arch_register_t *out = get_out_reg(copy, 0);
2527 /* copies of vf nodes aren't real... */
2528 if (arch_register_get_class(in) == &ia32_reg_classes[CLASS_ia32_vfp])
2531 if (get_irn_mode(copy) == mode_E) {
2534 assert(arch_register_get_class(in) == &ia32_reg_classes[CLASS_ia32_gp]);
2536 bemit_modrr(in, out);
2540 static void bemit_perm(const ir_node *node)
2542 const arch_register_t *in0 = arch_get_irn_register(get_irn_n(node, 0));
2543 const arch_register_t *in1 = arch_get_irn_register(get_irn_n(node, 1));
2544 const arch_register_class_t *cls0 = arch_register_get_class(in0);
2546 assert(cls0 == arch_register_get_class(in1) && "Register class mismatch at Perm");
2548 if (cls0 == &ia32_reg_classes[CLASS_ia32_gp]) {
2549 if (in0->index == REG_GP_EAX) {
2550 bemit8(0x90 + reg_gp_map[in1->index]);
2551 } else if (in1->index == REG_GP_EAX) {
2552 bemit8(0x90 + reg_gp_map[in0->index]);
2555 bemit_modrr(in0, in1);
2557 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_xmm]) {
2558 panic("unimplemented"); // TODO implement
2559 //ia32_emitf(NULL, "\txorpd %R, %R\n", in1, in0);
2560 //ia32_emitf(NULL, "\txorpd %R, %R\n", in0, in1);
2561 //ia32_emitf(node, "\txorpd %R, %R\n", in1, in0);
2562 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_vfp]) {
2564 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_st]) {
2567 panic("unexpected register class in be_Perm (%+F)", node);
2571 static void bemit_xor0(const ir_node *node)
2573 const arch_register_t *out = get_out_reg(node, 0);
2575 bemit_modrr(out, out);
2578 static void bemit_mov_const(const ir_node *node)
2580 const arch_register_t *out = get_out_reg(node, 0);
2581 bemit8(0xB8 + reg_gp_map[out->index]);
2582 bemit_immediate(node, false);
2586 * Creates a function for a Binop with 3 possible encodings.
2588 #define BINOP(op, op0, op1, op2, op2_ext) \
2589 static void bemit_ ## op(const ir_node *node) { \
2590 static const unsigned char op ## _codes[] = {op0, op1, op2, op2_ext}; \
2591 bemit_binop(node, op ## _codes); \
2594 /* insn def eax,imm imm */
2595 BINOP(add, 0x03, 0x05, 0x81, 0)
2596 BINOP(or, 0x0B, 0x0D, 0x81, 1)
2597 BINOP(adc, 0x13, 0x15, 0x81, 2)
2598 BINOP(sbb, 0x1B, 0x1D, 0x81, 3)
2599 BINOP(and, 0x23, 0x25, 0x81, 4)
2600 BINOP(sub, 0x2B, 0x2D, 0x81, 5)
2601 BINOP(xor, 0x33, 0x35, 0x81, 6)
2602 BINOP(test, 0x85, 0xA9, 0xF7, 0)
2604 #define BINOPMEM(op, ext) \
2605 static void bemit_##op(const ir_node *node) \
2608 unsigned size = get_mode_size_bits(get_ia32_ls_mode(node)); \
2611 val = get_irn_n(node, n_ia32_unary_op); \
2612 if (is_ia32_Immediate(val)) { \
2613 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(val); \
2614 int offset = attr->offset; \
2615 if (attr->symconst == NULL && get_signed_imm_size(offset) == 1) { \
2617 bemit_mod_am(ext, node); \
2621 bemit_mod_am(ext, node); \
2625 bemit_entity(attr->symconst, attr->sc_sign, offset, false); \
2629 bemit8(ext << 3 | 1); \
2630 bemit_mod_am(reg_gp_map[get_out_reg(val, 0)->index], node); \
2634 static void bemit_##op##8bit(const ir_node *node) \
2636 ir_node *val = get_irn_n(node, n_ia32_unary_op); \
2637 if (is_ia32_Immediate(val)) { \
2639 bemit_mod_am(ext, node); \
2640 bemit8(get_ia32_immediate_attr_const(val)->offset); \
2643 bemit_mod_am(reg_gp_map[get_out_reg(val, 0)->index], node); \
2655 * Creates a function for an Unop with code /ext encoding.
2657 #define UNOP(op, code, ext, input) \
2658 static void bemit_ ## op(const ir_node *node) { \
2659 bemit_unop(node, code, ext, input); \
2662 UNOP(not, 0xF7, 2, n_ia32_Not_val)
2663 UNOP(neg, 0xF7, 3, n_ia32_Neg_val)
2664 UNOP(mul, 0xF7, 4, n_ia32_Mul_right)
2665 UNOP(imul1op, 0xF7, 5, n_ia32_IMul1OP_right)
2666 UNOP(div, 0xF7, 6, n_ia32_Div_divisor)
2667 UNOP(idiv, 0xF7, 7, n_ia32_IDiv_divisor)
2669 /* TODO: am support for IJmp */
2670 UNOP(ijmp, 0xFF, 4, n_ia32_IJmp_target)
2672 #define SHIFT(op, ext) \
2673 static void bemit_##op(const ir_node *node) \
2675 const arch_register_t *out = get_out_reg(node, 0); \
2676 ir_node *count = get_irn_n(node, 1); \
2677 if (is_ia32_Immediate(count)) { \
2678 int offset = get_ia32_immediate_attr_const(count)->offset; \
2679 if (offset == 1) { \
2681 bemit_modru(out, ext); \
2684 bemit_modru(out, ext); \
2689 bemit_modru(out, ext); \
2693 static void bemit_##op##mem(const ir_node *node) \
2696 unsigned size = get_mode_size_bits(get_ia32_ls_mode(node)); \
2699 count = get_irn_n(node, 1); \
2700 if (is_ia32_Immediate(count)) { \
2701 int offset = get_ia32_immediate_attr_const(count)->offset; \
2702 if (offset == 1) { \
2703 bemit8(size == 8 ? 0xD0 : 0xD1); \
2704 bemit_mod_am(ext, node); \
2706 bemit8(size == 8 ? 0xC0 : 0xC1); \
2707 bemit_mod_am(ext, node); \
2711 bemit8(size == 8 ? 0xD2 : 0xD3); \
2712 bemit_mod_am(ext, node); \
2722 static void bemit_shld(const ir_node *node)
2724 const arch_register_t *in = get_in_reg(node, n_ia32_ShlD_val_low);
2725 const arch_register_t *out = get_out_reg(node, pn_ia32_ShlD_res);
2726 ir_node *count = get_irn_n(node, n_ia32_ShlD_count);
2728 if (is_ia32_Immediate(count)) {
2730 bemit_modrr(out, in);
2731 bemit8(get_ia32_immediate_attr_const(count)->offset);
2734 bemit_modrr(out, in);
2738 static void bemit_shrd(const ir_node *node)
2740 const arch_register_t *in = get_in_reg(node, n_ia32_ShrD_val_low);
2741 const arch_register_t *out = get_out_reg(node, pn_ia32_ShrD_res);
2742 ir_node *count = get_irn_n(node, n_ia32_ShrD_count);
2744 if (is_ia32_Immediate(count)) {
2746 bemit_modrr(out, in);
2747 bemit8(get_ia32_immediate_attr_const(count)->offset);
2750 bemit_modrr(out, in);
2755 * binary emitter for setcc.
2757 static void bemit_setcc(const ir_node *node)
2759 const arch_register_t *dreg = get_out_reg(node, pn_ia32_Setcc_res);
2761 ia32_condition_code_t cc = get_ia32_condcode(node);
2762 cc = determine_final_cc(node, n_ia32_Setcc_eflags, cc);
2763 if (cc & ia32_cc_float_parity_cases) {
2764 if (cc & ia32_cc_negated) {
2767 bemit8(0x90 | pnc2cc(cc));
2768 bemit_modrm8(REG_LOW, dreg);
2773 bemit_modrm8(REG_HIGH, dreg);
2775 /* orb %>dreg, %<dreg */
2777 bemit_modrr8(REG_LOW, dreg, REG_HIGH, dreg);
2781 bemit8(0x90 | pnc2cc(cc));
2782 bemit_modrm8(REG_LOW, dreg);
2787 bemit_modrm8(REG_HIGH, dreg);
2789 /* andb %>dreg, %<dreg */
2791 bemit_modrr8(REG_LOW, dreg, REG_HIGH, dreg);
2796 bemit8(0x90 | pnc2cc(cc));
2797 bemit_modrm8(REG_LOW, dreg);
2801 static void bemit_cmovcc(const ir_node *node)
2803 const ia32_attr_t *attr = get_ia32_attr_const(node);
2804 int ins_permuted = attr->data.ins_permuted;
2805 const arch_register_t *out = arch_irn_get_register(node, pn_ia32_res);
2806 ia32_condition_code_t cc = get_ia32_condcode(node);
2807 const arch_register_t *in_true;
2808 const arch_register_t *in_false;
2810 cc = determine_final_cc(node, n_ia32_CMovcc_eflags, cc);
2812 in_true = arch_get_irn_register(get_irn_n(node, n_ia32_CMovcc_val_true));
2813 in_false = arch_get_irn_register(get_irn_n(node, n_ia32_CMovcc_val_false));
2815 /* should be same constraint fullfilled? */
2816 if (out == in_false) {
2817 /* yes -> nothing to do */
2818 } else if (out == in_true) {
2819 assert(get_ia32_op_type(node) == ia32_Normal);
2820 ins_permuted = !ins_permuted;
2824 bemit8(0x8B); // mov %in_false, %out
2825 bemit_modrr(in_false, out);
2829 cc = ia32_negate_condition_code(cc);
2831 if (cc & ia32_cc_float_parity_cases)
2832 panic("cmov can't handle parity float cases");
2835 bemit8(0x40 | pnc2cc(cc));
2836 if (get_ia32_op_type(node) == ia32_Normal) {
2837 bemit_modrr(in_true, out);
2839 bemit_mod_am(reg_gp_map[out->index], node);
2843 static void bemit_cmp(const ir_node *node)
2845 unsigned ls_size = get_mode_size_bits(get_ia32_ls_mode(node));
2851 right = get_irn_n(node, n_ia32_binary_right);
2852 if (is_ia32_Immediate(right)) {
2853 /* Use in-reg, because some instructions (cmp, test) have no out-reg. */
2854 const ir_node *op = get_irn_n(node, n_ia32_binary_right);
2855 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(op);
2858 if (attr->symconst != NULL) {
2861 /* check for sign extension */
2862 size = get_signed_imm_size(attr->offset);
2867 bemit8(0x81 | SIGNEXT_IMM);
2868 /* cmp has this special mode */
2869 if (get_ia32_op_type(node) == ia32_AddrModeS) {
2870 bemit_mod_am(7, node);
2872 const arch_register_t *reg = get_in_reg(node, n_ia32_binary_left);
2873 bemit_modru(reg, 7);
2875 bemit8((unsigned char)attr->offset);
2879 /* check for eax variant: this variant is shorter for 32bit immediates only */
2880 if (get_ia32_op_type(node) == ia32_AddrModeS) {
2882 bemit_mod_am(7, node);
2884 const arch_register_t *reg = get_in_reg(node, n_ia32_binary_left);
2885 if (reg->index == REG_GP_EAX) {
2889 bemit_modru(reg, 7);
2892 if (ls_size == 16) {
2893 bemit16(attr->offset);
2895 bemit_entity(attr->symconst, attr->sc_sign, attr->offset, false);
2899 panic("invalid imm size?!?");
2901 const arch_register_t *out = get_in_reg(node, n_ia32_binary_left);
2903 if (get_ia32_op_type(node) == ia32_Normal) {
2904 const arch_register_t *op2 = get_in_reg(node, n_ia32_binary_right);
2905 bemit_modrr(op2, out);
2907 bemit_mod_am(reg_gp_map[out->index], node);
2912 static void bemit_cmp8bit(const ir_node *node)
2914 ir_node *right = get_irn_n(node, n_ia32_binary_right);
2915 if (is_ia32_Immediate(right)) {
2916 if (get_ia32_op_type(node) == ia32_Normal) {
2917 const arch_register_t *out = get_in_reg(node, n_ia32_Cmp_left);
2918 if (out->index == REG_GP_EAX) {
2922 bemit_modru(out, 7);
2926 bemit_mod_am(7, node);
2928 bemit8(get_ia32_immediate_attr_const(right)->offset);
2930 const arch_register_t *out = get_in_reg(node, n_ia32_Cmp_left);
2932 if (get_ia32_op_type(node) == ia32_Normal) {
2933 const arch_register_t *in = get_in_reg(node, n_ia32_Cmp_right);
2934 bemit_modrr(out, in);
2936 bemit_mod_am(reg_gp_map[out->index], node);
2941 static void bemit_test8bit(const ir_node *node)
2943 ir_node *right = get_irn_n(node, n_ia32_Test8Bit_right);
2944 if (is_ia32_Immediate(right)) {
2945 if (get_ia32_op_type(node) == ia32_Normal) {
2946 const arch_register_t *out = get_in_reg(node, n_ia32_Test8Bit_left);
2947 if (out->index == REG_GP_EAX) {
2951 bemit_modru(out, 0);
2955 bemit_mod_am(0, node);
2957 bemit8(get_ia32_immediate_attr_const(right)->offset);
2959 const arch_register_t *out = get_in_reg(node, n_ia32_Test8Bit_left);
2961 if (get_ia32_op_type(node) == ia32_Normal) {
2962 const arch_register_t *in = get_in_reg(node, n_ia32_Test8Bit_right);
2963 bemit_modrr(out, in);
2965 bemit_mod_am(reg_gp_map[out->index], node);
2970 static void bemit_imul(const ir_node *node)
2972 ir_node *right = get_irn_n(node, n_ia32_IMul_right);
2973 /* Do we need the immediate form? */
2974 if (is_ia32_Immediate(right)) {
2975 int imm = get_ia32_immediate_attr_const(right)->offset;
2976 if (get_signed_imm_size(imm) == 1) {
2977 bemit_unop_reg(node, 0x6B, n_ia32_IMul_left);
2980 bemit_unop_reg(node, 0x69, n_ia32_IMul_left);
2985 bemit_unop_reg(node, 0xAF, n_ia32_IMul_right);
2989 static void bemit_dec(const ir_node *node)
2991 const arch_register_t *out = get_out_reg(node, pn_ia32_Dec_res);
2992 bemit8(0x48 + reg_gp_map[out->index]);
2995 static void bemit_inc(const ir_node *node)
2997 const arch_register_t *out = get_out_reg(node, pn_ia32_Inc_res);
2998 bemit8(0x40 + reg_gp_map[out->index]);
3001 #define UNOPMEM(op, code, ext) \
3002 static void bemit_##op(const ir_node *node) \
3004 bemit_unop_mem(node, code, ext); \
3007 UNOPMEM(notmem, 0xF6, 2)
3008 UNOPMEM(negmem, 0xF6, 3)
3009 UNOPMEM(incmem, 0xFE, 0)
3010 UNOPMEM(decmem, 0xFE, 1)
3012 static void bemit_ldtls(const ir_node *node)
3014 const arch_register_t *out = get_out_reg(node, 0);
3016 bemit8(0x65); // gs:
3017 if (out->index == REG_GP_EAX) {
3018 bemit8(0xA1); // movl 0, %eax
3020 bemit8(0x8B); // movl 0, %reg
3021 bemit8(MOD_IND | ENC_REG(reg_gp_map[out->index]) | ENC_RM(0x05));
3029 static void bemit_lea(const ir_node *node)
3031 const arch_register_t *out = get_out_reg(node, 0);
3033 bemit_mod_am(reg_gp_map[out->index], node);
3036 /* helper function for bemit_minus64bit */
3037 static void bemit_helper_mov(const arch_register_t *src, const arch_register_t *dst)
3039 bemit8(0x8B); // movl %src, %dst
3040 bemit_modrr(src, dst);
3043 /* helper function for bemit_minus64bit */
3044 static void bemit_helper_neg(const arch_register_t *reg)
3046 bemit8(0xF7); // negl %reg
3047 bemit_modru(reg, 3);
3050 /* helper function for bemit_minus64bit */
3051 static void bemit_helper_sbb0(const arch_register_t *reg)
3053 bemit8(0x83); // sbbl $0, %reg
3054 bemit_modru(reg, 3);
3058 /* helper function for bemit_minus64bit */
3059 static void bemit_helper_sbb(const arch_register_t *src, const arch_register_t *dst)
3061 bemit8(0x1B); // sbbl %src, %dst
3062 bemit_modrr(src, dst);
3065 /* helper function for bemit_minus64bit */
3066 static void bemit_helper_xchg(const arch_register_t *src, const arch_register_t *dst)
3068 if (src->index == REG_GP_EAX) {
3069 bemit8(0x90 + reg_gp_map[dst->index]); // xchgl %eax, %dst
3070 } else if (dst->index == REG_GP_EAX) {
3071 bemit8(0x90 + reg_gp_map[src->index]); // xchgl %src, %eax
3073 bemit8(0x87); // xchgl %src, %dst
3074 bemit_modrr(src, dst);
3078 /* helper function for bemit_minus64bit */
3079 static void bemit_helper_zero(const arch_register_t *reg)
3081 bemit8(0x33); // xorl %reg, %reg
3082 bemit_modrr(reg, reg);
3085 static void bemit_minus64bit(const ir_node *node)
3087 const arch_register_t *in_lo = get_in_reg(node, 0);
3088 const arch_register_t *in_hi = get_in_reg(node, 1);
3089 const arch_register_t *out_lo = get_out_reg(node, 0);
3090 const arch_register_t *out_hi = get_out_reg(node, 1);
3092 if (out_lo == in_lo) {
3093 if (out_hi != in_hi) {
3094 /* a -> a, b -> d */
3097 /* a -> a, b -> b */
3100 } else if (out_lo == in_hi) {
3101 if (out_hi == in_lo) {
3102 /* a -> b, b -> a */
3103 bemit_helper_xchg(in_lo, in_hi);
3106 /* a -> b, b -> d */
3107 bemit_helper_mov(in_hi, out_hi);
3108 bemit_helper_mov(in_lo, out_lo);
3112 if (out_hi == in_lo) {
3113 /* a -> c, b -> a */
3114 bemit_helper_mov(in_lo, out_lo);
3116 } else if (out_hi == in_hi) {
3117 /* a -> c, b -> b */
3118 bemit_helper_mov(in_lo, out_lo);
3121 /* a -> c, b -> d */
3122 bemit_helper_mov(in_lo, out_lo);
3128 bemit_helper_neg( out_hi);
3129 bemit_helper_neg( out_lo);
3130 bemit_helper_sbb0(out_hi);
3134 bemit_helper_zero(out_hi);
3135 bemit_helper_neg( out_lo);
3136 bemit_helper_sbb( in_hi, out_hi);
3140 * Emit a single opcode.
3142 #define EMIT_SINGLEOP(op, code) \
3143 static void bemit_ ## op(const ir_node *node) { \
3148 //EMIT_SINGLEOP(daa, 0x27)
3149 //EMIT_SINGLEOP(das, 0x2F)
3150 //EMIT_SINGLEOP(aaa, 0x37)
3151 //EMIT_SINGLEOP(aas, 0x3F)
3152 //EMIT_SINGLEOP(nop, 0x90)
3153 EMIT_SINGLEOP(cwtl, 0x98)
3154 EMIT_SINGLEOP(cltd, 0x99)
3155 //EMIT_SINGLEOP(fwait, 0x9B)
3156 EMIT_SINGLEOP(sahf, 0x9E)
3157 //EMIT_SINGLEOP(popf, 0x9D)
3158 EMIT_SINGLEOP(leave, 0xC9)
3159 EMIT_SINGLEOP(int3, 0xCC)
3160 //EMIT_SINGLEOP(iret, 0xCF)
3161 //EMIT_SINGLEOP(xlat, 0xD7)
3162 //EMIT_SINGLEOP(lock, 0xF0)
3163 EMIT_SINGLEOP(rep, 0xF3)
3164 //EMIT_SINGLEOP(halt, 0xF4)
3165 EMIT_SINGLEOP(cmc, 0xF5)
3166 EMIT_SINGLEOP(stc, 0xF9)
3167 //EMIT_SINGLEOP(cli, 0xFA)
3168 //EMIT_SINGLEOP(sti, 0xFB)
3169 //EMIT_SINGLEOP(std, 0xFD)
3172 * Emits a MOV out, [MEM].
3174 static void bemit_load(const ir_node *node)
3176 const arch_register_t *out = get_out_reg(node, 0);
3178 if (out->index == REG_GP_EAX) {
3179 ir_node *base = get_irn_n(node, n_ia32_base);
3180 int has_base = !is_ia32_NoReg_GP(base);
3181 ir_node *index = get_irn_n(node, n_ia32_index);
3182 int has_index = !is_ia32_NoReg_GP(index);
3183 if (!has_base && !has_index) {
3184 ir_entity *ent = get_ia32_am_sc(node);
3185 int offs = get_ia32_am_offs_int(node);
3186 /* load from constant address to EAX can be encoded
3189 bemit_entity(ent, 0, offs, false);
3194 bemit_mod_am(reg_gp_map[out->index], node);
3198 * Emits a MOV [mem], in.
3200 static void bemit_store(const ir_node *node)
3202 const ir_node *value = get_irn_n(node, n_ia32_Store_val);
3203 unsigned size = get_mode_size_bits(get_ia32_ls_mode(node));
3205 if (is_ia32_Immediate(value)) {
3208 bemit_mod_am(0, node);
3209 bemit8(get_ia32_immediate_attr_const(value)->offset);
3210 } else if (size == 16) {
3213 bemit_mod_am(0, node);
3214 bemit16(get_ia32_immediate_attr_const(value)->offset);
3217 bemit_mod_am(0, node);
3218 bemit_immediate(value, false);
3221 const arch_register_t *in = get_in_reg(node, n_ia32_Store_val);
3223 if (in->index == REG_GP_EAX) {
3224 ir_node *base = get_irn_n(node, n_ia32_base);
3225 int has_base = !is_ia32_NoReg_GP(base);
3226 ir_node *index = get_irn_n(node, n_ia32_index);
3227 int has_index = !is_ia32_NoReg_GP(index);
3228 if (!has_base && !has_index) {
3229 ir_entity *ent = get_ia32_am_sc(node);
3230 int offs = get_ia32_am_offs_int(node);
3231 /* store to constant address from EAX can be encoded as
3232 * 0xA2/0xA3 [offset]*/
3240 bemit_entity(ent, 0, offs, false);
3252 bemit_mod_am(reg_gp_map[in->index], node);
3256 static void bemit_conv_i2i(const ir_node *node)
3258 ir_mode *smaller_mode = get_ia32_ls_mode(node);
3267 if (mode_is_signed(smaller_mode)) opcode |= 0x08;
3268 if (get_mode_size_bits(smaller_mode) == 16) opcode |= 0x01;
3269 bemit_unop_reg(node, opcode, n_ia32_Conv_I2I_val);
3275 static void bemit_push(const ir_node *node)
3277 const ir_node *value = get_irn_n(node, n_ia32_Push_val);
3279 if (is_ia32_Immediate(value)) {
3280 const ia32_immediate_attr_t *attr
3281 = get_ia32_immediate_attr_const(value);
3282 unsigned size = get_signed_imm_size(attr->offset);
3288 bemit8((unsigned char)attr->offset);
3293 bemit_immediate(value, false);
3296 } else if (is_ia32_NoReg_GP(value)) {
3298 bemit_mod_am(6, node);
3300 const arch_register_t *reg = get_in_reg(node, n_ia32_Push_val);
3301 bemit8(0x50 + reg_gp_map[reg->index]);
3308 static void bemit_pop(const ir_node *node)
3310 const arch_register_t *reg = get_out_reg(node, pn_ia32_Pop_res);
3311 bemit8(0x58 + reg_gp_map[reg->index]);
3314 static void bemit_popmem(const ir_node *node)
3317 bemit_mod_am(0, node);
3320 static void bemit_call(const ir_node *node)
3322 ir_node *proc = get_irn_n(node, n_ia32_Call_addr);
3324 if (is_ia32_Immediate(proc)) {
3326 bemit_immediate(proc, true);
3328 bemit_unop(node, 0xFF, 2, n_ia32_Call_addr);
3332 static void bemit_jmp(const ir_node *dest_block)
3335 bemit_jmp_destination(dest_block);
3338 static void bemit_jump(const ir_node *node)
3340 if (can_be_fallthrough(node))
3343 bemit_jmp(get_cfop_target_block(node));
3346 static void bemit_jcc(int pnc, const ir_node *dest_block)
3348 unsigned char cc = pnc2cc(pnc);
3351 bemit_jmp_destination(dest_block);
3354 static void bemit_jp(bool odd, const ir_node *dest_block)
3358 bemit_jmp_destination(dest_block);
3361 static void bemit_ia32_jcc(const ir_node *node)
3363 ia32_condition_code_t cc = get_ia32_condcode(node);
3364 const ir_node *proj_true;
3365 const ir_node *proj_false;
3366 const ir_node *dest_true;
3367 const ir_node *dest_false;
3369 cc = determine_final_cc(node, 0, cc);
3371 /* get both Projs */
3372 proj_true = get_proj(node, pn_ia32_Jcc_true);
3373 assert(proj_true && "Jcc without true Proj");
3375 proj_false = get_proj(node, pn_ia32_Jcc_false);
3376 assert(proj_false && "Jcc without false Proj");
3378 if (can_be_fallthrough(proj_true)) {
3379 /* exchange both proj's so the second one can be omitted */
3380 const ir_node *t = proj_true;
3382 proj_true = proj_false;
3384 cc = ia32_negate_condition_code(cc);
3387 dest_true = get_cfop_target_block(proj_true);
3388 dest_false = get_cfop_target_block(proj_false);
3390 if (cc & ia32_cc_float_parity_cases) {
3391 /* Some floating point comparisons require a test of the parity flag,
3392 * which indicates that the result is unordered */
3393 if (cc & ia32_cc_negated) {
3394 bemit_jp(false, dest_true);
3396 /* we need a local label if the false proj is a fallthrough
3397 * as the falseblock might have no label emitted then */
3398 if (can_be_fallthrough(proj_false)) {
3400 bemit8(0x06); // jp + 6
3402 bemit_jp(false, dest_false);
3406 bemit_jcc(cc, dest_true);
3408 /* the second Proj might be a fallthrough */
3409 if (can_be_fallthrough(proj_false)) {
3410 /* it's a fallthrough */
3412 bemit_jmp(dest_false);
3416 static void bemit_switchjmp(const ir_node *node)
3418 unsigned long interval;
3422 const arch_register_t *in;
3424 /* fill the table structure */
3425 generate_jump_table(&tbl, node);
3427 /* two-complement's magic make this work without overflow */
3428 interval = tbl.max_value - tbl.min_value;
3430 in = get_in_reg(node, 0);
3431 /* emit the table */
3432 if (get_signed_imm_size(interval) == 1) {
3433 bemit8(0x83); // cmpl $imm8, %in
3437 bemit8(0x81); // cmpl $imm32, %in
3441 bemit8(0x0F); // ja tbl.defProj
3443 ia32_emitf(tbl.defProj, ".long %L - . - 4\n");
3445 if (tbl.num_branches > 1) {
3447 bemit8(0xFF); // jmp *tbl.label(,%in,4)
3448 bemit8(MOD_IND | ENC_REG(4) | ENC_RM(0x04));
3449 bemit8(ENC_SIB(2, reg_gp_map[in->index], 0x05));
3450 be_emit_irprintf("\t.long %s\n", tbl.label);
3452 be_gas_emit_switch_section(GAS_SECTION_RODATA);
3453 be_emit_cstring(".align 4\n");
3454 be_emit_irprintf("%s:\n", tbl.label);
3456 last_value = tbl.branches[0].value;
3457 for (i = 0; i != tbl.num_branches; ++i) {
3458 while (last_value != tbl.branches[i].value) {
3459 ia32_emitf(tbl.defProj, ".long %L\n");
3462 ia32_emitf(tbl.branches[i].target, ".long %L\n");
3465 be_gas_emit_switch_section(GAS_SECTION_TEXT);
3467 /* one jump is enough */
3468 panic("switch only has one case");
3469 //ia32_emitf(tbl.branches[0].target, "\tjmp %L\n");
3472 be_emit_write_line();
3480 static void bemit_return(const ir_node *node)
3482 unsigned pop = be_Return_get_pop(node);
3483 if (pop > 0 || be_Return_get_emit_pop(node)) {
3485 assert(pop <= 0xffff);
3492 static void bemit_subsp(const ir_node *node)
3494 const arch_register_t *out;
3497 /* mov %esp, %out */
3499 out = get_out_reg(node, 1);
3500 bemit8(MOD_REG | ENC_REG(reg_gp_map[out->index]) | ENC_RM(0x04));
3503 static void bemit_incsp(const ir_node *node)
3506 const arch_register_t *reg;
3510 offs = be_get_IncSP_offset(node);
3521 size = get_signed_imm_size(offs);
3522 bemit8(size == 1 ? 0x83 : 0x81);
3524 reg = get_out_reg(node, 0);
3525 bemit_modru(reg, ext);
3534 static void bemit_copybi(const ir_node *node)
3536 unsigned size = get_ia32_copyb_size(node);
3538 bemit8(0xA4); // movsb
3541 bemit8(0xA5); // movsw
3545 bemit8(0xA5); // movsl
3549 static void bemit_fbinop(const ir_node *node, unsigned code, unsigned code_to)
3551 if (get_ia32_op_type(node) == ia32_Normal) {
3552 const ia32_x87_attr_t *x87_attr = get_ia32_x87_attr_const(node);
3553 const arch_register_t *in1 = x87_attr->x87[0];
3554 const arch_register_t *in = x87_attr->x87[1];
3555 const arch_register_t *out = x87_attr->x87[2];
3559 } else if (out == in) {
3563 if (out->index == 0) {
3565 bemit8(MOD_REG | ENC_REG(code) | ENC_RM(in->index));
3568 bemit8(MOD_REG | ENC_REG(code_to) | ENC_RM(out->index));
3571 if (get_mode_size_bits(get_ia32_ls_mode(node)) == 32) {
3576 bemit_mod_am(code, node);
3580 static void bemit_fbinopp(const ir_node *node, unsigned const code)
3582 const ia32_x87_attr_t *x87_attr = get_ia32_x87_attr_const(node);
3583 const arch_register_t *out = x87_attr->x87[2];
3585 bemit8(code + out->index);
3588 static void bemit_fabs(const ir_node *node)
3596 static void bemit_fadd(const ir_node *node)
3598 bemit_fbinop(node, 0, 0);
3601 static void bemit_faddp(const ir_node *node)
3603 bemit_fbinopp(node, 0xC0);
3606 static void bemit_fchs(const ir_node *node)
3614 static void bemit_fdiv(const ir_node *node)
3616 bemit_fbinop(node, 6, 7);
3619 static void bemit_fdivp(const ir_node *node)
3621 bemit_fbinopp(node, 0xF8);
3624 static void bemit_fdivr(const ir_node *node)
3626 bemit_fbinop(node, 7, 6);
3629 static void bemit_fdivrp(const ir_node *node)
3631 bemit_fbinopp(node, 0xF0);
3634 static void bemit_fild(const ir_node *node)
3636 switch (get_mode_size_bits(get_ia32_ls_mode(node))) {
3638 bemit8(0xDF); // filds
3639 bemit_mod_am(0, node);
3643 bemit8(0xDB); // fildl
3644 bemit_mod_am(0, node);
3648 bemit8(0xDF); // fildll
3649 bemit_mod_am(5, node);
3653 panic("invalid mode size");
3657 static void bemit_fist(const ir_node *node)
3659 switch (get_mode_size_bits(get_ia32_ls_mode(node))) {
3661 bemit8(0xDF); // fists
3665 bemit8(0xDB); // fistl
3669 panic("invalid mode size");
3671 bemit_mod_am(2, node);
3674 static void bemit_fistp(const ir_node *node)
3676 switch (get_mode_size_bits(get_ia32_ls_mode(node))) {
3678 bemit8(0xDF); // fistps
3679 bemit_mod_am(3, node);
3683 bemit8(0xDB); // fistpl
3684 bemit_mod_am(3, node);
3688 bemit8(0xDF); // fistpll
3689 bemit_mod_am(7, node);
3693 panic("invalid mode size");
3697 static void bemit_fld(const ir_node *node)
3699 switch (get_mode_size_bits(get_ia32_ls_mode(node))) {
3701 bemit8(0xD9); // flds
3702 bemit_mod_am(0, node);
3706 bemit8(0xDD); // fldl
3707 bemit_mod_am(0, node);
3712 bemit8(0xDB); // fldt
3713 bemit_mod_am(5, node);
3717 panic("invalid mode size");
3721 static void bemit_fld1(const ir_node *node)
3725 bemit8(0xE8); // fld1
3728 static void bemit_fldcw(const ir_node *node)
3730 bemit8(0xD9); // fldcw
3731 bemit_mod_am(5, node);
3734 static void bemit_fldz(const ir_node *node)
3738 bemit8(0xEE); // fldz
3741 static void bemit_fmul(const ir_node *node)
3743 bemit_fbinop(node, 1, 1);
3746 static void bemit_fmulp(const ir_node *node)
3748 bemit_fbinopp(node, 0xC8);
3751 static void bemit_fpop(const ir_node *node)
3753 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
3755 bemit8(0xD8 + attr->x87[0]->index);
3758 static void bemit_fpush(const ir_node *node)
3760 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
3762 bemit8(0xC0 + attr->x87[0]->index);
3765 static void bemit_fpushcopy(const ir_node *node)
3767 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
3769 bemit8(0xC0 + attr->x87[0]->index);
3772 static void bemit_fst(const ir_node *node)
3774 switch (get_mode_size_bits(get_ia32_ls_mode(node))) {
3776 bemit8(0xD9); // fsts
3780 bemit8(0xDD); // fstl
3784 panic("invalid mode size");
3786 bemit_mod_am(2, node);
3789 static void bemit_fstp(const ir_node *node)
3791 switch (get_mode_size_bits(get_ia32_ls_mode(node))) {
3793 bemit8(0xD9); // fstps
3794 bemit_mod_am(3, node);
3798 bemit8(0xDD); // fstpl
3799 bemit_mod_am(3, node);
3804 bemit8(0xDB); // fstpt
3805 bemit_mod_am(7, node);
3809 panic("invalid mode size");
3813 static void bemit_fsub(const ir_node *node)
3815 bemit_fbinop(node, 4, 5);
3818 static void bemit_fsubp(const ir_node *node)
3820 bemit_fbinopp(node, 0xE8);
3823 static void bemit_fsubr(const ir_node *node)
3825 bemit_fbinop(node, 5, 4);
3828 static void bemit_fsubrp(const ir_node *node)
3830 bemit_fbinopp(node, 0xE0);
3833 static void bemit_fnstcw(const ir_node *node)
3835 bemit8(0xD9); // fnstcw
3836 bemit_mod_am(7, node);
3839 static void bemit_fnstsw(void)
3841 bemit8(0xDF); // fnstsw %ax
3845 static void bemit_ftstfnstsw(const ir_node *node)
3849 bemit8(0xD9); // ftst
3854 static void bemit_fucomi(const ir_node *node)
3856 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
3857 bemit8(0xDB); // fucomi
3858 bemit8(0xE8 + attr->x87[1]->index);
3861 static void bemit_fucomip(const ir_node *node)
3863 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
3864 bemit8(0xDF); // fucomip
3865 bemit8(0xE8 + attr->x87[1]->index);
3868 static void bemit_fucomfnstsw(const ir_node *node)
3870 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
3871 bemit8(0xDD); // fucom
3872 bemit8(0xE0 + attr->x87[1]->index);
3876 static void bemit_fucompfnstsw(const ir_node *node)
3878 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
3879 bemit8(0xDD); // fucomp
3880 bemit8(0xE8 + attr->x87[1]->index);
3884 static void bemit_fucomppfnstsw(const ir_node *node)
3888 bemit8(0xDA); // fucompp
3893 static void bemit_fxch(const ir_node *node)
3895 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
3897 bemit8(0xC8 + attr->x87[0]->index);
3901 * The type of a emitter function.
3903 typedef void (*emit_func) (const ir_node *);
3906 * Set a node emitter. Make it a bit more type safe.
3908 static void register_emitter(ir_op *op, emit_func func)
3910 op->ops.generic = (op_func) func;
3913 static void ia32_register_binary_emitters(void)
3915 /* first clear the generic function pointer for all ops */
3916 clear_irp_opcodes_generic_func();
3918 /* benode emitter */
3919 register_emitter(op_be_Copy, bemit_copy);
3920 register_emitter(op_be_CopyKeep, bemit_copy);
3921 register_emitter(op_be_IncSP, bemit_incsp);
3922 register_emitter(op_be_Perm, bemit_perm);
3923 register_emitter(op_be_Return, bemit_return);
3924 register_emitter(op_ia32_Adc, bemit_adc);
3925 register_emitter(op_ia32_Add, bemit_add);
3926 register_emitter(op_ia32_AddMem, bemit_addmem);
3927 register_emitter(op_ia32_AddMem8Bit, bemit_addmem8bit);
3928 register_emitter(op_ia32_And, bemit_and);
3929 register_emitter(op_ia32_AndMem, bemit_andmem);
3930 register_emitter(op_ia32_AndMem8Bit, bemit_andmem8bit);
3931 register_emitter(op_ia32_Breakpoint, bemit_int3);
3932 register_emitter(op_ia32_CMovcc, bemit_cmovcc);
3933 register_emitter(op_ia32_Call, bemit_call);
3934 register_emitter(op_ia32_Cltd, bemit_cltd);
3935 register_emitter(op_ia32_Cmc, bemit_cmc);
3936 register_emitter(op_ia32_Cmp, bemit_cmp);
3937 register_emitter(op_ia32_Cmp8Bit, bemit_cmp8bit);
3938 register_emitter(op_ia32_Const, bemit_mov_const);
3939 register_emitter(op_ia32_Conv_I2I, bemit_conv_i2i);
3940 register_emitter(op_ia32_Conv_I2I8Bit, bemit_conv_i2i);
3941 register_emitter(op_ia32_CopyB_i, bemit_copybi);
3942 register_emitter(op_ia32_Cwtl, bemit_cwtl);
3943 register_emitter(op_ia32_Dec, bemit_dec);
3944 register_emitter(op_ia32_DecMem, bemit_decmem);
3945 register_emitter(op_ia32_Div, bemit_div);
3946 register_emitter(op_ia32_FldCW, bemit_fldcw);
3947 register_emitter(op_ia32_FnstCW, bemit_fnstcw);
3948 register_emitter(op_ia32_FtstFnstsw, bemit_ftstfnstsw);
3949 register_emitter(op_ia32_FucomFnstsw, bemit_fucomfnstsw);
3950 register_emitter(op_ia32_Fucomi, bemit_fucomi);
3951 register_emitter(op_ia32_FucompFnstsw, bemit_fucompfnstsw);
3952 register_emitter(op_ia32_Fucompi, bemit_fucomip);
3953 register_emitter(op_ia32_FucomppFnstsw, bemit_fucomppfnstsw);
3954 register_emitter(op_ia32_IDiv, bemit_idiv);
3955 register_emitter(op_ia32_IJmp, bemit_ijmp);
3956 register_emitter(op_ia32_IMul, bemit_imul);
3957 register_emitter(op_ia32_IMul1OP, bemit_imul1op);
3958 register_emitter(op_ia32_Inc, bemit_inc);
3959 register_emitter(op_ia32_IncMem, bemit_incmem);
3960 register_emitter(op_ia32_Jcc, bemit_ia32_jcc);
3961 register_emitter(op_ia32_Jmp, bemit_jump);
3962 register_emitter(op_ia32_LdTls, bemit_ldtls);
3963 register_emitter(op_ia32_Lea, bemit_lea);
3964 register_emitter(op_ia32_Leave, bemit_leave);
3965 register_emitter(op_ia32_Load, bemit_load);
3966 register_emitter(op_ia32_Minus64Bit, bemit_minus64bit);
3967 register_emitter(op_ia32_Mul, bemit_mul);
3968 register_emitter(op_ia32_Neg, bemit_neg);
3969 register_emitter(op_ia32_NegMem, bemit_negmem);
3970 register_emitter(op_ia32_Not, bemit_not);
3971 register_emitter(op_ia32_NotMem, bemit_notmem);
3972 register_emitter(op_ia32_Or, bemit_or);
3973 register_emitter(op_ia32_OrMem, bemit_ormem);
3974 register_emitter(op_ia32_OrMem8Bit, bemit_ormem8bit);
3975 register_emitter(op_ia32_Pop, bemit_pop);
3976 register_emitter(op_ia32_PopEbp, bemit_pop);
3977 register_emitter(op_ia32_PopMem, bemit_popmem);
3978 register_emitter(op_ia32_Push, bemit_push);
3979 register_emitter(op_ia32_RepPrefix, bemit_rep);
3980 register_emitter(op_ia32_Rol, bemit_rol);
3981 register_emitter(op_ia32_RolMem, bemit_rolmem);
3982 register_emitter(op_ia32_Ror, bemit_ror);
3983 register_emitter(op_ia32_RorMem, bemit_rormem);
3984 register_emitter(op_ia32_Sahf, bemit_sahf);
3985 register_emitter(op_ia32_Sar, bemit_sar);
3986 register_emitter(op_ia32_SarMem, bemit_sarmem);
3987 register_emitter(op_ia32_Sbb, bemit_sbb);
3988 register_emitter(op_ia32_Setcc, bemit_setcc);
3989 register_emitter(op_ia32_Shl, bemit_shl);
3990 register_emitter(op_ia32_ShlD, bemit_shld);
3991 register_emitter(op_ia32_ShlMem, bemit_shlmem);
3992 register_emitter(op_ia32_Shr, bemit_shr);
3993 register_emitter(op_ia32_ShrD, bemit_shrd);
3994 register_emitter(op_ia32_ShrMem, bemit_shrmem);
3995 register_emitter(op_ia32_Stc, bemit_stc);
3996 register_emitter(op_ia32_Store, bemit_store);
3997 register_emitter(op_ia32_Store8Bit, bemit_store);
3998 register_emitter(op_ia32_Sub, bemit_sub);
3999 register_emitter(op_ia32_SubMem, bemit_submem);
4000 register_emitter(op_ia32_SubMem8Bit, bemit_submem8bit);
4001 register_emitter(op_ia32_SubSP, bemit_subsp);
4002 register_emitter(op_ia32_SwitchJmp, bemit_switchjmp);
4003 register_emitter(op_ia32_Test, bemit_test);
4004 register_emitter(op_ia32_Test8Bit, bemit_test8bit);
4005 register_emitter(op_ia32_Xor, bemit_xor);
4006 register_emitter(op_ia32_Xor0, bemit_xor0);
4007 register_emitter(op_ia32_XorMem, bemit_xormem);
4008 register_emitter(op_ia32_XorMem8Bit, bemit_xormem8bit);
4009 register_emitter(op_ia32_fabs, bemit_fabs);
4010 register_emitter(op_ia32_fadd, bemit_fadd);
4011 register_emitter(op_ia32_faddp, bemit_faddp);
4012 register_emitter(op_ia32_fchs, bemit_fchs);
4013 register_emitter(op_ia32_fdiv, bemit_fdiv);
4014 register_emitter(op_ia32_fdivp, bemit_fdivp);
4015 register_emitter(op_ia32_fdivr, bemit_fdivr);
4016 register_emitter(op_ia32_fdivrp, bemit_fdivrp);
4017 register_emitter(op_ia32_fild, bemit_fild);
4018 register_emitter(op_ia32_fist, bemit_fist);
4019 register_emitter(op_ia32_fistp, bemit_fistp);
4020 register_emitter(op_ia32_fld, bemit_fld);
4021 register_emitter(op_ia32_fld1, bemit_fld1);
4022 register_emitter(op_ia32_fldz, bemit_fldz);
4023 register_emitter(op_ia32_fmul, bemit_fmul);
4024 register_emitter(op_ia32_fmulp, bemit_fmulp);
4025 register_emitter(op_ia32_fpop, bemit_fpop);
4026 register_emitter(op_ia32_fpush, bemit_fpush);
4027 register_emitter(op_ia32_fpushCopy, bemit_fpushcopy);
4028 register_emitter(op_ia32_fst, bemit_fst);
4029 register_emitter(op_ia32_fstp, bemit_fstp);
4030 register_emitter(op_ia32_fsub, bemit_fsub);
4031 register_emitter(op_ia32_fsubp, bemit_fsubp);
4032 register_emitter(op_ia32_fsubr, bemit_fsubr);
4033 register_emitter(op_ia32_fsubrp, bemit_fsubrp);
4034 register_emitter(op_ia32_fxch, bemit_fxch);
4036 /* ignore the following nodes */
4037 register_emitter(op_ia32_ProduceVal, emit_Nothing);
4038 register_emitter(op_be_Keep, emit_Nothing);
4039 register_emitter(op_be_Start, emit_Nothing);
4040 register_emitter(op_Phi, emit_Nothing);
4041 register_emitter(op_Start, emit_Nothing);
4044 static void gen_binary_block(ir_node *block)
4048 ia32_emit_block_header(block);
4050 /* emit the contents of the block */
4051 sched_foreach(block, node) {
4052 ia32_emit_node(node);
4056 void ia32_gen_binary_routine(ir_graph *irg)
4058 ir_entity *entity = get_irg_entity(irg);
4059 const arch_env_t *arch_env = be_get_irg_arch_env(irg);
4060 ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
4061 ir_node **blk_sched = irg_data->blk_sched;
4064 isa = (ia32_isa_t*) arch_env;
4066 ia32_register_binary_emitters();
4068 be_gas_emit_function_prolog(entity, ia32_cg_config.function_alignment);
4070 /* we use links to point to target blocks */
4071 ir_reserve_resources(irg, IR_RESOURCE_IRN_LINK);
4072 irg_block_walk_graph(irg, ia32_gen_labels, NULL, NULL);
4074 /* initialize next block links */
4075 n = ARR_LEN(blk_sched);
4076 for (i = 0; i < n; ++i) {
4077 ir_node *block = blk_sched[i];
4078 ir_node *prev = i > 0 ? blk_sched[i-1] : NULL;
4080 set_irn_link(block, prev);
4083 for (i = 0; i < n; ++i) {
4084 ir_node *block = blk_sched[i];
4085 gen_binary_block(block);
4088 be_gas_emit_function_epilog(entity);
4089 be_dbg_method_end();
4091 be_emit_write_line();
4093 ir_free_resources(irg, IR_RESOURCE_IRN_LINK);
4097 void ia32_init_emitter(void)
4099 lc_opt_entry_t *be_grp;
4100 lc_opt_entry_t *ia32_grp;
4102 be_grp = lc_opt_get_grp(firm_opt_get_root(), "be");
4103 ia32_grp = lc_opt_get_grp(be_grp, "ia32");
4105 lc_opt_add_table(ia32_grp, ia32_emitter_options);
4109 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.emitter");